Synchronous rectification structure and method of CLLLC circuit based on DSP

Abstract

The invention discloses a CLLLC circuit synchronous rectification structure and method based on a DSP. The structure comprises a primary side full-bridge circuit, a resonant cavity, a secondary side synchronous rectification full-bridge circuit and a comparison module. The method comprises the following steps: S1, judging whether a circuit structure is enabled or not; s2, the DSP sends a primary side PWM rising edge signal to a primary side full-bridge circuit, and a secondary side PWM synchronously generates a rising edge signal; s3, a comparison module detects the primary side sampling current and the secondary side sampling current and carries out comparison and judgment; s4, when the secondary side sampling current is greater than the primary side sampling current, a switching tube in the secondary side synchronous rectification full-bridge circuit does not execute an action; and S5, when the secondary side sampling current is equal to the primary side sampling current, setting the secondary side PWM to generate a falling edge signal. According to the invention, the switch-on and switch-off time of the switch tube can be flexibly controlled, and the efficiency of the converter is improved on the premise of protecting the circuit from being damaged by overvoltage or overcurrent.

Description

Technical Field

[0001] The present invention relates to the technical field of synchronous rectification, and in particular to a CLLLC circuit synchronous rectification structure and method based on DSP. Background Art

[0002] To improve power converter efficiency, synchronous rectification technology is often incorporated into resonant converters. Existing synchronous rectification techniques often use MOS transistors (MOSFETs) to replace traditional mechanical switches, achieving higher efficiency and lower losses. However, synchronous rectification control strategies are difficult to design. When the dead time is too long, the switch is mostly off, causing current to flow through the diode, increasing losses. When the dead time is too short, the upper and lower rectifiers can directly conduct, damaging the transformer and the switch. Summary of the Invention

[0003] The present invention provides a DSP-based CLLLC circuit synchronous rectification structure and method that flexibly controls the on- and off-timing of the switch tube to better protect the circuit from damage caused by overvoltage or overcurrent. This improves converter efficiency while protecting the circuit from damage caused by overvoltage or overcurrent, and can at least solve one of the above-mentioned technical problems.

[0004] In order to solve the above technical problems, the present invention adopts the following technical solutions: A DSP-based CLLLC circuit synchronous rectification structure includes a primary full-bridge circuit, a resonant cavity, and a secondary synchronous rectification full-bridge circuit, wherein the primary full-bridge circuit and the secondary synchronous rectification full-bridge circuit are connected via the resonant cavity; The primary full-bridge circuit includes a first switch tube SP1, a second switch tube SP2, a third switch tube SP3 and a fourth switch tube SP4; The resonant cavity includes a resonant first inductor Lr, a resonant second inductor Ls, a resonant first capacitor Cr, a resonant second capacitor Cs and a transformer, and the transformer includes an excitation inductor Lm; The secondary side synchronous rectification full-bridge circuit includes a first switch tube SSP1, a second switch tube SSP2, a third switch tube SSP3 and a fourth switch tube SSP4; The midpoint of the first switch tube SP1 and the second switch tube SP2 of the primary full-bridge circuit is connected to the resonant first inductor Lr, the midpoint of the third switch tube SP3 and the fourth switch tube SP4 of the primary full-bridge circuit is connected to the resonant first capacitor Cr, and the resonant first inductor Lr and the resonant first capacitor Cr are connected to the primary side of the transformer; The first switch tube SSP1 and the second switch tube SSP2 of the secondary side synchronous rectification full-bridge circuit are connected to the resonant second inductor Ls, the third switch tube SSP3 and the fourth switch tube SSP4 of the secondary side synchronous rectification full-bridge circuit are connected to the resonant second capacitor Cs, and the resonant second inductor Ls and the resonant second capacitor Cs are connected to the secondary side of the transformer.

[0005] Furthermore, it also includes a comparison module, which is a functional module in the DSP chip, used to detect and compare the primary side collected voltage / current of the primary side full-bridge circuit and the secondary side collected voltage / current of the secondary side synchronous rectification full-bridge circuit, and determine whether the switch tube in the secondary side synchronous rectification full-bridge circuit is turned off or not.

[0006] Furthermore, the switch tube in the secondary-side synchronous rectification full-bridge circuit is used to perform no action or perform a shutdown action according to the comparison result of the comparison module.

[0007] A DSP-based CLLLC circuit synchronous rectification method is implemented using the DSP-based CLLLC circuit synchronous rectification structure, comprising the following steps: S1: Determine whether the synchronous rectification structure of the DSP-based CLLLC circuit is enabled; S2: In the enabled state, the DSP chip sends the primary-side PWM rising edge signal to the primary-side full-bridge circuit, and the secondary-side PWM synchronously generates a rising edge signal to turn on the switch tube of the secondary-side synchronous rectification full-bridge circuit; S3: The comparison module in the DSP chip detects the primary-side sampling current input by the primary-side full-bridge circuit and the secondary-side sampling current input by the secondary-side synchronous rectification full-bridge circuit, and makes a comparison and judgment; S4: When the secondary side sampling current is greater than the primary side sampling current, the switch tube in the secondary side synchronous rectification full-bridge circuit does not perform any action; S5: When the secondary side sampling current is equal to the primary side sampling current, the secondary side PWM is set to generate a falling edge signal to turn off the switch tube in the secondary side synchronous rectification full-bridge circuit in advance.

[0008] Furthermore, when the synchronous rectification structure of the DSP-based CLLLC circuit is in a light-load state and the comparison module detects that the output current is greater than the minimum current reference value, the software determines to enable; When the synchronous rectification structure of the DSP-based CLLLC circuit is in the under-resonance and quasi-resonance state, and the comparison module detects that the output current is greater than the current reference value, the software determines to enable; When the synchronous rectification structure of the DSP-based CLLLC circuit is in an over-resonant state, it should be considered that the over-resonant secondary current is an asymmetric sine wave and cannot achieve ZCS. Therefore, the threshold current is set to be larger than the threshold current in the under-resonant or quasi-resonant state. Among them, the output current is the actual current, which refers to the secondary side sampling current of the secondary side synchronous rectification full-bridge circuit, and the current reference value is the reference current, which refers to the primary side sampling current of the primary side full-bridge circuit.

[0009] Furthermore, the conduction of the switch tube is determined by the voltage of the switch tube in the secondary synchronous rectification full-bridge circuit. When the voltage of the switch tube in the secondary synchronous rectification full-bridge circuit passes through zero and is delayed for a dead time, the switch tube is turned on.

[0010] Furthermore, the shutdown of the switch tube in the secondary-side synchronous rectification full-bridge circuit is determined by the secondary-side sampling current. When it is detected that the secondary-side sampling current is greater than the threshold current, the switch tube in the secondary-side synchronous rectification full-bridge circuit is turned off.

[0011] The beneficial effects of the present invention are embodied in: The present invention combines external-drive synchronous rectification with internal-drive synchronous rectification. Compared with traditional external drive, this circuit structure does not require additional circuits or control chips, thereby reducing design costs. Compared with traditional internal drive, this circuit structure does not require judgment of the number of zero crossings and whether each zero crossing corresponds to on or off. The turning on of the secondary rectifier tube follows the primary switch tube, and the turning off of the secondary rectifier tube compares the reference current and the actual current. The control logic is relatively simple and clear. At the same time, it can provide a reasonable dead time, ensuring that the current passes through the switch tube most of the time while ensuring safety, thereby improving the efficiency of the converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The drawings described herein are used to provide further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute improper limitations on the present application.

[0013] Figure 1 2 is a schematic diagram of a synchronous rectification structure according to an embodiment of the present invention.

[0014] Figure 2 4 is a flow chart of a synchronous rectification method according to an embodiment of the present invention.

[0015] Figure 3 2 is a schematic diagram of a CMPSS comparison module according to an embodiment of the present invention.

[0016] Figure 4 1 is a schematic diagram of synchronous rectification switch waveforms according to an embodiment of the present invention.

[0017] Figure 5 It is a structural block diagram of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. In the absence of conflict, the embodiments in this application and the features in the embodiments can be combined with each other. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0019] It should be noted that if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features specified as "first" and "second" may explicitly or implicitly include at least one of such features. In addition, the meaning of "and / or" appearing throughout the text includes three parallel schemes. Taking "A and / or B" as an example, it includes scheme A, scheme B, or schemes in which A and B are satisfied at the same time.

[0020] See also Figure 1 An embodiment of the present invention provides a DSP-based CLLLC circuit synchronous rectification structure, comprising a primary full-bridge circuit, a resonant cavity, and a secondary synchronous rectification full-bridge circuit, wherein the primary full-bridge circuit and the secondary synchronous rectification full-bridge circuit are connected via the resonant cavity; The primary full-bridge circuit includes a first switch tube SP1, a second switch tube SP2, a third switch tube SP3 and a fourth switch tube SP4; The resonant cavity includes a resonant first inductor Lr, a resonant second inductor Ls, a resonant first capacitor Cr, a resonant second capacitor Cs and a transformer, and the transformer includes an excitation inductor Lm; The secondary side synchronous rectification full-bridge circuit includes a first switch tube SSP1, a second switch tube SSP2, a third switch tube SSP3 and a fourth switch tube SSP4; The midpoint of the first switch tube SP1 and the second switch tube SP2 of the primary full-bridge circuit is connected to the resonant first inductor Lr, the midpoint of the third switch tube SP3 and the fourth switch tube SP4 of the primary full-bridge circuit is connected to the resonant first capacitor Cr, and the resonant first inductor Lr and the resonant first capacitor Cr are connected to the primary side of the transformer; The first switch tube SSP1 and the second switch tube SSP2 of the secondary side synchronous rectification full-bridge circuit are connected to the resonant second inductor Ls, the third switch tube SSP3 and the fourth switch tube SSP4 of the secondary side synchronous rectification full-bridge circuit are connected to the resonant second capacitor Cs, and the resonant second inductor Ls and the resonant second capacitor Cs are connected to the secondary side of the transformer.

[0021] The present invention combines external-driven synchronous rectification with internal-driven synchronous rectification. Compared with traditional external drive, this circuit structure does not require additional circuits or control chips, reducing design costs. Compared with traditional internal drive, this circuit structure does not need to determine the number of zero crossings and whether each zero crossing corresponds to on or off, and the control logic is relatively simple.

[0022] See also Figure 3 In this embodiment, a comparison module is also included. The comparison module is a functional module in the DSP chip, which is used to detect and compare the primary-side sampled voltage / current of the primary full-bridge circuit and the secondary-side sampled voltage / current of the secondary synchronous rectification full-bridge circuit, and determine whether the switch tube in the secondary synchronous rectification full-bridge circuit is turned off. In this application, the comparison module uses a CMPSS module to compare input A and input B, setting input A as the secondary-side sampled current and input B as the reference current. That is, in the primary-side sampling circuit, when input A is greater than input B, the switch tube in the secondary synchronous rectification full-bridge circuit does not operate. When input A is less than input B, the secondary-side PWM is set to generate a falling edge signal to prematurely shut down the switch tube in the secondary synchronous rectification full-bridge circuit to ensure circuit safety. The magnitude of the reference current is determined based on the actual design scheme and circuit characteristics, and should ensure safe shutdown under all operating conditions.

[0023] It should be noted that the CMPSS module is used to implement shutdown in this embodiment. If other MCUs are used, the actual current collected by the current sensor and the reference current can also be subtracted. If the error is within an acceptable error range (determined by the actual situation), a shutdown command is issued. It should also be noted that the comparison module described in this application is a unique functional module in the DSP chip, rather than an actual hardware circuit module.

[0024] In this embodiment, the switch tube in the secondary-side synchronous rectification full-bridge circuit is used to perform no action or perform a shutdown action according to the comparison result of the comparison module.

[0025] See also Figure 2 The embodiment of the present invention further provides a DSP-based CLLLC circuit synchronous rectification method, which is implemented using the DSP-based CLLLC circuit synchronous rectification structure and includes the following steps: S1: Determine whether the synchronous rectification structure of the DSP-based CLLLC circuit is enabled; S2: In the enabled state, the DSP chip sends the primary-side PWM rising edge signal to the primary-side full-bridge circuit, and the secondary-side PWM synchronously generates a rising edge signal to turn on the switch tube of the secondary-side synchronous rectification full-bridge circuit; S3: The comparison module in the DSP chip detects the primary-side sampling current input by the primary-side full-bridge circuit and the secondary-side sampling current input by the secondary-side synchronous rectification full-bridge circuit, and makes a comparison and judgment; S4: When the secondary side sampling current is greater than the primary side sampling current, the switch tube in the secondary side synchronous rectification full-bridge circuit does not perform any action; S5: When the secondary side sampling current is equal to the primary side sampling current, the secondary side PWM is set to generate a falling edge signal to turn off the switch tube in the secondary side synchronous rectification full-bridge circuit in advance; It should be noted that, ideally, the falling edge signal should be triggered when the secondary-side sampling current is equal to the primary-side sampling current. However, considering that there is an error in circuit sampling in actual conditions, the falling edge signal should be triggered when the secondary-side sampling current is slightly larger than the primary-side sampling current to turn off the switch tube in advance. The purpose is to achieve zero-power shutdown as much as possible while protecting the circuit.

[0026] Common implementation methods of synchronous rectification include self-drive and external drive. The main difference between the two lies in the source of the drive voltage and the circuit complexity.

[0027] The driving voltage for self-driven synchronous rectification (SR) comes from the circuit's own voltage or current, such as the voltage in the transformer's synchronous rectifier circuit or from other auxiliary windings. This approach offers the following advantages: 1. It's cost-effective, eliminating the need for expensive components; 2. Its circuitry is relatively simple; 3. It's suitable for driving transformers with non-sinusoidal waveforms, such as resonant LLC topologies. However, it has the following challenges: 1. The driving method is highly dependent on the circuit topology itself, making design difficult; 2. The drive level is significantly affected by the input voltage and output voltage; 3. It's affected by transformer leakage inductance; and 4. Controlling the on / off process is difficult.

[0028] Externally driven synchronous rectification, on the other hand, uses a primary-side drive signal to control the switching of the rectifier. It has the following advantages: 1. It reduces the dead zone of the rectifier and easily implements timing; 2. It can flexibly control the on and off timing of the switch, thereby achieving better rectification; 3. It can control the on and off of the switch by detecting the circuit voltage and current, thereby better protecting the circuit from damage caused by overvoltage and overcurrent. However, it has the following problems: 1. It increases circuit complexity, cost, and reliability; 2. It requires the development or use of a dedicated chip to control the drive circuit; 3. The control circuit and driver itself will cause additional losses, making it unsuitable for low-power applications; 4. It is expensive and has a long development cycle.

[0029] Therefore, the present invention provides a new synchronous rectification method that combines external drive and internal drive, has a simpler design, does not require an additional driver chip, can provide a reasonable dead time, and improves the efficiency of the converter while ensuring the safety of the circuit structure.

[0030] In this embodiment, when the DSP-based CLLLC circuit synchronous rectification structure is in a light-load state and the comparison module detects that the output current is greater than the minimum current reference value, the software determines to enable; When the synchronous rectification structure of the DSP-based CLLLC circuit is in the under-resonance and quasi-resonance state, and the comparison module detects that the output current is greater than the current reference value, the software determines to enable; When the synchronous rectification structure of the DSP-based CLLLC circuit is in an over-resonant state, it should be considered that the over-resonant secondary current is an asymmetric sine wave and cannot achieve ZCS. Therefore, the threshold current is set to be larger than the threshold current in the under-resonant or quasi-resonant state. Among them, the output current is the actual current, which refers to the secondary side sampling current of the secondary side synchronous rectification full-bridge circuit, and the current reference value is the reference current, which refers to the primary side sampling current of the primary side full-bridge circuit.

[0031] When the synchronous rectification structure of the DSP-based CLLLC circuit is in a light-load state, the bidirectional conduction characteristics of the freewheeling MOS tube enable the inductance and current in this state to reverse. Since the secondary-side synchronous rectification full-bridge circuit cannot automatically switch from CCM mode to DCM mode, large circulating current losses will be generated. Therefore, the synchronous rectification is not turned on at this time.

[0032] In this embodiment, the conduction of the switch tube is determined by the voltage of the switch tube in the secondary synchronous rectification full-bridge circuit. When the voltage of the switch tube in the secondary synchronous rectification full-bridge circuit passes through zero and is delayed for a dead time, the switch tube is turned on.

[0033] The dead time is determined by the specific circuit conditions and needs to be determined by considering multiple factors: 1) Consider the characteristics of the switch: Different types of switches (such as MOSFETs or IGBTs) have different switching characteristics and delay times. When selecting the dead time, the switching speed and conduction characteristics of the switch need to be considered.

[0034] 2) Avoid cross conduction: A dead time that is too short may cause two switches to conduct at the same time, causing a short circuit and damage. Therefore, it is necessary to ensure that the dead time is long enough to avoid cross conduction.

[0035] 3) Improve efficiency: During the dead time, the switch tube cannot effectively transfer energy to the load. Therefore, too long a dead time will lead to increased switching losses. An appropriate dead time can improve efficiency while avoiding cross conduction.

[0036] When selecting dead time, you can first simulate the impact of dead time on circuit characteristics and then determine the ideal optimal dead time through experimental testing. In the actual test bench, all operating states should be tested to ensure that the circuit can operate in all operating states.

[0037] In this embodiment, the shutdown of the switches in the secondary-side synchronous rectification full-bridge circuit is determined by the secondary-side sampled current. When the secondary-side sampled current is detected to be greater than a threshold current, the switches in the secondary-side synchronous rectification full-bridge circuit are shut off. The threshold current should be greater than 0 for shutdown. In actual operation, the threshold value should be maintained based on circuit operating conditions to ensure that sensor sampling errors do not cause the switches to short-circuit and damage the circuit.

[0038] In summary, the threshold current should be considered to avoid cross-conduction circuit at the maximum frequency in the over-resonance state to ensure the safety of the circuit.

[0039] See also Figure 4 The following is an example of over-resonance, where SP1 represents the primary switch tubes SSP1 and SSP3, and SP2 represents the primary switch tubes SSP2 and SSP4. Lr is the resonant current, i Lm is the excitation current, i ref To turn off the reference current; When SP1 is turned on, SS1 is turned on after the dead time. When SP2 is turned on, SS2 is turned on after the dead time. When the current on the secondary switch tube reaches i ref When , the switch tube is closed.

[0040] The following are the explanations of some terms in this application: DSP chip: A commonly used chip for digital signal processing. This application uses the TI TMS320F280049 DSP component, a 32-bit real-time microcontroller (MCU) from TI's (Texas Instruments) C2000 series, specifically designed for complex systems requiring high-performance real-time control. Other DSP chip models may also be used, depending on the functionality being implemented; no specific restrictions are imposed here.

[0041] CLLLC circuit: A commonly used switching tube circuit in the secondary-side synchronous rectification full-bridge circuit, which can realize bidirectional energy flow.

[0042] CCM mode (Continuous Conduction Mode): In this mode, the current in the inductor always remains at a fixed positive value and does not drop to zero, which means that the current in the inductor always flows continuously during a complete switching cycle.

[0043] DCM (discontinuous conduction mode): In this mode, the current in the inductor will drop to zero, and the inductor will go through two stages of conduction and shutdown in a complete switching cycle. That is, there is a period of time in the switching cycle when the inductor is non-conductive.

[0044] ZCS: Zero Current Shutdown, which reduces the current level to close to zero when a power switch (such as a MOSFET or IGBT) is turned off, thereby reducing power consumption and electromagnetic interference (EMI) during switching.

[0045] An embodiment of the present invention further provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the processor is caused to perform the steps of the above method.

[0046] See also Figure 5 An embodiment of the present invention further provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor executes the steps of the above method.

[0047] An embodiment of the present invention further provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute any one of the DSP-based CLLLC circuit synchronous rectification methods in the above embodiments.

[0048] It is understandable that the structure, device and storage medium provided in the embodiments of the present invention correspond to the method provided in the embodiments of the present invention, and the explanation, examples and beneficial effects of the relevant contents can refer to the corresponding parts of the above methods.

[0049] It should be noted that those skilled in the art will appreciate that all or part of the steps implemented in the embodiments of the present invention can be implemented in whole or in part via software, hardware, firmware, or any combination thereof. When implemented using software, they can be implemented in whole or in part in the form of a computer program product. The computer program product comprises one or more computer instructions. When loaded and executed on a computer, the computer program instructions fully or partially perform the processes or functions described in the embodiments of the present application. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible by a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

[0050] It should be understood that the examples and implementation methods described herein are for illustrative purposes only and are not intended to limit the present invention. Those skilled in the art may make various modifications or changes based on them. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A CLLLC circuit synchronous rectification structure based on DSP, characterized in that: It includes a primary full-bridge circuit, a resonant cavity and a secondary synchronous rectification full-bridge circuit, wherein the primary full-bridge circuit and the secondary synchronous rectification full-bridge circuit are connected via the resonant cavity; The primary full-bridge circuit includes a first switch tube SP1, a second switch tube SP2, a third switch tube SP3 and a fourth switch tube SP4; The resonant cavity includes a resonant first inductor Lr, a resonant second inductor Ls, a resonant first capacitor Cr, a resonant second capacitor Cs and a transformer, and the transformer includes an excitation inductor Lm; The secondary side synchronous rectification full-bridge circuit comprises a first switch tube SSP1, a second switch tube SSP2, a third switch tube SSP3 and a fourth switch tube SSP4; The midpoints of the first switch tube SP1 and the second switch tube SP2 of the primary full-bridge circuit are connected to the resonant first inductor Lr, the midpoints of the third switch tube SP3 and the fourth switch tube SP4 of the primary full-bridge circuit are connected to the resonant first capacitor Cr, and the resonant first inductor Lr and the resonant first capacitor Cr are connected to the primary side of the transformer; The first switch tube SSP1 and the second switch tube SSP2 of the secondary side synchronous rectification full-bridge circuit are connected to the resonant second inductor Ls, the third switch tube SSP3 and the fourth switch tube SSP4 of the secondary side synchronous rectification full-bridge circuit are connected to the resonant second capacitor Cs, and the resonant second inductor Ls and the resonant second capacitor Cs are connected to the secondary side of the transformer.

2. The CLLLC circuit synchronous rectification structure based on DSP as claimed in claim 1, characterized in that: It also includes a comparison module, which is a functional module in the DSP chip, and is used to detect and compare the primary side collected voltage / current of the primary side full-bridge circuit and the secondary side collected voltage / current of the secondary side synchronous rectification full-bridge circuit, and to determine whether the switch tube in the secondary side synchronous rectification full-bridge circuit is turned off or not.

3. The CLLLC circuit synchronous rectification structure based on DSP as claimed in claim 2, characterized in that: The switch tube in the secondary-side synchronous rectification full-bridge circuit is used to perform no action or perform a shutdown action according to the comparison result of the comparison module.

4. A DSP-based CLLLC circuit synchronous rectification method, implemented by using the DSP-based CLLLC circuit synchronous rectification structure as claimed in any one of claims 1 to 3, characterized in that: The following steps are involved: S1: Determine whether the synchronous rectification structure of the CLLLC circuit based on DSP is enabled; S2: In the enabled state, the DSP chip sends the primary PWM rising edge signal to the primary full-bridge circuit, and the secondary PWM synchronously generates a rising edge signal to turn on the switch tube of the secondary synchronous rectification full-bridge circuit; S3: The comparison module in the DSP chip detects the primary sampling current input by the primary full-bridge circuit and the secondary sampling current input by the secondary synchronous rectification full-bridge circuit, and makes a comparison and judgment; S4: When the secondary side sampling current is greater than the primary side sampling current, the switch tube in the secondary side synchronous rectification full-bridge circuit does not perform an action; S5: When the secondary side sampling current is equal to the primary side sampling current, the secondary side PWM is set to generate a falling edge signal to turn off the switch tube in the secondary side synchronous rectification full-bridge circuit in advance.

5. The CLLLC circuit synchronous rectification method based on DSP as claimed in claim 1, characterized in that: When the synchronous rectification structure of the CLLLC circuit based on DSP is in a light load state and the comparison module detects that the output current is greater than the minimum current reference value, the software determines to enable; When the synchronous rectification structure of the CLLLC circuit based on DSP is in the under-resonance and quasi-resonance state, and the comparison module detects that the output current is greater than the current reference value, the software determines to enable; When the synchronous rectification structure of the DSP-based CLLLC circuit is in an over-resonance state, it should be considered that the over-resonance secondary current is an asymmetric sine wave and cannot achieve ZCS. Therefore, the threshold current is set larger than the threshold current in the under-resonance or quasi-resonance state; Among them, the output current is the actual current, which refers to the secondary side sampling current of the secondary side synchronous rectification full-bridge circuit, and the current reference value is the reference current, which refers to the primary side sampling current of the primary side full-bridge circuit.

6. The CLLLC circuit synchronous rectification method based on DSP as claimed in claim 1, characterized in that: The conduction of the switch tube is determined by the voltage of the switch tube in the secondary synchronous rectification full-bridge circuit. When the voltage of the switch tube in the secondary synchronous rectification full-bridge circuit passes through zero and the dead time is delayed, the switch tube is turned on.

7. The CLLLC circuit synchronous rectification method based on DSP as claimed in claim 1, characterized in that: The switch tube in the secondary synchronous rectification full-bridge circuit is turned off by the secondary sampling current. When it is detected that the secondary sampling current is greater than the threshold current, the switch tube in the secondary synchronous rectification full-bridge circuit is turned off.

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