High-precision pulse width generation circuit, method, controller and device

Abstract

The present application discloses a high-precision pulse width generation circuit, method, controller and device, the circuit includes a controller, a pulse width coarse adjustment circuit, a pulse width fine adjustment circuit and a pulse width synthesis module, the controller generates a coarse adjustment pulse width signal of an integer multiple of a system clock cycle through the pulse width coarse adjustment circuit, the pulse width coarse adjustment circuit is connected to the pulse width fine adjustment circuit to input the coarse adjustment pulse width signal, the controller is connected to the pulse width fine adjustment circuit for inputting a fine adjustment control signal, the pulse width fine adjustment circuit adjusts the coarse adjustment pulse width signal by less than one system cycle according to the fine adjustment control signal to generate a pulse width adjustment signal, and the pulse width synthesis module integrates the coarse adjustment pulse width signal and the pulse width adjustment signal to obtain a high-precision pulse width signal and output it. The present application can generate a high-precision pulse width signal and has low cost.

Description

Technical Field

[0001] The present application relates to the field of pulse width modulation, and in particular to a high-precision pulse width generation circuit, method, controller and device. Background Art

[0002] With the rapid development of electronic technology, traditional analog control methods are gradually being replaced by digital control technology. Digital control technology has become the first choice in modern electronic systems due to its stability and ease of implementation. Among the many digital control technologies, pulse width modulation (PWM) is widely used in motor drive, power management, LED lighting and other fields because it can accurately control power output by adjusting the duty cycle of the pulse.

[0003] Although pulse width modulation technology has performed well in many applications, traditional PWM technology has limitations in pulse width resolution and accuracy. There are currently two main ways to generate pulse width. One is the traditional pulse width generated by a counter, which has very low accuracy and can only be used in situations with relatively low requirements; the other is a high-precision pulse width method that controls a specific delay chain. This method has a relatively complex control and calibration algorithm, occupies a large amount of CPU resources, and requires precise adjustment during circuit implementation, which is costly. Summary of the invention

[0004] The present application proposes a high-precision pulse width generation circuit, method, controller and device, which can generate a high-precision pulse width signal with low cost.

[0005] A high-precision pulse width generating circuit according to an embodiment of the first aspect of the present application includes: a controller; a pulse width coarse adjustment circuit, wherein a first output end of the controller is connected to an input end of the pulse width coarse adjustment circuit so as to generate a coarse adjustment pulse width signal of an integer multiple of a system clock cycle through the pulse width coarse adjustment circuit; a pulse width fine adjustment circuit, wherein a first output end of the pulse width coarse adjustment circuit is connected to the pulse width fine adjustment circuit for inputting a coarse adjustment pulse width signal, wherein the controller is connected to the pulse width fine adjustment circuit for inputting a fine adjustment control signal, wherein the pulse width fine adjustment circuit is used to adjust the coarse adjustment pulse width signal by less than one system cycle according to the fine adjustment control signal to generate a pulse width adjustment signal; and a pulse width synthesis module, wherein a second output end of the pulse width coarse adjustment circuit and a first output end of the pulse width fine adjustment circuit are respectively connected to an input end of the pulse width synthesis module, wherein the pulse width synthesis module is used to integrate the coarse adjustment pulse width signal and the pulse width adjustment signal to obtain and output a high-precision pulse width signal.

[0006] According to some embodiments of the present application, a pulse width compensation circuit is further arranged between the pulse width coarse adjustment circuit and the pulse width synthesis module, the second output end of the pulse width coarse adjustment circuit is connected to the input end of the pulse width compensation circuit, and the output end of the pulse width compensation circuit is connected to an input end of the pulse width synthesis module.

[0007] According to the second aspect of the present application, the high-precision pulse width generation method comprises the following steps:

[0008] The controller obtains a system reference clock and a pulse width cycle setting value, and obtains a pulse width coarse adjustment setting value according to the system reference clock and the pulse width cycle setting value;

[0009] The controller inputs the pulse width coarse adjustment setting value to the pulse width coarse adjustment circuit, and the pulse width coarse adjustment circuit generates a coarse adjustment pulse width signal of an integer multiple of the system clock cycle;

[0010] The pulse width coarse adjustment circuit inputs the coarse adjustment pulse width signal into the pulse width fine adjustment circuit, and the controller inputs the fine adjustment control signal into the pulse width fine adjustment circuit. The pulse width fine adjustment circuit adjusts the coarse adjustment pulse width signal by less than one system cycle according to the fine adjustment control signal to generate a pulse width adjustment signal.

[0011] The pulse width coarse adjustment circuit inputs the coarse adjustment pulse width signal into the pulse width synthesis module, and the pulse width fine adjustment circuit inputs the pulse width adjustment signal into the pulse width synthesis module. The pulse width synthesis module integrates the coarse adjustment pulse width signal and the pulse width adjustment signal to obtain a high-precision pulse width signal and outputs it.

[0012] According to some embodiments of the present application, before the controller inputs the fine adjustment control signal into the pulse width fine adjustment circuit, the controller further includes:

[0013] The controller inputs the system reference clock into the pulse width fine adjustment circuit for calibration, and determines whether the pulse width fine adjustment circuit has overflow. If so, the frequency of the system reference clock is increased, and the system reference clock with increased frequency is input into the pulse width fine adjustment circuit for recalibration until it is determined that the pulse width fine adjustment circuit does not have overflow.

[0014] According to some embodiments of the present application, the pulse width fine adjustment circuit includes a plurality of latches connected in series in sequence, the controller inputs a system reference clock into the pulse width fine adjustment circuit for calibration, and in the step of determining whether the pulse width fine adjustment circuit has an overflow, the condition for determining whether the pulse width fine adjustment circuit has an overflow is:

[0015] The controller reads the output of the last-stage latch, and if it is a high level, it is determined that there is an overflow, and if it is a low level, it is determined that there is no overflow.

[0016] According to some embodiments of the present application, the pulse width coarse adjustment circuit inputs the coarse adjustment pulse width signal into the pulse width synthesis module, including:

[0017] The pulse width coarse adjustment circuit first inputs the coarse adjustment pulse width signal into the pulse width compensation circuit for pulse width compensation to obtain a target coarse adjustment pulse width signal, wherein the target coarse adjustment pulse width signal is the coarse adjustment pulse width signal after pulse width compensation;

[0018] Input the target coarse-adjusted pulse width signal into the pulse width synthesis module.

[0019] The pulse width modulation controller according to the third aspect of the present application includes the above-mentioned high-precision pulse width generating circuit.

[0020] An electronic device according to an embodiment of the fourth aspect of the present application includes the above-mentioned pulse width modulation controller.

[0021] The high-precision pulse width generation circuit, method, controller and device according to the embodiments of the present application have at least the following beneficial effects:

[0022] In the embodiment of the present application, the controller first generates a coarse pulse width signal of an integer multiple of the system clock cycle through the pulse width coarse adjustment circuit, and then adjusts the coarse pulse width signal by less than one system cycle according to the fine adjustment control signal through the pulse width fine adjustment circuit to generate a pulse width adjustment signal; finally, the coarse pulse width signal and the pulse width adjustment signal are integrated through the pulse width synthesis module to obtain a high-precision pulse width signal and output it. It can generate a high-precision pulse width signal with low cost and without occupying a large amount of CPU resources.

[0023] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The present application is further described below with reference to the accompanying drawings and embodiments, wherein:

[0025] Figure 1 : is a principle block diagram of a high-precision pulse width generating circuit in an embodiment of the present application;

[0026] Figure 2 1 is a principle block diagram of a high-precision pulse width generating circuit with pulse width compensation in an embodiment of the present application;

[0027] Figure 3 A circuit diagram of a pulse width fine adjustment circuit in an embodiment of the present application;

[0028] Figure 4 is a circuit diagram of a pulse width compensation circuit in an embodiment of the present application;

[0029] Figure 5 : is a circuit diagram of a pulse width synthesis module in an embodiment of the present application;

[0030] Figure 6 Waveform diagram of the pulse width synthesis module in the embodiment of the present application;

[0031] Figure 7 This is a flow chart of a high-precision pulse width generation method in an embodiment of the present application;

[0032] Figure 8 This is a calibration waveform diagram of the pulse width high-precision adjustment circuit in the embodiment of the present application. DETAILED DESCRIPTION

[0033] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0034] In the description of the present application, it should be understood that the descriptions involving orientation, such as the orientation or positional relationship indicated as up, down, etc., are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0035] In the description of this application, "a plurality" means more than two. If there is a description of "first" or "second", it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0036] In the description of this application, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in this application based on the specific content of the technical solution.

[0037] Reference Figure 1 As shown, a high-precision pulse width generating circuit includes: a controller, a pulse width coarse adjustment circuit, a pulse width fine adjustment circuit and a pulse width synthesis module. Specifically, the controller is responsible for interacting with bus information, that is, the controller communicates with a host computer or other devices through the bus, such as receiving a system reference clock sent by a clock circuit, and receiving a reset command or interrupt command sent by the host computer. In addition to bus information interaction, the controller is also responsible for controlling the pulse width coarse adjustment circuit and the pulse width fine adjustment circuit.

[0038] The first output end of the controller is connected to the input end of the pulse width coarse adjustment circuit. The controller generates a control signal of the pulse width coarse adjustment circuit according to the system reference clock, and controls the pulse width coarse adjustment circuit to generate a coarse adjustment pulse width signal of an integer multiple of the system clock cycle; the first output end of the pulse width coarse adjustment circuit is connected to the pulse width fine adjustment circuit, and the coarse adjustment pulse width signal is input to the pulse width fine adjustment circuit. The controller is connected to the pulse width fine adjustment circuit for inputting a fine adjustment control signal. The pulse width fine adjustment circuit adjusts the coarse adjustment pulse width signal by less than one system cycle according to the fine adjustment control signal to generate a pulse width adjustment signal; the second output end of the pulse width coarse adjustment circuit and the first output end of the pulse width fine adjustment circuit are respectively connected to an input end of a pulse width synthesis module. The pulse width synthesis module integrates the coarse adjustment pulse width signal and the pulse width adjustment signal to obtain a high-precision pulse width signal and outputs it.

[0039] In the embodiment of the present application, the controller first generates a coarse pulse width signal of an integer multiple of the system clock cycle through the pulse width coarse adjustment circuit, and then adjusts the coarse pulse width signal by less than one system cycle according to the fine adjustment control signal through the pulse width fine adjustment circuit to generate a pulse width adjustment signal; finally, the coarse pulse width signal and the pulse width adjustment signal are integrated through the pulse width synthesis module to obtain a high-precision pulse width signal and output it. It can generate a high-precision pulse width signal with low cost and without occupying a large amount of CPU resources.

[0040] Specifically, the pulse width coarse adjustment circuit is composed of an n-bit counter. The controller first obtains the system reference clock RefClk through the bus. Assuming that the period of the system reference clock RefClk is T1, the pulse width period setting value is T2, and the pulse width period setting value is the period of the high-level pulse width to be generated is T2, then the coarse adjustment pulse width signal is calculated according to the following formula:

[0041] ;

[0042] Among them, by setting the Counter[n:0] value N2, the coarse adjustment pulse width period generated is:

[0043] ;

[0044] in, f(RefClk) is the frequency of the system reference clock RefClk.

[0045] Specifically, refer to Figure 3As shown, the pulse width fine adjustment circuit in the present application is composed of a multi-level latch. The controller first sets the calibration selection CalSel input of the pulse width fine adjustment circuit to RefClk, and then sets CalSel to select the P2E signal input, wherein P2 is the pulse width coarse adjustment signal output by the pulse width coarse adjustment circuit, which is the P2E signal after being enabled by the control circuit. The pulse width coarse adjustment circuit realizes the input of the pulse width coarse adjustment signal to the pulse width fine adjustment circuit through the Enable signal. The Enable signal is the enable signal for the pulse width coarse adjustment circuit to output the pulse width coarse adjustment signal to the pulse width fine adjustment circuit, and the falling edge is effective. It should be noted that when the pulse width coarse adjustment circuit is completed, a coarse adjustment pulse width signal is output, and the pulse width fine adjustment circuit is enabled at the falling edge of the output coarse adjustment pulse width signal, and the coarse adjustment pulse width signal is input to the pulse width fine adjustment circuit. If the pulse width coarse adjustment circuit does not complete the output of the coarse adjustment pulse width signal, the pulse width fine adjustment circuit will be closed and will only be enabled at the falling edge of the coarse adjustment pulse width.

[0046] It should be noted that the controller obtains the fine-tuning control signal through calculation. The fine-tuning control signal is the Sel value of the pulse width fine-tuning circuit. The Sel value is the number of latch outputs that the pulse width fine-tuning circuit needs to select and adjust. The number of latch outputs that the pulse width fine-tuning circuit needs to select and adjust is:

[0047] ;

[0048] Wherein, Tpd is the delay of a single latch in the pulse width fine-tuning circuit.

[0049] According to some embodiments of the present application, reference Figure 2 As shown, a pulse width compensation circuit is also arranged between the pulse width coarse adjustment circuit and the pulse width synthesis module. The second output end of the pulse width coarse adjustment circuit is connected to the input end of the pulse width compensation circuit, and the output end of the pulse width compensation circuit is connected to an input end of the pulse width synthesis module.

[0050] In this embodiment, by providing a pulse width compensation circuit between the pulse width coarse adjustment circuit and the pulse width synthesis module, the coarse adjustment pulse width signal and the pulse width adjustment signal can be integrated without generating glitches, thereby further improving the accuracy of the high-precision pulse width signal.

[0051] refer to Figure 4 As shown, P1 is the coarse-adjusted pulse width signal, and P3 is the target coarse-adjusted pulse width signal after compensation. Since the pulse width coarse-adjusted circuit enables the pulse width fine-adjusted circuit and inputs the coarse-adjusted pulse width signal to the pulse width fine-adjusted circuit, which will cause a delay in the pulse width signal, a pulse width compensation circuit is added between the pulse width coarse-adjusted circuit and the pulse width synthesis module in the present application, so that the coarse-adjusted pulse width signal and the pulse width adjustment signal do not generate glitches when the pulse width is integrated.

[0052] refer to Figure 5 and Figure 6As shown, assuming that the target coarse-adjusted pulse width signal output by the pulse width compensation circuit is P3, and the pulse width adjustment signal output by the pulse width fine adjustment circuit is P4, the pulse width synthesis module integrates the output P3 of the pulse width compensation circuit with the output P4 of the high-precision pulse width adjustment circuit to generate a high-precision pulse width signal P5. After integration by the pulse width synthesis module, the output pulse signal accuracy can reach 50~100ps.

[0053] refer to Figure 7 As shown, the present application also relates to a high-precision pulse width generation method, comprising the following steps:

[0054] S101, the controller obtains a system reference clock and a pulse width cycle setting value, and obtains a pulse width coarse adjustment setting value according to the system reference clock and the pulse width cycle setting value;

[0055] S102, the controller inputs the pulse width coarse adjustment setting value to the pulse width coarse adjustment circuit, and the pulse width coarse adjustment circuit generates a coarse adjustment pulse width signal of an integer multiple of the system clock cycle;

[0056] S103, the pulse width coarse adjustment circuit inputs the coarse adjustment pulse width signal into the pulse width fine adjustment circuit, the controller inputs the fine adjustment control signal into the pulse width fine adjustment circuit, and the pulse width fine adjustment circuit adjusts the coarse adjustment pulse width signal by less than one system cycle according to the fine adjustment control signal to generate a pulse width adjustment signal;

[0057] S104, the pulse width coarse adjustment circuit inputs the coarse adjustment pulse width signal into the pulse width synthesis module, the pulse width fine adjustment circuit inputs the pulse width adjustment signal into the pulse width synthesis module, and the pulse width synthesis module integrates the coarse adjustment pulse width signal and the pulse width adjustment signal to obtain a high-precision pulse width signal and outputs it.

[0058] In this embodiment, the controller first obtains the system reference clock and the pulse width cycle setting value, obtains the pulse width coarse adjustment setting value according to the system reference clock and the pulse width cycle setting value, and then the controller inputs the pulse width coarse adjustment setting value to the pulse width coarse adjustment circuit, generates a coarse adjustment pulse width signal of an integer multiple of the system clock cycle through the pulse width coarse adjustment circuit, and then the pulse width coarse adjustment circuit inputs the coarse adjustment pulse width signal into the pulse width fine adjustment circuit, the controller inputs the fine adjustment control signal into the pulse width fine adjustment circuit, the pulse width fine adjustment circuit adjusts the coarse adjustment pulse width signal by less than one system cycle according to the fine adjustment control signal, and generates a pulse width adjustment signal, and finally the pulse width coarse adjustment circuit inputs the coarse adjustment pulse width signal into the pulse width synthesis module, the pulse width fine adjustment circuit inputs the pulse width adjustment signal into the pulse width synthesis module, and the pulse width synthesis module integrates the coarse adjustment pulse width signal and the pulse width adjustment signal to obtain a high-precision pulse width signal and outputs it. It can generate a high-precision pulse width signal, with low cost and without occupying a large amount of CPU resources.

[0059] The working principle of the above-mentioned high-precision pulse width generating method is the same as that of the high-precision pulse width generating circuit, and will not be described in detail here.

[0060] In some embodiments of the present application, before the controller inputs the fine adjustment control signal into the pulse width fine adjustment circuit, the controller further includes:

[0061] The controller inputs the system reference clock into the pulse width fine adjustment circuit for calibration, and determines whether the pulse width fine adjustment circuit has overflow. If so, the frequency of the system reference clock is increased, and the system reference clock with increased frequency is input into the pulse width fine adjustment circuit for recalibration until it is determined that the pulse width fine adjustment circuit has no overflow.

[0062] In this implementation, the controller inputs the system reference clock into the pulse width fine adjustment circuit for calibration, which can avoid overflow of the pulse width fine adjustment circuit and further improve the accuracy of the pulse width signal output.

[0063] The controller determines whether the pulse width fine adjustment circuit has overflow conditions as follows:

[0064] The controller reads the output of the last-stage latch, and if it is a high level, it is determined that there is an overflow, and if it is a low level, it is determined that there is no overflow.

[0065] refer to Figure 3 and Figure 8 The following is a specific example to illustrate the process of the controller calibrating the pulse width fine adjustment circuit and controlling the output, as follows:

[0066] S201, the controller sets the calibration selection CalSel input of the pulse width fine adjustment circuit to RefClk, and starts the calibration function;

[0067] S202, the controller reads the output of the last latch of the pulse width fine adjustment circuit, if it is a high level, it is determined that there is overflow, and returns to step S201, increases the frequency of RefClk, and re-calibrates, if it is a low level, it is determined that there is no overflow, and proceeds to the next step;

[0068] S203, record T / 2 latch [N], record each level latch output value Q [n] in the pulse width fine adjustment circuit, where the latch Q terminal output value is 1. It should be noted that the output Q [N: 0] indicates a valid latch, that is, the output value of the valid latch is latch [N: 0];

[0069] S204, set Sel[N:0] to 1, output Q[N:0] to QS[N:0] to enter the OR gate, QS[n:N] is 0; Sel[n:0] is the control signal of the mux selector in the pulse width fine-tuning circuit, and selects the pulse width adjustment signal to be output to the pulse width synthesis circuit.

[0070] In some embodiments of the present application, the pulse width coarse adjustment circuit inputs the coarse adjustment pulse width signal into the pulse width synthesis module, which may include:

[0071] The pulse width coarse adjustment circuit first inputs the coarse adjustment pulse width signal into the pulse width compensation circuit for pulse width compensation to obtain a target coarse adjustment pulse width signal, where the target coarse adjustment pulse width signal is the coarse adjustment pulse width signal after pulse width compensation;

[0072] Input the target coarse-adjusted pulse width signal into the pulse width synthesis module.

[0073] In this embodiment, the coarse adjustment pulse width signal is compensated by the pulse width compensation circuit and then input into the pulse width synthesis module, so that the coarse adjustment pulse width signal and the pulse width adjustment signal do not generate burrs when the pulse width is integrated, further improving the accuracy of the high-precision pulse width signal.

[0074] The present application also relates to a pulse width modulation controller, comprising the high-precision pulse width generating circuit of the above embodiment.

[0075] The present application also relates to an electronic device, comprising the pulse width modulation controller of the above embodiment.

[0076] The embodiments of the present application are described in detail above in conjunction with the accompanying drawings, but the present application is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present application.

Claims

1. A high-precision pulse width generating circuit, characterized in that: include: Controller; A pulse width coarse modulation circuit, wherein the first output terminal of the controller is connected to the input terminal of the pulse width coarse modulation circuit so as to generate a coarse modulation pulse width signal of an integer multiple of a system clock cycle through the pulse width coarse modulation circuit; A pulse width fine adjustment circuit, wherein the first output end of the pulse width coarse adjustment circuit is connected to the pulse width fine adjustment circuit for inputting the coarse adjustment pulse width signal, the controller is connected to the pulse width fine adjustment circuit for inputting the fine adjustment control signal, and the pulse width fine adjustment circuit is used to adjust the coarse adjustment pulse width signal by less than one system cycle according to the fine adjustment control signal to generate a pulse width adjustment signal; A pulse width synthesis module, wherein the second output end of the pulse width coarse adjustment circuit and the first output end of the pulse width fine adjustment circuit are respectively connected to an input end of the pulse width synthesis module, and the pulse width synthesis module is used to integrate the coarse adjustment pulse width signal and the pulse width adjustment signal to obtain a high-precision pulse width signal and output it; The high-precision pulse width generating circuit outputs a high-precision pulse width signal through a high-precision pulse width generating method, and the high-precision pulse width generating method comprises the following steps: The controller obtains a system reference clock and a pulse width cycle setting value, and obtains a pulse width coarse adjustment setting value according to the system reference clock and the pulse width cycle setting value; The controller inputs the pulse width coarse adjustment setting value to the pulse width coarse adjustment circuit, and the pulse width coarse adjustment circuit generates a coarse adjustment pulse width signal of an integer multiple of the system clock cycle; The pulse width coarse adjustment circuit inputs the coarse adjustment pulse width signal into the pulse width fine adjustment circuit, and the controller inputs the fine adjustment control signal into the pulse width fine adjustment circuit. The pulse width fine adjustment circuit adjusts the coarse adjustment pulse width signal by less than one system cycle according to the fine adjustment control signal to generate a pulse width adjustment signal. The pulse width coarse adjustment circuit inputs the coarse adjustment pulse width signal into the pulse width synthesis module, and the pulse width fine adjustment circuit inputs the pulse width adjustment signal into the pulse width synthesis module. The pulse width synthesis module integrates the coarse adjustment pulse width signal and the pulse width adjustment signal to obtain a high-precision pulse width signal and outputs it. Before the controller inputs the fine adjustment control signal into the pulse width fine adjustment circuit, the controller further includes: The controller inputs the system reference clock into the pulse width fine adjustment circuit for calibration, and determines whether the pulse width fine adjustment circuit has overflow. If overflow occurs, the frequency of the system reference clock is increased, and the system reference clock with increased frequency is input into the pulse width fine adjustment circuit for recalibration, until it is determined that the pulse width fine adjustment circuit has no overflow. The pulse width fine adjustment circuit includes a plurality of latches connected in series in sequence. The controller inputs a system reference clock into the pulse width fine adjustment circuit for calibration. In the step of determining whether the pulse width fine adjustment circuit has overflow, the condition for determining whether the pulse width fine adjustment circuit has overflow is: The controller reads the output of the last-stage latch, and if it is a high level, it is determined that there is an overflow, and if it is a low level, it is determined that there is no overflow.

2. The high-precision pulse width generating circuit according to claim 1, characterized in that: A pulse width compensation circuit is also provided between the pulse width coarse adjustment circuit and the pulse width synthesis module. The second output end of the pulse width coarse adjustment circuit is connected to the input end of the pulse width compensation circuit. The output end of the pulse width compensation circuit is connected to an input end of the pulse width synthesis module.

3. A pulse width modulation controller, characterized in that: A high-precision pulse width generating circuit comprising any one of claims 1 to 2.

4. An electronic device, characterized in that: Includes the pulse width modulation controller as described in claim 3.

Images