Low-offset subsampling phase detector and phase detection method

Abstract

The invention discloses a low-offset sub-sampling phase detector and a phase detection method. A phase detection method includes receiving a reference clock and an input clock including a first input signal and a second input signal; sampling a first input signal and a second input signal according to the reference clock to obtain a first sample and a second sample; converting the first sample and the second sample into a first current and a second current; converting the first current into a third current by using a voltage-stabilizing current mirror; using the first current guiding network to guide the second current to the fourth current or the fifth current according to a pulse signal; using a second current guiding network to guide a third current to a sixth current or a seventh current according to the pulse signal; connecting a low-pass filter to the output node to establish an output voltage and a low-pass filtered voltage; and using a unity gain buffer to equalize the standby voltage to the low-pass filtered voltage.

Description

Technical Field

[0001] The present disclosure relates to a phase detector, and more particularly to a sub-sampling phase detector with low offset and a phase detection method. Background Art

[0002] Those skilled in the art may understand the terms and basic concepts related to microelectronics used in the present disclosure, such as “voltage”, “current”, “signal”, “differential”, “logic signal”, “switch”, “clock”, “frequency”, “capacitor”, “low-pass filter”, “resistor”, “metal oxide semiconductor transistor”, “p-type metal oxide semiconductor transistor (p-channel metal oxide semiconductor transistor)”, “n-type metal oxide semiconductor transistor (n-channel metal oxide semiconductor transistor)”, “AC (alternating current)”, “DC (direct current)”, “DC coupling”, “AC coupling”, “source”, “gate”, “drain”, “node”, “ground node”, “power supply node”, “current mirror”, “current source”, “current sink”, “operational amplifier” and “common source amplifier”. Such terms and basic concepts are obvious to those skilled in the art, so their details are not repeated here.

[0003] A person skilled in the art can recognize symbols for resistors, capacitors, inductors, and metal oxide semiconductor transistors for P-type metal oxide semiconductor transistors (p-channel metal oxide semiconductor transistors) and N-type metal oxide semiconductor transistors (n-channel metal oxide semiconductor transistors). They can also recognize the "source terminal", "gate terminal", and "drain terminal" of metal oxide semiconductor transistors. For the sake of brevity, in the following description of metal oxide semiconductor transistors, the "source terminal" will be referred to as the "source", the "gate terminal" will be referred to as the "gate", and the "drain terminal" will be referred to as the "drain".

[0004] Those skilled in the art will appreciate that a circuit diagram includes resistors, capacitors, inductors, N-type metal oxide semiconductor transistors and P-type metal oxide semiconductor transistors, and there is no need to explain in detail how transistors, resistors, inductors or capacitors are connected to each other in the circuit diagram.

[0005] A DC (direct current) node is a circuit node with a substantially fixed potential. Throughout this disclosure, a ground node is referred to as “V SS ”, and the power node is represented by “V DD " indicates grounding "V SS ”Node and power supply “V DD ” All nodes are DC nodes.

[0006] A signal may be a voltage with a variable level, which may carry specific information and may change over time. The level of the signal at a particular moment represents the state of the signal at that particular moment.

[0007] A logic signal is a voltage signal with two logic states: low level and high level; when the voltage level of the logic signal is higher than a trigger point, the logic signal is at a high level, otherwise it is at a low level. The low level is also called the "0" state, and the high level is also called the "1" state. Regarding the logic signal Q, such as "Q is high" or "Q is low" means "Q is at a high level" or "Q is at a low level". Similarly, "Q is 1" or "Q is 0" means "Q is in the 1 state" or "Q is in the 0 state".

[0008] The trigger point of the first logic signal may not be the same as that of the second logic signal.

[0009] If the first logic signal and the second logic signal are always in opposite states, the first logic signal is called the inverted logic of the second logic signal. That is, when the first logic signal is low (high), the second logic signal is high (low). When the first logic signal is the inverted logic of the second logic signal, it means that the first logic signal is complementary to the second logic signal.

[0010] A logic signal can be used to control a function to enable or disable the function. When the logic signal is in the state of enabling the function, the logic signal is called "asserted"; otherwise, the logic signal is called "de-asserted".

[0011] A switch is a device with two possible states, the two states being "on" or "off". When the switch is in the "on" state it represents a nearly short circuit, and when the switch is in the "off" state it represents a nearly open circuit. A switch can be implemented using an NMOS transistor or a PMOS transistor. When a MOS transistor (whether an NMOS transistor or a PMOS transistor) is used to implement a switch, it is controlled by a control signal, which is a logic signal applied to the gate of the MOS transistor. When the control signal is high, the switch implemented with the NMOS transistor is in the "on" state, and when the control signal is low, the switch implemented with the NMOS transistor is in the "off" state. When the control signal is low, the switch implemented with the PMOS transistor is in the "on" state, and when the control signal is high, the switch implemented with the PMOS transistor is in the "off" state. In any state, when the control signal of the switch is valid (invalid), the switch is in the "on" ("off") state.

[0012] A clock is a logic signal that switches back and forth between low and high levels periodically. The phase of a clock represents the time point when the clock transitions from low to high or from high to low.

[0013] The phase detector receives a reference clock and an input clock, detects the phase difference between the reference clock and the input clock, and outputs a charge to the subsequent circuit according to the phase difference. Ideally, the charge is proportional to the phase difference, and when the phase difference is zero, the charge is zero. However, in practical applications, due to imperfections in implementation, when the phase difference is zero, the charge is usually not zero. When the phase difference is equal to a non-zero value called the offset of the phase detector, the charge is zero.

[0014] A sub-sampling phase detector is a type of phase detector in which the frequency of the input clock is an integer multiple of the frequency of the reference clock, and the phase difference between the reference clock and the input clock is detected by sampling the input clock using the reference clock for detection. A conventional sub-sampling phase detector includes: a sampling circuit for generating a voltage sample of the input clock using the reference clock; a charge pump that operates in a pulsed manner and is used to convert the voltage sample into a net charge; and a load for receiving the charge and establishing an output voltage accordingly. In an embodiment of a differential signal, the input clock includes a first voltage V i+ and the second voltage V i- , which can be mathematically modeled by the following two equations:

[0015] V i+ =V i0 +A i sin(2πf i t+θ) (1)

[0016] V i- =V i0 -A i sin(2πf i t+θ) (2)

[0017] As shown above, V i0 , A i 、f i and θ represent the DC (direct current) potential, AC (alternating current) amplitude, frequency, and phase of the input clock, respectively, and t represents a time variable.

[0018] The reference clock voltage is V r , which can be mathematically modeled by the following equation:

[0019] V r =V r0 +A r sign[sin(2πf r t)] (3)

[0020] As shown above, V r0 , A r , f r and θ represent the DC (direct current) potential, AC (alternating current) amplitude, frequency and phase of the input clock, respectively, while t represents the time variable, and sign[·] represents a sign function, which is 1 if its argument is positive or zero, and -1 if its argument is negative. In addition, f r With f i The following relationship exists:

[0021] f i =N·f r (4)

[0022] As shown above, N is the clock multiplication factor, which is an integer greater than 1.

[0023] V i+ and V i- Sampling occurs at the edge of the reference clock, such as the rising edge, when t is equal to 0, 1 / f r , 2 / f r , 3 / f r At the same time point, two voltage samples V s+ and V s- is obtained by sampling, where:

[0024] V s+ =V i0 +A i sin(θ) (5)

[0025] V s- =V i0 -A i sin(θ) (6)

[0026] Sub-sampling phase detectors are usually used in phase-locked loops. In the steady state, θ is very small, and the above formulas (5) and (6) can be rewritten as:

[0027] V s+ ≈V i0 +A i θ (7)

[0028] V s- ≈V i0 -A i θ (8)

[0029] The current pump includes a current source and a current sink. The current source is based on V s+ -V s- To output the first current I p to the load, the current sink is based on V s+ -Vs- To output the second current I n to load, where:

[0030] I p =I p0 +G p (V s+ -V s- )≈I p0 +2G p A i θ (9)

[0031] I n =-I n0 -G n (V s+ -V s- )≈-I n0 -2G n A i θ (10)

[0032] As shown above, G p is the voltage-to-current conversion ratio of the current source, I p0 is the constant current provided by the current source, G n is the voltage-to-current conversion ratio of the current sink, I n0 is the constant current provided by the current sink. Note that the current sink outputs a negative current because it draws current from the output. Therefore, the second current I n The value of is negative. The current pump is pulsed and turned on for a time interval τ; the load receives a net charge Q net for:

[0033] Q net =(I p +I n )τ≈(I p0 -I n0 )τ+2(G p -G n )A i θτ

[0034] If I p0 Equal to I n0 , when θ (i.e., the phase difference between the input clock and the reference clock) is zero, the net charge Q net will be zero. However, in practical applications, the current source and the current sink must be implemented by different devices; for example, in an embodiment using CMOS (complementary metal oxide semiconductor) process technology, the current source is implemented by a PMOS transistor, and the current sink is implemented by an NMOS transistor. Usually, due to the mismatch between the NMOS transistor and the PMOS transistor, commonly known as "PN mismatch", I p0 will not be equal to In0 ; In this case, even if the phase difference is zero, the net charge Q net will not be zero. Therefore, PN mismatch will cause an offset in the sub-sampling phase detector.

[0035] Sub-sampling phase detectors are often used in phase-locked loops to control an input clock so that its phase is aligned with that of a reference clock. Drift in the sub-sampling phase detector is often undesirable because it forces the phase-locked loop to a state where the phase difference between the input clock and the phase clock is not zero, but equal to the offset; this results in the sub-sampling phase detector's available detection range being reduced by the amount of the offset. This is particularly troublesome for applications where the input clock frequency is high (e.g., 8 GHz), where even seemingly small drifts (e.g., 20 ps) are significant relative to the period of the input clock (e.g., 125 ps).

[0036] Therefore, there is a need in the art for a sub-sampling phase detector with low offset. Summary of the invention

[0037] One of the objectives of the present disclosure is to reduce the offset of a sub-sampling phase detector.

[0038] Another object of the present disclosure is to allow a sub-sampling phase detector to have a smaller offset and maintain nearly the same DC state despite the output being generated in a pulsed manner.

[0039] Another object of the present disclosure is to allow a sub-sampling phase detector to have an adjustable gain.

[0040] In one embodiment, the sub-sampling phase detector includes: a pulse generator for receiving a reference clock and generating a pulse signal synchronized with the reference clock; a sampling network for sampling an input clock including a first input voltage and a second input voltage according to the reference clock to obtain a first sample and a second sample stored in a first capacitor and a second capacitor respectively; a V2I (voltage-to-current converter) for converting the first sample and the second sample into a first current and a second current according to a bias voltage; a regulated current mirror for mirroring the first current into a third current according to a standby voltage on a standby node in a closed loop manner; flow; a first current steering network, used to guide the second current to a fourth current flowing to a standby node or a fifth current flowing to an output node according to the pulse signal; a second current steering network, used to guide the third current to a sixth current flowing to the standby node or a seventh current flowing to the output node according to the pulse signal; a load, connected to the output node, including a low-pass filter, and used to respond to a sum of the fifth current and the seventh current to establish an output voltage at the output node, wherein a low-pass filter voltage is an output of the low-pass filter; and a unit gain buffer, used to receive the low-pass filter voltage and establish the standby voltage.

[0041] In one embodiment, a phase detection method includes: receiving a reference clock and an input clock, wherein the input clock includes a first input signal and a second input signal; sampling the first input signal and the second input signal according to the reference clock to obtain a first sample and a second sample stored in a first capacitor and a second capacitor respectively; using a voltage-to-current converter to convert the first sample and the second sample into a first current and a second current; using a voltage-stabilized current mirror to adopt a closed-loop method to convert the first current into a third current according to a standby voltage on a standby node; using a first current steering network to guide the second current to a fourth current flowing to the standby node or a fifth current flowing to an output node according to a pulse signal synchronized with the reference clock; using a second current steering network to guide the third current to a sixth current flowing to the standby node or a seventh current flowing to the output node according to the pulse signal; connecting a low-pass filter to the output node to establish an output voltage and a low-pass filter voltage; and using a unity gain buffer to make the standby voltage equal to the low-pass filter voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A schematic diagram of a sub-sampling phase detector according to an embodiment of the present disclosure;

[0043] Figure 2AA method for use in accordance with an embodiment of the present disclosure is shown in FIG. Figure 1 A schematic diagram of a pulse generator of a sub-sampling phase detector;

[0044] Figure 2B A method according to an embodiment of the present disclosure is shown in FIG. Figure 2A A timing diagram of a pulse generator;

[0045] Figure 2C A method for use in accordance with an embodiment of the present disclosure is shown in FIG. Figure 2A A schematic diagram of a delay buffer with a programmable delay for a pulse generator; and

[0046] Figure 3 The present invention is a flowchart of a phase detection method according to some embodiments of the present disclosure.

[0047] Explanation of symbols

[0048] 100: Sub-sampling phase detector

[0049] 110: Pulse generator

[0050] 120: Sampling Network

[0051] 130: V2I (voltage to current converter)

[0052] 131: First NMOS transistor

[0053] 132: Second NMOS transistor

[0054] 133: The third NMOS transistor

[0055] 140: Regulated current mirror

[0056] 141: First PMOS transistor

[0057] 142: Second PMOS transistor

[0058] 160: Load

[0059] 200: Pulse generator

[0060] 210: Delay Buffer

[0061] 211: Delay Line

[0062] 211_0, 211_1, 211_2, 211_3, 211_4: Inverting buffer 212: Multiplexer (MUX)

[0063] 220: First inverter

[0064] 230: AND gate

[0065] 240: Second inverter

[0066] 300: Methods

[0067] 310~380: Steps

[0068] C1: First capacitor

[0069] C2: Second capacitor

[0070] CS: Load capacitance

[0071] CM1: Current mirror

[0072] CS1: Current Sink

[0073] CSN1: First Current Steering Network

[0074] CSN2: Second Current Steering Network

[0075] DCSA1: Differential Common Source Amplifier

[0076] DS1: First virtual switch

[0077] DS2: Second virtual switch

[0078] I1: First current

[0079] I2: Second current

[0080] I3: The third current

[0081] I4: Fourth current

[0082] I5: Fifth current

[0083] I6: Sixth current

[0084] I7: Seventh current

[0085] I8: Eighth Current

[0086] I9: Ninth Current

[0087] I out : Output current

[0088] I bias : Bias current

[0089] NOP: Output Node

[0090] NSB: Standby Node

[0091] NMW: Middle Node

[0092] OP1: first operational amplifier OP2: second operational amplifier PE: pulse signal

[0093] PD: Pulse signal

[0094] RS: Series resistance

[0095] SS1: First sampling switch SS2: Second sampling switch SW1: First switch

[0096] SW2: Second switch

[0097] SW3: The third switch

[0098] SW4: Fourth switch UGB1: Unity gain buffer V i1 : The first input signal V i2 : The second input signal V s1 : The first sampling V s2 : The second sampling V sb : Standby voltage V g : Gate voltage V mw : Intermediate voltage V bias : Bias voltage V R : Reference clock V out : Output voltage V lpf : Low pass filter voltage V DD : Power supply node V SS : Ground node V RD : Delay clock V RI : Inverted clock

[0099] V RD0 、V RD1 , V RD2 、V RD3 、V RD4 : Delay clock

[0100] τ: delay DETAILED DESCRIPTION

[0101] The present disclosure relates to a sub-sampling phase detector. Although the specification describes multiple embodiments of the present disclosure, and these embodiments are considered to be preferred modes for implementing the present disclosure, it should be understood that the present disclosure can be implemented in many ways and is not limited to the specific examples described below or the specific ways of implementing any features of these examples. In other cases, well-known details are not shown or described to avoid obscuring the key points of the present disclosure.

[0102] In this disclosure, "DC" stands for direct current, and "AC" stands for alternating current. A DC voltage is a voltage that remains essentially constant. An AC voltage is a voltage that changes over time in an oscillating manner, also known as a dynamic voltage. Generally speaking, a signal contains a DC component, which remains essentially constant and fixed over the time period of interest, and an AC component, which is dynamic and changes over time over the time period of interest.

[0103] A DC node is a node with a substantially fixed voltage. In this disclosure, “V DD ” represents the first DC node, also known as the power node, and “V SS ” represents the second DC node, also known as the ground node.

[0104] A circuit is a collection of transistors, capacitors, inductors, resistors, and / or other electronic devices that are interconnected in some way to achieve a certain function. A network is a circuit or a collection of circuits to achieve a certain function.

[0105] In the present disclosure, if the meaning of a “circuit node” is clear and unambiguous to people in the field of microelectronics from the context and will not cause confusion, the “circuit node” will be simply referred to as a “node”.

[0106] like Figure 1 As shown in the schematic diagram, in one embodiment of the present disclosure, the sub-sampling phase detector 100 includes: a pulse generator 110 for receiving a reference clock V R and outputting a pulse signal, which includes a first logic signal PD (representing pulse-disable) and a second logic signal PE (representing pulse-enable) which is inverted from the first logic signal PD; the sampling network 120 is used to generate a pulse signal according to the reference clock V R The first input signal V i1 And the second input signal V i2 Sampling is the first sampling V s1 And the second sample V s2 , where in the differential signal embodiment, the first input signal V i1 And the second input signal V i2 The V2I (voltage to current converter) 130 is used to convert the bias voltage V bias The first sample V s1 And the second sample V s2 The voltage-stabilizing current mirror 140 is used to adopt a closed loop method to convert the standby voltage V on the standby node NSB into a first current I1 and a second current I2. sbThe first current I1 is mirrored into a third current I3; the first current guiding network CSN1 is used to guide the second current I2 to a fourth current I4 flowing to the standby node NSB or a fifth current I5 flowing to the output node NOP according to the pulse signal (PE and PD); the second current guiding network CSN2 is used to guide the third current I3 to a sixth current I6 flowing to the standby node NSB or a seventh current I7 flowing to the output node NOP according to the pulse signal (PE and PD); the load 160 is connected to the output node NOP, which includes a low-pass filter and is used to receive the output current I out , which is the sum of the fifth current I5 and the seventh current I7 outputted by the output node NOP, and accordingly establishes the output voltage V out And the low-pass filter voltage V lpf ; and a unit gain buffer UGB1 for receiving a low pass filter voltage V lpf And the standby voltage V of the output standby node NSB sb .

[0107] In terms of function: sampling network 120 represents a phase detector, which generates V s1 and V s2 To represent the input clock (in V i1 and V i2 implementation) and the reference clock V R The phase difference between s1 and V s2 The larger the difference between the reference clock V R The larger the phase difference between the input clock and the input clock, the greater the phase difference between the input clock and the input clock. V2I 130, the voltage regulator current mirror 140 and the two current guide networks CSN1 and CSN2 jointly implement a charge pump, which converts V s1 and V s2 Convert to I out The pulse signals (PE and PD) are generated by the pulse generator 110 and are connected to the reference clock V R and a unit gain buffer UGB1 to ensure that the charge pump can maintain a stable DC (direct current) state, so that even if the charge pump operates in a pulse mode, the DC potential of the standby node NSB and the output node NOP remains the same.

[0108] The sampling network 120 includes a first sampling switch SS1 for sampling a voltage according to V R V i1 The sample is stored in the first capacitor C1. s1 ; and the second sampling switch SS2 is used according to V R V i2 The sample is stored in the second capacitor C2. s2 .

[0109] Figure 2A FIG. 2 is a schematic diagram of a pulse generator 200 that can be used to implement the pulse generator 110 according to an embodiment of the present disclosure. The pulse generator 200 includes a delay buffer 210 for receiving a reference clock V R And the output delay clock V RD The first inverter 220 is used to receive the reference clock V R And output inverted clock V RI AND gate 230 is used to receive the delayed clock V RD And the inverted clock V RI and outputs a second logic signal PE; and the second inverter 240 is used to receive the second logic signal PE and output a first logic signal PD, which is the logic inversion of PE. Figure 2B FIG. 2 shows an exemplary timing diagram of the pulse generator 200. As shown in the figure, V RD V R The timing delay state is delayed by τ; V RI V R The logic inversion of PE is V RD and V RI The AND operation (AND operation) of PD is the result of the AND operation; and PD is the logical inversion of PE. AND gates and inverters are well known to those skilled in the art, so they are not described in detail. The delay τ determines the effective period of PE, and therefore determines the output current I out The delay buffer 210 can be implemented by a delay line of inverters, which includes a series connection of an even number of inverters, wherein the number of series connection stages determines the delay: the more series connection stages, the greater the delay. In a further embodiment, the delay of the delay buffer 210 is programmable and is controlled by a control code C DL The present disclosure illustratively shows, but is not limited to, an embodiment of the delay buffer 210 with programmable delay as shown in Figure 2C As shown in the figure, the delay buffer 210 includes a delay line 211, which includes five two-stage inverting buffers 211_0, 211_1, 211_2, 211_3 and 211_4 connected in series, which are used to receive V R And output five delayed clocks V RD0 、V RD1 、V RD2 、V RD3 and V RD4 , and a multiplexer (MUX) 212 for controlling the control code C DL Select V RD0 、V RD1 、V RD2 、V RD3and V RD4 One of them is used as the output V RD , control code C DL is an integer not less than 0 and not greater than 4. DL is 0 (1, 2, 3, 4), V RD0 (V RD1 、V RD2 、V RD3 and V RD4 ) is selected as V RD The principles of the inverter, the multiplexer and the delay buffer 210 are well known to those skilled in the art and are not described in detail. When the delay of the delay buffer 210 is programmable, the pulse width of the pulse signal (PE and PD) is programmable, and the output current I out The effective period is programmable, so if Figure 2C The delay buffer 210 is used in the pulse generator 110, and the gain of the sub-sampling phase detector 100 is programmable.

[0110] V2I 130 includes a differential common source amplifier DCSA1, which includes a first NMOS transistor 131 and a second NMOS transistor 132, and is respectively used to bias Receive V s1 and V s2 And output I1 and I2, bias current I bias The current sink CS1 is provided by the third NMOS transistor 133 and is connected to V bias control. It should be noted that although Figure 1 It seems to show I bias flows from CS1 to DCSA1, but I bias The direction is shown in a logical manner only for the purpose of functional description to illustrate that after CS1 is activated, the I bias The generation of DCSA1 then receives I bias , and react accordingly. The actual physical current flows in the opposite direction, that is, the bias current I bias Flows from DCSA1 to CS1, because CS1 is a current sink, it will attract the current to flow in. In other words, I bias The same situation also occurs in I1 and I2, which will not be described in detail here.

[0111] The first current steering network CSN1 includes: a first switch SW1, which is controlled by PD and used to guide I2 to I4 flowing to the standby node NSB when PD is valid; and a second switch SW2, which is controlled by PE and used to guide I2 to I5 flowing to the output node NOP when PE is valid. The second current steering network CSN2 includes a third switch SW3, which is controlled by PD and used to guide I3 to I6 flowing to the standby node NSB when PD is valid; and a fourth switch SW4, which is controlled by PE and used to guide I3 to I7 flowing to the output node NOP when PE is valid.

[0112] The load 160 is connected to the output node NOP, and the load 160 includes a series resistor RS and a load capacitor CS connected in series, which form a low-pass filter. lpf Stored in the load capacitor CS, which is V out The low-pass filtered output has a out The same DC value. The principle that the low-pass filter and the series resistor RS and the load CS constitute the low-pass filter is well known to those skilled in the art, and thus will not be described in detail.

[0113] The unity gain buffer UGB1 includes a first operational amplifier OP1 configured in a unity gain architecture, wherein the positive input terminal “+” is coupled to V lpf , and the negative input terminal "-" is coupled to V sb , which is the output of OP1. Due to the unity gain buffer UGB1, regardless of the state of the pulse signal (PD and PE) and the switching conditions of the first current steering network CSN1 and the second current steering network CSN2, V sb and V out have the same DC value (because V out and V lpf have the same DC value and UGB1 forces V sb Same as V lpf ).

[0114] The voltage-stabilized current mirror 140 includes: a first virtual switch DS1 for guiding the first current I1 to an eighth current I8 flowing to the middle node NMW; a second virtual switch DS2 for guiding the eighth current I8 to a ninth current I9; a current mirror CM1 including a first PMOS transistor 141 and a second PMOS transistor 142 for mirroring the ninth current I9 to a third current I3; and a second operational amplifier OP2 for outputting a gate voltage V g According to the intermediate voltage V of the intermediate node NMW mw The standby voltage V sbThe voltage difference between them is used to control the current mirror CM1. The first virtual switch DS1 is used to simulate SW1 and SW2. It should be noted that between SW1 and SW2, at a given time point, one of them is turned on and the other is turned off, depending on the state of the pulse signal (PE and PD). On the other hand, DS1 is always turned on (such as Figure 1 Similarly, the second virtual switch DS2 is used to simulate SW3 and SW4 and is always turned on. The second operational amplifier OP2 and the first PMOS transistor 141 form a negative feedback loop to adjust the gate voltage V in a closed loop. g To force V mw Same as V sb Therefore, the intermediate voltage V mw , the standby voltage V of the standby node NSB sb And the output voltage V of the output node NOP out All have the same DC potential. Thus, at a given time point, the first current I1 and the second current I2 have the same conduction state under DC conditions. Similarly, the ninth current I9 and the third current I3 have the same conduction state. In the current mirror CM1, the first PMOS transistor 141 and the second PMOS transistor 142 are the same. Since the PMOS transistor 141 and the PMOS transistor 142 have the same source voltage (“V DD ”), the same gate voltage (V g ) and the same drain voltage (V mw Add the voltage drop of DS2, V sb plus the voltage drop of SW3 or V out Adding the voltage drop of SW4), they must have the same drain current. Therefore, the current mirror CM1 is in a voltage-regulating state, and the third current I3 is the same as the ninth current I9 (in magnitude). Since I9 is ​​the same as I1, I3 is the same as I1 (in magnitude).

[0115] When the reference clock V R Aligned to the input clock (by V i1 and V i2 V s1 Same as V s2 , so I1 is the same as I2 in size, and I3 is the same as I2, the output current I out =0, because I2 and I3 have the same magnitude but opposite signs. Thus, the sub-sampling phase detector 100 has an offset of almost zero.

[0116] It should be noted that the two virtual switches DS1 and DS2 are used to make the two PMOS transistors 141 and 142 have the same DC state at their drains, thereby improving the accuracy of the current mirroring of the current mirror CM1. This is effective but not absolutely necessary. The circuit designer can selectively remove DS1 and DS2 and replace them with short circuits; in this way, the complexity of the sub-sampling phase detector 100 can be reduced, at the expense of lower current mirroring accuracy of the current mirror CM1 (because there is no DS2 to simulate the voltage drop of SW3 and SW4, and there is no DS1 to simulate the voltage drop of SW1 and SW2), so the phase detection offset is larger, but the function of the sub-sampling phase detector 100 can still be maintained.

[0117] For any given circuit including NMOS transistors and / or PMOS transistors, the functionality of the circuit is maintained if each NMOS transistor is replaced by a PMOS transistor, each PMOS transistor is replaced by an NMOS transistor, each power supply node is replaced by a ground node, and each ground node is replaced by a power supply node; in other words, the NMOS transistors and PMOS transistors are interchangeable, and the power supply nodes and ground nodes are interchangeable. Therefore, in the appended claims, NMOS transistors and PMOS transistors will not be explicitly stated; instead, they will be stated as "first type MOS transistors" and "second type MOS transistors"; in one embodiment, "first type MOS transistors" and "second type MOS transistors" represent NMOS transistors and PMOS transistors, respectively; in other embodiments, "first type MOS transistors" and "second type MOS transistors" represent PMOS transistors and NMOS transistors, respectively. Similarly, power supply nodes and ground nodes will not be explicitly stated; instead, they will be stated as "first DC node" and "second DC node".

[0118] like Figure 3The flow chart shown in FIG. 1 shows a phase detection method comprising the following steps: (step 310) receiving a reference clock and an input clock, which include a first input signal and a second input signal; (step 320) sampling the first input signal and the second input signal according to the reference clock to obtain a first sample and a second sample stored in a first capacitor and a second capacitor, respectively; (step 330) using a voltage-to-current converter to convert the first sample and the second sample into a first current and a second current; (step 340) using a voltage-regulated current mirror in a closed loop to convert the first sample and the second sample into a first current and a second current according to the standby voltage on the standby node; The first current is converted into a third current; (step 350) using a first current steering network to guide the second current to a fourth current flowing to a standby node or a fifth current flowing to an output node according to a pulse signal synchronized with a reference clock; (step 360) using a second current steering network to guide the third current to a sixth current flowing to a standby node or a seventh current flowing to an output node according to a pulse signal; (step 370) connecting a low-pass filter to the output node to establish an output voltage and a low-pass filter voltage; and (step 380) using a unity gain buffer to make the standby voltage equal to the low-pass filter voltage.

[0119] Although the embodiments of the present disclosure are described above, these embodiments are not intended to limit the present disclosure. Those skilled in the art may make changes to the technical features of the present disclosure based on the explicit or implicit contents of the present disclosure. All these changes may fall within the scope of patent protection sought by the present disclosure. In other words, the scope of patent protection of the present disclosure shall be based on what is defined in the claims of this specification.

Claims

1. A sub-sampling phase detector comprising: a pulse generator for receiving a reference clock and generating a pulse signal synchronized with the reference clock; a sampling network for sampling an input clock including a first input voltage and a second input voltage according to the reference clock to obtain a first sample and a second sample stored in a first capacitor and a second capacitor respectively; a voltage-to-current converter, configured to convert the first sample and the second sample into a first current and a second current according to a bias voltage; a voltage-stabilized current mirror, mirroring the first current into a third current in a closed-loop manner according to a standby voltage on a standby node; a first current steering network for steering the second current to a fourth current flowing toward the standby node or a fifth current flowing toward an output node according to the pulse signal; a second current steering network for steering the third current to a sixth current flowing toward the standby node or a seventh current flowing toward the output node according to the pulse signal; a load connected to the output node, comprising a low-pass filter and configured to establish an output voltage at the output node in response to a sum of the fifth current and the seventh current, wherein a low-pass filtered voltage is an output of the low-pass filter; as well as A unity gain buffer is used to receive the low-pass filtered voltage and establish the standby voltage.

2. The sub-sampling phase detector of claim 1, wherein the pulse signal comprises a first logic signal and a second logic signal, wherein the second logic signal is inverted with respect to the first logic signal.

3. The sub-sampling phase detector of claim 2 , wherein the first current steering network comprises a first switch controlled by the first logic signal to steer the second current to the fourth current; and a second switch controlled by the second logic signal to steer the second current to the fifth current; wherein the second current steering network comprises a third switch controlled by the first logic signal to steer the third current to the sixth current; and a fourth switch controlled by the second logic signal to steer the third current to the seventh current.

4. The sub-sampling phase detector of claim 1 , wherein the voltage-to-current converter comprises a differential common-source amplifier, the differential common-source amplifier comprising a first metal oxide semiconductor transistor of a first type and a second metal oxide semiconductor transistor of the first type, wherein the first metal oxide semiconductor transistor and the second metal oxide semiconductor transistor respectively receive the first sample and the second sample according to a bias current controlled by the bias voltage and output the first current and the second current.

5. The sub-sampling phase detector of claim 4 , wherein the regulated current mirror comprises a third MOS transistor of the second type and a fourth MOS transistor of the second type, wherein the third MOS transistor and the fourth MOS transistor have the same source voltage and the same gate voltage, the third MOS transistor of the second type is configured to receive the first current, and the fourth MOS transistor of the second type is configured to output the third current.

6. The sub-sampling phase detector of claim 5 , wherein the regulated current mirror further comprises an operational amplifier, the operational amplifier configured to output the gate voltage according to a difference between the standby voltage and an intermediate voltage, the intermediate voltage being an intermediate node between the first metal oxide semiconductor transistor of the first type and the third metal oxide semiconductor transistor of the second type.

7. The sub-sampling phase detector of claim 6, wherein the regulated current mirror further comprises a first virtual switch, wherein the first virtual switch is kept turned on and is used to provide a conduction path for the first current to reach the intermediate node.

8. The sub-sampling phase detector of claim 7 , wherein the regulated current mirror further comprises a second dummy switch, wherein the second dummy switch is kept on and configured to provide a conduction path so that the first current reaches the third MOS transistor of the second type after reaching the intermediate node.

9. The sub-sampling phase detector of claim 2 , wherein the pulse generator comprises a delay line, an inverter, and an AND gate, wherein a delay of the delay line is approximately equal to a pulse width of the pulse signal, and the delay line is configured to receive the reference clock and output a third logic signal, wherein the inverter is configured to receive the reference clock and output a fourth logic signal, and wherein the AND gate is configured to receive the third logic signal and the fourth logic signal and output the second logic signal.

10. A phase detection method comprising the following steps: receiving a reference clock and an input clock, wherein the input clock comprises a first input signal and a second input signal; Sampling the first input signal and the second input signal according to the reference clock to obtain a first sample and a second sample stored in a first capacitor and a second capacitor respectively; Using a voltage-to-current converter to convert the first sample and the second sample into a first current and a second current; Using a regulated current mirror in a closed loop manner to convert the first current into a third current according to a standby voltage on a standby node; Using a first current steering network to guide the second current to a fourth current flowing toward the standby node or a fifth current flowing toward an output node according to a pulse signal synchronized with the reference clock; using a second current steering network to direct the third current to a sixth current flowing toward the standby node or a seventh current flowing toward the output node according to the pulse signal; Connecting a low-pass filter to the output node to establish an output voltage and a low-pass filtered voltage; and A unity gain buffer is used to make the standby voltage equal to the low pass filtered voltage.

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