AC-Coupled Level Shifter

Abstract

The present invention discloses an AC-coupled level shifter, belonging to the field of integrated circuits. In order to speed up the level conversion speed of high-speed signals, in the AC-coupled level shifter of the present invention, the input signal is connected to the gate of the first NMOS tube and the gate of the first PMOS tube, the source of the first PMOS tube is connected to the first device working voltage, the drain of the first PMOS tube is connected to the drain of the first NMOS tube, and the source of the first NMOS tube is connected to the first common ground terminal voltage; the drain of the first PMOS tube is also connected to the gate of the second NMOS tube and the gate of the second PMOS tube; the source of the second PMOS tube is connected to the second device working voltage, the drain of the second PMOS tube is connected to the drain of the second NMOS tube, and the source of the second NMOS tube is connected to the second common ground terminal voltage; the drain of the second PMOS tube leads to the output signal; the gate of the first NMOS tube is connected to the first end of the capacitor, and the drain of the second PMOS tube is connected to the second end of the capacitor. The present invention has the advantages of low delay and low duty cycle loss.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to an AC coupling level shifter. Background Art

[0002] In the fifth generation (DDR5) memory interface chip of Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), with the continuous increase in data rate and the requirement for optimizing chip power consumption and energy efficiency, the chip supply voltage has been reduced to 1.1V. In order to further improve the energy efficiency, a multi-voltage domain strategy is usually adopted in the design of the transmitter: that is, the output stage operates in the 1.1V voltage domain, while the front stage operates in a lower voltage domain to reduce power consumption. In this multi-voltage domain design, the level shift between different voltage domains is completed by the level shifter (LS). As a key component connecting different voltage domains, the performance of the level shifter not only affects the quality of high-speed signal conversion, but also directly determines the final performance of the entire transmitter.

[0003] In a double data rate (DDR) high-speed link, signal integrity is one of the important factors to ensure the overall system performance. Therefore, the signal after level shifting must maintain high quality, which is specifically manifested in fast and low-latency conversion characteristics, while minimizing the duty cycle loss of the signal during the conversion process. This poses a challenge to the design of the level shifter, because when the high-speed data signal passes through the level shifter, it is easy to cause the signal's duty cycle loss during the level shifting process due to the difference in the voltage domains of the previous and next stages. In addition, achieving low latency is also a key problem in the design of the level shifter. Summary of the invention

[0004] In order to alleviate or partially alleviate the above technical problems, the solution of the present invention is as follows:

[0005] An AC coupling level shifter comprises: a first NMOS tube, a second NMOS tube, a first PMOS tube, a second PMOS tube and a capacitor; wherein an input signal is connected to the gate of the first NMOS tube and the gate of the first PMOS tube, the source of the first PMOS tube is connected to a first device operating voltage, the drain of the first PMOS tube is connected to the drain of the first NMOS tube, and the source of the first NMOS tube is connected to a first common ground terminal voltage; the drain of the first PMOS tube is also connected to the gate of the second NMOS tube and the gate of the second PMOS tube; the source of the second PMOS tube is connected to a second device operating voltage, the drain of the second PMOS tube is connected to the drain of the second NMOS tube, and the source of the second NMOS tube is connected to a second common ground terminal voltage; the drain of the second PMOS tube leads to an output signal; the gate of the first NMOS tube is connected to a first end of the capacitor, and the drain of the second PMOS tube is connected to a second end of the capacitor; the voltage value of the second common ground terminal voltage is greater than the voltage value of the first common ground terminal voltage, and the voltage value of the second device operating voltage is greater than the voltage value of the first device operating voltage.

[0006] Further, the conduction threshold of the second PMOS tube is greater than the conduction threshold of the first PMOS tube, and the conduction threshold of the second NMOS tube is greater than the conduction threshold of the first NMOS tube.

[0007] Furthermore, the second common ground terminal voltage is generated by a low voltage drop linear regulator.

[0008] The technical solution of the present invention has one or more of the following beneficial technical effects:

[0009] (1) Through the design of AC and DC paths, the level conversion speed of high-speed signals is greatly accelerated, and the delay can be as low as picoseconds, ensuring good duty cycle performance of the output signal.

[0010] (2) Reduces DC path delay and protects devices from overvoltage.

[0011] (3) After the power supply is turned on, the DC path can directly reset the voltage across the capacitor without the need for an additional reset circuit.

[0012] (4) Simple structure, good high-frequency performance, small area and low static power consumption.

[0013] (5) The duty cycle loss of the output signal is very small, and high-speed random data signals and high-speed clock signals can be transmitted.

[0014] In addition, other beneficial effects of the present invention will be mentioned in the specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a circuit diagram of a level shifter in the prior art;

[0016] Figure 2 It is another level shifter circuit diagram in the prior art;

[0017] Figure 3 is a circuit diagram of a level shifter circuit of the present invention;

[0018] Figure 4 It is a schematic diagram of the principle of the level shifter circuit of the present invention. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same or similar items with substantially the same functions and effects. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order.

[0021] Figure 1 The circuit diagram of a level shifter in the prior art includes two voltage domains: a first common ground voltage (Voltage Source-to-Source, VSS) VSS1 and a first device operating voltage (Voltage Drain-to-Drain, VDD) VDD1, and a second common ground voltage VSS2 and a second device operating voltage VDD2.

[0022] In this example, it is assumed that V S1 is the voltage value of the first common ground terminal voltage VSS1, V S2 is the voltage value of the second common ground terminal voltage VSS2, V D1 is the voltage value of the first device operating voltage VDD1, V D2 is the voltage value of the second device operating voltage VDD2.

[0023] The level shifter includes N-channel Metal Oxide Semiconductor (NMOS) tubes M1, M2, M3 and M4, wherein the input signal swing of the NMOS tubes M1 and M2 is VSS1~VDD1, and in order to improve the speed of the level shifter, the NMOS tubes M1 and M2 are usually low-voltage NMOS tubes with a low conduction threshold.

[0024] P-channel Metal Oxide Semiconductor (PMOS) M5 and PMOS tube M6 are high-voltage PMOS tubes. The drain of PMOS tube M6 serves as the output end of the level shifter, and the output signal swing is VSS2~VDD2. Inverter INV1 is an inverter composed of a low-voltage tube, and inverter INV2 and inverter INV3 are inverters composed of high-voltage tubes.

[0025] When the input signal is V S1 When the voltage reaches V, the NMOS tube M2 is turned on, the drain voltage of the PMOS tube M6 decreases, the PMOS tube M5 begins to turn on gradually, and the drain voltage of the PMOS tube M5 begins to rise to V D2 Due to positive feedback, the drain voltage of PMOS tube M5 will accelerate the drain voltage of PMOS tube M6 to drop to V S1 After passing through inverters INV2 and INV3, the voltage value of the output signal becomes V S2 voltage value, thereby realizing the conversion from VSS1 to VSS2.

[0026] Similarly, when the input signal changes from V S1 When the voltage value jumps to the VDD1 voltage value, the NMOS tube M1 is turned on, the PMOS tube M6 is gradually turned on, and the drain voltage of the PMOS tube M6 gradually rises to VDD2, and then passes through the inverter INV2 and the inverter INV3, thereby realizing the conversion from VDD1 to VDD2.

[0027] However, the above-mentioned level shifter uses an NMOS tube with a faster conduction speed, but since a level of NMOS tube and PMOS tube are stacked, the overall speed of the circuit is limited, resulting in a large delay, which makes it difficult to meet the delay requirements of the link.

[0028] At the same time, due to the existence of a positive feedback loop, the pull-down capability of the NMOS tube in the input pair needs to be stronger than the pull-up capability of the PMOS tube in order to correctly distribute the input signal. This also causes the duty cycle of the output signal to be naturally small, causing a large duty cycle loss.

[0029] Figure 2This is another level shifter circuit diagram in the prior art. This circuit also includes inverters INV1, INV2 and INV3, and also includes NMOS tubes M1, M2, M3, M4, and PMOS tubes M5 and M6. Figure 1 Compared with the level shifter shown in FIG. 1 , the main difference lies in the gate connection mode of the PMOS tube M5 and the PMOS tube M6.

[0030] Since the PMOS tube M5 is self-biased, the output duty cycle mainly depends on the device size ratio of the PMOS tube and the NMOS tube. By selecting a reasonable device size ratio, the output signal can have a good duty cycle.

[0031] However, this type of level shifter still has a large delay, a slow high-frequency response, and a certain amount of static power consumption, which affects the energy efficiency of the DDR interface.

[0032] Figure 3 : is a circuit diagram of a level shifter circuit of the present invention. The present invention is an AC coupled level shifter, including two voltage domains, VSS1~VDD1 and VSS2~VDD2. S2 The voltage value is greater than V S1 Voltage value, V D2 The voltage value is greater than V D1 Voltage value.

[0033] The AC coupling level shifter includes a first NMOS transistor N1, a second NMOS transistor N2, a first PMOS transistor P1 and a second PMOS transistor P2. The first NMOS transistor N1 and the first PMOS transistor P1 are low voltage transistors, working at VSS1~VDD1; the second NMOS transistor N2 and the second PMOS transistor P2 are high voltage transistors, working at VSS2~VDD2.

[0034] Specifically, in the AC-coupled level shifter of the present invention, the input signal is connected to the gate of the first NMOS tube N1 and the gate of the first PMOS tube P1, the source of the first PMOS tube P1 is connected to the first device operating voltage VDD1, the drain of the first PMOS tube P1 is connected to the drain of the first NMOS tube N1, and the source of the first NMOS tube N1 is connected to the first common ground voltage VSS1.

[0035] The drain of the first PMOS tube P1 is also connected to the gate of the second NMOS tube N2 and the gate of the second PMOS tube P2. The source of the second PMOS tube P2 is connected to the second device operating voltage VDD2, the drain of the second PMOS tube P2 is connected to the drain of the second NMOS tube N2, and the source of the second NMOS tube N2 is connected to the second common ground voltage VSS2. The drain of the second PMOS tube P2 leads to an output signal.

[0036] In addition, the gate of the first NMOS transistor N1 is connected to the first end of the capacitor, and the drain of the second PMOS transistor P2 is connected to the second end of the capacitor.

[0037] In the present invention, the input signal swing is VSS1-VDD1, and the output signal swing is VSS2-VDD2.

[0038] Figure 4 The schematic diagram of the principle of the level shifter circuit of the present invention. The present invention includes two signal paths: an alternating current (AC) path and a direct current (DC) path, which process signals of different frequency components respectively. The low-frequency part of the input signal is transmitted through the DC path, while the high-frequency part, such as the rising edge and falling edge of the high-speed signal during the switching process, is transmitted through the AC path formed by the capacitor.

[0039] In the present invention, it is assumed that the delay generated by the first PMOS transistor P1 and the first NMOS transistor N1 is T2, the delay generated by the second PMOS transistor P2 and the second NMOS transistor N2 is T3, and the delay of the AC path formed by the capacitor is T1.

[0040] To ensure the integrity of high-frequency signals, the input signal swing and output signal swing should be consistent. S2 =V D2 -(V D1 -V S1 ), where V S1 is the voltage value of the first common ground terminal voltage VSS1, V S2 is the voltage value of the second common ground terminal voltage VSS2, V D1 is the voltage value of the first device operating voltage VDD1, V D2 is the voltage value of the second device operating voltage VDD2. In addition, V S2 It can be generated by a low dropout linear regulator.

[0041] Assume that after each power supply is powered on successfully, the initial state of the input signal is V D1 Voltage value, the DC signal output voltage after passing through the DC path is V D2 Voltage value, so the voltage between the two plates of the capacitor is determined, and the charge Q0 stored in the capacitor is:

[0042] Q0 = (V D2 -V D1 ) × C;

[0043] At the next data cycle, the input signal is V D1 The voltage drops to V S1During the voltage value process, the voltage value of the output signal is V out1 , when the high-frequency signal reaches a steady state, the charge Q1 stored in the capacitor is:

[0044] Q1 = (V out1 -V S1 ) × C;

[0045] Since the signal switching process is a high-frequency signal, the high-frequency signal can quickly pass through the AC path formed by the capacitor; while the DC path is two sets of inverters, the delay of the high-frequency signal passing through the DC path is equal to T2+T3, which is longer than the delay T1 of the AC path. Therefore, for the high-frequency signal, when it reaches the output end through the AC path, the signal of the DC path has not arrived yet. At this time, the amount of charge stored in the capacitor before and after is conserved, that is, Q0=Q1, and we can get:

[0046] V out1 =V D2 -V D1 +V S1 =V S2 ;

[0047] Therefore, the output signal transition can be greatly accelerated through capacitive coupling, and the delay T1 of the AC path can be reduced to less than 5 picoseconds.

[0048] Similarly, when the input signal jumps from VSS1 to VDD1, the steady-state voltage of the AC path signal reaching the output end is V out2 , the amount of charge Q2 stored in the capacitor is:

[0049] Q2 = (V out2 -V D1 ) × C;

[0050] According to the conservation of charge before and after, Q2=Q1, that is, V out2 =V D1 +V S2 -V S1 =V D2 , completing high-speed conversion of voltage domain.

[0051] In the present invention, the AC path accelerates the signal transition, and the DC path transmits the low-frequency signal while resetting the initial voltage value at both ends of the capacitor.

[0052] At the same time, since the rising edge and the falling edge of the input signal are directly coupled to the output through the capacitor, the rising edge and the falling speed of the output signal are synchronized with the input signal, so the duty cycle loss of the output signal is very small, which can be less than 0.1%, ensuring good duty cycle performance during high-speed signal level conversion.

[0053] In order to improve performance, the first-stage inverter in the DC path uses the first PMOS tube P1 and the first NMOS tube N1 with a low conduction threshold, which can reduce the delay T2, thereby reducing the DC path delay in high-frequency signal transmission and reducing the impact of the inconsistent delay between the DC path and the AC path on the output signal.

[0054] Furthermore, the second-stage inverter uses a second PMOS tube P2 and a second NMOS tube N2 with a high conduction threshold to achieve voltage domain conversion and device overvoltage protection, protecting the first-stage inverter low-voltage device and the output post-stage low-voltage device from overvoltage. In other words, the conduction threshold of the second PMOS tube P2 is greater than the conduction threshold of the first PMOS tube P1, and the conduction threshold of the second NMOS tube N2 is greater than the conduction threshold of the first NMOS tube N1.

[0055] In order to better illustrate the present invention, numerous specific details are provided in the above specific embodiments. It should be understood by those skilled in the art that the present invention can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present invention.

[0056] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. An AC-coupled level shifter, characterized in that: include: A first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor and a capacitor; wherein, The input signal is connected to the gate of the first NMOS tube and the gate of the first PMOS tube, the source of the first PMOS tube is connected to the first device operating voltage, the drain of the first PMOS tube is connected to the drain of the first NMOS tube, and the source of the first NMOS tube is connected to the first common ground voltage; The drain of the first PMOS tube is also connected to the gate of the second NMOS tube and the gate of the second PMOS tube; the source of the second PMOS tube is connected to the second device operating voltage, the drain of the second PMOS tube is connected to the drain of the second NMOS tube, and the source of the second NMOS tube is connected to the second common ground terminal voltage; the drain of the second PMOS tube leads to an output signal; The gate of the first NMOS tube is connected to the first end of the capacitor, and the drain of the second PMOS tube is connected to the second end of the capacitor; The voltage value of the second common ground terminal voltage is greater than the voltage value of the first common ground terminal voltage, and the voltage value of the second device operating voltage is greater than the voltage value of the first device operating voltage; The conduction threshold of the second PMOS tube is greater than the conduction threshold of the first PMOS tube, and the conduction threshold of the second NMOS tube is greater than the conduction threshold of the first NMOS tube.

2. The AC-coupled level shifter according to claim 1, wherein: The second common ground terminal voltage is generated by a low voltage drop linear regulator.

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