Clock circuit, signal receiving end and electronic equipment

Abstract

The invention discloses a clock circuit, a signal receiving end and electronic equipment, and belongs to the technical field of clocks. The clock circuit comprises a phase-locked loop circuit and a peripheral circuit, wherein the phase-locked loop circuit is connected with the peripheral circuit; the phase-locked loop circuit is used for outputting a first clock based on a reference clock of a reference clock end and a configuration parameter, the first clock is used for transmitting a data stream, and the configuration parameter is determined based on a relationship between the reference clock and a sampling clock of the data stream; and the peripheral circuit is used for controlling configuration parameters of the phase-locked loop circuit according to the second clock and time information for transmitting the data stream through the second clock so as to reduce clock skew between the first clock and the sampling clock, and the time information indicates the relation between the second clock and the sampling clock. According to the clock circuit, clock skew caused by cross-clock domain transmission is reduced, the accuracy of data stream transmission is improved, and the clock circuit can adapt to a universal phase-locked loop.

Description

Technical Field

[0001] The present application relates to the field of clock technology, and in particular to a clock circuit, a signal receiving end and an electronic device. Background Art

[0002] In High Definition Multimedia Interface (HDMI) applications, real-time transmission of audio data streams is required. Due to the setting of HDMI transmission protocol, the audio data stream is embedded in the Transition Minimized Differential Signaling (TMDS) clock domain of the video data stream and sent. The receiving end of the audio data stream generally uses the Inter-IC Sound (I2S) interface to pass the audio data stream to the next level application through the I2S clock.

[0003] Therefore, the receiving end needs to recover the sampling clock of the audio data stream from the TMDS clock domain through the clock circuit to achieve stable cross-clock domain transmission from the TMDS clock domain to the I2S clock domain and meet the real-time requirements of the audio data stream. Summary of the invention

[0004] The present application provides a clock circuit, a signal receiving end and an electronic device, which are used to reduce the clock deviation between the first clock of the transmission data stream output by the phase-locked loop circuit and the sampling clock of the data stream. The technical solution is as follows:

[0005] In one aspect, a clock circuit is provided, the clock circuit comprising: a phase-locked loop circuit and a peripheral circuit, the phase-locked loop circuit being connected to the peripheral circuit;

[0006] The phase-locked loop circuit is used to output a first clock based on a reference clock at a reference clock terminal and a configuration parameter, the first clock is used to transmit a data stream, and the configuration parameter is determined based on a relationship between the reference clock and a sampling clock of the data stream;

[0007] The peripheral circuit is used to control the configuration parameters of the phase-locked loop circuit according to a second clock and time information of transmitting the data stream through the second clock to reduce the clock deviation between the first clock and the sampling clock, and the time information indicates the relationship between the second clock and the sampling clock.

[0008] In a possible implementation manner, the peripheral circuit includes: a control circuit and a negative feedback circuit, the control circuit is respectively connected to the clock end of the second clock domain, the negative feedback circuit and the phase-locked loop circuit, and the negative feedback circuit is also connected to the phase-locked loop circuit;

[0009] The control circuit is used to obtain a first synchronization clock according to the second clock and the time information;

[0010] The negative feedback circuit is used to obtain a second synchronization clock according to the first clock and the time information;

[0011] The control circuit is further configured to obtain a reference clock difference between the first synchronous clock and the second synchronous clock, and control configuration parameters of the phase-locked loop circuit based on the reference clock difference.

[0012] In a possible implementation manner, the control circuit includes a phase detector and an adjustment module, and the phase detector is connected to the adjustment module;

[0013] The phase detector is used to output a deviation signal based on the first synchronous clock and the second synchronous clock, wherein the deviation signal indicates a reference clock difference between the first synchronous clock and the second synchronous clock;

[0014] The adjustment module is used to obtain adjusted configuration parameters based on the reference clock difference when the reference clock difference indicated by the deviation signal is greater than a difference threshold, and send the adjusted configuration parameters to the phase-locked loop circuit.

[0015] In a possible implementation, the adjustment module is used to determine an adjustment amplitude based on the reference clock difference and the corresponding relationship, adjust the configuration parameters of the phase-locked loop circuit according to the adjustment amplitude, and obtain the adjusted configuration parameters, and the corresponding relationship indicates the relationship between the clock deviation and the adjustment amplitude.

[0016] In a possible implementation, when the phase-locked loop circuit is an integer phase-locked loop, the adjusted configuration parameters include an integer division ratio; when the phase-locked loop circuit is a fractional phase-locked loop, the adjusted configuration parameters include an integer division ratio and a fractional division ratio.

[0017] In a possible implementation manner, the time information includes a periodic timestamp and a multiple coefficient; the control circuit further includes a first frequency divider, the first frequency divider is connected to the phase detector, and is used to divide the second clock based on the periodic timestamp to obtain the first synchronous clock;

[0018] The negative feedback circuit includes a second frequency divider, which is connected to the phase detector and is used to divide the first clock based on the multiple coefficient to obtain the second synchronous clock.

[0019] In a possible implementation manner, the phase detector is connected to the adjustment module via a low-pass filter; the low-pass filter is used to smooth the deviation signal and output the smoothed deviation signal to the adjustment module.

[0020] In a possible implementation, the control circuit further includes an enabling circuit, which is connected to the phase detector; the enabling circuit is used to enable transmission of the data stream through the first clock when the reference clock difference indicated by the deviation signal meets an enabling condition, and the enabling condition is that the reference clock difference is less than or equal to the difference threshold within a continuous reference time period.

[0021] On the other hand, a signal receiving end is provided, and the signal receiving end includes the clock circuit as described in the above aspect.

[0022] On the other hand, an electronic device is provided, comprising the signal receiving end as described in the other hand.

[0023] In summary, the technical solution provided by this application can at least bring the following beneficial effects:

[0024] The clock circuit adopts a universal phase-locked loop circuit, and through the design of peripheral circuits, reduces the clock deviation between the first clock of the transmission data stream output by the phase-locked loop circuit and the sampling clock of the data stream, that is, reduces the clock deviation caused by cross-clock domain transmission, and improves the accuracy and stability of data stream transmission. In addition, the clock circuit can adapt to any type of universal phase-locked loop, has strong adaptability, does not require customized design of the phase-locked loop, and effectively reduces development costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 It is a schematic diagram of a data stream transmission method provided in an embodiment of the present application;

[0027] Figure 2 is a schematic diagram of the structure of a clock circuit provided in an embodiment of the present application;

[0028] Figure 3 is a schematic diagram of the structure of another clock circuit provided in an embodiment of the present application;

[0029] Figure 4 is a schematic diagram of the structure of another clock circuit provided in an embodiment of the present application;

[0030] Figure 5 is a schematic diagram of the structure of another clock circuit provided in an embodiment of the present application;

[0031] Figure 6 is a schematic diagram of the structure of another clock circuit provided in an embodiment of the present application;

[0032] Figure 7 It is a schematic diagram of the internal structure of a phase chasing circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0034] In the transmission process of audio data stream, there is a need for stable transmission from TMDS clock domain to I2S clock domain. According to the HDMI transmission protocol, audio data stream is transmitted at the pulse code modulation (PCM) level, that is, uncompressed transmission, and PCM data is scattered into each data packet for transmission. Therefore, the receiving end of the audio data stream needs to restore the audio sampling rate to obtain the data of each audio frame.

[0035] For example, the transmission method of the Audio data stream specified in HDMI is as follows: Figure 1 As shown. The source (transmitter) converts the sampling clock information into time information such as cycle timestamp (CTS) and multiple coefficient (N) related to the TMDS clock (represented by TMDS_CLK), and transmits it to the sink (receiving end) through the data stream. That is, CTS = N*f(TMDS_CLK) / Fs, f(TMDS_CLK) represents the frequency of TMDS_CLK, and Fs represents the frequency of the sampling clock. The receiving end receives the data stream and parses and restores CTS and N. Based on TMDS_CLK, Fs is obtained by frequency division. That is, Fs = f(TMDS_CLK)*N / CTS. Among them, it is necessary to ensure that the clock deviation between TMDS_CLK and Fs meets the audio transmission requirements.

[0036] Due to the relevant provisions of the HDMI protocol and the real-time characteristics of the audio stream, the frequency width of TMDS_CLK is large, for example, the frequency width of TMDS_CLK is 25-594 MHz, the output clock accuracy is high, and the output needs to be dynamically adjusted to eliminate clock offset errors. Therefore, the audio clock circuit needs to be customized for the above technical indicators, and the development cost is high.

[0037] The embodiment of the present application provides a clock circuit, which realizes the function of an audio clock (Audio PLL) by designing a peripheral circuit and cooperating with a universal phase locked loop (PLL). A phase locked loop is a negative feedback control system that uses a voltage generated by phase synchronization to tune a voltage controlled oscillator to generate a target clock. Figure 2 Schematic diagram of a clock circuit provided by an embodiment of the present application. Figure 2 As shown, the clock circuit 00 includes: a phase-locked loop circuit 01 and a peripheral circuit 02, and the phase-locked loop circuit 01 is connected to the peripheral circuit 02.

[0038] The phase-locked loop circuit 01 is used to output a first clock based on the reference clock of the reference clock terminal and the configuration parameters, the first clock is used to transmit the data stream, and the configuration parameters are determined based on the relationship between the reference clock and the sampling clock of the data stream. The reference clock can be generated by a crystal oscillator, that is, the reference clock terminal is a crystal oscillator, and the phase-locked loop circuit 01 is also connected to the reference clock terminal.

[0039] Optionally, the phase-locked loop circuit 01 can be any general PLL, and the configuration parameters of the PLL are determined based on the relationship between the reference clock and the sampling clock of the data stream, so that the frequency point output by the PLL based on the reference clock is the frequency of the sampling clock, or a multiple of the frequency of the sampling clock. Alternatively, the phase-locked loop circuit 01 includes any general PLL and a frequency divider, and the configuration parameters of the PLL are determined based on the relationship between the reference clock and the sampling clock of the data stream, so that the frequency point output by the PLL based on the reference clock is the frequency of the sampling clock or a multiple of the frequency of the sampling clock after being divided by the frequency divider.

[0040] Exemplarily, according to the output frequency band of the actual PLL, the output frequency point of the PLL is set to M*128Fs, and then according to the reference clock f(refclk), the configuration parameters corresponding to the PLL are set. M can be any non-zero number. For an integer-type PLL, the configuration parameters may include an integer multiplication coefficient, which is also called an integer division ratio. For a fractional-type PLL, the configuration parameters may include an integer multiplication coefficient and a fractional multiplication coefficient, which is also called a fractional division ratio.

[0041] The peripheral circuit 02 is used to control the configuration parameters of the phase-locked loop circuit 01 according to the second clock and the time information of the data stream transmitted by the second clock to reduce the clock deviation between the first clock and the sampling clock, and the time information indicates the relationship between the second clock and the sampling clock. The clock includes two parameters, frequency and phase, and the clock deviation includes at least one of a frequency difference or a phase difference.

[0042] In the embodiment of the present application, for the transmission scenario of the audio data stream, the first clock corresponds to the audio clock domain, for example, the I2S clock domain; the second clock corresponds to the video clock domain, for example, the TMDS clock domain. Exemplarily, the time information of the transmission data stream in the second clock domain may refer to CTS and N.

[0043] Since the time information indicates the relationship between the second clock and the sampling clock, the peripheral circuit 02 can recover the sampling clock according to the time information and the second clock, and dynamically control the configuration parameters of the phase-locked loop circuit 01 according to the recovered sampling clock, so that the clock deviation between the first clock output by the phase-locked loop circuit 01 and the sampling clock is less than the difference threshold.

[0044] The clock circuit adopts a universal phase-locked loop circuit, and reduces the clock deviation between the first clock output by the phase-locked loop circuit and the sampling clock by designing peripheral circuits, thereby realizing stable transmission of the data stream through the first clock, reducing the clock deviation caused by cross-clock domain transmission, and improving the transmission accuracy of the data stream. In addition, the clock circuit can adapt to any type of universal phase-locked loop, has strong adaptability, does not require customized design of the phase-locked loop, and effectively reduces development costs.

[0045] Figure 3 Another clock circuit provided in the embodiment of the present application is Figure 2 The clock circuit shown, the peripheral circuit 02 includes: a control circuit 021 and a negative feedback circuit 022, the control circuit 021 is respectively connected to the clock end of the second clock domain, the negative feedback circuit 022 and the phase-locked loop circuit 01, and the negative feedback circuit 022 is also connected to the phase-locked loop circuit 01.

[0046] Among them, the control circuit 021 is used to obtain the first synchronization clock according to the second clock and time information; the negative feedback circuit 022 is used to obtain the second synchronization clock according to the first clock and time information; the control circuit 021 is also used to obtain the reference clock difference between the first synchronization clock and the second synchronization clock, and control the configuration parameters of the phase-locked loop circuit 01 based on the reference clock difference.

[0047] Take the example that the time information includes CTS and N, the second clock corresponds to f(TMDS_CLK), and the first clock corresponds to f(PLL). The first synchronization clock may be f(TMDS_CLK)*N / CTS, and the second synchronization clock is f(PLL); or, the first synchronization clock may be f(TMDS_CLK)*N, and the second synchronization clock is f(PLL)*CTS; or, the first synchronization clock may be f(TMDS_CLK) / CTS, and the second synchronization clock is f(PLL) / N; or, the first synchronization clock may be f(TMDS_CLK), and the second synchronization clock is f(PLL)*CTS / N.

[0048] Figure 4 Another clock circuit provided in the embodiment of the present application is Figure 3 In the clock circuit shown, the control circuit 021 includes a phase detector 0211 and an adjustment module 0212, and the phase detector 0211 is connected to the adjustment module 0212. The phase detector 0211 is used to output a deviation signal based on the first synchronous clock and the second synchronous clock, and the deviation signal indicates the reference clock difference between the first synchronous clock and the second synchronous clock. The adjustment module 0212 is used to obtain the adjusted configuration parameters based on the reference clock difference when the reference clock difference indicated by the deviation signal is greater than the difference threshold, and send the adjusted configuration parameters to the phase-locked loop circuit 01. The difference threshold can be set based on experience, or flexibly adjusted according to the application scenario, and can meet the data transmission requirements. The clock relationship between the reference clock difference and the difference threshold reflects the clock relationship between the first clock and the sampling clock.

[0049] When the first synchronization clock is f(TMDS_CLK) / CTS and the second synchronization clock is f(PLL) / N, Figure 4 As shown, the control circuit 021 further includes a first frequency divider 0213, which is connected to the phase detector 0211 and is used to divide the second clock based on CTS to obtain a first synchronous clock ( Figure 4 The negative feedback circuit 022 includes a second frequency divider 0221, which is connected to the phase detector 0211 and is used to divide the first clock based on N to obtain a second synchronous clock ( Figure 4 Indicated by f2).

[0050] In an embodiment of the present application, the adjustment module 0212 is used to determine the adjustment amplitude based on the correspondence between the clock deviation and the adjustment amplitude and the reference clock difference, and adjust the configuration parameters of the phase-locked loop circuit 01 according to the adjustment amplitude to obtain the adjusted configuration parameters. Among them, the correspondence can indicate the relationship between the clock deviation and the adjustment amplitude, so that after obtaining the reference clock difference, the reference clock difference can be found in the clock deviation included in the correspondence, and then the adjustment amplitude corresponding to the reference clock difference in the correspondence is used as the adjustment amplitude determined based on the reference clock difference. The correspondence can be flexibly configured according to the application scenario. By configuring different correspondences, the effect of adjusting different amplitudes for the same clock deviation can be achieved, so that the clock circuit has a flexible and configurable function.

[0051] Exemplarily, the corresponding relationship indicates that when the clock deviation is in the first range, the adjustment range is an increase of 10%; when the clock deviation is in the second range, the adjustment range is an increase of 20%; when the clock deviation is in the third range, the adjustment range is a decrease of 10%; when the clock deviation is in the fourth range, the adjustment range is a decrease of 20%, and so on.

[0052] The clock circuit 00 can support different types of phase-locked loop circuits. When the phase-locked loop circuit 01 is an integer phase-locked loop, the adjusted configuration parameters include an integer frequency division ratio; when the phase-locked loop circuit 01 is a fractional phase-locked loop, the adjusted configuration parameters include an integer frequency division ratio and a fractional frequency division ratio. For example, when the adjusted configuration parameters are obtained according to the adjustment amplitude, for an integer PLL, the adjusted configuration parameters are converted into an integer frequency division ratio, and for a fractional PLL, the adjusted configuration parameters are converted into an integer frequency division ratio and a fractional frequency division ratio.

[0053] Figure 5 Another clock circuit provided in the embodiment of the present application is Figure 4 In the clock circuit shown, the phase detector 0211 is connected to the adjustment module 0212 via a low-pass filter 0214; the low-pass filter 0214 is used to smooth the deviation signal and output the smoothed deviation signal to the adjustment module 0212. Optionally, the smoothing process includes removing noise and high-frequency interference, etc. Therefore, the adjustment module 0212 is used to determine the parameter clock difference based on the smoothed deviation signal.

[0054] Continue to see Figure 5 , the control circuit 021 also includes an enabling circuit 0215, which is connected to the phase detector 0211; the enabling circuit 0215 is used to enable the data stream to be transmitted through the first clock when the reference clock difference indicated by the deviation signal meets the enabling condition, and the enabling condition is that the reference clock difference is less than or equal to the difference threshold value within the continuous reference time length. In other words, when the reference clock difference obtained by the phase detector 0211 is maintained at a low level, that is, less than or equal to the difference threshold value, and the set reference time length is maintained, the clock circuit 00 is considered to be locked, and the clock circuit 00 can also be called Audio PLL. Among them, the reference time length can be set according to experience, or flexibly adjusted according to the application scenario.

[0055] Exemplarily, the enabling circuit 0215 may include a lock signal, and the data stream is transmitted through a first-in-first-out (FIFO) memory. After the Audio PLL is considered locked, the digital part lock signal is pulled high as a flag for opening the subsequent read channel of the Audio FIFO, that is, the data stream can be transmitted based on the audio clock domain. The FIFO memory is a first-in-first-out dual-port buffer, that is, the first data to enter it is removed first, one of which is the input port of the memory, and the other is the output port of the memory.

[0056] Next, we take the cross-clock domain scenario of audio data stream as an example and combine Figure 6The clock circuit shown is used as an example. Figure 6 As shown, the phase-locked loop circuit 01 includes a PLL and a diva divider, and TMDS_CLK is not directly input to the PLL, thereby relaxing the input requirements for the reference clock of the PLL. For example, the reference clock can use a crystal clock. On the other hand, the accuracy of the input clock source, i.e., the reference clock, can be improved, and the input error can be reduced. According to the HDMI protocol, the relationship between the TMDS clock and CTS is f(TMDS_CLK)*N / CTS=128Fs, where the Audio reference clock is 128 times the sampling rate FS.

[0057] The first frequency divider 0213 is a 1 / CTS frequency divider, and the frequency division coefficient of the 1 / CTS frequency divider is 1 / CTS; the second frequency divider 0221 is a divb frequency divider, and the frequency division coefficient of the divb frequency divider is N. After TMDS_CLK is divided by CTS, TMDS_DIV_CLK, i.e., the first synchronous clock, is obtained. TMDS_DIV_CLK is generally around 1 kHz. According to the output frequency band FVCO of the voltage controlled oscillator (VCO) of the actual PLL, the output frequency FOUT is set to M*128Fs, and then the initial integer multiplication coefficient (for integer PLL) corresponding to the PLL is set according to the reference clock (for integer PLL), or the integer multiplication coefficient and the fractional multiplication coefficient (for fractional PLL).

[0058] When the PLL starts working, the clock deviation introduced by the reference clock of the actual input PLL and the TMDS clock may cause clock deviation between the output frequency FOUT and the TMDS clock. After the diva and divb divisions, the feedback clock Fback, i.e., the second synchronous clock, is obtained. According to theoretical results, the Fback clock and the TMDS_DIV_CLK clock should be of the same frequency and phase, but due to errors, there is a frequency difference and phase difference between the two. The clock deviation between the two clocks is calculated by the phase-chasing circuit. The clock deviation is the frequency difference and the phase difference. After conversion, the integer multiplication factor and the fractional multiplication factor of the PLL are dynamically adjusted according to the clock deviation to form negative feedback and adjust the output clock of the PLL in real time.

[0059] Figure 7 is a block diagram of the internal structure of a phase chasing circuit provided in an embodiment of the present application. Figure 7It is the digital circuit. TMDS_DIV_CLK is the clock after the previous stage TMDS clock CTS is divided. BBPFD is the phase detector 0211, which is used to achieve the frequency and phase tracking of the first clock output by PLL and TMDS_DIV_CLK, and output the deviation signal indicating the clock deviation to the next stage. LPF is a low-pass filter, which is mainly used to smooth the output and remove noise and high-frequency interference. The calc_k module mainly realizes the compensation for clock deviation. For example, BBPFD outputs a deviation signal, and calc_k outputs an adjustment amplitude according to the deviation signal. The adjustment amplitude is used to adjust the configuration parameters of PLL. Optionally, the adjustment amplitude can be represented by the K value.

[0060] In order to increase adaptability, the selection of fractional PLL and integer PLL is supported. For the external integer PLL, a delta_sigma module is built in. This module converts the K value (i.e. adjustment amplitude) output by the calc_k module into an integer division ratio (i.e. Figure 7 In order to select the external fractional PLL, a ktofrac module is built in. This module converts the K value output by the calc_k module from the adjustment range of -2 to +2 to a fractional value of 0 to 1 (i.e., the fractional division ratio, i.e. Figure 7 frac in) and the corresponding M value (integer factor, that is, integer division ratio, that is, Figure 7 The fbdiv in is input to the fractional PLL to adapt the high-precision fractional PLL.

[0061] For example, for an integer PLL, if the current division ratio of the integer PLL is 25, and the K value output by the calc_k module is 1.9, the delta_sigma module converts the K value into an integer division ratio such as 26, 27, 27, 27, 26, 27, etc. based on the current division ratio 25, and inputs the integer division ratios 26, 27, 27, 27, 26, 27 to the integer PLL in sequence, so that the integer division ratio of the integer PLL floats between 26 and 27. That is, the division ratio of the integer PLL is adjusted by an integer amplitude of 2 rounded up or 1 rounded down corresponding to the K value on the basis of 25, thereby achieving an amplitude adjustment of the K value of 1.9 through an averaging effect.

[0062] For the fractional PLL, if the current division ratio of the fractional PLL is 25.001, when the K value output by the calc_k module is 1.9, the ktofrac module converts the K value into an integer division ratio of 26 based on the current division ratio 25.000, and the fractional division ratio is, for example, 0.901, 0.903, 0.900, 0.902, 0.906, etc. The integer division ratio 26 is input to the fractional PLL, so that the fractional PLL keeps the integer division ratio unchanged at 26, and the fractional division ratios of 0.901, 0.903, 0.900, 0.902, and 0.906 are input to the fractional PLL in sequence, so that the fractional division ratio of the fractional PLL fluctuates around 0.9. That is, the integer division ratio of the fractional PLL is adjusted based on 25, and the amplitude of the decimal part of the K value corresponding to the rounded-down value 1 is adjusted based on 0.001, so as to achieve precise amplitude adjustment at the decimal level.

[0063] Fback on the feedback loop is compared with TMDS_DIV_CLK in real time, the clock deviation is updated in real time, and the K value is adjusted, so as to adjust the PLL output in real time until the clock deviation tends to 0, and finally the clock deviation is on the center line of 0 with a small oscillation. Among them, when the clock deviation is kept at a low level (lower than the lock clock deviation setting threshold) and maintained for the set time (lock time threshold), it is considered that the Audio PLL is locked, and the digital part lock signal is pulled high as the subsequent audio fifo read channel opening flag.

[0064] In addition, in response to the needs of general adaptation applications, a variety of configurable functions are set up, including the control of the adjustment amplitude in the calc_k module, the configurable clock deviation threshold required for lock, i.e. the difference threshold, the configurable stable time threshold required for lock, i.e. the reference time, and integer / fractional PLL mode switching.

[0065] The embodiment of the present application provides a signal receiving end, which includes: Figure 2-6 Any of the clock circuits 00 shown. Thus, the signal receiving end can output a first clock for transmitting a data stream through the clock circuit 00, and the clock deviation between the first clock and the sampling clock of the data stream is small.

[0066] An electronic device provided by an embodiment of the present application includes the above-mentioned signal receiving end. Since the electronic device includes the above-mentioned signal receiving end, the electronic device can transmit a data stream through the first clock through the signal receiving end, thereby improving the accuracy of data stream transmission.

[0067] It should be understood that the terms used in the embodiments of the present disclosure are only used to explain the embodiments of the present disclosure, and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be the common meanings understood by people with ordinary skills in the field to which the present disclosure belongs.

[0068] For example, the words “first”, “second” or “third” and similar words used in the patent application specification and claims of this disclosure do not indicate any order, quantity or importance, but are merely used to distinguish different components.

[0069] Likewise, the words “a” or “an” and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

[0070] “Including” or “comprising” and similar words mean that the elements or objects appearing before “including” or “comprising” include the elements or objects listed after “including” or “comprising” and their equivalents, and do not exclude other elements or objects.

[0071] "Up", "down", "left" or "right" etc. are only used to indicate relative position relationship. When the absolute position of the described object changes, the relative position relationship may also change accordingly. "Connected" or "coupled" refers to electrical connection.

[0072] "And / or" indicates that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects before and after are in an "or" relationship.

[0073] Technicians in the relevant field can clearly understand that for the convenience and simplicity of description, the specific working processes of the gate drive circuit, shift register unit, each circuit and each sub-circuit described above can refer to the corresponding processes in the method embodiment and will not be repeated here.

[0074] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A clock circuit, characterized in that: The clock circuit comprises: a phase-locked loop circuit and a peripheral circuit, wherein the phase-locked loop circuit is connected to the peripheral circuit; The phase-locked loop circuit is used to output a first clock based on a reference clock at a reference clock terminal and a configuration parameter, the first clock is used to transmit a data stream, and the configuration parameter is determined based on a relationship between the reference clock and a sampling clock of the data stream; The peripheral circuit is used to control the configuration parameters of the phase-locked loop circuit according to a second clock and time information of transmitting the data stream through the second clock to reduce the clock deviation between the first clock and the sampling clock, and the time information indicates the relationship between the second clock and the sampling clock.

2. The clock circuit according to claim 1, characterized in that: The peripheral circuit comprises: a control circuit and a negative feedback circuit, wherein the control circuit is respectively connected to the clock end of the second clock domain, the negative feedback circuit and the phase-locked loop circuit, and the negative feedback circuit is also connected to the phase-locked loop circuit; The control circuit is used to obtain a first synchronization clock according to the second clock and the time information; The negative feedback circuit is used to obtain a second synchronization clock according to the first clock and the time information; The control circuit is further configured to obtain a reference clock difference between the first synchronous clock and the second synchronous clock, and control configuration parameters of the phase-locked loop circuit based on the reference clock difference.

3. The clock circuit according to claim 2, characterized in that: The control circuit comprises a phase detector and an adjustment module, wherein the phase detector is connected to the adjustment module; The phase detector is used to output a deviation signal based on the first synchronous clock and the second synchronous clock, wherein the deviation signal indicates a reference clock difference between the first synchronous clock and the second synchronous clock; The adjustment module is used to obtain adjusted configuration parameters based on the reference clock difference when the reference clock difference indicated by the deviation signal is greater than a difference threshold, and send the adjusted configuration parameters to the phase-locked loop circuit.

4. The clock circuit according to claim 3, characterized in that: The adjustment module is used to determine the adjustment amplitude based on the reference clock difference and the corresponding relationship, and adjust the configuration parameters of the phase-locked loop circuit according to the adjustment amplitude to obtain the adjusted configuration parameters. The corresponding relationship indicates the relationship between the clock deviation and the adjustment amplitude.

5. The clock circuit according to claim 3, characterized in that: When the phase-locked loop circuit is an integer phase-locked loop, the adjusted configuration parameters include an integer frequency division ratio; when the phase-locked loop circuit is a fractional phase-locked loop, the adjusted configuration parameters include an integer frequency division ratio and a fractional frequency division ratio.

6. The clock circuit according to any one of claims 3 to 5, characterized in that: The time information includes a periodic timestamp and a multiple coefficient; The control circuit further includes a first frequency divider, which is connected to the phase detector and is used to divide the second clock based on the periodic timestamp to obtain the first synchronous clock; The negative feedback circuit includes a second frequency divider, which is connected to the phase detector and is used to divide the first clock based on the multiple coefficient to obtain the second synchronous clock.

7. The clock circuit according to any one of claims 3 to 5, characterized in that: The phase detector is connected to the adjustment module via a low-pass filter; The low-pass filter is used to smooth the deviation signal and output the smoothed deviation signal to the adjustment module.

8. The clock circuit according to any one of claims 3 to 5, characterized in that: The control circuit further comprises an enabling circuit, wherein the enabling circuit is connected to the phase detector; The enabling circuit is used to enable the data stream to be transmitted through the first clock when the reference clock difference indicated by the deviation signal meets the enabling condition, and the enabling condition is that the reference clock difference is less than or equal to the difference threshold within a continuous reference time period.

9. A signal receiving end, comprising the clock circuit according to any one of claims 1 to 8.

10. An electronic device, comprising the signal receiving end according to claim 9.

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