Clock system and decentralized control system

Abstract

The utility model provides a clock system and dispersion control system, this clock system includes: clock antenna, switching device, main server and slave server, clock antenna, when being powered, clock synchronization signal is transmitted to switching device, switching device, when main server is in normal state, signal connection with main server is established, to clock synchronization signal is transmitted to main server, and after main server switches from normal state to abnormal state, signal connection with slave server is established, to clock synchronization signal is transmitted to slave server, main server, when main server is in normal state, clock data is calibrated based on clock synchronization signal, and the clock data after calibration is sent to target bus, slave server, after main server switches from normal state to abnormal state, clock data is calibrated based on clock synchronization signal, and the clock data after calibration is sent to target bus. This scheme can improve the stability and accuracy of clock system.

Description

Technical Field

[0001] This utility model relates to the field of clock synchronization technology, and in particular to a clock system and a distributed control system. Background Technology

[0002] In industrial settings such as power plants, clock systems can be used to synchronize the clocks of various DCS devices in a distributed control system (DCS) to ensure stable operation of the DCS.

[0003] The current clock system includes an antenna for providing a standard time source, a first server, and a second server. The antenna is connected to the first server, which provides power to the antenna and sends clock information to each DCS device based on the clock signal received from the antenna to synchronize the clocks of each DCS device. When the first server malfunctions, the second server uses its internal crystal oscillator to perform timing, thus synchronizing the clocks of each DCS device in place of the first server.

[0004] However, when the first server malfunctions, the second server relies on its own internal crystal oscillator for clock synchronization. Over time, this leads to significant clock deviations, resulting in poor stability and accuracy of the clock system. Utility Model Content

[0005] To address the issue of low clock accuracy in clock systems, this invention provides a clock system and a distributed control system that can improve the clock accuracy of the clock system.

[0006] According to a first aspect of the embodiments of this application, an embodiment of this application provides a clock system, the clock system comprising: a clock antenna, a switching device, a master server, and a slave server; the clock antenna is connected to the switching device and transmits a clock synchronization signal to the switching device when powered; the switching device is connected to the master server and the slave server, and when the master server is in a normal state, establishes a signal connection with the master server to transmit the clock synchronization signal to the master server, and after the master server switches from the normal state to an abnormal state, establishes a signal connection with the slave server to transmit the clock synchronization signal. The clock data is transmitted to the slave server. When the master server is in a normal state, it calibrates the clock data generated by the master server based on the received clock synchronization signal and sends the calibrated clock data to the target bus included in the distributed control system. Multiple devices are connected to the target bus, and the target bus synchronizes the time of the multiple devices based on the received calibrated clock data. After the master server switches from the normal state to the abnormal state, the slave server calibrates the clock data generated by the slave server based on the received clock synchronization signal and sends the calibrated clock data to the target bus.

[0007] In one possible implementation, the switching device includes a signal switching mechanism. The switching device is connected to the master server via a first signal line group, and the switching device is connected to the slave server via a second signal line group. When the master server is in the normal state, the signal switching mechanism connects to the first signal line group to establish a signal connection between the switching device and the master server. After the master server switches from the normal state to the abnormal state, the mechanism disconnects from the first signal line group and connects to the second signal line group to disconnect the signal connection between the switching device and the master server and establish a signal connection between the switching device and the slave server.

[0008] In one possible implementation, a third signal line group is connected between the clock antenna and the signal switching mechanism; the clock antenna transmits the clock synchronization signal to the signal switching mechanism through the third signal line group.

[0009] In one possible implementation, the switching device establishes a power supply connection with the master server when the master server is in a normal state, and disconnects the power supply connection with the master server and establishes a power supply connection with the slave server after the master server switches from the normal state to the abnormal state. The master server, when in a normal state, provides power to the switching device through the power supply connection with the master server. The slave server, after the master server switches from the normal state to the abnormal state, provides power to the switching device through the power supply connection with the slave server. The switching device, after receiving the power supply voltage, transmits the power supply voltage to the clock antenna to power the clock antenna.

[0010] In one possible implementation, the switching device further includes a power switching mechanism. The switching device is connected to the master server via a first power line group, and the switching device is connected to the slave server via a second power line group. When the master server is in a normal state, the power switching mechanism connects to the first power line group to establish a power supply connection between the switching device and the master server. After the master server switches from the normal state to the abnormal state, the mechanism disconnects from the first power line group and connects to the second power line group to disconnect the power supply connection with the master server and establish a power supply connection with the slave server.

[0011] In one possible implementation, a third power line group is connected between the clock antenna and the power switching mechanism; the power switching mechanism, after being supplied with the power supply voltage, transmits the power supply voltage to the clock antenna through the third power line group.

[0012] In one possible implementation, the power switching mechanism sends a switching signal to the signal switching mechanism after the master server switches from the normal state to the abnormal state; the signal switching mechanism is further configured to determine that the master server is in the normal state when it does not receive the switching signal, and to determine that the master server switches from the normal state to the abnormal state after receiving the switching signal.

[0013] In one possible implementation, a status signal transmission line is connected between the master server and the power switching mechanism; when the master server is in a normal state, it sends a status signal to the power switching mechanism through the status signal transmission line, and when the master server is in an abnormal state, it stops sending the status signal to the power switching mechanism through the status signal transmission line; when the power switching mechanism receives the status signal, it determines that the master server is in a normal state, and when it does not receive the status signal, it determines that the master server switches from the normal state to the abnormal state.

[0014] In one possible implementation, a data transmission cable connects the master server and the slave server; the slave server periodically obtains status data from the master server through the data transmission cable to indicate whether the master server is in a normal state, and determines whether the master server is in a normal or abnormal state based on the status data.

[0015] According to a second aspect of the embodiments of this application, a distributed control system is provided, comprising: a clock system and a target bus as described in the first aspect or any implementation thereof; the clock system, including the master server and the slave server, are respectively connected to the target bus; a plurality of devices are mounted on the target bus, and the target bus performs time synchronization on the plurality of devices based on received calibrated clock data.

[0016] The above technical solution employs a clock system including a clock antenna, a switching device, a master server, and a slave server. When the master server is in a normal state, the switching device establishes a signal connection with the master server and transmits the clock synchronization signal sent by the clock antenna to the master server, enabling the master server to send calibrated clock data to the target bus. When the master server is in an abnormal state, the switching device establishes a signal connection with the slave server and transmits the clock synchronization signal sent by the clock antenna to the slave server, enabling the slave server to send calibrated clock data to the target bus. Therefore, regardless of whether the master server is abnormal, the calibrated clock data output by the clock system is obtained based on the clock synchronization signal transmitted by the clock antenna. Compared to a scheme where the slave server relies on its internal crystal oscillator to generate clock data when the master server is abnormal, this invention still determines the calibrated clock data based on the clock synchronization signal output by the clock antenna even when the master server is abnormal, reducing clock deviation and improving the stability and accuracy of the clock system. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a distributed control system provided in an embodiment of this application;

[0018] Figure 2 This is a schematic diagram of a clock system provided in an embodiment of this application;

[0019] Figure 3 This is a schematic diagram of a distributed control system provided in an embodiment of this application.

[0020] List of reference numerals in the attached diagram:

[0021] Detailed Implementation

[0022] As mentioned earlier, in industrial settings such as power plants, clock systems can be used to synchronize the clocks of various DCS devices within a Distributed Control System (DCS) to ensure stable DCS operation. Current clock systems typically include an antenna providing a standard time source, a first server, and a second server. The antenna is connected to the first server, which powers the antenna and sends clock information to each DCS device based on the clock signal received from the antenna, thus synchronizing the clocks of all DCS devices. The second server synchronizes the clock based on the first server's clock signal and, in the event of a malfunction in the first server, relies on its internal crystal oscillator for timing, thus synchronizing the clocks of the DCS devices in place of the first server. However, because the second server relies on its own internal crystal oscillator for clock synchronization when the first server malfunctions, significant clock deviations can occur over time, resulting in poor stability and accuracy of the clock system.

[0023] In this embodiment, a clock system comprising a clock antenna, a switching device, a master server, and a slave server is employed. When the master server is in a normal state, the switching device establishes a signal connection with the master server and transmits the clock synchronization signal sent by the clock antenna to the master server, enabling the master server to send calibrated clock data to the target bus. When the master server is in an abnormal state, the switching device establishes a signal connection with the slave server and transmits the clock synchronization signal sent by the clock antenna to the slave server, enabling the slave server to send calibrated clock data to the target bus. Therefore, regardless of whether the master server is abnormal, the calibrated clock data output by the clock system is obtained based on the clock synchronization signal transmitted by the clock antenna. Compared to a scheme where the slave server relies on its internal crystal oscillator to generate clock data when the master server is abnormal, this invention still determines the calibrated clock data based on the clock synchronization signal output by the clock antenna even when the master server is abnormal, reducing clock deviation and improving the stability and accuracy of the clock system.

[0024] The clock system and distributed control system provided in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0025] This application provides a clock system for use in distributed control systems. Figure 1 This is a schematic diagram of a distributed control system provided in an embodiment of this application. Figure 1 As shown, the distributed control system may also include a target bus 200, and a clock system 100 is used to send calibrated clock data to the target bus 200. Multiple devices (all of which are DCS devices in the distributed control system) are connected to the target bus 200. After receiving the calibrated clock data, the target bus 200 can synchronize the time of the multiple devices based on the calibrated clock data.

[0026] In a specific example, the distributed control system is applied to factories such as power plants. Based on this, the target bus 200 can be the factory bus, and the aforementioned multiple devices can all be DCS devices mounted on the factory bus.

[0027] Figure 2 This is a schematic diagram of a clock system provided in an embodiment of this application. For example... Figure 2 As shown, the clock system 100 includes: a clock antenna 101, a switching device 102, a master server 103, and a slave server 104; the clock antenna 101 is connected to the switching device 102 and transmits a clock synchronization signal to the switching device 102 when powered; the switching device 102 is connected to the master server 103 and the slave server 104, and establishes a signal connection with the master server 103 when the master server 103 is in a normal state to transmit the clock synchronization signal to the master server 103, and establishes a signal connection with the slave server 104 after the master server 103 switches from a normal state to an abnormal state to transmit the clock synchronization signal to the slave server 104; the master... Server 103, connected to target bus 200, calibrates the clock data generated by master server 103 based on the received clock synchronization signal when master server 103 is in normal state, and sends the calibrated clock data to target bus 200. Target bus 200 has multiple devices connected to it, and performs time synchronization on the multiple devices based on the received calibrated clock data. Slave server 104, connected to target bus 200, calibrates the clock data generated by slave server 104 based on the received clock synchronization signal after master server 103 switches from normal state to abnormal state, and sends the calibrated clock data to target bus 200.

[0028] The clock synchronization signal can be a Dispersion Compensation Fiber (DCF) signal from the Federal Republic of Germany. When the clock antenna is powered, it can obtain the clock synchronization signal based on the time signal received from a satellite navigation system (such as the BeiDou Navigation Satellite System or the Global Positioning System, GPS). Figure 3 As shown, the master server 103 is connected to the target bus 200, and the slave server 104 is connected to the target bus 200. For example, the master server 103 is connected to the target bus 200 via Ethernet, and the slave server 104 can be connected to the target bus 200 via Ethernet. Both the master server 103 and the slave server 104 can generate clock data by oscillating their own crystal oscillators. The clock data can include time information and transmission protocol information, etc. This application embodiment does not limit this. The calibrated clock data is the clock data obtained after time calibration based on the clock synchronization signal.

[0029] In this embodiment, a clock system 100 including a clock antenna 101, a switching device 102, a master server 103, and a slave server 104 is used. When the master server 103 is in a normal state, the switching device 102 establishes a signal connection with the master server 103 and transmits the clock synchronization signal sent by the clock antenna 101 to the master server 103, so that the master server 103 sends calibrated clock data to the target bus 200. When the master server 103 is in an abnormal state, the switching device 102 establishes a signal connection with the slave server 104 and transmits the clock synchronization signal sent by the clock antenna 101 to the slave server 104, so that the slave server 104 sends calibrated clock data to the target bus 200. As can be seen, regardless of whether the master server 103 is malfunctioning, the calibrated clock data output by the clock system 100 is obtained based on the clock synchronization signal transmitted by the clock antenna 101. Compared with the scheme where the slave server 104 relies on its own internal crystal oscillator to generate clock data when the master server 103 is malfunctioning, the calibrated clock data in this invention is still determined based on the clock synchronization signal output by the clock antenna 101 when the master server 103 is malfunctioning, which reduces clock deviation and improves the stability and accuracy of the clock system 100.

[0030] Furthermore, this invention can improve the integrity of the clock data output by the clock system 100, reduce the possibility of inaccurate timestamps written to the DCS device after the main server 103 malfunctions, and during the output of calibrated clock data from the server 104, maintenance personnel can also troubleshoot and repair the main server 103, thereby improving the maintainability and flexibility of the clock system 100.

[0031] In one possible implementation, such as Figure 2 As shown, the switching device 102 includes a signal switching mechanism 1022. A first signal line group is connected between the switching device 102 and the master server 103, and a second signal line group is connected between the switching device 102 and the slave server 104. When the master server 103 is in a normal state, the signal switching mechanism 1022 connects to the first signal line group to establish a signal connection between the switching device 102 and the master server 103. After the master server 103 switches from a normal state to an abnormal state, the signal switching mechanism 102 disconnects from the first signal line group and connects to the second signal line group to disconnect the signal connection between the switching device 102 and the master server 103 and establish a signal connection between the switching device 102 and the slave server 104.

[0032] In this embodiment of the application, by employing a switching device 102 including a signal switching mechanism 1022, and a first signal line group and a second signal line group used in conjunction with the switching device 102, when the master server 103 is in a normal state, the signal switching mechanism 1022 can synchronize the clock of the master server 103 through the first signal line group, and when the master server 103 is in an abnormal state, the signal switching mechanism 1022 can synchronize the clock of the slave server 104 through the second signal line group, thereby realizing the switching of the signal connection object with the switching device 102 and improving the stability of signal transmission.

[0033] In one possible implementation, such as Figure 2 As shown, a third signal line group is connected between the clock antenna 101 and the signal switching mechanism 1022; the clock antenna 101 transmits a clock synchronization signal to the signal switching mechanism 1022 through the third signal line group. Thus, the clock signal transmission between the clock antenna 101 and the switching device 102 is realized through the third signal line group, thereby improving the stability of signal transmission.

[0034] Optionally, such as Figure 2 As shown, the first signal line group includes a first positive signal line v1 and a first negative signal line v2, the second signal line group includes a second positive signal line v3 and a second negative signal line v4, and the third signal line group includes a third positive signal line v5 and a third negative signal line v6.

[0035] In one specific embodiment, one end of the first positive signal line is connected to the positive port of the clock antenna 101 for outputting the clock synchronization signal, and the other end of the first positive signal line is connected to the positive port of the switching device 102 for receiving the clock synchronization signal; one end of the first negative signal line is connected to the negative port of the clock antenna 101 for outputting the clock synchronization signal, and the other end of the first negative signal line is connected to the negative port of the switching device 102 for receiving the clock synchronization signal; one end of the second positive signal line is connected to the positive port of the switching device 102 for outputting the clock synchronization signal, and the other end of the second positive signal line is connected to the positive port of the main server 103 for receiving the clock synchronization signal. The first negative signal line is connected to the negative port of the switching device 102 for outputting the clock synchronization signal, and the other end of the second negative signal line is connected to the negative port of the master server 103 for receiving the clock synchronization signal; the second positive signal line is connected to the positive port of the switching device 102 for outputting the clock synchronization signal, and the other end of the third positive signal line is connected to the positive port of the slave server 104 for receiving the clock synchronization signal; the third negative signal line is connected to the negative port of the switching device 102 for outputting the clock synchronization signal, and the other end of the third negative signal line is connected to the negative port of the slave server 104 for receiving the clock synchronization signal.

[0036] In one possible implementation, such as Figure 2 As shown, the switching device 102 establishes a power supply connection with the master server 103 when the master server 103 is in a normal state, and disconnects the power supply connection with the master server 103 and establishes a power supply connection with the slave server 104 after the master server 103 switches from a normal state to an abnormal state. When the master server 103 is in a normal state, it supplies power to the switching device 102 through the power supply connection between the master server 103 and the switching device 102. When the master server 103 switches from a normal state to an abnormal state, it supplies power to the switching device 102 through the power supply connection between the master server 103 and the switching device 104. After receiving the power supply voltage, the switching device 102 transmits the power supply voltage to the clock antenna 101 to power the clock antenna 101.

[0037] The voltage value of the power supply voltage provided by the main server 103 to the switching device 102 is equal to the voltage value of the power supply voltage provided by the server 104 to the switching device 102. The specific value of this voltage value is not limited in this embodiment of the application, but may be 24 volts.

[0038] Therefore, when the master server 103 is in a normal state, the master server 103 can supply power to the clock antenna 101 through the switching device 102. When the master server 103 is in an abnormal state, the slave server 104 can supply power to the clock antenna 101 through the switching device 102. Compared with supplying power to the clock antenna 101 through an external power source, in this application, the clock antenna 101 can be directly supplied through the existing master server 103 and slave server 104 in the clock system 100, which simplifies the structure of the clock system 100 and reduces costs.

[0039] In one possible implementation, such as Figure 2 As shown, the switching device 102 also includes a power switching mechanism 1021. A first power line group is connected between the switching device 102 and the master server 103, and a second power line group is connected between the switching device 102 and the slave server 104. When the master server 103 is in a normal state, the power switching mechanism 1021 is connected to the first power line group to establish a power supply connection between the switching device 102 and the master server 103. After the master server 103 switches from a normal state to an abnormal state, it disconnects from the first power line group and connects to the second power line group to disconnect from the power supply connection with the master server 103 and establishes a power supply connection with the slave server 104.

[0040] In this embodiment, by employing a switching device 102 including a power switching mechanism 1021, and a first power line group and a second power line group used in conjunction with the switching device 102, when the master server 103 is in a normal state, the master server 103 can provide power supply voltage to the power switching mechanism 1021 through the first power line group. When the master server 103 is in an abnormal state, the slave server 104 can provide power supply voltage to the power switching mechanism 1021 through the second power line group. This realizes the switching of the object providing power supply voltage to the switching device 102, and also reduces the possibility that the clock system 100 will not work properly due to the master server 103 malfunctioning and causing the switching device 102 to lose power.

[0041] In one possible implementation, such as Figure 2 As shown, a third power line group is connected between the clock antenna 101 and the power switching mechanism 1021; after being supplied with power supply voltage, the power switching mechanism 1021 transmits the power supply voltage to the clock antenna 101 through the third power line group to power the clock antenna 101.

[0042] The voltage value of the power supply voltage transmitted to the clock antenna 101 is equal to the voltage value of the power supply voltage provided by the master server 103 or the slave server 104.

[0043] Therefore, the third power supply line group provides power to the clock antenna 101, reducing the possibility that the clock antenna 101 will fail to output the clock synchronization signal normally due to the abnormality of the main server 103, and improving the operational stability of the clock antenna 101.

[0044] In one possible implementation, such as Figure 2 As shown, the first power line group includes a first positive line d1 and a first negative line d2, the second power line group includes a second positive line d3 and a second negative line d4, and the third power line group includes a third positive line d5 and a third negative line d6. Taking the above-mentioned power supply voltage of 24 volts as an example, the first positive line d1, the second positive line d3, and the third positive line d5 can all be positive lines used to pass 24 volts of positive voltage, and the first negative line d2, the second negative line d4, and the third negative line d6 can all be negative lines used for grounding.

[0045] Thus, the first positive line and the first negative line provide a transmission line for the power supply voltage output by the main server 103, the second positive line and the second negative line provide a transmission line for the power supply voltage output from the server 104, and the third positive line and the third negative line provide a transmission line for the power supply voltage output by the power switching mechanism 1021, thereby reducing power loss.

[0046] In one possible implementation, such as Figure 2 As shown, the power switching mechanism 1021 sends a switching signal to the signal switching mechanism 1022 after the main server 103 switches from the normal state to the abnormal state; the signal switching mechanism 1022 determines that the main server 103 is in the normal state when it does not receive the switching signal, and determines that the main server 103 switches from the normal state to the abnormal state after receiving the switching signal.

[0047] In this application embodiment, the specific signal type of the switching signal is not limited. For example, the switching signal can be a high-level signal.

[0048] Therefore, after the main server 103 switches from a normal state to an abnormal state, the signal switching mechanism 1022 can automatically determine that the main server 103 has switched states by switching signals, thereby improving efficiency.

[0049] In one possible implementation, such as Figure 2As shown, a status signal transmission line a connects the main server 103 and the power switching mechanism 1021. When the main server 103 is in a normal state, it sends a status signal to the power switching mechanism 1021 through the status signal transmission line. When the main server 103 is in an abnormal state, it stops sending status signals to the power switching mechanism 1021 through the status signal transmission line. When the power switching mechanism 1021 receives a status signal, it determines that the main server 103 is in a normal state. After not receiving a status signal, it determines that the main server 103 switches from the normal state to the abnormal state.

[0050] The status signal can be, for example, a voltage signal, a pulse signal, or other signals. This application does not limit the specific type of status signal.

[0051] Therefore, the power switching mechanism 1021 can automatically determine the working status of the main server 103 through the status signal transmission line, which is convenient and quick, and improves the working efficiency of the clock system 100.

[0052] It should be noted that this application embodiment does not limit the specific method by which the main server 103 determines its own working status. In one example, the main server 103 can determine its own working status in the following way: if the power supply voltage provided by the main server 103 to the power switching mechanism 1021 is within the target voltage range, then the main server 103 is determined to be in a normal state; if the power supply voltage provided by the main server 103 to the power switching mechanism 1021 is less than the minimum value of the target voltage range, then the main server 103 is determined to be in an abnormal state. Here, the voltage value of the aforementioned power supply voltage is within the target voltage range. The target voltage range can be a range value or a single value. For example, if the power supply voltage value is equal to 24 volts, the target voltage range is also 24 volts.

[0053] Based on this, in a specific example, when the main server 103 fails to supply power or cannot provide a sufficiently large supply voltage, the supply voltage sent by the main server 103 to the power switching mechanism 1021 is less than the minimum value of the target voltage range. As a result, the main server 103 can detect that it is in an abnormal state and stop sending status signals to the power switching mechanism 1021, so that the power switching mechanism 1021 disconnects from the first power line and connects to the second power line group.

[0054] In one possible implementation, such as Figure 2 As shown, a data transmission cable (e.g., a data transfer cable) is connected between the master server 103 and the slave server 104. Figure 2(g1 and g2 in the text), the data transmission cable can be an optical fiber cable, etc., and the specific type of data transmission cable is not limited in this application embodiment; the server 104 periodically obtains status data from the main server 103 through the data transmission cable to indicate whether the main server 103 is in a normal state, and determines whether the main server 103 is in a normal state or an abnormal state based on the status data.

[0055] In one specific implementation, the slave server 104 periodically sends status data acquisition requests to the master server 103. In response to these requests, the master server 103 sends status data to the slave server 104. This status data indicates whether the master server 103 is in an abnormal or normal state. If the status data indicates that the master server 103 is in a normal state, the slave server 104 determines that the master server 103 is in a normal state; if the status data indicates that the master server 103 is in an abnormal state, the slave server 104 determines that the master server 103 is in an abnormal state. Furthermore, at the master server 103... In normal state, the slave server 104 can determine that the master server 103 is in normal state by obtaining the status data, and set the priority of the master server 103 to be higher than that of the slave server 104, so that the slave server 104 does not perform the work of receiving clock synchronization signals and outputting power supply voltage. After the master server 103 switches from normal state to abnormal state, the slave server 104 can determine that the master server 103 has switched from normal state to abnormal state, and set the priority of the master server 103 to be lower than that of the slave server 104, so that the slave server 104 performs the work of receiving clock synchronization signals and outputting power supply voltage.

[0056] Therefore, the slave server 104 can determine the working status of the master server 103 through the data transmission cable, so that the slave server 104 can quickly take over the work of the master server 103 when the master server 103 is abnormal, thus improving work efficiency.

[0057] Optionally, the slave server 104 can also synchronize time with the master server 103 via a data transmission cable, so that it can calibrate its own time information, etc., even when the slave server 104 does not receive the clock synchronization signal sent by the clock antenna 101.

[0058] This application also provides a distributed control system, such as Figure 1 As shown, the distributed control system includes: the aforementioned clock system 100 and target bus 200; the clock system 100 includes a master server 103 and a slave server 104, which are respectively connected to the target bus 200; multiple devices are mounted on the target bus 200, and the target bus 200 performs time synchronization on the multiple devices based on the received calibrated clock data.

[0059] The distributed control system has been described in the aforementioned clock system embodiment and will not be repeated here.

[0060] It should be noted that the distributed control system of this embodiment includes the clock system 100 in the aforementioned embodiment and has corresponding beneficial effects, which will not be repeated here.

[0061] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Nouns and pronouns relating to persons in this patent application are not limited to specific genders.

[0062] Not all steps and modules in the above process and system structure diagrams are mandatory; some steps or modules can be omitted as needed. The execution order of each step is not fixed and can be adjusted as required. The system structure described in the above embodiments can be a physical structure or a logical structure. That is, some modules may be implemented by the same physical entity, or some modules may be implemented by multiple physical entities, or they may be jointly implemented by certain components in multiple independent devices.

[0063] In the above embodiments, the hardware modules can be implemented mechanically or electrically. For example, a hardware module may include permanent, dedicated circuitry or logic (such as a dedicated processor, FPGA, or ASIC) to perform the corresponding operations. The hardware module may also include programmable logic or circuitry (such as a general-purpose processor or other programmable processor), which can be temporarily configured by software to perform the corresponding operations. The specific implementation method (mechanical, dedicated, permanent circuitry, or temporarily configured circuitry) can be determined based on cost and time considerations.

[0064] The present invention has been shown and described in detail above with reference to the accompanying drawings and preferred embodiments. However, the present invention is not limited to these disclosed embodiments. Based on the above multiple embodiments, those skilled in the art will know that more embodiments of the present invention can be obtained by combining the code review methods in the different embodiments. These embodiments are also within the protection scope of the present invention.

Claims

1. A clock system (100) applied to a distributed control system, characterized in that, The clock system (100) includes: a clock antenna (101), a switching device (102), a master server (103), and a slave server (104). The clock antenna (101) is connected to the switching device (102) and transmits a clock synchronization signal to the switching device (102) when powered. The switching device (102) is connected to the master server (103) and the slave server (104). When the master server (103) is in a normal state, it establishes a signal connection with the master server (103) to transmit the clock synchronization signal to the master server (103). After the master server (103) switches from the normal state to the abnormal state, it establishes a signal connection with the slave server (104) to transmit the clock synchronization signal to the slave server (104). When the master server (103) is in a normal state, it calibrates the clock data generated by the master server (103) based on the received clock synchronization signal, and sends the calibrated clock data to the target bus (200) included in the distributed control system. The target bus (200) is equipped with multiple devices, and the target bus (200) performs time synchronization on the multiple devices based on the received calibrated clock data. After the master server (103) switches from the normal state to the abnormal state, the slave server (104) calibrates the clock data generated by the slave server (104) based on the received clock synchronization signal and sends the calibrated clock data to the target bus (200).

2. The clock system (100) according to claim 1, characterized in that, The switching device (102) includes a signal switching mechanism (1022), a first signal line group is connected between the switching device (102) and the master server (103), and a second signal line group is connected between the switching device (102) and the slave server (104); When the master server (103) is in the normal state, the signal switching mechanism (1022) connects to the first signal line group to establish a signal connection between the switching device (102) and the master server (103). After the master server (103) switches from the normal state to the abnormal state, the switching device (102) disconnects from the first signal line group and connects to the second signal line group to disconnect the signal connection between the switching device (102) and the master server (103) and establish a signal connection between the switching device (102) and the slave server (104).

3. The clock system (100) according to claim 2, characterized in that, A third signal line group is connected between the clock antenna (101) and the signal switching mechanism (1022); The clock antenna (101) transmits the clock synchronization signal to the signal switching mechanism (1022) through the third signal line group.

4. The clock system (100) according to claim 2, characterized in that, The switching device (102) establishes a power supply connection with the master server (103) when the master server (103) is in a normal state, and disconnects the power supply connection with the master server (103) and establishes a power supply connection with the slave server (104) after the master server (103) switches from the normal state to the abnormal state. When the main server (103) is in normal condition, it provides power supply voltage to the switching device (102) through the power supply connection between the main server (103) and the switching device (102); After the master server (103) switches from the normal state to the abnormal state, the slave server (104) supplies power to the switching device (102) through the power supply connection between the switching device (102) and the slave server (104). The switching device (102), after being supplied with the power supply voltage, transmits the power supply voltage to the clock antenna (101) to power the clock antenna (101).

5. The clock system (100) according to claim 4, characterized in that, The switching device (102) further includes a power switching mechanism (1021). A first power cable group is connected between the switching device (102) and the master server (103), and a second power cable group is connected between the switching device (102) and the slave server (104). When the main server (103) is in a normal state, the power switching mechanism (1021) is connected to the first power line group to establish a power supply connection between the switching device (102) and the main server (103). After the main server (103) switches from the normal state to the abnormal state, it disconnects from the first power line group and connects to the second power line group to disconnect from the power supply connection with the main server (103) and establishes a power supply connection with the slave server (104).

6. The clock system (100) according to claim 5, characterized in that, A third power line group is connected between the clock antenna (101) and the power switching mechanism (1021); After being supplied with the power supply voltage, the power switching mechanism (1021) transmits the power supply voltage to the clock antenna (101) through the third power line group.

7. The clock system (100) according to claim 5, characterized in that, The power switching mechanism (1021) sends a switching signal to the signal switching mechanism (1022) after the main server (103) switches from the normal state to the abnormal state; The signal switching mechanism (1022) is also configured to determine that the master server (103) is in a normal state when the switching signal is not received, and to determine that the master server (103) switches from the normal state to the abnormal state after the switching signal is received.

8. The clock system (100) according to claim 7, characterized in that, A status signal transmission line is connected between the main server (103) and the power switching mechanism (1021); When the main server (103) is in a normal state, it sends a status signal to the power switching mechanism (1021) through the status signal transmission line, and when the main server (103) is in an abnormal state, it stops sending the status signal to the power switching mechanism (1021) through the status signal transmission line. When the power switching mechanism (1021) receives the status signal, it determines that the main server (103) is in a normal state, and when it does not receive the status signal, it determines that the main server (103) switches from the normal state to the abnormal state.

9. The clock system (100) according to any one of claims 1-8, characterized in that, A data transmission cable connects the master server (103) and the slave server (104); The slave server (104) periodically obtains status data from the master server (103) through the data transmission cable to indicate whether the master server (103) is in a normal state, and determines whether the master server (103) is in a normal or abnormal state based on the status data.

10. A distributed control system, characterized in that, include: The clock system (100) and target bus (200) as described in any one of claims 1-9. The clock system (100) includes a master server (103) and a slave server (104) that are respectively connected to the target bus (200); Multiple devices are connected to the target bus (200), and the target bus (200) synchronizes the time of the multiple devices based on the received calibrated clock data.

Images