A discrete-time delta-sigma analog-to-digital converter and method of controlling the same

Abstract

The application discloses a discrete-time incremental analog-to-digital converter and a control method thereof. The analog-to-digital converter comprises a modulator and a digital filter. The modulator comprises an integrator module, a single-bit quantizer, a FIR feedback digital-to-analog converter, a first compensation path and a second compensation path. The control method comprises: performing noise shaping processing on an input signal and an output signal of the single-bit quantizer to obtain a preliminary output signal; and the digital filter is used for performing filtering processing on the preliminary output signal to obtain an output signal of the analog-to-digital converter. The embodiment of the application can reduce hardware consumption and digital power consumption, improve conversion accuracy of the analog-to-digital converter and reduce signal distortion degree of the analog-to-digital converter. The application can be widely applied to the technical field of mixed signal circuits.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of mixed signal circuit, and in particular to a discrete-time delta-sigma analog-to-digital converter and a control method thereof. BACKGROUND

[0002] Single-bit quantization has intrinsic linearity, and the required single-bit digital-to-analog converter is not affected by mismatch, and thus is more suitable for high-precision applications. The difficulty of single-bit quantization is that it introduces a large level step at the input of the loop filter, thus greatly increasing the speed requirement for establishing the amplifier in the first-stage integrator, and further increasing the power consumption of the circuit.

[0003] To solve the above problems caused by single-bit quantization, one of the related technologies is to use an inverter-based amplifier. This type of amplifier greatly reduces the quiescent current of the amplifier under the same driving capability through a dynamic working mode, thereby reducing the power consumption of the circuit. However, due to the lack of a stable quiescent bias point, the performance of the inverter-based amplifier will fluctuate greatly with process, temperature, and power voltage. In addition, the gain of this type of amplifier is low, and it is difficult to meet the design requirements of high-precision delta-sigma modulators of 18 bits or more. Another related technology is to use a FIR digital-to-analog converter. This technology converts a single-bit, large-amplitude feedback signal into a multi-bit, small-amplitude feedback signal by constructing a FIR filter at the feedback branch, thereby greatly reducing the level step at the input of the loop filter. Compared with traditional multi-bit quantization, the device mismatch in the FIR digital-to-analog converter will only cause a change in the transfer function of the digital-to-analog converter, and will not cause nonlinearity, and thus no calibration circuit is required. However, the use of the FIR digital-to-analog converter will change the signal transfer function and the noise transfer function of the original delta-sigma modulator, causing high-frequency spikes on the signal transfer function, thereby amplifying the high-frequency noise in the input signal. The change in the noise transfer function will deviate the noise shaping effect of the modulator from the original design, and weaken the suppression of quantization noise. In addition, since the delta-sigma modulator is obtained by applying a reset to the delta-sigma modulator, the introduction of the FIR DAC in the design of the delta-sigma modulator poses new challenges to the design of the reset logic and the digital filter of the modulator.

[0004] In summary, the technical problems in the related art need to be improved. SUMMARY

[0005] The main purpose of the embodiments of the present application is to provide a discrete-time delta-sigma analog-to-digital converter and a control method thereof, which can reduce hardware consumption and digital power consumption, and improve the conversion accuracy of the analog-to-digital converter and reduce the signal distortion of the analog-to-digital converter.

[0006] To achieve the above object, one aspect of the embodiments of the present application proposes a discrete-time delta-sigma analog-to-digital converter, the analog-to-digital converter comprising a modulator and a digital filter, the modulator comprising an integrator module, a single-bit quantizer, a FIR feedback digital-to-analog converter, a first compensation path and a second compensation path, an output terminal of the modulator being connected with an input terminal of the digital filter, wherein:

[0007] The modulator is configured to perform noise shaping processing on an input signal and an output signal of the single-bit quantizer to obtain a preliminary output signal.

[0008] The digital filter is configured to perform filtering processing on the preliminary output signal to obtain an output signal of the analog-to-digital converter.

[0009] In some embodiments, the integrator module comprises a first-stage integrator, a second-stage integrator, a third-stage integrator and a fourth-stage integrator, an output terminal of the FIR feedback digital-to-analog converter being connected with an input terminal of the first-stage integrator, a first output terminal of the first-stage integrator, an input terminal of the first compensation path and an input terminal of the second-stage integrator being connected with each other, a first output terminal of the second-stage integrator being connected with an input terminal of the third-stage integrator, a first output terminal of the third-stage integrator being connected with an input terminal of the fourth-stage integrator, an output terminal of the fourth-stage integrator, an output terminal of the second compensation path, a second output terminal of the first-stage integrator, a second output terminal of the second-stage integrator and a second output terminal of the third-stage integrator being connected with an input terminal of the single-bit quantizer, an output terminal of the single-bit quantizer being connected with an input terminal of the FIR feedback digital-to-analog converter, an input terminal of the first compensation path and an input terminal of the second compensation path, respectively, wherein:

[0010] The single-bit quantizer is configured to perform quantization processing on an input signal of the single-bit quantizer to obtain an output signal of the single-bit quantizer.

[0011] The FIR feedback digital-to-analog converter is configured to perform conversion processing on the output signal of the single-bit quantizer and subtract the input signal to obtain an input signal of the first-stage integrator.

[0012] The first compensation path is configured to perform conversion processing on the output signal of the single-bit quantizer and subtract an output signal of the first-stage integrator to obtain an input signal of the second-stage integrator.

[0013] The second compensation path is used to convert the output signal of the single-bit quantizer and subtract it from the input signal, the output signal of the first-stage integrator, the output signal of the second-stage integrator, the output signal of the third-stage integrator and the output signal of the fourth-stage integrator to obtain the input signal of the single-bit quantizer.

[0014] In some embodiments, it further includes:

[0015] The first-stage integrator is used to perform integration and noise shaping on the input signal of the first-stage integrator to obtain the output signal of the first-stage integrator;

[0016] The second-stage integrator is used to perform integration and noise shaping on the input signal of the second-stage integrator to obtain the output signal of the second-stage integrator;

[0017] The third-stage integrator is used to perform integration and noise shaping on the input signal of the third-stage integrator to obtain the output signal of the third-stage integrator;

[0018] The fourth-stage integrator is used to perform integration and noise shaping processing on the input signal of the fourth-stage integrator to obtain the output signal of the fourth-stage integrator.

[0019] In some embodiments, the FIR feedback digital-to-analog converter includes a first FIR filter and a first digital-to-analog converter, the first compensation path includes a second FIR filter and a second digital-to-analog converter, and the second compensation path includes a third FIR filter and a third digital-to-analog converter, wherein the output end of the first FIR filter is connected to the input end of the first digital-to-analog converter, the output end of the second FIR filter is connected to the input end of the second digital-to-analog converter, and the output end of the third FIR filter is connected to the input end of the third digital-to-analog converter.

[0020] In some embodiments, the first digital-to-analog converter, the second digital-to-analog converter, and the third digital-to-analog converter are all capacitive digital-to-analog converters composed of switched capacitor circuits, and the first FIR filter, the second FIR filter, and the third FIR filter are all composed of several D flip-flops.

[0021] In some embodiments, the Z-domain transfer function of the first FIR filter is 0.5+0.5Z -1 , the Z-domain transfer function of the second FIR filter is 0.5c1Z -1 , the Z-domain transfer function of the third FIR filter is 0.5a1c1Z -1wherein a1 represents an output feedforward coefficient of the first-stage integrator, and c1 represents an input scaling coefficient of the first-stage integrator.

[0022] In some embodiments, further comprising:

[0023] The first FIR filter is configured to filter the output signal of the single-bit quantizer to obtain a first output digital code.

[0024] The first digital-to-analog converter is configured to convert the first output digital code to obtain a first output analog signal.

[0025] The second FIR filter is configured to filter the output signal of the single-bit quantizer to obtain a second output digital code.

[0026] The second digital-to-analog converter is configured to convert the second output digital code to obtain a second output analog signal.

[0027] The third FIR filter is configured to filter the output signal of the single-bit quantizer to obtain a third output digital code.

[0028] The third digital-to-analog converter is configured to convert the third output digital code to obtain a third output analog signal.

[0029] In some embodiments, the digital filter comprises a digital integrator module and a gain unit, the digital integrator module comprises a first-stage digital integrator, a second-stage digital integrator, a third-stage digital integrator, and a fourth-stage digital integrator, the first-stage digital integrator, the second-stage digital integrator, the third-stage digital integrator, the fourth-stage digital integrator, and the gain unit are connected in sequence, wherein:

[0030] The digital integrator module is configured to integrate the preliminary output signal to obtain an output signal of the digital integrator module.

[0031] The gain unit is configured to amplify the output signal of the digital integrator module to obtain an output signal of the analog-to-digital converter.

[0032] To achieve the above object, another aspect of the embodiment of the present application proposes a control method of a discrete-time delta-sigma analog-to-digital converter, the method comprising:

[0033] Performing noise shaping on the input signal and the output signal of the single-bit quantizer to obtain a preliminary output signal.

[0034] Filtering the preliminary output signal to obtain an output signal of the analog-to-digital converter.

[0035] In some embodiments, the noise shaping processing on the input signal and the output signal of the single-bit quantizer obtains a preliminary output signal, comprising:

[0036] Obtaining the input signal and the output signal of the single-bit quantizer;

[0037] Converting the output signal of the single-bit quantizer and subtracting the input signal to obtain the input signal of the first integrator;

[0038] Converting the output signal of the single-bit quantizer and subtracting the output signal of the first integrator to obtain the input signal of the second integrator;

[0039] Converting the output signal of the single-bit quantizer and subtracting the input signal, the output signal of the first integrator, the output signal of the second integrator, the output signal of the third integrator and the output signal of the fourth integrator to obtain the input signal of the single-bit quantizer;

[0040] Quantizing the input signal of the single-bit quantizer to obtain the preliminary output signal.

[0041] The embodiments of the present application at least have the following beneficial effects: the present application provides a discrete-time delta-sigma analog-to-digital converter and a control method thereof, the scheme introduces a FIR feedback digital-to-analog converter, a first compensation path and a second compensation path, and a digital filter, adopts a delta-sigma modulator of the FIR feedback digital-to-analog converter, resets the integrator, the FIR feedback path and the two compensation paths, realizes compensation of the FIR feedback, the compensation path eliminates the signal transfer function peak introduced by the FIR feedback digital-to-analog converter, restores the noise transfer function, realizes higher conversion precision, the digital filter simplifies the design of the digital filter, reduces hardware consumption and digital power consumption, and further reduces signal distortion of the analog-to-digital converter. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 is a structure schematic diagram of a discrete-time delta-sigma analog-to-digital converter provided by the embodiments of the present application;

[0043] Figure 2 is a step schematic diagram of a control method of a discrete-time delta-sigma analog-to-digital converter provided by the embodiments of the present application;

[0044] Figure 3 is a comparison schematic diagram of modulator signals before and after compensation provided by the embodiments of the present application;

[0045] Figure 4is a comparison diagram of pre and post compensation noise transfer function provided by the embodiment of the present application;

[0046] Figure 5 is a timing diagram of reset signal provided by the embodiment of the present application;

[0047] Figure 6 is a structure diagram of traditional digital filter provided by the embodiment of the present application;

[0048] Figure 7 is a structure diagram of simplified digital filter provided by the embodiment of the present application;

[0049] Figure 8 is a diagram of output spectrum of FIR feedback fourth order delta sigma analog to digital converter without enabling provided by the embodiment of the present application;

[0050] Figure 9 is a diagram of output spectrum of FIR feedback fourth order delta sigma analog to digital converter with enabling provided by the embodiment of the present application;

[0051] Figure 10 is a diagram of output swing comparison of first stage integrator without FIR feedback provided by the embodiment of the present application;

[0052] Figure 11 is a diagram of output swing comparison of first stage integrator with FIR feedback provided by the embodiment of the present application.

[0053] Reference signs: 100, FIR feedback digital to analog converter; 101, first digital to analog converter; 102, first FIR filter; 103, first node; 110, first compensation path; 111, second digital to analog converter; 112, second FIR filter; 113, second node; 120, second compensation path; 121, third digital to analog converter; 122, third FIR filter; 123, third node; 140, single bit quantizer; 131, first stage integrator; 132, second stage integrator; 133, third stage integrator; 134, fourth stage integrator; 201, first stage digital integrator; 202, second stage digital integrator; 203, third stage digital integrator; 204, fourth stage digital integrator; 205, gain unit. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application is further described in detail below in combination with the drawings and examples. It should be understood that the specific examples described herein are only used to explain the present application and are not used to limit the present application. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following example embodiments do not represent all implementations consistent with embodiments of the present application. They are merely examples of systems and methods consistent with some aspects of the embodiments of the present application as detailed in the appended claims.

[0055] It can be understood that the terms "first", "second", and the like as used in the present application can be used herein to describe various concepts, but unless specifically stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of the present application, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as the first information. Depending on the context, the word "if" as used herein can be interpreted as "when" or "upon" or "in response to a determination".

[0056] The terms "at least one", "multiple", "each", "any", and the like used in the present application include one, two or more, multiple includes two or more, and each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0058] Before the embodiments of the present application are described in detail, first, some nouns and terms involved in the embodiments of the present application are described, and the nouns and terms involved in the embodiments of the present application are applicable to the following explanations.

[0059] As a bridge between the analog domain and the digital domain, the analog-to-digital converter occupies an important position in the field of mixed-signal integrated circuits and even the entire integrated circuit field. In the application of electroencephalogram / electrocardiogram signal acquisition, new energy automobile battery management system and geological exploration, the analog-to-digital converter is often required to have high conversion precision, and the requirement for conversion speed is relatively low. For these applications, the discrete-time delta-sigma analog-to-digital converter is widely used due to its low in-band noise, easy multiplexing, small conversion delay and good robustness.

[0060] A discrete-time incremental analog-to-digital converter (ADC) consists of a discrete-time delta-sigma modulator, a reset circuit, and a digital filter. The modulator, in turn, includes a switched-capacitor integrator based on an active op amp, a quantizer, and a feedback digital-to-analog converter. The quantizer can be categorized as either multi-bit or single-bit. Each additional bit reduces quantization noise by 6dB, but multi-bit quantization requires a multi-bit feedback digital-to-analog converter (DAC). This converter can produce severe nonlinearity due to mismatch errors in circuit manufacturing, requiring additional calibration circuitry. In contrast, single-bit quantization is inherently linear, and the required single-bit DAC is unaffected by mismatch, making it more suitable for high-precision applications. A challenge with single-bit quantization is that it introduces large level steps at the input of the loop filter, significantly increasing the settling speed requirements of the amplifier in the first-stage integrator and, in turn, increasing circuit power consumption.

[0061] There are some shortcomings in the related technology. For example, the gain of the inverter-based amplifier is low, which makes it difficult to meet the design requirements of high-precision Delta-Sigma modulators above 18 bits. By constructing an FIR filter at the feedback branch, the signal transfer function and noise transfer function of the original Delta-Sigma modulator will be changed, causing high-frequency spikes in the signal transfer function, thereby amplifying the high-frequency noise in the input signal; the change in the noise transfer function will cause the noise shaping effect of the modulator to deviate from the original design, weakening the suppression of quantization noise.

[0062] In view of this, a discrete-time incremental analog-to-digital converter is provided in an embodiment of the present application. By designing and introducing a FI R feedback digital-to-analog converter, a first compensation path, a second compensation path, and a digital filter, the output voltage swing of the first-stage integrator in the incremental analog-to-digital converter can be greatly reduced, and the circuit distortion can be significantly reduced; the design of the digital filter is simplified, and hardware consumption and digital power consumption are reduced.

[0063] Reference Figure 1 , Figure 1 A flowchart of a discrete time incremental analog-to-digital converter provided by an embodiment of the present invention, referring to Figure 1 The analog-to-digital converter includes a modulator and a digital filter. The modulator includes an integrator module, a single-bit quantizer 140, a FIR feedback digital-to-analog converter 100, a first compensation path 110, and a second compensation path 120. The output of the modulator is connected to the input of the digital filter, wherein:

[0064] The modulator is used to perform noise shaping processing on the input signal and the output signal of the single-bit quantizer to obtain a preliminary output signal;

[0065] It needs to be further explained that the integrator module comprises a first integrator 131, a second integrator 132, a third integrator 133 and a fourth integrator 134, the output end of the FIR feedback digital-to-analog converter is connected with the input end of the first integrator, the first output end of the first integrator and the input end of the first compensation path are connected with the input end of the second integrator, the first output end of the second integrator is connected with the input end of the third integrator, the first output end of the third integrator is connected with the input end of the fourth integrator, the output end of the fourth integrator, the output end of the second compensation path, the second output end of the first integrator, the second output end of the second integrator and the second output end of the third integrator are connected with the input end of the single-bit quantizer, and the output end of the single-bit quantizer is respectively connected with the input end of the FIR feedback digital-to-analog converter, the input end of the first compensation path and the input end of the second compensation path, wherein: the first integrator is used for integrating and noise shaping the input signal of the first integrator to obtain the output signal of the first integrator; the second integrator is used for integrating and noise shaping the input signal of the second integrator to obtain the output signal of the second integrator; the third integrator is used for integrating and noise shaping the input signal of the third integrator to obtain the output signal of the third integrator; and the fourth integrator is used for integrating and noise shaping the input signal of the fourth integrator to obtain the output signal of the fourth integrator.

[0066] Further, the single-bit quantizer is used for quantizing the input signal of the single-bit quantizer to obtain the output signal of the single-bit quantizer;

[0067] Further, the FIR feedback digital-to-analog converter is used for converting the output signal of the single-bit quantizer and subtracting the input signal to obtain the input signal of the first integrator;

[0068] Specifically, the FIR feedback digital-to-analog converter comprises a first FIR filter 102 and a first digital-to-analog converter 101, the first compensation path comprises a second FIR filter 112 and a second digital-to-analog converter 111, and the second compensation path comprises a third FIR filter 122 and a third digital-to-analog converter 121, wherein the output end of the first FIR filter is connected with the input end of the first digital-to-analog converter, the output end of the second FIR filter is connected with the input end of the second digital-to-analog converter, and the output end of the third FIR filter is connected with the input end of the third digital-to-analog converter;

[0069] It needs to be explained that the first digital-to-analog converter, the second digital-to-analog converter and the third digital-to-analog converter are capacitive digital-to-analog converters composed of a switched capacitor circuit, and the first FIR filter, the second FIR filter and the third FIR filter are composed of a plurality of D flip-flops;

[0070] The Z-domain transfer function of the first FIR filter is 0.5 + 0.5Z -1 The Z-domain transfer function of the second FIR filter is 0.5c1Z -1 The Z-domain transfer function of the third FIR filter is 0.5a1c1Z -1 wherein a1 represents an output feedforward coefficient of the first integrator, and c1 represents an input scaling coefficient of the first integrator.

[0071] The first FIR filter is configured to filter the output signal of the single-bit quantizer to obtain a first output digital code; the first digital-to-analog converter is configured to convert the first output digital code to obtain a first output analog signal; the second FIR filter is configured to filter the output signal of the single-bit quantizer to obtain a second output digital code; the second digital-to-analog converter is configured to convert the second output digital code to obtain a second output analog signal; the third FIR filter is configured to filter the output signal of the single-bit quantizer to obtain a third output digital code; and the third digital-to-analog converter is configured to convert the third output digital code to obtain a third output analog signal.

[0072] In this embodiment, the FIR feedback digital-to-analog converter is composed of the first FIR filter and the first digital-to-analog converter, and is configured to convert the output signal of the single-bit quantizer into an analog signal, and subtract the analog signal from the input signal at the first node 103 to form the input of the first integrator. The input of the first FIR filter is connected to the output of the single-bit quantizer, and the output of the first FIR filter is connected to the input of the first digital-to-analog converter. The first FIR filter is composed of a D flip-flop, and is configured to filter the output digital code. The first digital-to-analog converter converts the output digital code of the first FIR filter into an analog output, and the analog output is summed at the first node 103 to enter the first integrator.

[0073] The first compensation path is configured to convert the output signal of the single-bit quantizer and subtract the output signal of the first integrator from the converted output signal to obtain the input signal of the second integrator.

[0074] In this embodiment, the first compensation path is composed of the second FIR filter and the second digital-to-analog converter, and is configured to restore the loop filter transfer function changed by the FIR feedback digital-to-analog converter. The input of the second FIR filter is connected to the output of the single-bit quantizer, and the output of the second FIR filter is connected to the input of the second digital-to-analog converter. The second FIR filter is composed of a D flip-flop, and is configured to filter the output digital code. The second digital-to-analog converter converts the output digital code of the second FIR filter into an analog output, and the analog output is summed at the second node 113 to enter the second integrator.

[0075] The second compensation path is used to convert the output signal of the single-bit quantizer and subtract the input signal, the output signal of the first-stage integrator, the output signal of the second-stage integrator, the output signal of the third-stage integrator and the output signal of the fourth-stage integrator, to obtain the input signal of the single-bit quantizer.

[0076] In the embodiment, the second compensation path is composed of a third FIR filter and a third digital-to-analog converter, and is responsible for restoring the loop filter transfer function changed by the FIR feedback digital-to-analog converter. The input of the third FIR filter is connected with the output of the single-bit quantizer, and the output of the third FIR filter is connected with the input of the third digital-to-analog converter. The third FIR filter is composed of a D flip-flop, and completes the filtering function of the output digital code. The third digital-to-analog converter converts the output digital code of the third FIR filter into an analog output, which is summed at the third node 123 and enters the single-bit quantizer.

[0077] The digital filter is used to filter the preliminary output signal to obtain the output signal of the analog-to-digital converter.

[0078] The digital filter includes a digital integrator module and a gain unit 205, the digital integrator module includes a first-stage digital integrator 201, a second-stage digital integrator 202, a third-stage digital integrator 203 and a fourth-stage digital integrator 204, and the first-stage digital integrator, the second-stage digital integrator, the third-stage digital integrator, the fourth-stage digital integrator and the gain unit are connected in sequence, wherein:

[0079] The digital integrator module is used to integrate the preliminary output signal to obtain the output signal of the digital integrator module;

[0080] The gain unit is used to amplify the output signal of the digital integrator module to obtain the output signal of the analog-to-digital converter.

[0081] In the embodiment, Figure 7 The figure of the digital filter used by the analog-to-digital converter is given, which completes the decimation filtering function of the modulator output. The digital filter 200 includes a first-stage digital integrator, a second-stage digital integrator, a third-stage digital integrator, a fourth-stage digital integrator and a gain unit. The input of the first-stage digital integrator is connected with the output of the single-bit quantizer, and the output of the first-stage digital integrator is connected with the input of the second-stage digital integrator. The output of the second-stage digital integrator is connected with the input of the third-stage digital integrator. The output of the third-stage digital integrator is connected with the input of the fourth-stage digital integrator. The output of the fourth-stage digital integrator is connected with the input of the gain unit. The gain unit provides the final output of the analog-to-digital converter.

[0082] Please refer to Figure 2 The embodiment of the application further provides a control method of the discrete-time delta-sigma analog-to-digital converter, which can realize the above discrete-time delta-sigma analog-to-digital converter, and the system comprises:

[0083] S100, performing noise shaping processing on the input signal and the output signal of the single-bit quantizer to obtain a preliminary output signal;

[0084] It should be noted that in some embodiments, the step S100 can comprise: S110, acquiring the input signal and the output signal of the single-bit quantizer; S120, performing conversion processing on the output signal of the single-bit quantizer and subtracting the input signal to obtain the input signal of the first integrator; S130, performing conversion processing on the output signal of the single-bit quantizer and subtracting the output signal of the first integrator to obtain the input signal of the second integrator; S140, performing conversion processing on the output signal of the single-bit quantizer and subtracting the input signal, the output signal of the first integrator, the output signal of the second integrator, the output signal of the third integrator and the output signal of the fourth integrator to obtain the input signal of the single-bit quantizer; S150, performing quantization processing on the input signal of the single-bit quantizer to obtain the preliminary output signal.

[0085] S200, performing filtering processing on the preliminary output signal to obtain the output signal of the analog-to-digital converter;

[0086] It should be noted that the application proposes a digital filter suitable for a FIR feedback digital-to-analog converter delta-sigma modulator, which is used to Figure 1 The specific principle is analyzed as follows by taking the modulator in the application as an example.

[0087] The output x1[m] of the first integrator at the mth clock cycle is:

[0088]

[0089] Wherein U[i] is the input signal at the ith clock cycle, and V[i] is the output of the quantizer at the ith clock cycle. Similarly, the outputs of the second to fourth integrators are obtained as follows:

[0090]

[0091]

[0092]

[0093] Note that U[i] can be considered as a constant due to over-sampling. Then the output of the fourth integrator can be expressed as

[0094]

[0095] where the coefficients are Then, according to the relationship between the analog input and the digital output, it can be obtained that in order to recover the correct analog input from the single-bit output, the structure of the conventional digital filter is as shown in Figure 6 which is composed of a first-order FIR filter, a fourth-order integrator, a third-order integrator and a summation circuit.

[0096] Further simplifying the relationship between the analog input and the digital output, it can be obtained that

[0097]

[0098] Thus, the digital filter used by the delta-sigma analog-to-digital converter proposed in the present application is obtained, as shown in Figure 7 The filter is a simple fourth-order cascaded integrator type filter, which, compared with Figure 6 , omits three digital integrators and an FIR filter.

[0099] In summary, the present application introduces two compensation paths, i.e., a first compensation path and a second compensation path, at the output of the first integrator and the input of the single-bit quantizer, the Z-domain transfer functions of the first compensation path and the second compensation path are 0.5c1Z -1 and 0.5a1c1Z -1 respectively, which realize compensation for the FIR feedback; the transfer functions are also realized by D flip-flop circuits, wherein a1 is the output feedforward coefficient of the first integrator, and c1 is the input scaling coefficient of the first integrator. Figure 1 A behavioral level schematic diagram is given taking a fourth-order delta-sigma modulator as an example. Figure 3 and Figure 4 Signal transfer functions and noise transfer functions of the modulator with and without compensation paths are given. As can be seen from the figures, the compensation paths eliminate the signal transfer function peak introduced by the FIR feedback analog-to-digital converter, and restore the noise transfer function, realizing higher conversion accuracy.

[0100] Further, the application proposes a reset strategy for the above-mentioned delta-sigma modulator. The traditional delta-sigma modulator only resets the integrator. For the delta-sigma modulator with FIR feedback D / A converter proposed by the application, the integrator, the FIR feedback path and the two compensation paths are all reset, and the reset signal RSTN2 of the FIR feedback path and the two compensation paths is delayed by one modulator clock cycle compared with the reset signal RSTN1 of the integrator, so that the modulator is completely reset after each conversion, and the information of the current conversion is avoided to be reserved for the next conversion. The timing diagram of the reset signal is shown in Figure 5 .

[0101] Finally, the design method proposed by the application is verified by a fourth-order single-bit quantization delta-sigma ADC with a sampling clock frequency of 10.24MHz and a bandwidth of 20kHz. Figure 8 And Figure 9 the output spectrum of the delta-sigma ADC without enabling the FIR feedback is compared with that of the delta-sigma ADC with enabling the FIR feedback under the same power consumption; the former has SNR=105.6dB and SNDR=99.7dB, and the latter has SNR=109.2dB and SNDR=106.3dB; the introduction of the FIR feedback and the compensation branch increases the SNDR of the circuit by 6.6dB. The FIR feedback ADC reduces the level step value of the feedback signal, as shown in Figure 10 and Figure 11 , reduces the nonlinearity in the establishment process of the switched-capacitor integrator, and thus significantly reduces the distortion of the ADC, and the designed compensation branch ensures that the modulator still has good noise shaping ability after the introduction of the FIR feedback, so that the modulator has high SNR; finally, the digital filter proposed by the application completes the filtering of the output of the modulator with very small hardware consumption, and obtains the correct output signal.

[0102] It can be understood that the contents in the above-mentioned method embodiments are all applicable to the system embodiments, the system embodiments specifically realize the same functions as the above-mentioned method embodiments, and achieve the same beneficial effects as the above-mentioned method embodiments.

[0103] The preferred embodiments of the application are described above with reference to the accompanying drawings, and the scope of the right of the application is not limited by this. Any modification, equivalent replacement and improvement made by those skilled in the art without departing from the scope and essence of the application should be within the scope of the right of the application.

Claims

1. A discrete-time increment-type analog-to-digital converter, characterized by, The analog-to-digital converter comprises a modulator and a digital filter, the modulator comprises an integrator module, a single-bit quantizer, a FIR feedback digital-to-analog converter, a first compensation path and a second compensation path, an output end of the modulator is connected with an input end of the digital filter, wherein: The modulator is used for noise shaping processing of an input signal and an output signal of the single-bit quantizer to obtain a preliminary output signal; The digital filter is used for filtering processing of the preliminary output signal to obtain an output signal of the analog-to-digital converter; The integrator module comprises a first-stage integrator, a second-stage integrator, a third-stage integrator and a fourth-stage integrator, an output end of the FIR feedback digital-to-analog converter is connected with an input end of the first-stage integrator, a first output end of the first-stage integrator, an input end of the first compensation path and an input end of the second-stage integrator are connected with an input end of the second-stage integrator, a first output end of the second-stage integrator is connected with an input end of the third-stage integrator, a first output end of the third-stage integrator is connected with an input end of the fourth-stage integrator, an output end of the fourth-stage integrator, an output end of the second compensation path, a second output end of the first-stage integrator, a second output end of the second-stage integrator and a second output end of the third-stage integrator are connected with an input end of the single-bit quantizer, an output end of the single-bit quantizer is connected with an input end of the FIR feedback digital-to-analog converter, an input end of the first compensation path and an input end of the second compensation path, wherein: The single-bit quantizer is used for quantization processing of an input signal of the single-bit quantizer to obtain an output signal of the single-bit quantizer; The FIR feedback digital-to-analog converter is used for conversion processing of the output signal of the single-bit quantizer and subtraction with the input signal to obtain an input signal of the first-stage integrator; The first compensation path is used for conversion processing of the output signal of the single-bit quantizer and subtraction with an output signal of the first-stage integrator to obtain an input signal of the second-stage integrator; The second compensation path is used for conversion processing of the output signal of the single-bit quantizer and subtraction with the input signal, the output signal of the first-stage integrator, the output signal of the second-stage integrator, the output signal of the third-stage integrator and the output signal of the fourth-stage integrator to obtain an input signal of the single-bit quantizer.

2. The analog-to-digital converter of claim 1, wherein, Further comprising: The first-stage integrator is used for integration and noise shaping processing of an input signal of the first-stage integrator to obtain an output signal of the first-stage integrator; The second-stage integrator is used for integration and noise shaping processing of an input signal of the second-stage integrator to obtain an output signal of the second-stage integrator; The third-stage integrator is used for integration and noise shaping processing of an input signal of the third-stage integrator to obtain an output signal of the third-stage integrator; The fourth-stage integrator is used for integration and noise shaping processing of an input signal of the fourth-stage integrator to obtain an output signal of the fourth-stage integrator. The fourth-stage integrator is configured to integrate and noise-shape an input signal of the fourth-stage integrator to obtain an output signal of the fourth-stage integrator.

3. The analog-to-digital converter of claim 1, wherein, The FIR feedback digital-to-analog converter comprises a first FIR filter and a first digital-to-analog converter, the first compensation path comprises a second FIR filter and a second digital-to-analog converter, and the second compensation path comprises a third FIR filter and a third digital-to-analog converter, wherein an output terminal of the first FIR filter is connected with an input terminal of the first digital-to-analog converter, an output terminal of the second FIR filter is connected with an input terminal of the second digital-to-analog converter, and an output terminal of the third FIR filter is connected with an input terminal of the third digital-to-analog converter.

4. The analog-to-digital converter of claim 3, wherein, The first digital-to-analog converter, the second digital-to-analog converter and the third digital-to-analog converter are capacitive digital-to-analog converters composed of switched-capacitor circuits, and the first FIR filter, the second FIR filter and the third FIR filter are composed of a plurality of D flip-flops.

5. The analog-to-digital converter of claim 3, wherein, The Z-domain transfer function of the first FIR filter is The Z-domain transfer function of the second FIR filter is The Z-domain transfer function of the third FIR filter is wherein denotes an output feedforward coefficient of the first integrator stage, denotes an input scaling coefficient of the first integrator stage.

6. The analog-to-digital converter of claim 3, wherein, Further comprising: The first FIR filter is configured to filter an output signal of the single-bit quantizer to obtain a first output digital code; The first digital-to-analog converter is configured to convert the first output digital code to obtain a first output analog signal; The second FIR filter is configured to filter an output signal of the single-bit quantizer to obtain a second output digital code; The second digital-to-analog converter is configured to convert the second output digital code to obtain a second output analog signal; The third FIR filter is configured to filter an output signal of the single-bit quantizer to obtain a third output digital code; The third digital-to-analog converter is configured to convert the third output digital code to obtain a third output analog signal.

7. The analog-to-digital converter of claim 1, wherein, The digital filter comprises a digital integrator module and a gain unit, the digital integrator module comprises a first-stage digital integrator, a second-stage digital integrator, a third-stage digital integrator and a fourth-stage digital integrator, and the first-stage digital integrator, the second-stage digital integrator, the third-stage digital integrator, the fourth-stage digital integrator and the gain unit are connected in sequence, wherein: The digital integrator module is configured to integrate the preliminary output signal to obtain an output signal of the digital integrator module; The gain unit is configured to amplify the output signal of the digital integrator module to obtain an output signal of the analog-to-digital converter.

8. A control method for a discrete-time increment A / D converter according to any one of claims 1 to 7, characterized in that The method comprises the following steps: Noise-shaping an input signal and an output signal of a single-bit quantizer to obtain a preliminary output signal; Filtering the preliminary output signal to obtain an output signal of an analog-to-digital converter.

9. The method of claim 8, wherein, The noise-shaping an input signal and an output signal of a single-bit quantizer to obtain a preliminary output signal comprises: Obtaining the input signal and the output signal of the single-bit quantizer; Converting the output signal of the single-bit quantizer and subtracting the input signal to obtain an input signal of a first-stage integrator; The output signal of the single-bit quantizer is converted and subtracted from the output signal of the first integrator to obtain an input signal of a second integrator; The output signal of the single-bit quantizer is converted and subtracted from the input signal, the output signal of the first integrator, the output signal of the second integrator, the output signal of a third integrator and the output signal of a fourth integrator to obtain an input signal of the single-bit quantizer; The input signal of the single-bit quantizer is quantized to obtain the preliminary output signal.

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