Communication method of DFE based on radio frequency front end and DFE communication system

Abstract

The invention provides a DFE communication method based on a radio frequency front end and a DFE communication system. The method comprises the steps of obtaining to-be-processed data, obtaining a target task, performing DFE processing in a semi-parallel mode, and completing scheduling of a base band to the DFE in a multi-task mode. According to the scheme, the problem that in the prior art, the power consumption of the DFE accounts for the power consumption of the whole baseband chip, and the area proportion is high is solved.

Description

Technical Field

[0001] The present application relates to the field of DFE processing technology, and more specifically, to a communication method, device, computer-readable storage medium, computer program product, and DFE communication system based on a radio frequency front-end (RFF). Background Art

[0002] DFE (Digital Front End) is the bridge between the RF front end and the baseband digital signal processing module. The RF transmission frequency is usually in the GHz range, and the baseband signal needs to be modulated by RF to reach the transmission frequency. The baseband of 5G transmitters is usually 100M, and that of 4G is usually 20M. The bandwidth of long-distance communication protocols such as satellites is even lower. In order to ensure the out-of-band suppression, in-band ripple, EVM and other indicators of data sent and received by RF, DFE is required to perform digital signal processing on the signal to meet the signal quality requirements of the transmitter and receiver.

[0003] When designing DFE, the inventors of the present application found that the power consumption of DFE accounts for a relatively high proportion of the power consumption and area of ​​the entire baseband chip, and therefore a solution that can reduce the power consumption of DFE is urgently needed. Summary of the invention

[0004] The present application relates to the field of DFE processing technology, and more specifically, to a communication method, device, computer-readable storage medium, computer program product and DFE communication system based on a radio frequency front end, so as to at least solve the problem in the prior art that the power consumption of DFE accounts for a relatively high proportion of the power consumption and area of ​​the entire baseband chip.

[0005] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a communication method based on a DFE of a radio frequency front end is provided, including: obtaining data to be processed, wherein the data to be processed is received RFIC data or data to be sent by the baseband; obtaining a target task, wherein the target task is a task configured to complete the scheduling of the baseband; performing DFE processing in a semi-parallel manner, and completing the scheduling of the DFE by the baseband in a multi-tasking manner, wherein the semi-parallel and multi-tasking methods are used together to execute the data processing method of the DFE, the DFE processing is to process the data to be processed in a DFE manner, and the scheduling of the DFE by the baseband is to schedule the data to be processed.

[0006] Optionally, after obtaining the data to be processed, the method further includes: receiving the baseband data and sending it to the RFIC, and performing DFE processing during the sending process, wherein the processing performed by DFE on the sent baseband data includes one or more of shaping filtering processing, multi-stage interpolation filtering processing and frequency conversion processing, the shaping filtering processing is used to remove inter-code crosstalk, the multi-stage interpolation filtering processing is used to meet the rate requirements of different channels and different numbers of carriers, and the frequency conversion processing is used to adjust the frequencies of different carriers.

[0007] Optionally, after obtaining the data to be processed, the method further includes: receiving the data from the RFIC and sending it to the baseband, performing DFE processing on the received data, wherein the data received from the RFIC is processed and sent to the baseband after processing, wherein the processing of the data received from the RFIC includes at least one or more of frequency conversion processing, multi-stage extraction filtering processing and matched filtering processing, the frequency conversion processing is used to adjust the frequency of multi-carrier data, the multi-stage extraction filtering processing is used to downsample the data and remove aliasing, and the matched filtering processing is used to remove inter-code crosstalk.

[0008] Optionally, after obtaining the data to be processed, the method also includes: data processing performed between the RFIC and the baseband, the data processing performed between the RFIC and the baseband includes: obtaining an air interface sending reference time point and an air interface receiving reference time point, wherein the air interface sending reference time point is a reference time for transmitting data, and the air interface receiving reference time point is another reference time for transmitting data; writing the data sent by the baseband into the sending link of the DFE, and when the current time reaches the air interface sending reference time point, sending the data processed by the DFE to the RFIC; when the current time reaches the air interface receiving reference time point, writing the data received by the RFIC into the receiving link of the DFE, and sending the data to the baseband after processing by the DFE.

[0009] Optionally, before performing DFE processing in a semi-parallel manner, the method further includes: obtaining relevant information of the filter, wherein the relevant information includes at least one or more of an input data rate of the filter, an order of the filter, a number of carriers supported by the filter, a decimation multiple of the filter, and an interpolation multiple of the filter; and constructing a simulation model of the DFE, wherein the simulation model is a model of wireless communication obtained by simulating different application scenarios.

[0010] Optionally, after acquiring the target task, the method further includes: using an APB interface and / or an AXI interface to transmit the data to be processed to the baseband; and transmitting the data to be processed to the RFIC via an RF interface.

[0011] According to another aspect of the present application, a communication device based on a radio frequency front-end DFE is provided, including: a first acquisition unit, used to acquire data to be processed, wherein the data to be processed is received RFIC data or data to be sent by the baseband; a second acquisition unit, used to acquire a target task, wherein the target task is a task configured to complete the scheduling of the baseband; a first processing unit, used to perform DFE processing in a semi-parallel manner, and complete the scheduling of the DFE by the baseband in a multi-tasking manner, wherein the semi-parallel and multi-tasking methods of executing the data processing of the DFE together, the DFE processing is to process the data to be processed in a DFE manner, and the scheduling of the DFE by the baseband is to schedule the data to be processed.

[0012] According to another aspect of the present application, a computer-readable storage medium is provided, wherein the computer-readable storage medium includes a stored program, wherein when the program is executed, the device where the computer-readable storage medium is located is controlled to execute any one of the communication methods based on the DFE of the RF front end.

[0013] According to another aspect of the present application, a computer program product is provided, including a computer program, wherein when the computer program is executed by a processor, the steps of any one of the communication methods based on the DFE of the radio frequency front end are implemented.

[0014] According to another aspect of the present application, a DFE processing system is provided, comprising: one or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and the one or more programs include a method for executing any one of the communication methods of the RF front-end-based DFE.

[0015] By applying the technical solution of the present application, a new design is made for the communication mode of DFE. Through multi-tasking execution, the processing rate can be increased and the processing time can be reduced. In addition, multiple tasks are executed in a semi-parallel manner. Semi-parallelism can execute multiple tasks alternately, which can effectively utilize computing resources and improve the overall operating efficiency. In this way, the response speed of DFE is faster, and the DFE does not need to run at a higher clock, which can reduce the proportion of DFE power consumption in the power consumption of the entire baseband chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0017] Figure 1A hardware structure block diagram of a mobile terminal for executing a communication method based on a DFE of a radio frequency front end provided in an embodiment of the present application is shown;

[0018] Figure 2 A schematic flow chart of a communication method based on a DFE of a radio frequency front end provided according to an embodiment of the present application is shown;

[0019] Figure 3 A schematic diagram showing existing DFE communication;

[0020] Figure 4 A schematic diagram showing DFE communication according to an embodiment is shown;

[0021] Figure 5 A schematic diagram showing DFE communication of another embodiment is shown;

[0022] Figure 6 A schematic diagram showing the switching of time slots for transmitting and receiving data is shown;

[0023] Figure 7 A schematic diagram of DFE transceiver control is shown;

[0024] Figure 8 A schematic diagram of a tapped FIR filter direct form is shown;

[0025] Fig. 9 A schematic diagram of a 4-tap transposed filter is shown;

[0026] Fig.10 shows a schematic diagram of a typical serial filter;

[0027] Fig.11 A structural block diagram of a DFE communication device provided according to an embodiment of the present application is shown.

[0028] The above drawings include the following reference numerals:

[0029] 102, processor; 104, memory; 106, transmission device; 108, input and output devices. DETAILED DESCRIPTION

[0030] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0031] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0032] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0033] As introduced in the background technology, in the prior art, the power consumption of DFE accounts for a high proportion of the power consumption and area of ​​the entire baseband chip. To solve the above problems, the embodiments of the present application provide a communication method, device, computer-readable storage medium, computer program product and DFE communication system based on a DFE of a radio frequency front end.

[0034] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0035] The method embodiments provided in the embodiments of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Taking running on a mobile terminal as an example, Figure 1 FIG. 1 is a hardware structure block diagram of a mobile terminal of a communication method based on a DFE of a radio frequency front end according to an embodiment of the present invention. Figure 1 As shown, the mobile terminal may include one or more ( Figure 1 Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the mobile terminal may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is for illustration only and does not limit the structure of the mobile terminal. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations shown.

[0036] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the display method of device information in the embodiment of the present invention. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, the above method is implemented. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories can be connected to the mobile terminal via a network. Examples of the above-mentioned network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The transmission device 106 is used to receive or send data via a network. The above-mentioned specific examples of the network may include a wireless network provided by a communication provider of the mobile terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0037] In this embodiment, a communication method based on a DFE of a radio frequency front end running on a mobile terminal, a computer terminal or a similar computing device is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0038] Figure 2 FIG. 1 is a flow chart of a communication method based on a DFE of a radio frequency front end according to an embodiment of the present application. Figure 2 As shown, the method comprises the following steps:

[0039] Step S201, obtaining data to be processed, wherein the data to be processed is received RFIC data or data to be sent by the baseband;

[0040] Specifically, data that is ready for communication between RFIC (radio frequency chip) and baseband DMA (direct memory access) can be obtained. This data transmission is usually used as a bridge between RF and baseband in wireless communication systems. RFIC is responsible for processing RF signals, while DMA provides an efficient data transmission mechanism to reduce the burden on the CPU and increase the speed of data transmission.

[0041] Step S202, obtaining a target task, wherein the target task is a task configured to complete the scheduling of the baseband;

[0042] Specifically, the target task is the task to be performed, that is, the task related to data transmission between RFIC and DMA. Data can be correctly transmitted from RFIC (which may be data extracted from the RF signal) to baseband DMA, or from baseband DMA (which may be data that needs to be sent by RFIC) to RFIC.

[0043] Step S203, DFE processing is performed in a semi-parallel manner, and the scheduling of the DFE by the baseband is completed in a multi-tasking manner, wherein the semi-parallel and multi-tasking methods are used together to perform the data processing of the DFE, the DFE processing is to process the data to be processed in a DFE manner, and the scheduling of the DFE by the baseband is to schedule the data to be processed.

[0044] Specifically, compared with full parallelism (i.e., all tasks are executed simultaneously) and full serialism (i.e., tasks are executed one after another), semi-parallelism is an execution mode between the two. In order to efficiently transmit the data to be transmitted between the radio frequency integrated circuit (RFIC) and the direct memory access (DMA), a semi-parallel method is used to execute multiple target tasks related to data transmission. In order to ensure the continuity of the data sent over the air interface, it is completed by sending multiple tasks. In order to ensure the continuity of the received data over the air interface, it is completed by receiving multiple tasks. Multitasking can not only ensure the continuity of the air interface data, but also reduce the circuit processing performance.

[0045] Through this embodiment, a new design is made for the communication mode of DFE. Through multi-tasking execution, the processing rate can be improved and the processing time can be reduced. In addition, multiple tasks are executed in a semi-parallel manner. Semi-parallelism can execute multiple tasks alternately, which can effectively utilize computing resources and improve overall operating efficiency. In this way, the response speed of DFE is faster, and the DFE does not need to run at a higher clock, which can reduce the proportion of DFE power consumption in the power consumption of the entire baseband chip.

[0046] In this solution, the data sent and received by DFE is obtained, and multi-tasking configuration of DFE is supported; semi-parallel filtering is performed, and the semi-parallel structure is the optimal choice between the area, power consumption, and processing capability of the DFE circuit. Multi-tasking reduces the circuit's requirements for processing capability, and semi-parallelism can reduce power consumption and area, so multi-tasking and semi-parallelism are used together in DFE design.

[0047] Specifically, Figure 3 As shown in the figure, DFE (Digital Front End) is a bridge between the RF front end (RF chip, RFIC) and the baseband digital signal processing module (baseband processing, DMA, i.e. direct access to memory). The RF transmission frequency is usually in the GHz range, and the baseband signal needs to be modulated by RF to reach the transmission frequency. The baseband of 5G transmitters is usually 100M, and that of 4G is usually 20M. The bandwidth of long-distance communication protocols such as satellites is even lower. In order to ensure the out-of-band suppression, in-band ripple, EVM and other indicators of data sent and received by RF, DFE is required to perform digital signal processing on the signal to meet the signal quality requirements of the transmitter and receiver.

[0048] Specifically, the design idea of ​​this application is as follows: Figure 4 As shown in the figure, DFE has a lot of filtering processing and needs to perform multiplication and accumulation operations. Multiplication and accumulation operations will increase the power consumption and area of ​​the chip. Therefore, the DFE design must comprehensively consider performance, power consumption, area, etc. to find the optimal design point. The DFE downlink direction is to receive data from the RF chip, perform down conversion (AFC), extraction filtering, matched filtering and other functions, and then send the data to the baseband for processing; the DFE uplink direction is to receive data from the baseband, perform shaping filtering, interpolation, up conversion (AFC) and other functions, and finally send the data to the RF chip.

[0049] A shaping filter is a filter that processes a signal to remove inter-symbol interference. An interpolation filter is a filter that processes a signal to increase the sampling rate of the signal. A matched filter is a filter that removes inter-symbol interference from received data. A decimation filter is a filter that downsamples or decimates a signal to reduce the sampling rate.

[0050] Shaping filtering is an important step in baseband processing to convert digital signals into analog signals suitable for transmission. It reduces inter-symbol interference (ISI) by limiting the bandwidth of the signal and ensures that the signal maintains its integrity during transmission. In satellite communications, digital signals (such as 0s and 1s) are converted into analog signals with specific spectral characteristics through shaping filters. A commonly used shaping filter is the square root raised cosine filter because it is able to generate signals with low ISI characteristics.

[0051] For example, there is a bit sequence of "10101". After passing through the shaping filter, each bit is no longer a simple pulse, but becomes an analog signal with a specific shape (such as a raised cosine waveform). The specific shape and bandwidth of this waveform depend on the design of the filter.

[0052] Interpolation filtering is used in digital signal processing to increase the sampling rate of a signal, usually in the up-sampling process. It increases the number of samples by inserting new sample points between existing samples. In satellite communications, interpolation filtering can be used to increase the sampling rate of a signal at the transmitter so that the original signal can be restored more accurately at the receiver. Interpolation filters are usually designed as low-pass filters to avoid introducing high-frequency noise during the interpolation process.

[0053] For example, the sampling rate of the original signal is 1MHz, that is, 1 million sample points are sampled per second. Through interpolation filtering, the sampling rate can be increased to 2MHz, that is, one or more new sample points are inserted between every two original sample points. The values ​​of these new sample points are calculated by the algorithm of the interpolation filter.

[0054] Matched filtering is a signal processing technique at the receiving end that is used to maximize the signal-to-noise ratio (SNR) of the received signal. It is matched to the shaping filter at the transmitting end to ensure that the signal is minimally disturbed during transmission. The matched filter is the inverse process of the shaping filter and is used at the receiving end. When the received signal passes through the matched filter, the signal components that match the filter characteristics are enhanced, while the noise components that do not match are suppressed.

[0055] For example, the shaping filter used at the transmitting end has a specific frequency response characteristic. At the receiving end, the matched filter will have a frequency response characteristic complementary to the shaping filter at the transmitting end. When the received signal passes through the matched filter, the useful components in the signal will be amplified, while the noise components will be suppressed, thereby improving the signal's SNR.

[0056] Decimation filtering is a down-sampling process in signal processing, which is used to reduce the sampling rate of a signal. It is usually used in conjunction with interpolation filtering to restore the sampling rate of the original signal at the receiving end. In satellite communications, decimation filtering is used to reduce the number of samples of a signal at the receiving end for subsequent processing or to reduce storage and transmission costs. The decimation filter is usually designed as a low-pass filter to avoid introducing aliasing effects during the decimation process.

[0057] For example, the received signal has a sampling rate of 2MHz, but only a sampling rate of 1MHz is required for subsequent processing. By decimating the filter, one sample point can be retained every other sample point, thereby reducing the sampling rate to 1MHz. In this process, the decimation filter will filter out high-frequency noise and aliasing components.

[0058] Specifically, the implementation devices of DFE are mainly DSP (Digital Signal Processor), FPGA (Field Programmable Gate Array) and ASIC (Application Specific Integrated Circuit). There are already dedicated multiplication units for DFE implementation on DSP, FPGA and other chips. Users complete the design of DFE through programming. The disadvantages are high power consumption and high cost. They are suitable for industrial applications and difficult to be applied on civilian terminals. DSP and FPGA chips should be mainly used in the industrial field and are not sensitive to power consumption. Therefore, the implementation scheme of DFE is relatively simple. ASIC is a customized chip, which is usually customized according to a specific communication protocol, such as LTE (Long Term Evolution) chip, NR (New Radio) 5G chip, WIFI (Wireless Fidelity) chip, and satellite communication chip. The advantages of ASIC are low power consumption and small chip area, which are suitable for scenarios on terminals or large-scale applications. The disadvantage is that it has no versatility and cannot adapt to various communication protocols at the same time. This solution designs a DFE module of a satellite communication protocol chip, which is applied to a satellite communication terminal chip. At present, appropriate algorithm models are selected according to the application scenarios of communication, and innovations are made in DFE implementation methods based on given algorithm models and design requirements. This solution is an improvement on the DFE design method based on satellite communication chips. Compared with traditional implementation methods, it has the advantages of low power consumption, flexible configuration, and small circuit area.

[0059] When designing DFE, the inventors of this application found that the power consumption of DFE accounts for a high proportion of the power consumption of the entire baseband chip, especially in multi-carrier design, because the power consumption of DFE will be greater due to the increase in filtering links. The power consumption of DFE mainly comes from two aspects. On the one hand, it is dynamic power consumption, which is caused by signal flipping during data processing; on the other hand, it is static power consumption, which is too large due to the large design circuit area. The function of DFE is determined based on the baseband and radio frequency, and the performance of DFE is determined based on link simulation. After determining the function and performance, the circuit design of DFE is carried out. The design of DFE mainly faces the following challenges:

[0060] 1. DFE parameters need to be updated frequently, and the update speed must ensure the continuity of air interface data;

[0061] 2. How does DFE support the configuration of physical layer multitasking?

[0062] 3. Reduce the number of filter multipliers and reduce chip power consumption;

[0063] 4. DFE needs to support AFC and frequency conversion of carriers in the case of multiple CCs (Component Carriers);

[0064] 5. To support flexible parameter configuration, the physical layer can change the configuration dynamically.

[0065] Based on the above design issues, the solution of this application adds multi-task function to DFE on the basis of traditional single-task; due to the design requirements of multiple CCs, the filter channels are increased, and the DFE area will increase, so a new filter is designed to support multi-CC semi-parallel filters; the 4CC DFE system designed by the inventor only increases the power consumption by about 1 times compared with the 1CC DFE used in the previous generation chip. The inventor designed a multi-task, low-power DFE, which improves the existing DFE design, and has the following main features:

[0066] 1. DFE supports multi-task processing. Up to 8 tasks can be configured at a time. Each task has its own time tag, indicating the time point of air interface transmission. Multi-task processing is supported for sending an entire link and receiving an entire link. The benefit is that DFE can be configured in advance, and two tasks can be seamlessly scheduled.

[0067] 2. The filter coefficients are configurable, and the interpolation and decimation multiples are configurable, supporting conventional DFE functions such as AFC, limiting, IQ switching, and DC removal;

[0068] Third, a multiplier-accumulator suitable for multi-CC filtering is designed to support semi-parallel filtering. Between the filter speed and chip area, a filter structure most suitable for satellite communication is found.

[0069] During the specific implementation process, after obtaining the data to be processed, the above method also includes the following steps: receiving the above baseband data and sending it to the above RFIC, and performing DFE processing during the sending process, wherein, for the above baseband data sent, the processing performed by DFE includes one or more of shaping filtering processing, multi-stage interpolation filtering processing and frequency conversion processing, the shaping filtering processing is used to remove inter-code crosstalk, the multi-stage interpolation filtering processing is used to meet the rate requirements of different channels and different numbers of carriers, and the frequency conversion processing is used to adjust the frequency of different carriers.

[0070] In this solution, necessary processing is performed on the data sent by DMA to ensure that the data can meet the reception requirements of RFIC when it is transmitted to RFIC. These data have been optimized and are more suitable for further processing in RFIC or for the generation of RF signals. Shaping filter processing is used to remove inter-code crosstalk, which helps to reduce interference during data transmission and improve the signal-to-noise ratio of data. Multi-level interpolation filter processing is used to meet the rate requirements of different channels and different numbers of carriers, which helps to improve the time domain resolution of the data so that the data more accurately reflects the characteristics of the original signal. Frequency conversion processing is used to adjust the frequency of the data to adapt to different transmission requirements or the operating frequency of RFIC. This helps to ensure that the data can be correctly processed and utilized in RFIC. By pre-processing and optimizing data, the burden on RFIC in subsequent processing can be reduced, the communication processing speed and efficiency can be improved, and the overall performance of communication can be improved.

[0071] Specifically, multi-stage interpolation filtering is a technique commonly used in digital signal processing to insert new data points between original data points, thereby increasing the sampling rate of the signal. This is often used to reconstruct or enhance the signal in the digital domain for further processing or analysis. In satellite communications, multi-stage interpolation filtering is often used in baseband processing or digital front-end parts to improve the time domain resolution and frequency domain characteristics of the signal.

[0072] For example, the sampling rate of the original signal is 8kHz, that is, 8000 points are sampled per second. In order to perform more detailed analysis or processing, the sampling rate needs to be increased to 16kHz. At this time, multi-level interpolation filtering technology can be used to insert new data points between the original data points. For example, in a two-level interpolation filter, each level may double the number of sampling points. Therefore, after the first level of interpolation, the sampling rate becomes 16kHz (8kHz*2), and the number of data points increases accordingly; after the second level of interpolation (if it is still needed), the sampling rate can be further increased.

[0073] During the specific implementation process, after obtaining the data to be processed, the method also includes the following steps: receiving the data from the RFIC and sending it to the baseband, performing DFE processing on the received data, wherein the data received from the RFIC is processed and sent to the baseband after processing, wherein the processing of the data received from the RFIC includes at least one or more of frequency conversion processing, multi-stage extraction filtering processing and matched filtering processing, the frequency conversion processing is used to adjust the frequency of multi-carrier data, the multi-stage extraction filtering processing is used to downsample the data and remove aliasing, and the matched filtering processing is used to remove inter-code crosstalk.

[0074] In this scheme, when RFIC needs to send data to DMA, the data will first go through a series of preprocessing steps, which are to ensure that the data has the appropriate format and characteristics when it is transmitted to DMA so that DMA can efficiently receive and process it. The data has been optimized and is more suitable for the reception and processing requirements of DMA. In frequency conversion processing, since RFIC usually processes high-frequency signals, frequency conversion processing may be required before sending data to DMA to reduce the frequency of the signal to a range that DMA can handle, which helps to reduce the processing burden of DMA and avoid potential signal interference. Multi-stage extraction filtering processing is used to reduce the signal frequency while also downsampling the data to reduce the amount of data and reduce the transmission bandwidth requirements. Multi-stage extraction filtering processing can gradually reduce the sampling rate and remove possible aliasing effects in each step to ensure that the data still maintains its original characteristics after downsampling. Matched filtering processing is a special filtering technology that uses prior knowledge of the signal (such as the waveform and frequency of the signal) to design the filter so that the signal-to-noise ratio of the filter output signal is maximized. The various processing methods in the preprocessing step can be selected and combined according to the actual application scenario to meet different data transmission requirements and enhance the flexibility and adaptability of communication.

[0075] Specifically, multi-stage decimation filtering refers to the process of downsampling and filtering the signal step by step through multiple cascaded decimation filters during digital signal processing. Each decimation filter downsamples the input signal at a certain decimation rate (i.e., downsampling factor) and removes high-frequency components and possible aliasing effects through filtering.

[0076] For example, in the baseband processing of satellite communications, the sampling rate of the received signal is 8MHz, that is, 8,000,000 data points are collected per second. However, due to the limitation of subsequent processing capabilities or in order to save storage space, the sampling rate needs to be reduced to a lower level. At this time, multi-stage extraction filtering processing can be used to achieve this goal.

[0077] First stage decimation filter:

[0078] Decimation rate: 2;

[0079] Output sampling rate: 8MHz / 2=4MHz;

[0080] Assume that the first filter is a low-pass filter with a cutoff frequency of half the Nyquist frequency, i.e. 2MHz, to prevent aliasing effects.

[0081] Second stage decimation filter:

[0082] Decimation rate: 2;

[0083] Output sampling rate: 4MHz / 2=2MHz;

[0084] Similarly, the second-stage filter is also a low-pass filter, but the cutoff frequency needs to be adjusted accordingly based on the Nyquist frequency of the first-stage output signal to prevent aliasing when further downsampling occurs.

[0085] Specifically, Figure 5 As shown in the figure, this solution designs a new DFE architecture based on an in-depth analysis of the characteristics of satellite communication DFE. The DFE is improved in two aspects: the first is to support multi-task processing; the second is to support 4-carrier semi-parallel filters. The designed DFE supports shaping, interpolation, matching, extraction, AFC, AGC, masking and other functions, optimizes the design of DFE, and effectively reduces power consumption.

[0086] Specifically, Figure 6 As shown, the wireless chip requires the data to be sent to be aligned with the air interface time, which requires that the sending and receiving of data must meet the air interface time requirements. For example, if you want to send data of different channels in slot n (slot is the time slot or position in the communication process) and slot n+1, there is a GAP (Generic Access Profile) between slot n and slot n+1. It is a protocol specification defined in Bluetooth technology for communication connection and data transmission between devices. GAP defines the connection mode, broadcast data format, device discovery and connection and other basic functions between devices, and is the basis for communication and interaction between Bluetooth devices. Usually there is only a baseband data sampling point time. Therefore, in order to ensure the continuity of the two data transmissions, it is required that the DFE configuration parameters of slot n+1 be sent immediately after slot n sends the data, and the DFE processing of slot n+1 data is performed, and the data of slot n+1 is sent at the time point that meets the air interface requirements. In order to meet the switching speed of different channels in the two slots, the simplest way is to increase the system clock frequency, but the increase in clock frequency will increase the power consumption of the chip and increase the difficulty of chip backend processing. Receiving will also have the same problem as sending. To receive data from two different channels continuously, it is necessary to switch the DFE configuration to meet the signal processing requirements.

[0087] In addition, when the protocol stack schedules the control channel and service channel to be sent over the air interface, it can schedule several slots in advance. Depending on the service, the advance time varies. When the physical layer knows the scheduling information in advance, it can perform channel encoding and decoding, modulation and demodulation, etc. at the physical layer. For example, if the terminal needs to send data for several slots and knows the configuration information and data of these slots, it can complete the processing of the physical layer in advance. If the terminal can perform the processing of the physical layer in advance, it is equivalent to reducing the processing time of the physical layer and reducing the requirements of the physical layer on the clock frequency.

[0088] The reception and transmission of DFE need to be aligned with the air interface time to ensure that there is no interference in wireless communication and the delay is accurate. Usually, a data transceiver switch is set on the DFE interface to allow data to be sent accurately on the air interface. The transceiver switch is controlled by the TBU (Timer Base Unit). The physical layer configures the switch time point according to the schedule.

[0089] In some embodiments, after obtaining the data to be processed, the method further includes the following steps: data processing performed between the RFIC and the baseband, and the data processing performed between the RFIC and the baseband can be specifically implemented by the following steps: obtaining an air interface sending reference time point and an air interface receiving reference time point, wherein the air interface sending reference time point is a reference time for transmitting data, and the air interface receiving reference time point is another reference time for transmitting data; writing the data sent by the baseband into the sending link of the DFE, and when the current time reaches the air interface sending reference time point, sending the data processed by the DFE to the RFIC; when the current time reaches the air interface receiving reference time point, writing the data received by the RFIC into the receiving link of the DFE, and sending the data to the baseband after being processed by the DFE.

[0090] In this scheme, the air interface reference time point is an important reference for data transmission, which indicates when the data should be sent or received through the wireless interface (i.e., "air interface"). When the DMA is ready to send data, the data is first written into a buffer called the first queue, and the current time is constantly monitored to see if it has reached the air interface reference time point. If it has, it means that it is now the right time to send the data to the RFIC for wireless transmission. The data is taken out of the first queue and sent to the RFIC for processing and transmission. Similarly, when the RFIC receives data from the wireless interface, the data is written into another buffer called the second queue. However, unlike the transmission from DMA to RFIC, the data transmission from RFIC to DMA does not strictly depend on the air interface reference time point. If the current time has not reached the next air interface reference time point (i.e., it is not ready to send new data through the air interface), the data can be taken out of the second queue and sent to the DMA for processing. By relying on the air interface reference time point to schedule the sending and receiving of data, it can be ensured that the data is transmitted through the wireless interface at the right time, thereby improving the synchronization and accuracy of data transmission, and further reducing the proportion of DFE power consumption to the power consumption of the entire baseband chip.

[0091] Specifically, Figure 7As shown in the figure, TBU (time reference unit) provides the air interface reference time point, and the compare module compares the configured time point with the TBU time to generate the enable for sending and receiving data. In the traditional DFE transceiver architecture, the DFE transceiver tasks are serial in time. It is necessary to wait until a DFE configuration task is completed before configuring the next task. The switching of the two tasks must be completed within the scheduling time interval. In the sending direction, the physical layer puts the coded modulation data into the memory (memory storage space), and the DMA reads the data to the Tx DFE. After the DFE processing is completed, it is written into the FIFO (first queue). When the configured sending time point and the TBU time point are equal, the sending read FIFO (second queue) enable is generated. When the TBU does not reach the configured receiving data time point, the Rx DFE and DMA configurations are completed. After the transceiver is completed, the next transceiver configuration can be performed, waiting for the next data transceiver.

[0092] Specifically, the DFE contains multiple modules. The sending direction usually includes shaping filters, multiple interpolation filters, AFC (frequency conversion processing), gain control and other functions. The receiving direction includes matching filters, multiple extraction filters, AFC (frequency conversion processing), gain control and other functions. In the case of large-bandwidth baseband signals, DFE generally also includes CFR (Crest Factor Reduction) and DPD (Digital Pre-Distortion). In satellite communications, the DFE rates of different channels are different, and the data rate is generally changed by extraction and interpolation filters. The filter accounts for the largest proportion of power consumption in the DFE. The FIR (Finite Impulse Response) filter is used in the DFE. There are a large number of multiplications and accumulations, and the static power consumption and dynamic power consumption are very large. Optimizing the design of the filter has become the key to reducing the power consumption of the DFE. As the name suggests, the impulse response of FIR is composed of a finite number of sampling values. The impulse response output is as follows. Define a filtering operation, which is convolved by the current input and the past input, and waits for a current output. It takes N multiplications and N-1 additions to complete a filtering operation.

[0093] Specifically, the above formula is:

[0094] These two formulas are the transfer function and differential variance of a FIR system with a length (number of taps) of N and an order of N-1. H represents the system vector, H and Xn are called coefficient vectors and input vectors respectively, z represents the plane, N represents the tap tree, h(n) represents the filter tap coefficient, n represents the number of times, and y(n) represents the filter output. From the above expressions, it can be seen that H(z) is actually a polynomial of z-1, and its N-1 poles are all located at z=0, so an FIR filter is always stable. Its zero point distribution can be located at any position in the finite Z plane. When all zero points are located within the unit circle, it becomes a minimum phase system. The existence of only zero points is also the reason why FIR filters are called all-zero point filters.

[0095] Specifically, Figure 8 As shown in the figure, from the perspective of implementation, filters can be divided into parallel structures and serial structures. The parallel structure requires more multipliers and a larger area, but the clock frequency can be lower. The serial structure requires fewer multipliers, but requires a high-frequency clock. Parallel filters are divided into direct type and transposed type. Both are described from the time domain and have a large number of applications in engineering. The three basic units of the direct type filter are: tapped delay line, multiplier and adder. The direct type is a direct reflection of the convolution idea, so the structure is also called a convolution structure. The addition of the direct type can also improve the multiplication-addition tree structure to reduce line delay.

[0096] Specifically, Fig. 9 As shown, compared with the direct filter, the transposed filter has a shorter critical path delay. The difference between the direct and transposed structures is that the direct type directly delays the input data by clock, while the transposed type delays the multiplication and addition results by clock.

[0097] Specifically, Fig.10 As shown, the idea of ​​serial filter is to use only one multiplier and accumulator to complete filtering in chronological order. The FIR filter can be regarded as a data window, and only the data in the data window is filtered, which requires N multiplications and N-1 additions.

[0098] In some embodiments, before performing DFE processing in a semi-parallel manner, the method further includes: obtaining relevant information of the filter, wherein the relevant information includes at least one or more of an input data rate of the filter, an order of the filter, a number of carriers supported by the filter, a decimation multiple of the filter, and an interpolation multiple of the filter; and constructing a simulation model of the DFE, wherein the simulation model is a model of wireless communication obtained by simulating different application scenarios.

[0099] In this solution, the optimal filter architecture is automatically inferred by analyzing relevant information of the filter (such as input data rate, order, number of supported carriers, decimation multiple, interpolation multiple, etc.). By simulating the DFE, a simulation model of the DFE can be obtained, and the output can be dynamically adjusted according to different input requirements, which is suitable for a variety of scenarios.

[0100] The input data rate is the speed at which the filter processes data. The number of supported carriers is the number of carriers in the signal that the filter needs to process. The decimation factor is the number of times the sampling rate is reduced during the filtering process. The interpolation factor is the number of times the sampling rate is increased during the filtering process (although the original article mainly discusses decimation, interpolation is also an important concept in digital signal processing).

[0101] In some embodiments, after acquiring the target task, the method further includes the following steps: using an APB interface and / or an AXI interface to transmit the data to be processed to the baseband; and transmitting the data to be processed to the RFIC via an RF interface.

[0102] In this solution, data is transmitted through APB and AXI interfaces with DMA, and the appropriate interface can be selected according to different device characteristics and performance requirements. The APB interface is suitable for low-speed, low-power peripheral devices, which helps to reduce power consumption and complexity; while the AXI interface is suitable for high-performance, high-bandwidth devices, which can improve the efficiency and speed of data transmission.

[0103] Specifically, the satellite communication DFE system supporting multi-tasks in this solution has three external interfaces, namely APB interface (peripheral bus interface), AXI interface (advanced extensible interface), and RF interface (radio frequency interface). The physical layer interacts with DFE through APB and AXI, and RFIC interacts with DFE through the RF interface. The physical layer schedules DFE as follows:

[0104] Uplink direction:

[0105] A. Write the data to be sent to the RDMA of DFE through the AXI bus. If it is sent by multiple tasks, the data of multiple tasks can be written;

[0106] B. Initialize configuration parameters, including timestamp, RDMA, filter, AFC and other registers. If multiple tasks are sent, then the timestamp, RDMA, filter, AFC and other modules must be configured repeatedly. A maximum of 8 tasks can be configured at the same time.

[0107] C. Wait for TBU to count to the set timestamp, start DFE transmission, and start sending data to RFIC;

[0108] D. During the sending process, if there is a new DFE task, the new task data can be written to the DFE, and a new timestamp and related initialization parameters can be configured to the DFE;

[0109] E. In multitasking, two tasks are switched automatically without the need for additional processor intervention; an interrupt is sent to the processor each time a task is completed.

[0110] Downlink direction:

[0111] a. Initialize configuration parameters, including WDMA (wavelength division multiple access), filter, AFC and other modules. If multi-task reception is used, then the timestamp, RDMA, filter, AFC and other registers must be configured repeatedly;

[0112] b. Wait for TBU to count to the set timestamp, start DFE reception, receive data from RFIC to DFE, and after DFE processing, write it to AXI through WDMA;

[0113] c. If there is a new receiving task during the receiving process, the configuration parameters of the channel receiving task can be written into DFE;

[0114] d. During the multi-task reception process, the two tasks are automatically switched without the need for additional processor intervention. An interrupt will be sent to the processor each time a task is completed.

[0115] With the advancement of satellite communication technology and the increase in communication bandwidth, the demand for multi-carrier communication terminals has increased rapidly. However, multi-carrier communication will cause the power consumption of DFE to increase rapidly, which is almost proportional to the number of carriers. The purpose of the present invention is to solve the problem of high power consumption of 4CC DFE of satellite terminal chip, and design a satellite communication DFE system supporting 4CC. The system completes low-power design through multi-tasking, semi-parallel filtering and other methods, and realizes the design upgraded from 1CC to 4CC. The present invention is an implementation method of a DFE system, which includes a combination of an uplink sending DFE link, a downlink receiving DFE link, a configuration circuit, a DMA, an RF interface and other parts to form a complete module.

[0116] The key points of this solution are: supporting up to 8 DFE transceiver tasks, each task has its own timestamp, and a multi-task based DFE system, which allows the physical layer to configure the DFE in advance, while giving the physical layer more processing time, and switching the DFE configuration between two schedulings according to different tasks. Low power consumption technology, a semi-parallel filter supporting 4CC is designed, and the power consumption is reduced by half compared with no optimization. The present invention is a DFE system applied to a satellite terminal, supporting satellite communication protocols.

[0117] This solution is a multi-task satellite communication DFE system that supports multi-carrier transmission and can be applied to terminal chips. It has the following features: standard APB bus configuration interface; supports multi-task configuration, up to 8 tasks; interpolation filter interpolation multiples are configurable; decimation filter decimation multiples are configurable; key indicators: spurious and stopband suppression reaches 50dBc, image suppression 25dBc, passband flatness 1dB, EVM less than 1%;

[0118] The embodiment of the present application also provides a DFE communication device. It should be noted that the DFE communication device of the embodiment of the present application can be used to execute the communication method for DFE based on RF front end provided in the embodiment of the present application. The device is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware for a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0119] The following is an introduction to a communication device based on a DFE of a radio frequency front end provided in an embodiment of the present application.

[0120] Fig.11 is a structural block diagram of a communication device based on a DFE of a radio frequency front end according to an embodiment of the present application. Fig.11 As shown, the communication device based on the DFE of the radio frequency front end includes:

[0121] A first acquisition unit 10 is used to acquire data to be processed, wherein the data to be processed is received RFIC data or data to be sent by the baseband;

[0122] A second acquisition unit 20 is used to acquire a target task, wherein the target task is a task configured to complete the scheduling of the baseband;

[0123] The first processing unit 30 is used to perform DFE processing in a semi-parallel manner and complete the scheduling of the DFE by the baseband in a multi-tasking manner, wherein the semi-parallel and multi-tasking methods together execute the data processing method of the DFE, the DFE processing is to process the data to be processed in a DFE manner, and the scheduling of the DFE by the baseband is to schedule the data to be processed.

[0124] Through this embodiment, a new design is made for the communication mode of DFE. Through multi-tasking execution, the processing rate can be improved and the processing time can be reduced. In addition, multiple tasks are executed in a semi-parallel manner. Semi-parallelism can execute multiple tasks alternately, which can effectively utilize computing resources and improve overall operating efficiency. In this way, the response speed of DFE is faster, and the DFE does not need to run at a higher clock, which can reduce the proportion of DFE power consumption in the power consumption of the entire baseband chip.

[0125] During the specific implementation process, the above-mentioned device also includes a second processing unit, which is used to receive the above-mentioned baseband data and send it to the above-mentioned RFIC after obtaining the data to be processed. The sending process performs DFE processing, wherein for the above-mentioned baseband data sent, the processing performed by DFE includes one or more of shaping filtering processing, multi-stage interpolation filtering processing and frequency conversion processing. The shaping filtering processing is used to remove inter-code crosstalk, the multi-stage interpolation filtering processing is used to meet the rate requirements of different channels and different numbers of carriers, and the frequency conversion processing is used to adjust the frequency of different carriers.

[0126] In this solution, necessary processing is performed on the data sent by DMA to ensure that the data can meet the reception requirements of RFIC when it is transmitted to RFIC. These data have been optimized and are more suitable for further processing in RFIC or for the generation of RF signals. Shaping filter processing is used to remove inter-code crosstalk, which helps to reduce interference during data transmission and improve the signal-to-noise ratio of data. Multi-level interpolation filter processing is used to meet the rate requirements of different channels and different numbers of carriers, which helps to improve the time domain resolution of the data so that the data more accurately reflects the characteristics of the original signal. Frequency conversion processing is used to adjust the frequency of the data to adapt to different transmission requirements or the operating frequency of RFIC. This helps to ensure that the data can be correctly processed and utilized in RFIC. By pre-processing and optimizing data, the burden on RFIC in subsequent processing can be reduced, the communication processing speed and efficiency can be improved, and the overall performance of communication can be improved.

[0127] During the specific implementation process, the above-mentioned device also includes a third processing unit, which is used to receive the data of the above-mentioned RFIC and send it to the above-mentioned baseband after obtaining the data to be processed, and perform DFE processing on the received data, wherein the data received from the above-mentioned RFIC is processed and sent to the above-mentioned baseband after processing, wherein the processing of the data received from the above-mentioned RFIC includes at least one or more of frequency conversion processing, multi-stage extraction filtering processing and matched filtering processing, the frequency conversion processing is used to adjust the frequency of multi-carrier data, the multi-stage extraction filtering processing is used to downsample the data and remove aliasing, and the matched filtering processing is used to remove inter-code crosstalk.

[0128] In this scheme, when RFIC needs to send data to DMA, the data will first go through a series of preprocessing steps, which are to ensure that the data has the appropriate format and characteristics when it is transmitted to DMA so that DMA can efficiently receive and process it. The data has been optimized and is more suitable for the reception and processing requirements of DMA. In frequency conversion processing, since RFIC usually processes high-frequency signals, frequency conversion processing may be required before sending data to DMA to reduce the frequency of the signal to a range that DMA can handle, which helps to reduce the processing burden of DMA and avoid potential signal interference. Multi-stage extraction filtering processing is used to reduce the signal frequency while also downsampling the data to reduce the amount of data and reduce the transmission bandwidth requirements. Multi-stage extraction filtering processing can gradually reduce the sampling rate and remove possible aliasing effects in each step to ensure that the data still maintains its original characteristics after downsampling. Matched filtering processing is a special filtering technology that uses prior knowledge of the signal (such as the waveform and frequency of the signal) to design the filter so that the signal-to-noise ratio of the filter output signal is maximized. The various processing methods in the preprocessing step can be selected and combined according to the actual application scenario to meet different data transmission requirements and enhance the flexibility and adaptability of communication.

[0129] In some embodiments, the above-mentioned device also includes a fourth processing unit, which is used to perform data processing between the above-mentioned RFIC and the above-mentioned baseband after acquiring the data to be processed. The second processing unit includes an acquisition module, a first sending module and a second sending module. The acquisition module is used to acquire an air interface sending reference time point and an air interface receiving reference time point, wherein the above-mentioned air interface sending reference time point is a reference time for transmitting data, and the above-mentioned air interface receiving reference time point is another reference time for transmitting data; the first sending module is used to write the data sent by the above-mentioned baseband into the sending link of the above-mentioned DFE, and when the current time reaches the above-mentioned air interface sending reference time point, the data processed by the above-mentioned DFE is sent to the above-mentioned RFIC; the second sending module is used to write the data received by the above-mentioned RFIC into the receiving link of the above-mentioned DFE when the current time reaches the above-mentioned air interface receiving reference time point, and the above-mentioned DFE sends the data to the above-mentioned baseband after processing.

[0130] In this scheme, the air interface reference time point is an important reference for data transmission, which indicates when the data should be sent or received through the wireless interface (i.e., "air interface"). When the DMA is ready to send data, the data is first written into a buffer called the first queue, and the current time is constantly monitored to see if it has reached the air interface reference time point. If it has, it means that it is now the right time to send the data to the RFIC for wireless transmission. The data is taken out of the first queue and sent to the RFIC for processing and transmission. Similarly, when the RFIC receives data from the wireless interface, the data is written into another buffer called the second queue. However, unlike the transmission from DMA to RFIC, the data transmission from RFIC to DMA does not strictly depend on the air interface reference time point. If the current time has not reached the next air interface reference time point (i.e., it is not ready to send new data through the air interface), the data can be taken out of the second queue and sent to the DMA for processing. By relying on the air interface reference time point to schedule the sending and receiving of data, it can be ensured that the data is transmitted through the wireless interface at the right time, thereby improving the synchronization and accuracy of data transmission, and further reducing the proportion of DFE power consumption to the power consumption of the entire baseband chip.

[0131] In some embodiments, the apparatus further includes a third acquisition unit and a construction unit, wherein the third acquisition unit is used to acquire relevant information of the filter before performing DFE processing in a semi-parallel manner, wherein the relevant information at least includes one or more of the input data rate of the filter, the order of the filter, the number of carriers supported by the filter, the decimation multiples of the filter, and the interpolation multiples of the filter; and the construction unit is used to construct a simulation model of the DFE, wherein the simulation model is a model of wireless communication obtained by simulating different application scenarios.

[0132] In this solution, the optimal filter architecture is automatically inferred by analyzing relevant information of the filter (such as input data rate, order, number of supported carriers, decimation multiple, interpolation multiple, etc.). By simulating the DFE, a simulation model of the DFE can be obtained, and the output can be dynamically adjusted according to different input requirements, which is suitable for a variety of scenarios.

[0133] In some embodiments, the above-mentioned device also includes a fifth processing unit and a sixth processing unit. The fifth processing unit is used to transmit the above-mentioned data to be processed with the above-mentioned baseband through the APB interface and / or AXI interface after acquiring the target task; the sixth processing unit is used to transmit the above-mentioned data to be processed with the above-mentioned RFIC through the RF interface.

[0134] In this solution, data is transmitted through APB and AXI interfaces with DMA, and the appropriate interface can be selected according to different device characteristics and performance requirements. The APB interface is suitable for low-speed, low-power peripheral devices, which helps to reduce power consumption and complexity; while the AXI interface is suitable for high-performance, high-bandwidth devices, which can improve the efficiency and speed of data transmission.

[0135] The above-mentioned communication device based on the DFE of the radio frequency front end includes a processor and a memory, and the above-mentioned first acquisition unit, the second acquisition unit and the communication unit are all stored in the memory as program units, and the processor executes the above-mentioned program units stored in the memory to implement corresponding functions. The above-mentioned modules are all located in the same processor; or, the above-mentioned modules are located in different processors in any combination.

[0136] The processor includes a kernel, and the kernel calls the corresponding program unit from the memory. One or more kernels can be set, and the problem that the power consumption of DFE accounts for a high proportion of the power consumption of the entire baseband chip in the prior art can be solved by adjusting the kernel parameters.

[0137] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip.

[0138] An embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium includes a stored program, wherein when the program is executed, the device where the computer-readable storage medium is located is controlled to execute the communication method based on the DFE of the radio frequency front end.

[0139] An embodiment of the present invention provides a processor, and the processor is used to run a program, wherein the program executes the communication method based on the DFE of the radio frequency front end when running.

[0140] An embodiment of the present invention provides a device, which includes a processor, a memory, and a program stored in the memory and executable on the processor. When the processor executes the program, at least steps of a communication method based on a DFE of a radio frequency front end are implemented.

[0141] The devices in this article can be servers, PCs, PADs, mobile phones, etc.

[0142] A computer program product includes a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the communication method based on the DFE of the radio frequency front end in each embodiment of the present application are implemented.

[0143] The present application also provides a DFE communication system, comprising one or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and the one or more programs include methods for executing any of the above-mentioned DFE-based communication methods.

[0144] Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order than here, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.

[0145] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0146] The present application is described with reference to the method, device (system), or block diagram according to the embodiment of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0147] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1A function specified in one or more boxes.

[0148] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0149] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0150] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0151] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0152] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0153] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0154] 1) The DFE communication method of the present application has a completely new design for the communication mode of the DFE. Through multi-task execution, the processing rate can be increased and the processing time can be reduced. In addition, multiple tasks are executed in a semi-parallel manner. Semi-parallelism can alternately execute multiple tasks, which can effectively utilize computing resources and improve the overall operating efficiency. In this way, the response speed of the DFE is faster, so that the DFE does not need to run a higher clock, and the power consumption of the DFE can be reduced. The proportion of the power consumption of the entire baseband chip can be reduced.

[0155] 2) The communication device based on the DFE of the RF front end of the present application has a completely new design for the communication method of the DFE. Through multi-task execution, the processing rate can be improved and the processing time can be reduced. In addition, multiple tasks are executed in a semi-parallel manner. Semi-parallelism can execute multiple tasks alternately, which can effectively utilize computing resources and improve overall operating efficiency. In this way, the response speed of the DFE is faster, so that the DFE does not need to run a higher clock, and the power consumption of the DFE can be reduced. The proportion of the power consumption of the entire baseband chip can be reduced.

[0156] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A communication method based on a DFE of a radio frequency front end, characterized in that: include: Acquire data to be processed, wherein the data to be processed is received RFIC data or data to be sent by the baseband; Acquire a target task, wherein the target task is a task configured to complete the scheduling of the baseband; The DFE processing is performed in a semi-parallel manner, and the scheduling of the DFE by the baseband is completed in a multi-tasking manner, wherein the semi-parallel and multi-tasking methods together execute the data processing method of the DFE, the DFE processing is to process the data to be processed in a DFE manner, and the scheduling of the DFE by the baseband is to schedule the data to be processed.

2. The method according to claim 1, characterized in that After obtaining the data to be processed, the method further includes: The baseband data is received and sent to the RFIC, and DFE processing is performed during the sending process, wherein the processing performed by DFE on the sent baseband data includes one or more of shaping filter processing, multi-stage interpolation filter processing and frequency conversion processing, the shaping filter processing is used to remove inter-code crosstalk, the multi-stage interpolation filter processing is used to meet the rate requirements of different channels and different numbers of carriers, and the frequency conversion processing is used to adjust the frequencies of different carriers.

3. The method according to claim 1, characterized in that After obtaining the data to be processed, the method further includes: The data received from the RFIC is sent to the baseband, and DFE processing is performed on the received data, wherein the data received from the RFIC is processed and sent to the baseband after processing, wherein the processing of the data received from the RFIC includes at least one or more of frequency conversion processing, multi-stage extraction filtering processing and matched filtering processing, the frequency conversion processing is used to adjust the frequency of multi-carrier data, the multi-stage extraction filtering processing is used to downsample the data and remove aliasing, and the matched filtering processing is used to remove inter-code crosstalk.

4. The method according to claim 1, characterized in that: After acquiring the data to be processed, the method further includes: performing data processing between the RFIC and the baseband, The data processing performed between the RFIC and the baseband includes: Acquire an air interface sending reference time point and an air interface receiving reference time point, wherein the air interface sending reference time point is a reference time for transmitting data, and the air interface receiving reference time point is another reference time for transmitting data; Writing the data sent by the baseband into the transmission link of the DFE, and sending the data processed by the DFE to the RFIC when the current time reaches the air interface transmission reference time point; When the current time reaches the air interface reception reference time point, the data received by the RFIC is written into the receiving link of the DFE, and is processed by the DFE and sent to the baseband.

5. The method according to claim 1, characterized in that Before performing DFE processing in a semi-parallel manner, the method further includes: Acquire relevant information of the filter, wherein the relevant information includes at least one or more of an input data rate of the filter, an order of the filter, a number of carriers supported by the filter, a decimation multiple of the filter, and an interpolation multiple of the filter; A simulation model of DFE is constructed, wherein the simulation model is a model of wireless communication obtained by simulating different application scenarios.

6. The method according to any one of claims 1 to 5, characterized in that After acquiring the target task, the method further includes: Using an APB interface and / or an AXI interface to transmit the data to be processed to the baseband; The data to be processed is transmitted to the RFIC via an RF interface.

7. A communication device based on a DFE of a radio frequency front end, characterized in that: include: A first acquisition unit, used for acquiring data to be processed, wherein the data to be processed is received RFIC data or data to be sent by the baseband; A second acquisition unit, configured to acquire a target task, wherein the target task is a task configured to complete the scheduling of the baseband; The first processing unit is used to perform DFE processing in a semi-parallel manner and complete the scheduling of the DFE by the baseband in a multi-tasking manner, wherein the semi-parallel and multi-tasking methods together execute the data processing method of the DFE, the DFE processing is to process the data to be processed in a DFE manner, and the scheduling of the DFE by the baseband is to schedule the data to be processed.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored program, wherein when the program is executed, the device where the computer-readable storage medium is located is controlled to execute the communication method based on the DFE of the radio frequency front end according to any one of claims 1 to 6.

9. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the communication method based on the DFE of the radio frequency front end according to any one of claims 1 to 6 are implemented.

10. A DFE communication system, characterized in that: include: One or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and the one or more programs include a method for executing the communication method based on the DFE of the radio frequency front end as described in any one of claims 1 to 6.

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