A circuit and method for fast forwarding messages based on OSP protocol

Abstract

The present invention discloses a circuit and method for fast forwarding messages based on the OSP protocol, wherein the circuit includes: a data transmission rate detection circuit, a high-speed clock circuit, a frequency division circuit, a buffer and a sending circuit; the output end of the data transmission rate detection circuit is connected to the frequency division circuit, the data transmission rate detection circuit detects the data transmission rate of each bit, and outputs it to the frequency division circuit as a frequency division factor; one end of the high-speed clock circuit is loaded into the data transmission rate detection circuit, and the other end is connected to the frequency division circuit, and the output end of the frequency division circuit is connected to the sending circuit; one end of the buffer is connected to the receiving signal end RX of the data transmission rate detection circuit, and the other end of the buffer is also connected to the sending circuit. The present invention directly forwards the cached data, so that when RX is received, the sending circuit completes the subsequent sending according to the data transmission rate of the last bit, so that the sending and receiving speeds are consistent, avoiding the problem of catching up.

Description

Technical Field

[0001] The present invention relates to the technical field of message forwarding, and in particular to a circuit and method for fast message forwarding based on an OSP protocol. Background Art

[0002] The OSP protocol is a protocol developed by OSRAM. Since there is no separate clock line, it also uses Manchester encoding. The packet structure of the OSP protocol includes a preamble. The total word length is up to 12 bytes. The preamble is a fixed value of 1010, which can be used to calculate the data transmission rate of the bit. In the OSP protocol, bit is the basic unit of all transmitted data.

[0003] Manchester coding, also known as split phase coding, synchronization coding, and phase coding, is a coding method that uses level jumps to represent 1 or 0. Figure 1 ,Since Manchester code must change once at each clock bit, its coding efficiency can only reach about 50%;

[0004] The data transmission rate of the OSP protocol is 2.4Mhz. When the data transmission rate of the sender is higher than the processing capacity of the receiver, it is easy to cause a catch-up problem, such as the data of the sender is sent to the middle, and the receiver cannot receive and process the data in time; refer to Figure 2 , the RX (receiving) rate is slowly getting slower, but the TX (transmitting) rate is fixed, and it is counting from 29 (digital circuits all start counting from 0, taking the local clock 72M as an example, 72M / 2.4M = 30 cycles, and the maximum count is 29). Therefore, when RX receives 80 bits, TX has also completed sending 80 bits. In fact, RX is not ready to send the 81st bit, and a catch-up problem occurs at this time.

[0005] Therefore, further improvement of the technology is still needed. Summary of the invention

[0006] The object of the present invention is to provide a circuit and method for fast forwarding messages based on the OSP protocol to solve the problems raised in the above background technology.

[0007] The present invention provides the following technical solution: a circuit for fast message forwarding based on the OSP protocol, comprising: a data transmission rate detection circuit, a high-speed clock circuit, a frequency division circuit, a buffer and a sending circuit; wherein:

[0008] The data transmission rate detection circuit has a receiving signal terminal RX for receiving a signal sent by a previous device or host;

[0009] The output end of the data transmission rate detection circuit is connected to the frequency division circuit. The data transmission rate detection circuit detects the data transmission rate of each bit sent by the previous device or host, which is recorded as DataRate 周期 , and output to the frequency division circuit as the frequency division factor;

[0010] One end of the high-speed clock circuit is loaded into the data transmission rate detection circuit, and the other end is connected to the frequency division circuit, the output end of the frequency division circuit is connected to the sending circuit, and the high-speed clock circuit sends a 4.8M clock reference to the sending circuit through the frequency division circuit for sending Manchester encoded data;

[0011] One end of the buffer is connected to the receiving signal end RX of the data transmission rate detection circuit, and the other end of the buffer is also connected to the transmitting circuit, and the transmitting circuit has a transmitting signal end TX, and the transmitting circuit transmits the Manchester encoded data through the transmitting signal end TX.

[0012] Preferably, the transmitting circuit receives the cached data through a buffer, and the cached data is output to the transmitting circuit bit by bit, and each bit is Manchester encoded according to the 4.8M clock output by the frequency division circuit.

[0013] Preferably, a cycle counter is provided inside the frequency division circuit, and the data transmission rate detection circuit starts the cycle counter with 72M as the clock, and when the cycle counter counts to DataRate 周期 When the count reaches half of the value, the count is cleared.

[0014] Preferably, when the data received by RX is data not addressed by the device itself, the sending circuit does not wait until all the data are received before forwarding, but forwards the data when the 15th to 20th bits of the data are received.

[0015] On the other hand, the present invention provides the following technical solution: a method for fast forwarding messages based on the OSP protocol, the specific steps comprising:

[0016] Step S100: The data transmission rate detection circuit detects the data transmission rate of each bit sent by the previous device or host received by RX, which is recorded as DataRate. 周期 , and output to the frequency division circuit as the frequency division factor;

[0017] Step S200: DataRate 周期 The frequency is divided as the input of the frequency division circuit to obtain the data transmission rate of the frequency division period, which is recorded as DataRate 分频 , and at the end of RX reception, the subsequent DataRate 分频Continue to complete the frequency division according to the input value of the last frequency division circuit received;

[0018] Step S300: The buffer receives the buffered data from the RX serial output, and outputs the buffered data to the transmitting circuit bit by bit, and each bit is Manchester encoded according to the 4.8M clock of the frequency division circuit. When the transmitting circuit receives the 15th to 20th bit of the data, it forwards the buffered data.

[0019] The present invention has the following beneficial effects:

[0020] The present invention forwards the cached data so that when the RX reception is completed, the sending circuit sends the data according to the last DataRate. 周期 Complete subsequent transmissions so that the speed of transmission and reception are consistent, without causing cumulative errors and avoiding the problem of catching up. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a schematic diagram of the Manchester encoding timing of the present invention;

[0022] Figure 2 It is a schematic diagram of the structure of the present invention;

[0023] Figure 3 It is a schematic diagram of the circuit structure of the present invention;

[0024] Figure 4 This is a schematic diagram of a cycle counter circuit of the present invention;

[0025] Figure 5 A timing diagram of a cyclic counter counting data transmission rate of the present invention;

[0026] Figure 6 This is a schematic diagram of Manchester encoding using a 4.8M clock of a frequency division circuit in the present invention;

[0027] Figure 7 The DataRate of each bit sent by the previous device or host received by the present invention RX 周期 Timing diagram of . DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in the field of the present invention without creative work are within the scope of protection of the present invention.

[0029] refer to Figure 3, On the one hand, the present invention provides the following technical solution: A circuit for fast forwarding messages based on the OSP protocol, comprising: a data transmission rate detection circuit, a high-speed clock circuit, a frequency division circuit, a buffer and a sending circuit;

[0030] The data transmission rate detection circuit has a receiving signal terminal RX for receiving a signal sent by the previous device or host. The output terminal of the data transmission rate detection circuit is connected to the frequency division circuit. The data transmission rate detection circuit detects the data transmission rate of each bit sent by the previous device or host, which is recorded as DataRate. 周期 , and is output to the frequency division circuit as a frequency division factor.

[0031] In this embodiment, due to the DataRate of the OSP protocol osp is 2.4Mhz. Assuming that the main frequency of the high-speed clock circuit is 72Mhz, through Freq / DataRate osp Calculating DataRate 周期 , that is, DataRate 周期 72M / 2.4M= 30, where Figure 4 It can be seen that the received frequency is gradually getting lower.

[0032] One end of the high-speed clock circuit is loaded to the data transmission rate detection circuit, and the other end is connected to the frequency division circuit. The high-speed clock circuit sends a 4.8M clock reference to the sending circuit through the frequency division circuit for sending Manchester encoded data, wherein the 4.8M clock reference allows an error of + / -5%, and there is error accumulation; in this embodiment, the frequency of Manchester encoding is 2.4M, but one bit needs to generate 2 phases, so in order to generate 2 phases, two phases are required when sending, so 4.8M is required;

[0033] refer to Figure 4 and Figure 5 The frequency division circuit is provided with a cycle counter. In this embodiment, the data transmission rate detection circuit starts the cycle counter with 72M as the clock, and when the cycle counter counts to DataRate 周期 When the clock is half of the value, the count is cleared and a 4.8M clock is generated.

[0034] The output end of the frequency division circuit is connected to the transmitting circuit, and one end of the buffer is connected to the receiving signal end RX of the data transmission rate detection circuit, and the other end of the buffer is also connected to the transmitting circuit, and the transmitting circuit has a transmitting signal end TX; Figure 6In this embodiment, when the data received by RX is data not of the device address, in order to make the data on the OSP bus forward faster, the sending circuit needs to forward the data from the 15th to 20th bit received, instead of waiting until all the data are received before the sending circuit forwards it. The sending circuit first receives the data cached in the buffer, and the cached data is output to the sending circuit bit by bit, and each bit is Manchester encoded according to the 4.8M clock of the frequency division circuit. When the cached data is output to the sending circuit for Manchester encoding, if 1 is sent, it is encoded as 01; if 0 is sent, it is encoded as 10. The sending circuit sends the Manchester-encoded data through the sending signal terminal TX.

[0035] On the other hand, the present invention provides the following technical solution: a method for fast forwarding messages based on the OSP protocol, the specific steps comprising:

[0036] Step S100: Detect the DataRate of each bit sent by the previous device or host received by RX through the data transmission rate detection circuit. 周期 , and output to the frequency division circuit as the frequency division factor;

[0037] refer to Figure 7 In this embodiment, taking receiving 20 bits as an example, the data transmission rate detection circuit calculates the data transmission rate of each bit in real time, which is recorded as DataRate 周期 , where the DataRate of the first bit and the second bit 周期 29, the subsequent bit DataRate 周期 They are 29, 28, 27, 26, 26…25, 24, 23 until RX reception is terminated. The DataRate of the last bit 周期 is 22;

[0038] Step S200: DataRate 周期 The data transmission rate of the frequency division period is obtained by dividing the frequency as the input of the frequency division circuit, which is recorded as DataRate 分频 , and at the end of RX reception, the subsequent DataRate 分频 Continue to complete the frequency division according to the input value of the last frequency division circuit received;

[0039] refer to Figure 7 In this embodiment, DataRate 周期 The frequency division circuit is used as the input for frequency division, which is one bit later than the data transmission rate detection circuit, that is, the default frequency division cycle DataRate of the frequency division circuit. 分频 The DataRate of the frequency division cycle is 29. 分频They are 29, 29, 29, 28, 27, 26, 26, 25, 24, and 23 respectively. When it comes to the 20th cycle, RX reception is completed, and the subsequent frequency division circuit will continue to complete the frequency division according to the cycle 22 of the last bit.

[0040] Step S300: The buffer receives the buffered data from the RX serial output, and the buffered data is output to the sending circuit bit by bit, and each bit is Manchester encoded according to the 4.8M clock of the frequency division circuit. When the sending circuit receives the 15th to 20th bit of the data, it forwards the buffered data;

[0041] refer to Figure 7 In this embodiment, the transmitting circuit serially outputs the data of the receiving buffer BUF at the 15th bit of the received data. The first transmission cycle is 26, and the subsequent transmission cycles follow the frequency division circuit. When the RX reception is completed, the transmitting circuit completes the subsequent transmission according to the cycle 22 of the last bit. The subsequent transmission and reception speeds are consistent, which will not cause cumulative errors and avoid the problem of catching up.

[0042] Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments, or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A circuit for fast message forwarding based on OSP protocol, characterized in that: It includes: a data transmission rate detection circuit, a high-speed clock circuit, a frequency division circuit, a buffer and a transmission circuit; wherein, The data transmission rate detection circuit has a receiving signal terminal RX for receiving a signal sent by a previous device or host; The output end of the data transmission rate detection circuit is connected to the frequency division circuit. The data transmission rate detection circuit detects the data transmission rate of each bit sent by the previous device or host, which is recorded as DataRate 周期 , and output to the frequency division circuit as the frequency division factor; One end of the high-speed clock circuit is loaded into the data transmission rate detection circuit, and the other end is connected to the frequency division circuit, the output end of the frequency division circuit is connected to the sending circuit, and the high-speed clock circuit sends a 4.8M clock reference to the sending circuit through the frequency division circuit for sending Manchester encoded data; One end of the buffer is connected to the receiving signal terminal RX of the data transmission rate detection circuit, and the other end of the buffer is connected to the sending circuit, and the sending circuit has a sending signal terminal TX, and the sending circuit sends the Manchester-encoded data through the sending signal terminal TX; When RX is finished receiving, the sending circuit will send the data according to the last DataRate. 周期 Complete subsequent transmissions so that the speed of transmission and reception is consistent.

2. The circuit for fast message forwarding based on the OSP protocol according to claim 1, characterized in that: The frequency division circuit is provided with a cycle counter inside, and the data transmission rate detection circuit starts the cycle counter with 72M as the clock, and when the cycle counter counts to DataRate 周期 When the count reaches half of the value, the count is cleared.

3. The circuit for fast message forwarding based on the OSP protocol according to claim 1, characterized in that: The data transmission rate detection circuit detects the data transmission rate of each bit sent by the previous device or host, which is recorded as DataRate 周期 , the DataRate 周期 Calculated by the following formula: DataRate 周期 =Freq / DataRate osp , where Freq is the main frequency of the high-speed clock circuit, DataRate osp The data transmission rate of the OSP protocol.

4. The circuit for fast message forwarding based on the OSP protocol according to claim 1, characterized in that: The high-speed clock circuit sends a 4.8M clock reference to the sending circuit through a frequency division circuit, which allows an error of + / - 5%, and there is error accumulation.

5. The circuit for fast message forwarding based on the OSP protocol according to claim 1, characterized in that: When the data received by RX is not the data of the device address, the sending circuit forwards it when receiving the 15th to 20th bits of the data.

6. The circuit for fast message forwarding based on the OSP protocol according to claim 1, characterized in that: The transmitting circuit receives the buffered data through the buffer, and the buffered data is output to the transmitting circuit bit by bit, and each bit is Manchester encoded according to the 4.8M clock output by the frequency division circuit.

7. A method for fast forwarding messages based on the OSP protocol, characterized in that: The method is based on the circuit implementation of the fast forwarding message of the OSP protocol according to any one of claims 1 to 6, and the specific steps include: Step S100: The data transmission rate of each bit sent by the previous device or host received by the receiving signal terminal RX is detected by the data transmission rate detection circuit, which is recorded as DataRate. 周期 , and output to the frequency division circuit as the frequency division factor; Step S200: DataRate 周期 The data transmission rate of the frequency division period is obtained by dividing the frequency as the input of the frequency division circuit, which is recorded as DataRate 分频 , and at the end of RX reception, the subsequent DataRate 分频 Continue to complete the frequency division according to the input value of the last frequency division circuit received; Step S300: The buffer receives the buffered data from the RX serial output, and outputs the buffered data to the transmitting circuit bit by bit, and each bit is Manchester encoded according to the 4.8M clock of the frequency division circuit. When the transmitting circuit receives the 15th to 20th bit of the data, it forwards the buffered data.

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