Method for flexibly configuring terminal equipment by server based on PCIe switch
The method for configuring PCIe devices on servers with PCIe Switches addresses inefficiencies in maintenance by labeling and enumerating devices, ensuring accurate identification and secure configuration, thus resolving bandwidth and speed issues.
Patent Information
- Application Number
- CN202410954956.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-16
- Publication Date
- 2024-12-13
- Estimated Expiration
- 2044-07-16
AI Technical Summary
Existing methods for configuring terminal devices on servers with PCIe switches are inefficient, making it difficult to identify problem ports during maintenance, which disrupts the problem site and hinders effective troubleshooting.
A method for flexibly configuring terminal devices on a server using a PCIe Switch, involving port attribute labeling, enumeration of devices, and reporting PCIe-related information to the BMC through IPMI, enabling accurate identification of device locations and health status via Web UI or Redfish.
Enables precise location and health status display of PCIe devices, solving issues of bandwidth loss and speed loss, while supporting multiple working modes and securing firmware against malicious attacks.
Smart Images

Figure CN119135522A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of network communications, and in particular to a method for flexibly configuring terminal equipment on a server based on a PCIe switch. Background Art
[0002] The PCIe device used by the customer may be directly connected to the host through the PCIe bus, or it may be bridged by a PCIe Switch in the middle, and then the PCIe terminal device is mounted under the PCIe Switch. When the device is abnormal, it is difficult for the customer to know which port has the problem from the BMC interface in the server with the PCIe Switch module. During operation and maintenance, the customer can only dismantle the device or gradually locate the port where the device is located through other methods. This destroys the problem site and is not conducive to problem analysis.
[0003] Therefore, there is an urgent need for a method for a server to flexibly configure terminal devices. Summary of the invention
[0004] In order to solve the problems in the prior art, the present invention proposes a method for flexibly configuring terminal devices on a server based on a PCIe Switch.
[0005] The present invention is specifically implemented through the following technical solutions:
[0006] A method for flexibly configuring terminal devices on a server based on a PCIe Switch, the method comprising:
[0007] Configure the port attribute slot number for the PCIe Switch, including: first add a configuration port attribute Label in the firmware mfg xml configuration, then configure the attributes of all ports, and then configure the ChassisPhysSlotNum corresponding to all ports;
[0008] The Switch and Host are powered on at the same time. The Switch executes the firmware-related boot program, and the BIOS performs the corresponding initialization, enumerates the PCIe devices, obtains the total number of all PCIe devices, and then determines whether it is a Switch bridge device or an endpoint device based on the configuration space type read according to all PCIe devices. If it is a switch bridge device, mark its slot information and obtain the corresponding slot number until all devices are updated. Finally, the PCIe-related information is reported to the BMC through IPMI; the BMC receives the corresponding information, parses it, and presents it to the Web UI or gives it to Redfish.
[0009] As a further improvement of the present invention, the obtaining of the corresponding slot number specifically includes: after the Switch is powered on, the firmware of the Switch is first initialized, and then the firmware thread is started, the PCIeManager switch configuration and global configuration page are obtained, and then the platform override configuration PCIe Manager switch and global options are obtained, and then the Port attributes are read, and finally the PCIe slot control physical slot is set to be attached to the port.
[0010] As a further improvement of the present invention, the Port attribute includes a port number, a port type, and a ChassisPhysslotNum.
[0011] As a further improvement of the present invention, the hardware link of the PCIe Switch includes: directly connecting a plurality of NVME storage devices on the backplane, and then directly connecting the backplane to ST3 of the first PCIe Switch and / or the second PCIe Switch; other X16, X8, and X4 PCIe devices are connected to ST2, ST4, ST5, ST6, ST7, and ST8 of the first PCIe Switch and / or the second PCIe Switch; ST0 and ST1 of the first PCIe Switch and the second PCIe Switch are respectively connected to the first CPU and the second CPU through MCIO as the uplink of the Switch.
[0012] As a further improvement of the present invention, the Host hardware link includes: BIOS is linked to the NVME storage device through the PCH control board, BIOS is directly connected to other PCIe endpoints through the PCIe bus, and CPUs are linked through the UPI bus.
[0013] As a further improvement of the present invention, the method is adapted to PCIe devices mounted under the PCIe Switch, including network cards, graphics cards, SSDs, and NVME devices.
[0014] As a further improvement of the present invention, the method is adaptable to all working modes, including basic mode and comprehensive mode.
[0015] As a further improvement of the present invention, the method further includes performing RSA signing on the configuration file and the firmware.
[0016] The beneficial effects of the present invention are as follows: compared with the existing technology, the present invention adds a label in the Switchmfg configuration page, and indicates each label information port index, number, type, and ChassisPhysslotNum, then enumerates the PCIe devices after the firmware is initialized, and finally attaches special information ChassisPhysslotNum to each station. After the BIOS is initially powered on, the devices are enumerated, and the Switch Bridge and the PCIe devices under the Bridge and the endpoint devices directly hung under the Host are classified. The PCIe-related information is reported to the BMC through IPMI. After receiving the information, the BMC parses and passes it to the Web UI or Redfish, which can display the health status and location, silk screen and other information of the PCIe device. Through the present invention, multiple upstream ends of the PCIe Switch are configured, and multiple NVME devices are connected to the Switch terminal, and the relevant status information of the NVME device can be accurately located; the problem of bandwidth loss and speed loss of PCIe devices connected to multiple downstream ends is solved. The present invention supports multiple working modes of the Switch, and can also sign the firmware file to prevent malicious attacks. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 It is a schematic diagram of the PCIe Switch hardware link and the Host hardware link of the present invention;
[0018] Figure 2 A flowchart of configuring the Port attribute slot number of the present invention;
[0019] Figure 3 A flowchart of reading a PCIe device slot number according to the present invention;
[0020] Figure 4 Figure of the present invention. DETAILED DESCRIPTION
[0021] The present invention is further described below in conjunction with the accompanying drawings and specific implementation methods.
[0022] Glossary
[0023] BIOS: Basic Input Output System, which is mainly used for initialization and detection of various hardware devices during computer startup.
[0024] PCH: Platform Controller Hub, Intel's integrated south bridge.
[0025] PCIe: Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard.
[0026] NVME: Nonvolatile Memory Express, non-volatile fast memory.
[0027] MCIO: Mini Cool Edge IO, multi-channel input / output.
[0028] ST:station, workstation.
[0029] PCIe Switch: Peripheral Component Interconnect Express Switch". PCIE Switch is a device used to build a PCIe bus topology, which allows multiple PCIe devices to connect to the host system through a single PCIe root port, and can route and exchange data between these devices as needed. PCIE Switch plays a key role in building high-performance computer systems, servers, network equipment and other applications that require high-speed data transmission.
[0030] IPMI: Intelligent Platform Management Interface. IPMI is a standard hardware management interface specification that is designed to provide the ability to remotely manage and monitor server hardware, including remote power on and off, monitoring system temperature, voltage, fan speed and other parameters, and performing diagnostic and maintenance tasks.
[0031] ChassisPhysSlotNum: The number of physical slots in the chassis. These slots are used to install various hardware components, such as CPU, memory modules, expansion cards, etc. Each slot has its specific purpose and standard. For example, PCIe slots are used to install expansion hardware such as graphics cards and network cards, while DIMM slots are used to install RAM memory modules.
[0032] like Figure 1As shown, the Switch hardware link of the present invention and the server Host hardware link, wherein 4 NVME storage devices are directly connected to the backplane, and then the backplane is directly connected to ST3 of the first PCIe Switch (SWITCH1) and / or the second PCIeSwitch (SWITCH2). Other X16, X8, X4 PCIe devices are connected to ST2, ST4, ST5, ST6, ST7, ST8 of the first PCIe Switch and / or the second PCIeSwitch. ST0 and ST1 of SWITCH1 and SWITCH2 are connected to CPU1 and CPU2 respectively through MCIO as the uplink of the Switch. The server boot program BIOS is connected to the NVME storage device through the PCH control board, and the BIOS is directly connected to other PCIe endpoints, such as X16, X8 and other devices, through the PCIe bus, and the CPUs are connected through the UPI bus.
[0033] Switch programming:
[0034] The process of configuring the port attribute slot number is as follows: Figure 2 As shown: First, add a configuration port attribute Label in the firmware mfg xml configuration, configure the attributes of all ports, including port number index, port type type, number, clock, etc., and finally configure the ChassisPhysSlotNum corresponding to all ports, and build a map mapping table with station id, port, and ChassisPhysSlotNum.
[0035] The process of reading the PCIe device slot number is as follows Figure 3 As shown in the figure: After the Switch is powered on, the firmware of the Switch is initialized first, and then the firmware thread is started to obtain the PCIe Manager switch configuration and global configuration page, and then obtain the platform override configuration PCIe Manager switch and global options, and then read the Port properties (including port number, port type, ChassisPhysslotNum), and finally set the PCIe slot control physical slot attached to the port.
[0036] BIOS programming:
[0037] The switch and host are powered on at the same time. The switch executes the firmware-related boot program, and the BIOS performs the corresponding initialization, performs PCIe device enumeration, obtains the total number of all PCIe devices, and then configures the space of all PCIe devices. If the type of the configuration space read is 1, it is considered to be a switch bridge device, otherwise it is an endpoint device. If it is a switch bridge device, its slot information is marked as 0xff, and the corresponding slot number is obtained until all devices are updated. Finally, the PCIe-related information is reported to the BMC through IPMI. The BMC receives the corresponding information, parses it, and presents it to the Web UI or gives it to Redfish.
[0038] The solution of the present invention is adapted to all PCIe devices (including network cards, graphics cards, SSDs, NVME disks) mounted under the PCIe Switch, and is also adapted to all working modes (including basic modes and comprehensive modes, etc.).
[0039] The method of the present invention also includes performing RSA signing on the configuration file and the firmware to prevent malicious attacks.
[0040] The method of the present invention designs multiple upstream ends of a PCIe Switch and configures bandwidth, rate, etc. of the upstream and downstream ends. The CPU can remap the port according to the XML parameters configured in the design.
[0041] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention. For ordinary technicians in this field, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as belonging to the protection scope of the present invention.
Claims
1. A method for flexibly configuring terminal devices on a server based on a PCIe switch, characterized in that The method comprises: configuring a port attribute slot number for a PCIe Switch, specifically comprising: firstly adding a configuration port attribute Label in a firmware mfg xml configuration, then configuring the attributes of all ports, and then configuring the ChassisPhysSlotNum corresponding to all ports; The Switch and Host are powered on at the same time. The Switch executes the firmware-related boot program, and the BIOS performs the corresponding initialization. It enumerates the PCIe devices to obtain the total number of all PCIe devices. Then, based on the configuration space of all PCIe devices, it determines whether it is a Switch bridge device or an endpoint device based on the type of configuration space read. If it is a Switch bridge device, it marks its slot information and obtains the corresponding slot number until all devices are updated. Finally, the PCIe-related information is reported to the BMC through IPMI. The BMC receives the corresponding information, parses it, and presents it to the Web UI or gives it to Redfish.
2. The method of claim 1, wherein: The obtaining of the corresponding slot number specifically includes: after the Switch is powered on, the firmware of the Switch is first initialized, then the firmware thread is started, the PCIeManager switch configuration and global configuration page are obtained, then the platform override configuration PCIe Manager switch and global options are obtained, then the Port attribute is read, and finally the PCIe slot control physical slot is set to be attached to the port.
3. The method of claim 1, wherein: Port attributes include port number, port type, and ChassisPhysslotNum.
4. The method of claim 1, wherein: The hardware link of the PCIe Switch includes: directly connecting several NVME storage devices on the backplane, and then directly connecting the backplane to ST3 of the first PCIe Switch and / or the second PCIe Switch; other X16, X8, X4 PCIe devices are connected to ST2, ST4, ST5, ST6, ST7, ST8 of the first PCIe Switch and / or the second PCIe Switch; ST0, ST1 of the first PCIe Switch and the second PCIe Switch are connected to the first CPU and the second CPU respectively through MCIO as the uplink of the Switch.
5. The method of claim 1, wherein: Host hardware links include: BIOS connects to NVME storage devices through the PCH control board, BIOS directly connects to other PCIe endpoints through the PCIe bus, and CPUs are connected through the UPI bus.
6. The method of claim 1, wherein: The method is adapted to PCIe devices mounted under the PCIe Switch, including network cards, graphics cards, SSDs, and NVME devices.
7. The method of claim 1, wherein: The method is applicable to all working modes, including basic mode and comprehensive mode.
8. The method of claim 1, wherein: The method further comprises performing RSA signing on the configuration file and the firmware.
Citation Information
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