Network transmission module based on programmable logic array and PCIE controller
By designing a network transmission module based on a programmable logic array and a PCIE controller in the power system, and using the interconnection of CPU, FPGA and switching chips to form a redundant and heterogeneous network, the reliability and cost of power system network communication are solved. It realizes efficient and flexible network transmission.
Patent Information
- Application Number
- CN202411064354.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-05
- Publication Date
- 2024-12-13
AI Technical Summary
The prior art cannot meet the high reliability requirements of power system network communication, and the traditional CPU network interface expansion solution has problems of hardware decoupling and high cost and low flexibility.
Design a network transmission module based on programmable logic array and PCIE controller, interconnecting with the FPGA network module and the switching chip network module through the CPU module, forming a redundant and heterogeneous network, and using PCIE and GMAC interfaces to realize multi-network protocol processing and data transmission, reducing hardware costs and interface selection thresholds.
An efficient and flexible network transmission module is realized, which reduces hardware costs, improves scalability and flexibility, and solves the problems of high hardware costs, poor flexibility and poor scalability of network transmission modules in the prior art.
Smart Images
Figure CN119135632A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of power system communication, and more specifically, to a network transmission module based on a programmable logic array and a PCIE controller. Background Art
[0002] With the continuous development of the power system, the external network environment of power equipment is becoming more and more complex, and the communication requirements and reliability requirements of the external network of power equipment are also getting higher and higher. However, traditional CPUs generally only provide a small number of network interfaces, which cannot meet the needs of network communication, so it is necessary to expand the network module. The common solution is to connect an external switching chip or FPGA to a network interface and expand multiple network ports through a standard network interface. The disadvantage of this solution is that it is impossible to decouple the hardware of the expanded network ports. Single point failures (such as switching chip abnormalities, CPU network card controller abnormalities, etc.) will expand the scope of failure and reduce the reliability of the device network transmission. In addition, the network port of the switching chip and the network port from the perspective of the system software cannot correspond one to one, which does not meet the requirements of the independent logical network card of the device.
[0003] The prior art proposes a solution to add a PCIE interface to realize an independent network card, and adds a network card module through external hardware. The network card module has a separate processor and supports a PCIE interface and an external optical port\network port. When communicating with an external network, the independent network card module is responsible for exchanging the received message to the CPU driver module through the PCIE interface. For example, Chinese patent CN115733549A discloses a PCIE network card, which includes an Ethernet optical port and a main processor, and the Ethernet optical port is connected to the main processor.
[0004] However, the above solution requires the addition of an external independent network card module, which will increase the hardware cost of the device. In addition, PCIE is a point-to-point expansion, and one controller can only expand one network card, which has low scalability and flexibility. The number of PCIE chips that can be used currently cannot meet the requirements of power system protection and measurement and control devices. Therefore, it is urgent to design a network transmission module with low hardware cost, flexibility and strong scalability. Summary of the invention
[0005] In view of the deficiencies in the prior art, the present invention provides a network transmission module based on a programmable logic array and a PCIE controller.
[0006] The network transmission module based on a programmable logic array and a PCIE controller provided by the present invention includes:
[0007] CPU module, FPGA network module, switch chip network module, n common network ports and n redundant network ports;
[0008] The CPU module is interconnected with the FPGA network module through the PCIE interface to form a redundant network;
[0009] The CPU module is interconnected with the switch chip network module through the GMAC interface to form a heterogeneous network;
[0010] The FPGA network module receives network messages sent from the outside through n redundant network ports, and transmits the network messages to the CPU module through the PCIE bus;
[0011] The switch chip network module receives network messages sent from the outside through n-1 common network ports, communicates with the CPU module through the nth common network port, and transmits the network messages to the CPU module through the GMAC bus;
[0012] When the CPU module needs to send data to the outside through the redundant network, the data to be sent is transmitted to the FPGA network module through the PCIE bus, and the FPGA network module completes the sending of the external network message;
[0013] When the CPU module needs to send data externally through a heterogeneous network, the data to be sent is transmitted to the switch chip network module through the GMAC bus, and the switch chip network module completes the sending of external network messages.
[0014] Optionally, the CPU module includes a GMAC controller, an RC end of a PCIE controller, a general input / output port, a CPU driver module and a network protocol stack; wherein
[0015] The CPU module initiates data transmission with the switching chip network module through the GMAC controller, initiates data transmission to the FPGA network module through the RC end of the PCIE controller, notifies the CPU driver module to process network messages through the interrupt function of the general input / output port, and stores the network messages processed by the CPU driver module through the network protocol stack.
[0016] Optionally, the FPGA network module includes an EP end of a PCIE controller, an I / O resource submodule, a logic processing submodule, and a network transceiver submodule; wherein the EP end of the PCIE controller is responsible for interactive transmission of the PCIE bus with the CPU module; the I / O resource submodule is responsible for triggering the interrupt function of the general input / output port; and the logic processing submodule is responsible for processing and parsing multi-network port protocols;
[0017] In the stage of sending data externally through the redundant network, the CPU module transmits the data to be sent to the EP end of the PCIE controller of the FPGA network module through the PCIE bus, and the EP end of the PCIE controller transmits the data to be sent to the logic processing submodule. The FPGA network module parses and processes the data to be sent according to the multi-network port protocol in the logic processing submodule, and then pushes the message to the external n redundant network ports through the network transceiver submodule;
[0018] In the stage of receiving data externally through the redundant network, the FPGA network module receives network messages transmitted by n redundant network ports through the network transceiver submodule. After being processed by the logic processing submodule, the network message is placed in the specified memory location of the CPU module through the PCIE bus. After the transmission is completed, the interrupt function of the general input / output port is triggered through the I / O resource submodule to notify the CPU module to process the network message.
[0019] Optionally, for redundant networks, a network label field is added to the network messages between the CPU module and the FPGA network module. The network label field is used to distinguish the n redundant network ports of the FPGA network module to the outside world, thereby achieving logical independence of multiple network ports.
[0020] Optionally, during the process of sending a network message, the CPU module inserts the network card information field into the network message to be sent, and the FPGA network module is responsible for parsing the network card information field and recovering the network message, and then transmitting the network message to the corresponding redundant network port;
[0021] During the network message reception process, the FPGA network module inserts the received network port information field into the network message, the CPU module parses the network port information field, restores the network message, and pushes the corresponding network message to the network protocol stack.
[0022] Optionally, for a redundant network, after the general input / output port interrupt triggers the CPU module to process the network message, the CPU module turns off the interrupt function of the general input / output port, switches the reception of the network message to the polling mode, and continues to receive subsequent data packets; after the network message is received and sent to the corresponding network protocol stack, the CPU module reopens the interrupt function of the general input / output port.
[0023] Optionally, for heterogeneous networks, the CPU module uses a standard GMAC network transceiver process to communicate with the external network.
[0024] The present invention utilizes the existing programmable logic array (FPGA network module) and PCIE bus, combines the technical advantages of the programmable logic array and the PCIE controller, and designs an efficient and flexible network transmission module, which does not occupy the original network card controller, and utilizes the existing PCIE interface and GMAC interface of the CPU module to interconnect with the FPGA network module and the switching chip network module respectively, and obtains a redundant network through the expansion of the PCIE controller, and obtains a heterogeneous network through the expansion of the GMAC controller, with strong flexibility and scalability. In addition, the present invention utilizes the existing interface of the CPU module to interconnect with the FPGA network module and the switching chip network module respectively, which reduces the selection threshold of the CPU module, the FPGA network module and the switching chip network module in terms of the interface, and reduces the hardware cost. The technical problems of high hardware cost, poor flexibility and poor scalability of the existing network transmission module are solved. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] A more complete understanding of exemplary embodiments of the present invention may be obtained by referring to the following drawings:
[0026] Figure 1 It is a flow chart of a network transmission module based on a programmable logic array and a PCIE controller provided by an exemplary embodiment of the present invention;
[0027] Figure 2 It is a schematic diagram of data flow between different levels provided by an exemplary embodiment of the present invention. DETAILED DESCRIPTION
[0028] Below, the exemplary embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments of the present invention, and it should be understood that the present invention is not limited to the exemplary embodiments described here.
[0029] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
[0030] Those skilled in the art can understand that the terms "first" and "second" in the embodiments of the present invention are only used to distinguish different steps, devices or modules, etc., and neither represent any specific technical meaning nor indicate the necessary logical order between them.
[0031] It should also be understood that, in the embodiments of the present invention, “plurality” may refer to two or more than two, and “at least one” may refer to one, two or more than two.
[0032] It should also be understood that any component, data or structure mentioned in the embodiments of the present invention can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.
[0033] In addition, the term "and / or" in the present invention is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in the present invention generally indicates that the associated objects before and after are in an "or" relationship.
[0034] It should also be understood that the description of the various embodiments of the present invention focuses on the differences between the various embodiments, and the same or similar aspects thereof can be referenced to each other, and for the sake of brevity, they will not be described one by one.
[0035] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.
[0036] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
[0037] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.
[0038] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.
[0039] Definitions of abbreviations and key terms used in the present invention:
[0040] FPGA: Field Programmable Gate Array, programmable logic array;
[0041] PCIE: peripheral component interconnect express, a high-speed serial computer expansion bus standard;
[0042] GPIO: General-purpose input / output, general-purpose input / output port;
[0043] GMAC: igabit Media Access Controller, gigabit network controller.
[0044] Figure 1It is a structural diagram of a network transmission module based on a programmable logic array and a PCIE controller provided by an exemplary embodiment of the present invention. Figure 2 FIG. 1 is a schematic diagram of data flow between different levels provided by an exemplary embodiment of the present invention. Figure 1 and Figure 2 As shown, the network transmission module based on the programmable logic array and the PCIE controller includes: a CPU module, an FPGA network module, a switching chip network module, n ordinary network ports and n redundant network ports; wherein the CPU module is interconnected with the FPGA network module through a PCIE interface to form a redundant network; the CPU module is interconnected with the switching chip network module through a GMAC interface to form a heterogeneous network; the FPGA network module receives network messages sent from the outside through n redundant network ports, and transmits the network messages to the CPU module through a PCIE bus; the switching chip network module receives network messages sent from the outside through n-1 ordinary network ports, communicates with the CPU module through the nth ordinary network port, and transmits the network messages to the CPU module through a GMAC bus; when the CPU module needs to send data externally through a redundant network, the data to be sent is transmitted to the FPGA network module through the PCIE bus, and the FPGA network module completes the sending of the external network message; when the CPU module needs to send data externally through a heterogeneous network, the data to be sent is transmitted to the switching chip network module through the GMAC bus, and the switching chip network module completes the sending of the external network message.
[0045] Optionally, the CPU module includes a GMAC controller, an RC end of a PCIE controller, a general input / output port, a CPU driver module and a network protocol stack; wherein the CPU module initiates data transmission with the switching chip network module through the GMAC controller, initiates data transmission to the FPGA network module through the RC end of the PCIE controller, notifies the CPU driver module to process network messages through the interrupt function of the general input / output port, and stores the network messages processed by the CPU driver module through the network protocol stack.
[0046] Optionally, the FPGA network module includes an EP end of a PCIE controller, an I / O resource submodule, a logic processing submodule, and a network transceiver submodule; wherein the EP end of the PCIE controller is responsible for interactive transmission of the PCIE bus with the CPU module; the I / O resource submodule is responsible for triggering the interrupt function of the general input / output port; the logic processing submodule is responsible for processing and parsing multi-network port protocols; in the stage of sending data externally through a redundant network, the CPU module transmits the data to be sent to the EP end of the PCIE controller of the FPGA network module through the PCIE bus, and the EP end of the PCIE controller sends the data to be sent to the EP end of the PCIE controller. The data is transmitted to the logic processing submodule. The FPGA network module parses and processes the data to be sent according to the multi-network port protocol in the logic processing submodule, and then pushes the message to the n redundant network ports through the network transceiver submodule. In the stage of receiving data externally through the redundant network, the FPGA network module receives the network message transmitted by the n redundant network ports through the network transceiver submodule. After being processed by the logic processing submodule, the network message is placed in the designated memory location of the CPU module through the PCIE bus. After the transmission is completed, the interrupt function of the general input / output port is triggered through the I / O resource submodule to notify the CPU module to process the network message.
[0047] In the embodiment of the present invention, the network transmission module is composed of a CPU module, an FPGA network module, and a switch chip network module, and implements a multi-network port protocol. The FPGA network module implements the expansion and communication of the network module externally, and is connected to the multi-core CPU module internally through the PCIE bus. The FPGA network module is composed of a network transceiver submodule, a logic processing submodule, an EP terminal module of the PCIE controller, and an I / O resource submodule.
[0048] The network transceiver submodule is responsible for the encoding and decoding of network signals; the logic processing submodule is responsible for the processing and analysis of multi-network port protocols; the EP terminal module of the PCIE controller is responsible for the interactive transmission of the PCIE bus with the CPU module; the I / O resource submodule is responsible for the triggering of the general input / output port (GPIO) interrupt. In the sending stage, the CPU module transmits the data to be sent to the EP terminal module of the PCIE controller of the FPGA network module through the PCIE bus. The FPGA network module parses and processes the network message according to the multi-network port protocol in the logic processing submodule, and then pushes the message to the external redundant network port through the network transceiver submodule. In the receiving stage, the FPGA network module receives the external redundant network port message, and after being processed by the logic processing submodule, the network message is placed in the specified memory location of the CPU module through the PCIE bus. After the transmission is completed, the general input / output port interrupt is triggered through the I / O resource submodule to notify the CPU module to process the network message.
[0049] The switch chip network module performs network expansion based on the GMAC mechanism. The CPU module is interconnected with the switch chip network module through the GMAC interface, and the switch chip network module is responsible for the interaction between the external network port data and the CPU network port data. The CPU module interacts with the network data through the GMAC controller and the PCIE controller.
[0050] In the embodiment of the present invention, the CPU module can use the RK3568 multi-core processor of Rockchip (using a 4-core Cortex-A55 architecture and supporting 2-way PCIE3.0 interfaces), the FPGA network module can use the PG2L100H chip of Unigroup Tongchuang, and the switch chip network module can use the YT9215 chip of Yutai Chetong. The CPU module and the FPGA network module are interconnected through the PCIE bus to expand the redundant network port, and the CPU module and the switch chip network module are interconnected to expand the common network port.
[0051] The CPU module actively initiates data transmission through the RC end of the PCIE controller. When the FPGA network module (PG2L100H) receives a network message from the external network, it inserts the corresponding network port information into the network message, actively initiates PCIE transmission, and pushes the received message to the specified memory location on the CPU module (RK3568 multi-core processor) side without the intervention of the CPU module. Then, the GPIO interrupt is triggered to notify the CPU driver module to process the network message. The CPU driver module adopts the NAPI mechanism to enhance the efficiency of processing network messages. The CPU driver module is responsible for collecting and summarizing the data packets pushed to the memory by the FPGA controller, converting them into standard network messages, and handing them over to the network protocol stack.
[0052] When the RK3568 multi-core processor enters the GPIO interrupt, the NAPI mechanism is used. That is, after the GPIO interrupt triggers the RK3568 multi-core processor to process the network message, the GPIO interrupt function is immediately turned off, the network message reception is switched to the polling mode, and subsequent data packets are continuously received. The received data packets are parsed and processed, and sent to the corresponding network card protocol stack. After the network message is received and sent to the network protocol stack, the GPIO interrupt function is reopened.
[0053] The RK3568 multi-core processor inserts the network port information that needs to be sent into the network sending message, triggers PCIE transmission, and passes the network message to PG2L100H through the PCIE bus. PG2L100H is responsible for parsing the network card information and sending the network message to the specified network port, completing the process of sending the external network message.
[0054] Optionally, for redundant networks, a network label field is added to the network messages between the CPU module and the FPGA network module. The network label field is used to distinguish the n redundant network ports of the FPGA network module to the outside world, thereby achieving logical independence of multiple network ports.
[0055] In the embodiment of the present invention, a network tag field is added to the network message between the CPU module and the FPGA network module to distinguish the external RJ45 network port of the FPGA network module and realize the logical independence of multiple network ports. The FPGA network module and the CPU driver module are responsible for processing the tag field to realize the logically independent network port.
[0056] Optionally, during the process of sending network messages, the CPU module inserts the network card information field into the network message to be sent, the FPGA network module is responsible for parsing the network card information field and recovering the network message, and then passing the network message to the corresponding redundant network port; during the process of receiving network messages, the FPGA network module inserts the received network port information field into the network message, the CPU module parses the network port information field and recovers the network message, and pushes the corresponding network message to the network protocol stack.
[0057] In the embodiment of the present invention, during the network message sending process, the CPU module inserts the network card information into the network sending message, and the FPGA network module is responsible for parsing the network card information field and recovering the network sending message, and then passing the corresponding network sending message to the corresponding RJ45 network port. During the network message receiving process, the FPGA network module inserts the received network port information into the network receiving message, and the CPU module side parses the field and recovers the network receiving message, and sends the corresponding network receiving message to the network protocol stack of the corresponding network port.
[0058] Optionally, for a redundant network, after the general input / output port interrupt triggers the CPU module to process the network message, the CPU module turns off the interrupt function of the general input / output port, switches the reception of the network message to the polling mode, and continues to receive subsequent data packets; after the network message is received and sent to the corresponding network protocol stack, the CPU module reopens the interrupt function of the general input / output port.
[0059] Optionally, for heterogeneous networks, the CPU module uses a standard GMAC network transceiver process to communicate with the external network.
[0060] In an embodiment of the present invention, for the redundant network extended by the PCIE controller, the CPU module processes the message using the NAPI (hybrid interrupt + polling) mechanism, that is, after the general input / output port interrupt triggers the CPU module to process the network message, the general input / output port interrupt function is immediately turned off, the network message reception is switched to the polling mode, and subsequent data packets are continuously received. After the network message is received and sent to the corresponding network protocol stack, the general input / output port interrupt function is reopened. The CPU module sends the network message by triggering PCIE transmission, and passes the message to be sent to the FPGA network module through the PCIE bus. For the heterogeneous network extended by the switching chip network module, the standard GMAC network transceiver process is used to communicate with the external network.
[0061] In summary, the present invention utilizes the existing programmable logic array (FPGA network module) and PCIE bus, combines the technical advantages of the programmable logic array and the PCIE controller, and designs an efficient and flexible network transmission module, which does not occupy the original network card controller, and utilizes the existing PCIE interface and GMAC interface of the CPU module to interconnect with the FPGA network module and the switching chip network module respectively, and obtains a redundant network through the expansion of the PCIE controller, and obtains a heterogeneous network through the expansion of the GMAC controller, with strong flexibility and scalability. In addition, the present invention utilizes the existing interface of the CPU module to interconnect with the FPGA network module and the switching chip network module respectively, which reduces the selection threshold of the CPU module, the FPGA network module and the switching chip network module in terms of the interface, and reduces the hardware cost. The technical problems of high hardware cost, poor flexibility and poor scalability of the existing network transmission module are solved.
[0062] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present invention to the forms disclosed herein. Although a number of example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.
Claims
1. A network transmission module based on a programmable logic array and a PCIE controller, characterized in that: include: CPU module, FPGA network module, switch chip network module, n common network ports and n redundant network ports; in The CPU module is interconnected with the FPGA network module through the PCIE interface to form a redundant network; The CPU module is interconnected with the switch chip network module through the GMAC interface to form a heterogeneous network; The FPGA network module receives network messages sent from the outside through n redundant network ports, and transmits the network messages to the CPU module through the PCIE bus; The switch chip network module receives network messages sent from the outside through n-1 common network ports, communicates with the CPU module through the nth common network port, and transmits the network messages to the CPU module through the GMAC bus; When the CPU module needs to send data externally through the redundant network, the data to be sent is transmitted to the FPGA network module through the PCIE bus, and the FPGA network module completes the sending of external network messages; When the CPU module needs to send data externally through a heterogeneous network, the data to be sent is transmitted to the switch chip network module through the GMAC bus, and the switch chip network module completes the sending of external network messages.
2. The network transmission module according to claim 1, characterized in that: The CPU module includes a GMAC controller, an RC end of a PCIE controller, a general input / output port, a CPU driver module and a network protocol stack; in The CPU module initiates data transmission with the switching chip network module through the GMAC controller, initiates data transmission to the FPGA network module through the RC end of the PCIE controller, notifies the CPU driver module to process network messages through the interrupt function of the general input / output port, and stores the network messages processed by the CPU driver module through the network protocol stack.
3. The network transmission module according to claim 2, characterized in that: The FPGA network module includes an EP end of a PCIE controller, an I / O resource submodule, a logic processing submodule, and a network transceiver submodule; The EP end of the PCIE controller is responsible for interactive transmission of the PCIE bus with the CPU module; the I / O resource submodule is responsible for triggering the interrupt function of the general input / output port; the logic processing submodule is responsible for processing and parsing the multi-network port protocol; In the stage of sending data externally through the redundant network, the CPU module transmits the data to be sent to the EP end of the PCIE controller of the FPGA network module through the PCIE bus, and the EP end of the PCIE controller transmits the data to be sent to the logic processing submodule. The FPGA network module parses and processes the data to be sent according to the multi-network port protocol in the logic processing submodule, and then pushes the message to the external n redundant network ports through the network transceiver submodule; In the stage of receiving data externally through the redundant network, the FPGA network module receives network messages transmitted by n redundant network ports through the network transceiver submodule. After being processed by the logic processing submodule, the network message is placed in the specified memory location of the CPU module through the PCIE bus. After the transmission is completed, the interrupt function of the general input / output port is triggered through the I / O resource submodule to notify the CPU module to process the network message.
4. The network transmission module according to claim 3, characterized in that: For redundant networks, a network label field is added to the network messages between the CPU module and the FPGA network module. The network label field is used to distinguish the n redundant network ports of the FPGA network module to the outside world, thereby achieving logical independence of multiple network ports.
5. The network transmission module according to claim 3, characterized in that: During the network message sending process, the CPU module inserts the network card information field into the network message to be sent, and the FPGA network module is responsible for parsing the network card information field and recovering the network message, and then transmits the network message to the corresponding redundant network port; During the network message reception process, the FPGA network module inserts the received network port information field into the network message, the CPU module parses the network port information field, restores the network message, and pushes the corresponding network message to the network protocol stack.
6. The network transmission module according to claim 3, characterized in that: For redundant networks, after the general input / output port interrupt triggers the CPU module to process the network message, the CPU module turns off the general input / output port interrupt function, switches the reception of the network message to the polling mode, and continues to receive subsequent data packets; after the network message is received and sent to the corresponding network protocol stack, the CPU module reopens the general input / output port interrupt function.
7. The network transmission module according to claim 3, characterized in that: For heterogeneous networks, the CPU module uses the standard GMAC network transceiver process to communicate with the external network.