Fast PWM dimming device and control method

Abstract

An apparatus includes a turn-on timer, an offset current control stage, a current comparison stage, and a PWM comparator. The turn-on timer is configured to determine the turn-on time of a high-side switch of the step-down power converter; the offset current control stage is configured to convert a voltage difference between the compensation signal and a predetermined reference into a current difference; the current comparison stage is configured to amplify the sensed current signal; the input end of the PWM comparator is coupled to the two output ends of the current comparison stage and the two output ends of the offset current control stage, and during the load transient period from the first load level to the second load level and in the first switch-on pulse of the high-side switch, the PWM comparator is connected with the two output ends of the offset current control stage. The turn-on timer is disabled such that current flowing through the buck power converter reaches a second load level within a first turn-on pulse of the high side switch.

Description

Technical Field

[0001] The present invention relates to a fast pulse width modulation (PWM) dimming device and control method, and in a specific embodiment, to a fast PWM dimming device and control method for light emitting diode (LED) applications. Background Art

[0002] A light emitting diode is a semiconductor light source. When voltage is applied to an LED, current flows through the LED. In response to the current flowing through the LED, electrons and holes recombine in the diode's PN junction. During this recombination process, energy is released in the form of photons. The intensity of the light produced by the LED is proportional to the current flowing through the LED. The current flowing through the LED can be adjusted in order to change the brightness level of the LED.

[0003] The control process of adjusting the current flowing through the LED is usually called dimming. The dimming process can be divided into two categories, namely analog dimming and PWM dimming.

[0004] Analog dimming involves continuously changing the voltage or current supplied to the LED to adjust its brightness. During analog dimming, the controller changes the amplitude of the electrical signal in a smooth, continuous manner, allowing seamless adjustment of the brightness level.

[0005] On the other hand, PWM dimming involves rapidly switching the LED on and off at a fixed frequency. The brightness of the LED is controlled by changing the ratio of the time the LED is on to the time the LED is off during each cycle. This ratio is also called the duty cycle. For example, a longer on-time of the LED during each cycle results in increased brightness. Conversely, a shorter on-time of the LED during the cycle results in decreased brightness. PWM dimming is typically implemented using a suitable microcontroller such as a PWM controller, a dedicated LED driver, etc.

[0006] Constant on-time control schemes are widely used in PWM dimming to achieve fast transient response. Constant on-time control schemes are techniques used in power converters to regulate output voltage or current. For example, in a step-down power converter, when the output voltage decreases due to load changes or other factors, the constant on-time control circuit adjusts the off-time of the high-side switch to keep the on-time of the high-side switch constant. This means that the high-side switch is turned on for the same duration in each cycle, but the off-time varies according to the load conditions.

[0007] A buck power converter using a constant on-time control scheme may include only a comparator and an on-timer. In operation, the comparator directly compares the feedback signal with a predetermined reference. When the feedback signal is below the predetermined reference, the high-side switch of the buck power converter is turned on and remains on for a duration determined by the on-timer. As the high-side switch is turned on, the inductor current of the buck power converter rises. When the on-timer expires, the high-side switch of the buck power converter is turned off and is not turned on until the feedback signal drops below the predetermined reference again.

[0008] In summary, when a constant on-time control scheme is adopted in a power converter, the on-time of the high-side switch of the power converter is terminated by the on-timer, and the off-time of the high-side switch of the power converter is terminated by the comparator.

[0009] Typically, LED drivers based on constant on-time control tend to exhibit a hysteretic dynamic response during PWM dimming. This hysteresis poses a challenge in the process of output current being quickly consistent with the PWM dimming signal. It is desirable to have a fast PWM dimming device and control method to improve PWM dimming accuracy. The present disclosure addresses this need. Summary of the invention

[0010] These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred embodiments of the present disclosure that provide a fast PWM dimming apparatus and control method for LED applications.

[0011] According to one embodiment, a device includes: a conduction timer, an offset current control stage, a current comparison stage, and a PWM comparator. The conduction timer is configured to determine the conduction time of a high-side switch of a buck power converter; the offset current control stage is configured to convert a voltage difference between a compensation signal and a predetermined reference into a current difference; the current comparison stage is configured to amplify a sensed current signal; and an input terminal of the PWM comparator is coupled to two output terminals of the current comparison stage and two output terminals of the offset current control stage, wherein during a load transient from a first load level to a second load level and in a first turn-on pulse of the high-side switch, the conduction timer is disabled so that the current flowing through the buck power converter reaches the second load level within the first turn-on pulse of the high-side switch.

[0012] According to another embodiment, a method includes disabling an on-timer of a controller in a first turn-on pulse of a high-side switch of a buck power converter in response to a leading edge of a load transient signal; and configuring a current comparison stage of the controller to cause a current flowing through the buck power converter to reach a final load level of the load transient within the first turn-on pulse of the high-side switch.

[0013] According to yet another embodiment, a system includes a high-side switch and a low-side switch connected in series between an input voltage bus and ground; an inductor and a current sensing resistor connected in series between a common node of the high-side switch and the low-side switch and an output terminal of a buck power converter; an output capacitor connected between the output terminal of the buck power converter and ground; and a controller. The controller includes: an on-timer configured to determine a conduction time of the high-side switch of the buck power converter; an offset current control stage configured to convert a voltage difference between a compensation signal and a predetermined reference into a current difference; a current comparison stage configured to amplify the sensed current signal; and a PWM comparator, the input of which is coupled to two output terminals of the current comparison stage and two output terminals of the offset current control stage, wherein during a load transient from a first load level to a second load level and in a first on-pulse of the high-side switch, the on-timer is disabled so that the current flowing through the buck power converter reaches the second load level within the first on-pulse of the high-side switch.

[0014] The features and technical advantages of the present disclosure have been summarized quite broadly above so that the detailed description of the present disclosure below can be better understood. Additional features and advantages of the present disclosure will be described hereinafter, which form the subject matter of the claims of the present disclosure. It will be appreciated by those skilled in the art that the disclosed concepts and specific embodiments can be easily used as the basis for modifying or designing other structures or processes for achieving the same purpose as the present disclosure. It will also be appreciated by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present disclosure as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, in which:

[0016] Figure 1 A diagram illustrating a power conversion system with a fast PWM dimming device according to various embodiments of the present disclosure;

[0017] Figure 2 The present invention illustrates various embodiments of the present invention. Figure 1 A schematic diagram of a first implementation of a controller for a fast PWM dimming device shown;

[0018] Figure 3 The present invention illustrates various embodiments of the present invention. Figure 2 A schematic diagram of the enabling circuit shown;

[0019] Figure 4 FIG. 1 illustrates a voltage on a switching node and a current flowing through an inductor in a first implementation of a controller according to various embodiments of the present disclosure;

[0020] Figure 5The control diagram according to various embodiments of the present disclosure is shown. Figure 1 Flowchart of the buck converter shown;

[0021] Figure 6 The present invention illustrates various embodiments of the present invention. Figure 1 A schematic diagram of a second implementation of a controller for a fast PWM dimming device shown;

[0022] Figure 7 FIG. 1 illustrates the voltage on the switching node and the current flowing through the inductor in a second implementation of the controller according to various embodiments of the present disclosure;

[0023] Figure 8 The present invention illustrates various embodiments of the present invention. Figure 1 A schematic diagram of a third implementation of a controller of a fast PWM dimming device shown; and

[0024] Fig. 9 FIG. 4 illustrates the voltage on the switching node and the current flowing through the inductor in a third implementation of the controller according to various embodiments of the present disclosure.

[0025] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0026] The manufacture and use of the currently preferred embodiments are discussed in detail below. However, it should be understood that the present disclosure provides many applicable inventive concepts that can be implemented in a wide variety of specific contexts. The specific embodiments discussed merely illustrate specific ways to manufacture and use the present disclosure, and do not limit the scope of the present disclosure.

[0027] The present disclosure will be described with respect to a preferred embodiment in a specific context, namely a fast PWM dimming device for LED applications. However, the present invention can also be applied to various power supply applications. In the following, various embodiments will be explained in detail with reference to the accompanying drawings.

[0028] Figure 1 A diagram of a power conversion system with a fast PWM dimming device according to various embodiments of the present disclosure is illustrated. The power conversion system includes a buck power converter. The buck power converter includes a high-side switch Q1 and a low-side switch Q2 connected in series between an input voltage bus VIN and ground. The buck power converter also includes an inductor L1 and a current sensing resistor RCS connected in series between a common node of the high-side switch Q1 and the low-side switch Q2 and an output terminal Vo of the buck power converter. An output capacitor Co is connected between the output terminal Vo of the buck power converter and ground.

[0029] The common node of the high-side switch Q1 and the low-side switch Q2 is denoted as the switching node SW. The first end of the current sensing resistor RCS (the common node of the inductor L1 and the current sensing resistor RCS) is denoted as the CSP node. The second end of the current sensing resistor RCS is denoted as the CSN node.

[0030] According to an embodiment, Figure 1 The switches (e.g., switches Q1 and Q2) may be metal oxide semiconductor field effect transistor (MOSFET) devices. Alternatively, the switches may be any controllable switches, such as insulated gate bipolar transistor (IGBT) devices, integrated gate commutated thyristor (IGCT) devices, gate turn-off thyristor (GTO) devices, silicon controlled rectifier (SCR) devices, junction gate field effect transistor (JFET) devices, MOS controlled thyristor (MCT) devices, gallium nitride (GaN)-based power devices, silicon carbide (SiC)-based power devices, etc.

[0031] It should be noted that although Figure 1 The switches Q1 and Q2 are shown to be implemented as a single n-type transistor, but those skilled in the art will recognize that there are many variations, modifications, and substitutions. For example, at least some of the switches (e.g., Q1) may be implemented as p-type transistors, depending on different applications and design requirements. In addition, Figure 1 Each switch shown can be implemented as multiple switches connected in parallel. In addition, a capacitor can be connected in parallel with a switch to achieve zero voltage switching (ZVS) / zero current switching (ZCS).

[0032] like Figure 1 As shown, a load 120 is connected between the output terminal Vo of the buck power converter and the ground. In some embodiments, the load 120 includes a plurality of light emitting diodes connected in series. The brightness of the plurality of light emitting diodes is controlled by PWM dimming. During the PWM dimming process, the buck power converter quickly turns on and off the plurality of light emitting diodes at a fixed frequency. The brightness of the plurality of light emitting diodes is determined by the PWM dimming duty cycle. The PWM dimming duty cycle is the ratio of the duration of the logic high level of the PWM dimming signal to the period of the PWM dimming signal. The brightness of the plurality of light emitting diodes can be adjusted by changing the PWM dimming duty cycle. In some embodiments, the brightness of the plurality of light emitting diodes is proportional to the PWM dimming duty cycle.

[0033] In stable operation, Figure 1The buck power converter shown is controlled by a constant on-time control scheme, or the buck power converter operates in a constant on-time mode. During PWM dimming, the current flowing through the plurality of light emitting diodes changes from a first load level (e.g., zero amperes) to a second load level (e.g., one ampere or two amperes). In response to the leading edge of the PWM dimming signal, the constant on-time control scheme is temporarily disabled. A fast PWM dimming control scheme is adopted. In other words, the buck power converter operates in a fast PWM dimming mode. In the fast PWM dimming mode, the current flowing through the plurality of light emitting diodes can reach a predetermined PWM dimming current (e.g., a second load level) within a first turn-on pulse of the high-side switch Q1.

[0034] like Figure 1 As shown, the controller 100 is configured to receive a plurality of operating parameters, including a voltage signal on a CSP node, a voltage signal on a CSN node, a voltage signal on an input voltage bus VIN, a voltage signal on an output terminal Vo, etc. Based on the received signals, the controller 100 can generate gate drive signals DH and DL for the high-side switch Q1 and the low-side switch Q2, respectively. Figure 1 As shown, the high-side gate drive signal DH is fed to the gate of the high-side switch Q1 through the first driver 112. The low-side gate drive signal DL is fed to the gate of the low-side switch Q2 through the second driver 114. Both the first driver 112 and the second driver 114 have sufficient driving capabilities to reduce switching losses. Thus, the high-side switch Q1 and the low-side switch Q2 can operate at a predetermined high switching frequency. In addition, the controller 100 is configured to receive a PWM dimming signal. According to the PWM dimming signal, the buck power converter turns on and off the multiple light-emitting diodes at a predetermined PWM dimming duty cycle. More specifically, when the PWM dimming signal changes from a logic low state to a logic high state, the current flowing through the multiple light-emitting diodes changes from a first load level (e.g., zero amperes) to a second load level (e.g., two amperes). On the other hand, when the PWM dimming signal changes from a logic high state to a logic low state, the current flowing through the multiple light-emitting diodes changes from the second load level to the first load level.

[0035] In some embodiments, the controller 100 includes a conduction timer, an offset current control stage, an offset current control stage, a current comparison stage, a PWM comparator, and an enabling circuit. The conduction timer is configured to determine the conduction time of the high-side switch Q1 of the buck power converter. The offset current control stage is configured to convert the voltage difference between the compensation signal and the predetermined reference into a current difference. The current comparison stage is configured to amplify the sensed current signal. The sensed current signal is equal to or proportional to the voltage across the CSP node and the CSN node. Two input terminals of the PWM comparator are respectively coupled to two output terminals of the current comparison stage and two output terminals of the offset current control stage. The enabling circuit is configured so that during the PWM dimming process (for example, the PWM dimming signal changes from a logic low state to a logic high state, and the current flowing through the plurality of light-emitting diodes changes from a first load level to a second load level), in the first turn-on pulse of the high-side switch Q1, the conduction timer is disabled. Because the conduction timer is disabled, the current flowing through the buck power converter reaches the second load level within the first turn-on pulse of the high-side switch Q1.

[0036] During the PWM dimming process, in a first implementation of the controller 100, the two outputs of the offset current control stage are disconnected from the two inputs of the PWM comparator during the first on pulse of the high-side switch Q1. Figure 2 A detailed circuit diagram of a first implementation of the controller 100 is described.

[0037] During the PWM dimming process, in a second implementation of the controller 100, the two outputs of the offset current control stage are connected to the two inputs of the PWM comparator during the first on pulse of the high-side switch Q1. Figure 6 A detailed circuit diagram of a second implementation of the controller 100 is described.

[0038] During the PWM dimming process, in a third implementation of the controller 100, the two outputs of the offset current control stage are interchanged during the first on pulse of the high-side switch Q1 and then connected to the two inputs of the PWM comparator. Figure 8 A detailed circuit diagram of a third implementation of the controller 100 is described.

[0039] Figure 2 The present invention illustrates various embodiments of the present invention. Figure 1 The controller 100 includes a conduction timer 130 , an offset current control stage 150 , a current comparison stage 160 , a PWM comparator 125 , a logic circuit 120 and an enable circuit 140 .

[0040] The on-timer 130 is configured to determine the on-time of the high-side switch Q1 of the buck power converter. The on-timer 130 has three input terminals and one output terminal. Figure 2 As shown, the on-timer 130 is configured to receive the input voltage VIN, the output voltage Vo and the enable signal EN_SUM. Based on the received signals, the on-timer 130 is configured to generate a control signal fed to the logic circuit 120.

[0041] In some embodiments, the on-timer 130 includes a current source, a capacitor, a switch, and a comparator. The current source and the capacitor are connected in series. The switch and the capacitor are connected in parallel. The inverting terminal of the comparator is connected to a common node of the current source and the capacitor. The non-inverting terminal is a predetermined reference. In some embodiments, the current source can be coupled to an input voltage VIN. In addition, the current level of the current source is proportional to the input voltage VIN. More specifically, the current level of the current source can be equal to the input voltage VIN divided by a predetermined resistance. The predetermined reference can be proportional to the output voltage of the buck power converter.

[0042] like Figure 2 As shown, the current comparison stage 160 includes a first amplifier 121, a second amplifier 122, a first resistor R1, a second resistor R2, an adjustable current source Iadj, a third resistor R3 and a fourth resistor R4. In some embodiments, the gain of the first amplifier 121 is equal to 3. The gain of the second amplifier 122 is equal to 1. The resistance value of the first resistor R1 is 10,000 ohms. The resistance value of the second resistor R2 is 10,000 ohms. The resistance value of the third resistor R3 is 80,000 ohms. The resistance value of the fourth resistor R4 is 80,000 ohms. The current flowing through the adjustable current source Iadj is in the range of 1 microampere to 100 microamperes. In some embodiments, the current flowing through the adjustable current source Iadj is equal to 10 microamperes.

[0043] The non-inverting input terminal of the first amplifier 121 is connected to the CSP node (the common node of the inductor L1 and the current sensing resistor RCS) through the first resistor R1. The inverting input terminal of the first amplifier 121 is connected to the CSN node (the output terminal of the buck power converter) through the second resistor R2. The adjustable current source Iadj is connected to the non-inverting input terminal of the first amplifier 121. In operation, the current flowing through the adjustable current source Iadj is proportional to the PWM dimming current (e.g., two amperes).

[0044] The non-inverting input terminal of the second amplifier 122 is connected to the first output terminal of the first amplifier 121. The bus connected between the non-inverting input terminal of the second amplifier 122 and the first output terminal of the first amplifier 121 is represented as a CSP8 node. The inverting input terminal of the second amplifier 122 is connected to the second output terminal of the first amplifier 121. The bus connected between the inverting input terminal of the second amplifier 122 and the second output terminal of the first amplifier 121 is represented as a CSN8 node. The third resistor R3 is connected between the first output terminal of the second amplifier 122 and the inverting input terminal of the PWM comparator 125. The fourth resistor R4 is connected between the second output terminal of the second amplifier 122 and the non-inverting input terminal of the PWM comparator 125.

[0045] The voltage across the node CSP and the node CSN is a sensed current signal. The sensed current signal is proportional to the current flowing through the inductor L1. The current comparison stage 160 is configured to receive the sensed current signal and amplify the sensed current signal to an appropriate level fed into the PWM comparator 125.

[0046] The offset current control stage 150 includes a third amplifier 123, a compensation capacitor Ccomp, a fourth amplifier 124, a first auxiliary switch S1 and a second auxiliary switch S2. Figure 2 As shown, the non-inverting input terminal of the third amplifier 123 is connected to the inverting input terminal of the second amplifier 122. The inverting input terminal of the third amplifier 123 is connected to the non-inverting input terminal of the second amplifier 122. The compensation capacitor Ccomp is connected between the output terminal of the third amplifier 123 and the ground. The third amplifier 123 is configured to generate a compensation signal COMP on the compensation capacitor Ccomp. The non-inverting input terminal of the fourth amplifier 124 is configured to receive the compensation signal COMP. The inverting input terminal of the fourth amplifier 124 is configured to receive a predetermined reference VREF.

[0047] The first auxiliary switch S1 is connected between the first output terminal of the fourth amplifier 124 and the non-inverting input terminal of the PWM comparator 125. The second auxiliary switch S2 is connected between the second output terminal of the fourth amplifier 124 and the inverting input terminal of the PWM comparator 125. Both the first auxiliary switch S1 and the second auxiliary switch S2 are controlled by the enable signal EN_SUM generated by the enable circuit 140.

[0048] During normal operation, the enable signal EN_SUM is configured so that both the first auxiliary switch S1 and the second auxiliary switch S2 are turned on. Therefore, the offset current control stage 150 is connected to the PWM stage 125 through the turned-on S1 and S2. On the other hand, during the PWM dimming load transient, within the first turn-on pulse of the high-side switch Q1, both the first auxiliary switch S1 and the second auxiliary switch S2 are turned off. Therefore, the offset current control stage 150 is disconnected from the PWM stage 125.

[0049] In some embodiments, the third amplifier 123 is used as an integrator. The fourth amplifier 124 is used as a transconductance amplifier. The output current of the fourth amplifier 124 is proportional to the input voltage of the fourth amplifier 124. During normal operation, the offset current control stage 150 is configured to convert the voltage difference between the compensation signal and the predetermined reference into a current difference. The current difference is added to the input terminal of the PWM comparator 125 through the third resistor R3 and the fourth resistor R4. The offset current control stage 150 is used to determine the current ripple of the current flowing through the inductor L1.

[0050] The enable circuit 140 is configured to generate an enable signal EN_SUM. During normal operation, EN_SUM is configured such that the on-timer 130 is enabled and S1 and S2 are turned on. The offset current control stage 150 is connected to the PWM comparator 125. In response to the leading edge of the PWM dimming signal, EN_SUM is configured such that the on-timer 130 is disabled and S1 and S2 are turned off. The offset current control stage 150 is disconnected from the PWM comparator 125 in the first on pulse of the high-side switch Q1. Figure 3 A detailed circuit structure of the enabling circuit 140 is described.

[0051] In operation, when the on-timer 130 is enabled, the output of the on-timer 130 determines the turn-off edge or trailing edge of the gate drive signal applied to the high-side switch Q1. The PWM comparator 125 is configured to generate a control signal P1 that is fed into the logic circuit 120. The control signal P1 determines the turn-on edge or leading edge of the gate drive signal applied to the high-side switch Q1. When the on-timer 130 is disabled, the control signal P1 determines the turn-off edge of the gate drive signal applied to the high-side switch Q1.

[0052] During the PWM dimming process, during the load transient from the first load level to the second load level and in the first on-pulse of the high-side switch Q1, the two output terminals of the offset current control stage 150 are disconnected from the two input terminals of the PWM comparator 125 by turning off S1 and S2. The on-timer 130 is disabled. The PWM comparator 125 is configured to generate a logic high signal until a valley trigger occurs once the offset current control stage 150 is disconnected from the PWM comparator 125 and the on-timer 130 is disabled. In operation, a valley trigger occurs when the current flowing through the inductor L1 is equal to the desired current (the desired current is the PWM dimming current determined by the current of Iadj). In other words, the PWM comparator 125 can keep the high-side switch Q1 turned on until the current flowing through the inductor L1 is equal to the PWM dimming current. Since the low-side switch Q2 is not turned on, the current flowing through the buck power converter can reach the second load level within the first on-pulse of the high-side switch Q1.

[0053] Figure 3 The present invention illustrates various embodiments of the present invention. Figure 2 The enabling circuit 140 includes a first AND gate 511 , a second AND gate 512 , a first inverter 501 , a second inverter 502 , a latch 520 and a NOR gate 521 .

[0054] An input terminal of the first inverter 501 is configured to receive a control signal P1 generated by the PWM comparator 125. A first input terminal of the first AND gate 511 is configured to receive a gate drive enable signal DRV_EN. A second input terminal of the first AND gate 511 is configured to receive an output signal of the first inverter 501. A first input terminal of the second AND gate 512 is configured to receive a PWM dimming signal PWMDIM. A second input terminal of the second AND gate 512 is configured to receive a power converter enable signal EN.

[0055] The data input of the latch 520 is connected to the bias voltage bus DVDD. The clock input of the latch 520 is connected to the output of the first AND gate 501. The clear and reset inputs of the latch 520 are connected to the output of the second AND gate 512. The first input of the NOR gate 521 is connected to the output of the latch 520. The second input of the NOR gate 521 is configured to receive the signal DRV_EN_DLY. The signal DRV_EN_DLY is configured to determine the maximum pulse width of the first turn-on pulse of the high-side switch Q1. The input of the second inverter 502 is connected to the output of the NOR gate 521. The enable signal EN_SUM is generated at the output of the second inverter 502.

[0056] In normal operation, both DRV_EN and EN have a logic high state. The voltage on the bias voltage bus DVDD is equal to the logic high state. The signal DRV_EN_DLY is a protection signal. DRV_EN_DLY is related to the maximum pulse width of the first turn-on pulse of the high-side switch Q1. When the pulse width of the first turn-on pulse of the high-side switch Q1 is within a predetermined pulse width, DRV_EN_DLY has a logic low state. The enable signal EN_SUM is determined by the output signal of the latch 520. When the pulse width of the first turn-on pulse of the high-side switch Q1 exceeds the predetermined pulse width, DRV_EN_DLY has a logic high state. The logic high state of DRV_EN_DLY forces the enable signal EN_SUM to have a logic high state. In other words, the power converter leaves the fast PWM dimming mode and enters the normal operation mode. In the normal operation mode, the conduction timer turns off the high-side switch Q1 in each cycle to ensure that the conduction time of Q1 does not increase uncontrollably.

[0057] In response to the logic low state of the PWM dimming signal PWMDIM, the output of the latch 520 is reset. The logic low signal is fed to the NOR gate 521. Starting from the turn-on time of Q1, within a predetermined time period (e.g., 20 microseconds), DRV_EN_DLY has a logic low state. The output of the NOR gate 521 generates a logic high signal fed into the second inverter 502. In response to the logic high signal fed into the second inverter 502, the enable signal EN_SUM has a logic low state. This logic low state of EN_SUM serves as a disable signal. The disable signal turns off S1 and S2, thereby disconnecting the offset current control stage 150 from the PWM comparator 125. In addition, the disable signal is applied to the on-timer 130. Therefore, the on-timer 130 is disabled. Since the offset current control stage 150 is disconnected from the PWM comparator 125 and the on-timer 130 is disabled, the high-side switch Q1 remains on until the current flowing through the inductor L1 reaches a predetermined level (e.g., PWM dimming current). Once the current flowing through the inductor L1 reaches the predetermined level, the output signal (P1) of the PWM comparator 125 changes from a logic high state to a logic low state. In response to the logic low state of P1, the first inverter 501 generates a logic high signal fed to the first AND gate 511. In normal operation, DRV_EN has a logic high state. The output of the first AND gate 511 changes from a logic low state to a logic high state. In response to the rising edge of the output of the first AND gate 511, the output of the latch 520 generates a logic high signal. The logic high signal is fed to the NOR gate 521 and the second inverter 502. At the output of the second inverter 502, the enable signal EN_SUM changes from a logic low state to a logic high state. This logic high state of EN_SUM serves as an enable signal. The enable signal turns on S1 and S2, thereby connecting the offset current control stage 150 to the PWM comparator 125. In addition, the enable signal enables the on-timer 130. Since the offset current control stage 150 is connected to the PWM comparator 125 and the on-timer 130 is enabled, the buck power converter operates in a constant on-time mode.

[0058] Figure 4 FIG. 1 illustrates the voltage on the switching node and the current flowing through the inductor in a first implementation of the controller according to various embodiments of the present disclosure. Figure 4 The horizontal axis represents the time interval. Figure 4 There may be three rows in FIG. The first row represents the PWM dimming signal PWMDIM. The second row represents the voltage on the switching node SW. The third row represents the current flowing through the inductor L1.

[0059] At t1, the PWM dimming signal PWMDIM changes from a logic low state to a logic high state. In response to the leading edge of the PWM dimming signal, the current flowing through the inductor L1 changes from a first load level (e.g., zero amperes) to a second load level (e.g., two amperes). During this load transient, the voltage on the switching node SW remains high in a wide pulse from t1 to t2. The high voltage on the switching node SW indicates that the high-side switch Q1 remains on from t1 to t2.

[0060] From t1 to t2, return reference Figure 2 , the offset current control stage 150 is disconnected from the PWM comparator 125. In some embodiments, before the power converter leaves the fast PWM dimming mode and enters the constant on-time mode, the voltage value of the compensation signal is preset to a voltage level equal to the voltage value of the compensation signal in the previous PWM dimming cycle. In an alternative embodiment, the voltage value of the compensation signal is preset at a voltage level corresponding to one-quarter of the full current flowing through the buck power converter. The preset comp value helps the buck power converter achieve a smooth transition between the fast PWM dimming mode and the constant on-time mode.

[0061] At t2, the current flowing through the inductor L1 reaches the second load level. Figure 2 , the PWM comparator 125 generates a logic low signal to turn off the high-side switch Q1. This logic low signal is also fed into the enabling circuit 140. Figure 3 As described, the enable circuit 140 generates an enable signal in response to the logic low signal. At t2, the enable signal is configured to connect the offset current control stage 150 to the PWM comparator 125 and enable the conduction timer 130. The buck power converter operates in a constant on-time mode from t2 to t6. From t3 to t5, it is a switching cycle. The on-time of the high-side switch Q1 (from t3 to t4) is shorter than the first on-pulse of the high-side switch Q1 (from t1 to t2).

[0062] have Figure 4 An advantageous feature of the wide on pulse (from t1 to t2) shown in is the significantly enhanced transient response of the buck power converter in the present disclosure compared to conventional counterparts. This fast transient response proves to be particularly advantageous in applications with minimum PWM dimming duty cycle. In conventional buck converters, multiple switching cycles are typically required to obtain a satisfactory load transient response. It takes longer to achieve the desired current level. In applications employing a low PWM dimming duty cycle, load transients may remain incomplete within the low PWM dimming duty cycle, resulting in compromised accuracy. In contrast, the fast load transient response facilitated by the present disclosure can be achieved within a low PWM dimming duty cycle, thereby improving PWM dimming accuracy.

[0063] Figure 5The control diagram according to various embodiments of the present disclosure is shown. Figure 1 The flowchart of the buck converter is shown. Figure 5 The flowchart shown is merely an example, which should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, substitutions, and modifications. For example, additions, removals, substitutions, rearrangements, and repetitions may be made. Figure 5 The steps shown.

[0064] Return to reference Figure 1 , the buck converter includes a high-side switch Q1 and a low-side switch Q2 connected in series between an input voltage bus VIN and ground. The buck power converter also includes an inductor L1 and a current sensing resistor RCS connected in series between a common node of the high-side switch Q1 and the low-side switch Q2 and an output terminal of the buck power converter. An output capacitor Co is connected between the output terminal of the buck power converter and ground. A load 120 is connected between the output terminal of the buck power converter and ground. The load 120 includes a plurality of light-emitting diodes connected in series. The PWM dimming signal is used to adjust the brightness of the plurality of light-emitting diodes. In response to the leading edge of the PWM dimming signal, the current flowing through the inductor L1 changes from a first load level (e.g., zero amperes) to a second load level (e.g., two amperes). In response to the falling edge of the PWM dimming signal, the current flowing through the inductor L1 changes from the second load level to the first load level.

[0065] At step 502 , in response to a leading edge of a load transient signal, an on-timer of a controller is disabled during a first on-pulse of a high-side switch of a buck power converter.

[0066] At step 504 , the current comparison stage of the controller is configured to cause the current flowing through the buck power converter to reach a final load level of the load transient within a first turn-on pulse of the high-side switch.

[0067] Return to reference Figure 1 The step-down power converter includes: a high-side switch and a low-side switch connected in series between an input voltage bus and ground; an inductor and a current sensing resistor connected in series between a common node of the high-side switch and the low-side switch and an output terminal of the step-down power converter; and an output capacitor connected between the output terminal of the step-down power converter and ground.

[0068] Return to reference Figure 2, the current comparison stage includes: a first amplifier having a non-inverting input terminal connected to a common node of an inductor and a current sensing resistor through a first resistor and an inverting input terminal connected to an output terminal of a buck power converter through a second resistor; an adjustable current source connected to the non-inverting input terminal of the first amplifier, and wherein a current flowing through the adjustable current source is proportional to a final load level of a load transient; a second amplifier having a non-inverting input terminal connected to a first output terminal of the first amplifier and an inverting input terminal connected to a second output terminal of the first amplifier; a third resistor connected between the first output terminal of the second amplifier and an inverting input terminal of a PWM comparator; and a fourth resistor connected between the second output terminal of the second amplifier and the non-inverting input terminal of the PWM comparator.

[0069] Return to reference Figure 2 , the offset current control stage includes: a third amplifier having a non-inverting input terminal connected to the inverting input terminal of the second amplifier and an inverting input terminal connected to the non-inverting input terminal of the second amplifier; a compensation capacitor connected between the output terminal of the third amplifier and ground, and wherein the third amplifier is configured to generate a compensation signal across the compensation capacitor; a fourth amplifier having a non-inverting input terminal configured to receive the compensation signal and an inverting input terminal configured to receive a predetermined reference; and a first auxiliary switch and a second auxiliary switch coupled between each output terminal of the fourth amplifier and each input terminal of the PWM comparator.

[0070] The method also includes: in stable operation, configuring the buck power converter to operate in a constant on-time mode, wherein an on-timer is configured to determine a turn-on time of a high-side switch of the buck power converter; and in response to a leading edge of a load transient signal, in a first turn-on pulse of the high-side switch of the buck power converter, disconnecting two output terminals of the offset current control stage from two input terminals of a PWM comparator by turning off a first auxiliary switch and a second auxiliary switch.

[0071] The method also includes, in response to a leading edge of a load transient signal, configuring a first auxiliary switch and a second auxiliary switch in a first turn-on pulse of a high-side switch of a buck power converter so that the first auxiliary switch is turned on and coupled between a first output terminal of a fourth amplifier and a non-inverting input terminal of a PWM comparator, and the second auxiliary switch is turned on and coupled between a second output terminal of the fourth amplifier and an inverting input terminal of the PWM comparator, wherein due to the turning on of the first auxiliary switch and the second auxiliary switch, two output terminals of the offset current control stage are connected to two input terminals of the PWM comparator.

[0072] The method also includes, in stable operation, configuring the first auxiliary switch and the second auxiliary switch so that the first auxiliary switch is turned on and coupled between the first output terminal of the fourth amplifier and the non-inverting input terminal of the PWM comparator, and the second auxiliary switch is turned on and coupled between the second output terminal of the fourth amplifier and the inverting input terminal of the PWM comparator; and in response to the leading edge of the load transient signal, in a first turn-on pulse of the high-side switch of the buck power converter, configuring the first auxiliary switch and the second auxiliary switch so that the first auxiliary switch is turned on and coupled between the first output terminal of the fourth amplifier and the inverting input terminal of the PWM comparator, and the second auxiliary switch is turned on and coupled between the second output terminal of the fourth amplifier and the non-inverting input terminal of the PWM comparator.

[0073] Figure 6 The present invention illustrates various embodiments of the present invention. Figure 1 FIG. 1 is a schematic diagram of a second implementation of a controller of a fast PWM dimming device. Figure 6 The second implementation of the controller 100 shown in FIG. 1 is similar to Figure 2 The first implementation of the controller 100 shown in FIG. 1 is shown in FIG. 2 , except that during a load transient from a first load level to a second load level and in a first turn-on pulse of the high-side switch Q1, the first auxiliary switch S1 is turned on and coupled between the first output terminal of the fourth amplifier 124 and the non-inverting input terminal of the PWM comparator 125, and the second auxiliary switch S2 is turned on and coupled between the second output terminal of the fourth amplifier 124 and the inverting input terminal of the PWM comparator 125. Since the first auxiliary switch S1 and the second auxiliary switch S2 are turned on, the two output terminals of the offset current control stage 150 are connected to the two input terminals of the PWM comparator 125.

[0074] Figure 7 FIG. 4 illustrates the voltage on the switching node and the current flowing through the inductor in a second implementation of the controller according to various embodiments of the present disclosure. Figure 7 The horizontal axis represents the time interval. Figure 7 There may be three rows in FIG. The first row represents the PWM dimming signal PWMDIM. The second row represents the voltage on the switching node SW. The third row represents the current flowing through the inductor L1.

[0075] At t1, the PWM dimming signal PWMDIM changes from a logic low state to a logic high state. In response to the leading edge of the PWM dimming signal, the current flowing through the inductor L1 changes from a first load level (e.g., zero amperes) to a second load level (e.g., two amperes). During this load transient, the voltage on the switching node SW remains high in a wide pulse from t1 to t2. The high voltage on the switching node SW indicates that the high-side switch Q1 remains on from t1 to t2.

[0076] From t1 to t2, return reference Figure 6 , the offset current control stage 150 is connected to the PWM comparator 125. The offset current control stage 150 adds an offset. The offset is equal to half of the ripple current of the buck power converter. Figure 6 As shown in the circuit connection, the offset reduces the desired current value from the average value of the second load level to the average value of the second load level minus the offset. Therefore, at t2, the current flowing through the inductor L1 reaches a valley value having an inductor current equal to the average value of the second load level.

[0077] From t2 to t6, Figure 7 The waveform shown in Figure 4 , except that the off time of the high-side switch Q1 is varied over multiple cycles until it settles into stable operation.

[0078] Figure 8 The present invention illustrates various embodiments of the present invention. Figure 1 FIG. 1 is a schematic diagram of a third implementation of a controller of a fast PWM dimming device. Figure 8 The third implementation of the controller 100 shown in FIG. 1 is similar to Figure 2 The first implementation of the controller 100 shown in FIG. 1 is shown in FIG. 1 , except that during a load transient from a first load level to a second load level and in a first turn-on pulse of the high-side switch Q1, the first auxiliary switch S1 is turned on and coupled between the first output terminal of the fourth amplifier 124 and the inverting input terminal of the PWM comparator 125, and the second auxiliary switch S2 is turned on and coupled between the second output terminal of the fourth amplifier 124 and the non-inverting input terminal of the PWM comparator 125.

[0079] Fig. 9 FIG. 4 illustrates the voltage on the switching node and the current flowing through the inductor in a third implementation of the controller according to various embodiments of the present disclosure. Fig. 9 The horizontal axis represents the time interval. Fig. 9 There may be three rows in FIG. The first row represents the PWM dimming signal PWMDIM. The second row represents the voltage on the switching node SW. The third row represents the current flowing through the inductor L1.

[0080] At t1, the PWM dimming signal PWMDIM changes from a logic low state to a logic high state. In response to the leading edge of the PWM dimming signal, the current flowing through the inductor L1 changes from a first load level (e.g., zero amperes) to a second load level (e.g., two amperes). During this load transient, the voltage on the switching node SW remains high in a wide pulse from t1 to t2. The high voltage on the switching node SW indicates that the high-side switch Q1 remains on from t1 to t2.

[0081] From t1 to t2, return reference Figure 8, the offset current control stage 150 is connected to the PWM comparator 125. The offset current control stage 150 adds an offset. The offset is equal to half of the ripple current of the buck power converter. Figure 8 As shown in the circuit connection, the offset increases the desired current value from the average value of the second load level to the average value of the second load level plus the offset. Therefore, at t2, the current flowing through the inductor L1 reaches a peak value of the inductor current having an average value equal to the second load level.

[0082] From t2 to t6, Fig. 9 The waveform shown in Figure 4 The waveforms shown in are not discussed in detail here.

[0083] Although the embodiments of the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.

[0084] In addition, the scope of the present application is not intended to be limited to the specific embodiments of the processes, machines, manufactures, material compositions, devices, methods, and steps described in the specification. As will be readily understood by those of ordinary skill in the art from the disclosure of the present disclosure, according to the present disclosure, currently existing or later developed processes, machines, manufactures, material compositions, devices, methods, or steps that perform substantially the same functions as the corresponding embodiments described herein or achieve substantially the same results may be utilized. Therefore, the appended claims are intended to include such processes, machines, manufactures, material compositions, devices, methods, or steps within their scope.

Claims

1. A device comprising: an on-timer configured to determine an on-time of a high-side switch of a buck power converter; an offset current control stage configured to convert a voltage difference between the compensation signal and a predetermined reference into a current difference; a current comparison stage configured to amplify the sensed current signal; as well as a PWM comparator having input terminals coupled to two output terminals of the current comparison stage and two output terminals of the offset current control stage, wherein during a load transient from a first load level to a second load level and in a first turn-on pulse of the high-side switch, the on-timer is disabled so that the current flowing through the buck power converter reaches the second load level within the first turn-on pulse of the high-side switch.

2. The device according to claim 1, wherein: During steady operation, the buck power converter is controlled with a constant on-time control scheme.

3. The device according to claim 1, wherein: The first turn-on pulse of the high-side switch is counted from a start of the load transient, and wherein the load transient occurs in response to a PWM dimming signal.

4. The device according to claim 1, wherein: During the load transient from the first load level to the second load level and in the first turn-on pulse of the high-side switch, the two outputs of the offset current control stage are disconnected from the two input terminals of the PWM comparator so that the current flowing through the buck power converter reaches the second load level within the first turn-on pulse of the high-side switch.

5. The device according to claim 1, wherein: The step-down power converter comprises: a high-side switch and a low-side switch connected in series between an input voltage bus and ground; an inductor and a current sensing resistor, wherein the inductor and the current sensing resistor are connected in series between a common node of the high-side switch and the low-side switch and an output terminal of the buck power converter; and An output capacitor is connected between the output terminal of the step-down power converter and ground.

6. The device according to claim 5, wherein: The current comparison stage comprises: a first amplifier having a non-inverting input terminal connected to a common node of the inductor and the current sensing resistor through a first resistor, and an inverting input terminal connected to the output terminal of the buck power converter through a second resistor; an adjustable current source connected to the non-inverting input terminal of the first amplifier; a second amplifier having a non-inverting input terminal connected to the first output terminal of the first amplifier and an inverting input terminal connected to the second output terminal of the first amplifier; a third resistor connected between the first output terminal of the second amplifier and the inverting input terminal of the PWM comparator; and A fourth resistor is connected between the second output terminal of the second amplifier and the non-inverting input terminal of the PWM comparator.

7. The device according to claim 6, wherein: A current flowing through the adjustable current source is proportional to the second load level.

8. The device according to claim 6, wherein: The offset current control stage comprises: a third amplifier having a non-inverting input terminal connected to the inverting input terminal of the second amplifier and an inverting input terminal connected to the non-inverting input terminal of the second amplifier; a compensation capacitor connected between an output terminal of the third amplifier and ground, and wherein the third amplifier is configured to generate the compensation signal across the compensation capacitor; a fourth amplifier having a non-inverting input terminal configured to receive the compensation signal and an inverting input terminal configured to receive a predetermined reference; and A first auxiliary switch and a second auxiliary switch are coupled between an output terminal of the fourth amplifier and the input terminal of the PWM comparator.

9. The device according to claim 8, wherein: During steady operation, the first auxiliary switch and the second auxiliary switch are both configured to be turned on so that the offset current control stage is connected to the PWM comparator; as well as During the load transient from the first load level to the second load level and in the first turn-on pulse of the high-side switch, both the first auxiliary switch and the second auxiliary switch are configured to be turned off such that the offset current control stage is disconnected from the PWM comparator.

10. The apparatus according to claim 1, further comprising: An enabling circuit configured to receive the PWM dimming signal and generate a control signal to: enabling the on-timer during stable operation and configuring the offset current control stage to be connected to the PWM comparator; as well as The on-timer is disabled and the offset current control stage is configured to be disconnected from the PWM comparator during the load transient from the first load level to the second load level and in the first on-pulse of the high-side switch.

11. The apparatus of claim 10, wherein the enabling circuit comprises a first AND gate, a second AND gate, a first inverter, a second inverter, a latch, and a NOR gate, and wherein: The input terminal of the first inverter is configured to receive the output signal of the PWM comparator; The first input terminal of the first AND gate is configured to receive a gate drive enable signal; The second input terminal of the first AND gate is configured to receive the output signal of the first inverter; The first input terminal of the second AND gate is configured to receive a PWM dimming signal; The second input terminal of the second AND gate is configured to receive a power converter enable signal; The data input terminal of the latch is connected to a bias voltage bus; The clock input terminal of the latch is connected to the output terminal of the first AND gate; The clear and reset inputs of the latch are connected to the output of the second AND gate; The first input terminal of the NOR gate is connected to the output terminal of the latch; The second input terminal of the NOR gate is configured to receive a signal configured to determine a pulse width of the first on pulse of the high side switch; as well as The input terminal of the second inverter is connected to the output terminal of the NOR gate, and wherein: the enabling circuit being configured to generate an enabling signal in response to a falling edge of the output signal of the PWM comparator, and wherein in response to the enabling signal, the two output terminals of the offset current control stage are connected to the two input terminals of the PWM comparator; and The enabling circuit is configured to generate a disable signal in response to the PWM dimming signal, and wherein in response to the disable signal, the two output terminals of the offset current control stage are disconnected from the two input terminals of the PWM comparator.

12. A method comprising: In response to a leading edge of a load transient signal, disabling an on-timer of a controller during a first turn-on pulse of a high-side switch of a buck power converter; as well as The current comparison stage of the controller is configured so that the current flowing through the buck power converter reaches a final load level of a load transient within the first turn-on pulse of the high-side switch.

13. The method according to claim 12, wherein: The step-down power converter comprises: a high-side switch and a low-side switch connected in series between an input voltage bus and ground; an inductor and a current sensing resistor, the inductor and the current sensing resistor being connected in series between a common node of the high-side switch and the low-side switch and an output terminal of the buck power converter; and An output capacitor is connected between the output terminal of the step-down power converter and ground.

14. The method according to claim 13, wherein: The current comparison stage comprises: a first amplifier having a non-inverting input terminal connected to a common node of the inductor and the current sensing resistor through a first resistor, and an inverting input terminal connected to the output terminal of the buck power converter through a second resistor; an adjustable current source connected to the non-inverting input of the first amplifier and wherein a current flowing through the adjustable current source is proportional to the final load level of the load transient; a second amplifier having a non-inverting input terminal connected to the first output terminal of the first amplifier and an inverting input terminal connected to the second output terminal of the first amplifier; a third resistor connected between the first output terminal of the second amplifier and the inverting input terminal of the PWM comparator; and A fourth resistor is connected between the second output terminal of the second amplifier and the non-inverting input terminal of the PWM comparator.

15. The method according to claim 14, wherein: The controller further comprises an offset current control stage, the offset current control stage comprising: a third amplifier having a non-inverting input terminal connected to the inverting input terminal of the second amplifier and an inverting input terminal connected to the non-inverting input terminal of the second amplifier; a compensation capacitor connected between an output terminal of the third amplifier and ground, and wherein the third amplifier is configured to generate a compensation signal across the compensation capacitor; a fourth amplifier having a non-inverting input terminal configured to receive the compensation signal and an inverting input terminal configured to receive a predetermined reference; and A first auxiliary switch and a second auxiliary switch are coupled between an output terminal of the fourth amplifier and an input terminal of the PWM comparator.

16. The method according to claim 15, further comprising: In stable operation, configuring the buck power converter to operate in a constant on-time mode, wherein an on-timer is configured to determine an on-time of the high-side switch of the buck power converter; and In response to the leading edge of the load transient signal, in the first turn-on pulse of the high-side switch of the buck power converter, the two output terminals of the offset current control stage are disconnected from the two input terminals of the PWM comparator by turning off the first auxiliary switch and the second auxiliary switch.

17. The method according to claim 15, further comprising: In response to the leading edge of the load transient signal, in the first turn-on pulse of the high-side switch of the buck power converter, the first auxiliary switch and the second auxiliary switch are configured so that the first auxiliary switch is turned on and coupled between the first output terminal of the fourth amplifier and the non-inverting input terminal of the PWM comparator, and the second auxiliary switch is turned on and coupled between the second output terminal of the fourth amplifier and the inverting input terminal of the PWM comparator, and wherein due to the turning on of the first auxiliary switch and the second auxiliary switch, the two output terminals of the offset current control stage are connected to the two input terminals of the PWM comparator.

18. The method according to claim 15, further comprising: In stable operation, configuring the first auxiliary switch and the second auxiliary switch such that the first auxiliary switch is turned on and coupled between the first output terminal of the fourth amplifier and the non-inverting input terminal of the PWM comparator, and such that the second auxiliary switch is turned on and coupled between the second output terminal of the fourth amplifier and the inverting input terminal of the PWM comparator; and In response to the leading edge of the load transient signal, in the first turn-on pulse of the high-side switch of the buck power converter, the first auxiliary switch and the second auxiliary switch are configured such that the first auxiliary switch is turned on and coupled between the first output terminal of the fourth amplifier and the inverting input terminal of the PWM comparator, and the second auxiliary switch is turned on and coupled between the second output terminal of the fourth amplifier and the non-inverting input terminal of the PWM comparator.

19. A system comprising: a high-side switch and a low-side switch, wherein the high-side switch and the low-side switch are connected in series between an input voltage bus and ground; an inductor and a current sensing resistor, wherein the inductor and the current sensing resistor are connected in series between a common node of the high-side switch and the low-side switch and an output terminal of the buck power converter; an output capacitor connected between the output terminal of the step-down power converter and ground; as well as A controller, the controller comprising: an on-timer configured to determine an on-time of the high-side switch of the buck power converter; an offset current control stage configured to convert a voltage difference between the compensation signal and a predetermined reference into a current difference; a current comparison stage configured to amplify the sensed current signal; and a PWM comparator having input terminals coupled to two output terminals of the current comparison stage and two output terminals of the offset current control stage, wherein during a load transient from a first load level to a second load level and in a first turn-on pulse of the high-side switch, the on-timer is disabled so that the current flowing through the buck power converter reaches the second load level within the first turn-on pulse of the high-side switch.

20. The system of claim 19, wherein: The current comparison stage comprises: a first amplifier having a non-inverting input terminal connected to a common node of the inductor and the current sensing resistor through a first resistor, and an inverting input terminal connected to the output terminal of the buck power converter through a second resistor; an adjustable current source connected to the non-inverting input of the first amplifier and wherein a current flowing through the adjustable current source is proportional to the second load level; a second amplifier having a non-inverting input terminal connected to the first output terminal of the first amplifier and an inverting input terminal connected to the second output terminal of the first amplifier; a third resistor connected between the first output terminal of the second amplifier and the inverting input terminal of the PWM comparator; and a fourth resistor connected between the second output terminal of the second amplifier and the non-inverting input terminal of the PWM comparator; and The offset current control stage comprises: a third amplifier having a non-inverting input terminal connected to the inverting input terminal of the second amplifier and an inverting input terminal connected to the non-inverting input terminal of the second amplifier; a compensation capacitor connected between an output terminal of the third amplifier and ground, and wherein the third amplifier is configured to generate the compensation signal across the compensation capacitor; a fourth amplifier having a non-inverting input terminal configured to receive the compensation signal and an inverting input terminal configured to receive a predetermined reference; and A first auxiliary switch and a second auxiliary switch are coupled between an output terminal of the fourth amplifier and an input terminal of the PWM comparator.

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