Preparation method of semiconductor structure

Abstract

The embodiment of the invention relates to a preparation method of a semiconductor structure, and the method comprises the steps: providing a substrate, forming a laminated structure on the substrate, and enabling the laminated structure to comprise sacrificial layers and supporting layers, a through hole is formed in the laminated structure, the through hole penetrates through the laminated structure, the sacrificial layer comprises a protruding part, and the orthographic projection of the protruding part on the substrate partially coincides with the orthographic projection of an opening of the through hole on the substrate; injecting a doping element into the protruding part, wherein the doping element is used for changing the etching rate of the protruding part; and etching to remove the doped protruding part. After the doping element capable of changing the etching rate of the protruding part is injected into the protruding part, the doped protruding part can be removed, the difference value between the feature size of the top of the through hole and the feature size of the bottom of the through hole is reduced, the through hole with the vertical side wall is obtained, the bottom of the through hole can expose the bottom structure below the through hole, and the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular, to a method for preparing a semiconductor structure. Background Art

[0002] Dynamic Random Access Memory (DRAM) includes multiple memory cells, each of which includes a transistor and a capacitor. As the size of dynamic random access memory devices gradually decreases, the aspect ratio of the through-holes formed in the process of preparing the dynamic random access memory devices gradually increases. When a through-hole with a large aspect ratio is etched on a substrate, the characteristic size of the top of the through-hole is larger than the characteristic size of the bottom, and the depth of the capacitor hole in some areas will be less than the expected depth, and the bottom of the through-hole cannot expose the bottom structure below the through-hole. Summary of the invention

[0003] The embodiment of the present application provides a method for preparing a semiconductor structure, which can optimize the morphology of a through hole.

[0004] The present disclosure provides a method for preparing a semiconductor structure, comprising:

[0005] Providing a substrate, on which a stacked structure is formed, the stacked structure comprising sacrificial layers and supporting layers alternately stacked;

[0006] A through hole is formed in the laminated structure, wherein the through hole penetrates the laminated structure, the sacrificial layer comprises a protrusion, and an orthographic projection of the protrusion on the substrate partially overlaps with an orthographic projection of an opening of the through hole on the substrate;

[0007] Injecting a doping element into the protrusion, wherein the doping element is used to change the etching rate of the protrusion;

[0008] The doped protrusions are removed by etching.

[0009] In one of the embodiments, an extending direction of the protrusion is perpendicular to an extending direction of the through hole.

[0010] In one embodiment, the doping element includes a first doping element and a second doping element, and injecting the doping element into the protrusion includes:

[0011] Injecting a first doping element into the protrusion using a first injection process;

[0012] A second doping element is implanted into the protrusion by a second implantation process.

[0013] In one embodiment, the first doping element includes boron, the second doping element includes phosphorus, and the constituent material of the sacrificial layer includes silicon oxide.

[0014] In one embodiment, the injection directions of the first injection process and the second injection process are parallel to the extension direction of the through hole and perpendicular to the extension direction of the protrusion.

[0015] In one embodiment, the doping concentration of the first doping element is greater than the doping concentration of the second doping element.

[0016] In one embodiment, etching and removing the doped protrusions comprises:

[0017] The doped protrusions are removed by wet etching.

[0018] In one embodiment, the wet etching reagent includes a mixed etching solution of dilute sulfuric acid and hydrogen peroxide.

[0019] In one embodiment, before the doping element is injected into the protrusion, the method further comprises:

[0020] A cleaning process is used to remove the residue on the inner wall of the through hole.

[0021] In one embodiment, after etching away the doped protrusion, the method further comprises:

[0022] A capacitor structure is formed in the through hole.

[0023] The preparation method of the above-mentioned semiconductor structure forms a through hole that penetrates the stacked structure, and the orthographic projection of the protrusion on the substrate partially coincides with the orthographic projection of the opening of the through hole on the substrate. After injecting an impurity element that can change the etching rate of the protrusion into the protrusion, the doped protrusion can be removed, reducing the difference between the characteristic size of the top of the through hole and the characteristic size of other positions in the through hole, thereby obtaining a through hole with vertical side walls, and the bottom of the through hole can expose the bottom structure below the through hole, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 is a schematic flow chart of a method for preparing a semiconductor structure in one embodiment;

[0026] Figure 2 is a schematic cross-sectional view of a semiconductor structure after a through hole penetrating the stacked structure is formed in one embodiment;

[0027] Figure 3 for Figure 2 A cross-sectional schematic diagram of a semiconductor structure after implantation of doping elements in a corresponding embodiment;

[0028] Figure 4 for Figure 2 A cross-sectional schematic diagram of a semiconductor structure after the protrusion is removed in a corresponding embodiment;

[0029] Figure 5 is a schematic flow chart of a method for preparing a semiconductor structure in yet another embodiment;

[0030] Figure 6 is a schematic diagram of a process of injecting doping elements into a protrusion in one embodiment;

[0031] Figure 7 FIG. 4 is a schematic flow chart of a method for preparing a semiconductor structure in yet another embodiment.

[0032] Description of reference numerals:

[0033] 102, substrate; 104, stacked structure; 106, through hole; 107, first mask layer; 202, sacrificial layer; 204, supporting layer; 302, protrusion; 304, sacrificial structure. DETAILED DESCRIPTION

[0034] In order to facilitate understanding of the embodiments of the present application, the embodiments of the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the embodiments of the present application are given in the drawings. However, the embodiments of the present application can be implemented in many different forms and are not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the embodiments of the present application more thorough and comprehensive.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the technical field of the embodiments of the present application. The terms used herein in the specification of the embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to limit the embodiments of the present application. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0036] In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "vertical", "horizontal", "inside", "outside", etc. indicate orientations or positional relationships based on the methods or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the embodiments of the present application.

[0037] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first doping element may be referred to as a second doping element, and similarly, a second doping element may be referred to as a first doping element. Both the first doping element and the second doping element are doping elements, but they are not the same doping element.

[0038] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the description of the present application, the meaning of "several" is at least one, such as one, two, etc., unless otherwise clearly and specifically defined.

[0039] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0040] Figure 1 FIG. 1 is a schematic diagram of a process for preparing a semiconductor structure in an embodiment. Figure 1 As shown, in this embodiment, a method for preparing a semiconductor structure is provided, comprising:

[0041] S102, providing a substrate, on which a laminated structure is formed.

[0042] Figure 2 FIG. 1 is a schematic cross-sectional view of a semiconductor structure after a through hole is formed in one embodiment. Figure 2As shown, a substrate 102 is provided, and a stacked structure 104 is formed on the substrate 102, wherein the stacked structure includes sacrificial layers 202 and supporting layers 204 that are alternately stacked, wherein the sacrificial layers 202 and supporting layers 204 are alternately stacked in a direction from the surface of the substrate 102 that forms the stacked structure 104 to a direction away from the substrate 102, Figure 2 The constituent material of the substrate 102 includes, but is not limited to, undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). As an example, in this embodiment, the constituent material of the substrate 102 is selected from single crystal silicon. Among them, the bottom of the stacked structure 104 close to the substrate 102 can be either the sacrificial layer 202 or the supporting layer 204, and the top of the stacked structure 104 away from the substrate 102 can also be either the sacrificial layer 202 or the supporting layer 204. The present disclosure does not limit the top layer and the bottom layer of the stacked structure 104. At the same time, the present disclosure does not limit the number of sacrificial layers 202 and the thickness of each sacrificial layer 202, the number of supporting layers 204 and the thickness of each supporting layer 204 in the stacked structure 104. In the figure, the top layer of the stacked structure 104 is the supporting layer 204 and the bottom layer of the stacked structure 104 is the sacrificial layer 202, and the number of layers of the sacrificial layer 202 and the supporting layer 204 are both 2 for exemplary description.

[0043] S104, forming a through hole in the stacked structure, the through hole penetrates the stacked structure, the sacrificial layer includes a protrusion, and the orthographic projection of the protrusion on the substrate partially overlaps with the orthographic projection of the opening of the through hole on the substrate.

[0044] like Figure 2As shown, a through hole 106 is formed in the stacked structure 104 through a photolithography and etching process, and the through hole 106 penetrates the stacked structure 104. The sacrificial layer 202 includes a protrusion 302, and the orthographic projection of the protrusion 302 on the substrate 102 partially overlaps with the orthographic projection of the opening of the through hole 106 on the substrate 102; the bottom of the through hole 106 exposes the surface of the substrate 102, and the orthographic projection of the protrusion 302 on the sacrificial layer 202 overlaps with the part of the sacrificial layer 202. It can be understood that the opening size D1 of the through hole 106 is larger than the middle size D2 of the through hole 106 at the location of the sacrificial layer with the protrusion 302, and the through hole 1 The opening size D1 of the through hole 106 is also larger than the bottom size of the through hole 106. The portion of the opening of the through hole 106 where the orthographic projection of the sacrificial layer 202 does not overlap with the sacrificial layer 202 is the sacrificial structure 304. The protrusion 302 corresponds to the sacrificial layer 202. When the stacked structure 104 includes multiple sacrificial layers 304, the size of the protrusion 302 in the sacrificial layer 304 close to the opening position of the through hole 106 is smaller than the size of the protrusion 302 in the sacrificial layer 304 away from the opening position of the through hole 106. The number of the protrusions 302 is less than or equal to the number of layers of the sacrificial layer 202, that is, there is no protrusion 302 in a sacrificial layer 304 with more than or equal to one layer. Figure 2 For example, a protrusion 302 is provided in each sacrificial layer 202 in the stacked structure 104 .

[0045] S106, injecting doping elements into the protrusions, where the doping elements are used to change the etching rate of the protrusions.

[0046] Figure 3 for Figure 2 A cross-sectional schematic diagram of a semiconductor structure after implantation of doping elements in a corresponding embodiment is shown in FIG. Figure 3 As shown, the doping element 108 is injected into the protrusion 302, and the doped protrusion 302 is as shown in FIG. Figure 3 As shown, the doping element 108 is used to change the etching rate V of the protrusion 302 in the extension direction X of the through hole 106. By injecting the doping element 108, each part of the protrusion 302 in the extension direction X of the through hole 106 has an expected etching rate V, so that the protrusion 302 can be completely removed later to obtain the through hole 106 with vertical side walls.

[0047] S108, etching to remove the doped protrusions.

[0048] Figure 4 for Figure 2 A cross-sectional schematic diagram of a semiconductor structure after removing the protruding portion in a corresponding embodiment is shown in FIG. Figure 4As shown, the doped protrusion 302 is etched away by a suitable etching method and etching agent, such as a wet etching process, that is, the uneven protrusion of the side wall of the through hole 106 caused by the protrusion 302 is removed, so that the opening size D1 of the through hole 106 is equal to the middle size D2 of the through hole 106 where the sacrificial layer 202 with the protrusion 302 is located, and the opening size D1 of the through hole 106 is equal to the bottom size of the through hole 106, thereby obtaining a through hole 106 with vertical side walls.

[0049] In the method for preparing the semiconductor structure, a through hole 106 penetrating the stacked structure 104 is formed, and the orthographic projection of the protrusion 302 in the sacrificial layer 202 on the substrate 102 partially overlaps with the orthographic projection of the opening of the through hole 106 on the substrate 102. After the doping element that can change the etching rate of the protrusion 302 is injected into the protrusion 302, the doped protrusion 302 can be completely removed subsequently, and the difference between the characteristic size of the top of the through hole 106 and the characteristic size of other positions in the through hole 106 is reduced, so as to obtain a through hole 106 with vertical sidewalls, and the bottom of the through hole 106 can completely expose the bottom structure below the through hole 106, thereby improving the performance of the semiconductor structure.

[0050] In one embodiment, the through hole 106 includes a capacitor hole, and the step of forming the through hole 106 in the stacked structure 104 includes: forming a patterned mask layer on the stacked structure 104, the patterned mask layer defines the shape and position of the through hole 106, and patterning the stacked structure 104 using the patterned mask layer as a mask, removing the stacked structure 104 not covered by the patterned mask layer, and forming the through hole 106 in the stacked structure 104. Exemplarily, the constituent material of the patterned mask layer includes but is not limited to photoresist.

[0051] like Figure 2 As shown, before forming a patterned mask layer on the stacked structure 104, the method further includes: forming a mask material layer on the stacked structure 104, the patterned mask layer being located on the mask material layer, patterning the mask material layer using the patterned mask layer as a mask to obtain a first mask layer 107, and then patterning the stacked structure 104 using the first mask layer 107 as a mask to form a through hole 106 located in the stacked structure 104. Exemplarily, the constituent material of the first mask layer 107 includes, but is not limited to, an anti-reflection layer, silicon oxynitride, or polysilicon.

[0052] In one embodiment, after obtaining the first mask layer 107, the method further includes: removing the patterned mask layer.

[0053] In one embodiment, after etching away the doped protrusions, the process further includes: removing the first mask layer.

[0054] like Figure 2As shown, in one of the embodiments, the extension direction of the protrusion 302 is perpendicular to the extension direction of the through hole 106, and the extension direction of the protrusion 302 is the direction of the protrusion 302 toward the central axis of the through hole 106, that is, the extension direction of the protrusion 302 is the aperture direction of the through hole 106. The extension direction of the protrusion 302 in the figure is indicated by Y. It can be clearly seen that the extension direction of the protrusion 302 can be any direction on the horizontal plane where the Y direction is located and is parallel to the surface of the substrate 102. The extension direction of the through hole 106 is the direction from the bottom of the through hole 106 toward the opening of the through hole 106, that is, the direction perpendicular to the substrate 102, such as the X direction in the figure.

[0055] Figure 5 FIG. 1 is a schematic flow chart of a method for preparing a semiconductor structure in another embodiment. Figure 2 , Figure 5 As shown, the doping element 108 is injected into the protrusion 302 by an injection process, after the through hole 106 is formed in the stacked structure 104 and before the doping element 108 is injected into the protrusion 302, the process further includes:

[0056] S202, detecting the through hole and obtaining initial morphological parameters of the through hole.

[0057] S204, obtaining process parameters of the implantation process according to the initial morphology parameters.

[0058] The initial morphological parameters of the through hole 106 are obtained by detecting the characteristic size of the through hole 106. The initial morphological parameters include a first aperture and a second aperture. The first aperture is used to characterize the initial top size of the through hole 106, that is, the opening size D1 of the through hole 106. The second aperture is used to characterize the middle aperture D0 of the through hole 106 corresponding to any point O in the area where each sacrificial layer 202 is located in the extension direction X of the through hole 106. The morphology of the location of the sacrificial layer 202 and the difference between the morphology of the location of the sacrificial layer 202 and the opening position of the through hole 106, that is, the morphology of the protrusion 302 can be known through the first aperture and the second aperture. According to the initial morphological parameters (the morphology of the protrusion 302), the expected value of the etching rate corresponding to each position of the protrusion 302 in the extension direction X of the through hole 106 can be obtained, and then the process parameters of the implantation process, such as the type of implanted ions, the number of implantations, the implantation energy, the implantation dose, the implantation angle, etc. can be obtained.

[0059] In one embodiment, before the doping element 108 is injected into the protrusion 302, the process further includes: using a cleaning process to remove the residue on the inner wall of the through hole 106. It is understandable that, before the through hole 106 is detected and the initial morphology parameters of the through hole 106 are obtained in step S202, the cleaning process is used to remove the residue on the inner wall of the through hole 106. At this time, the obtained initial morphology parameters are more accurate.

[0060] Exemplarily, the cleaning agent of the cleaning process includes DSP (Dilute Sulfuric Peroxide Mixture), which is a mixture of sulfuric acid, hydrogen peroxide, hydrofluoric acid and deionized water. Among them, sulfuric acid and hydrogen peroxide can remove the residual metal compounds and the polymers generated by the reaction during the initial formation of the through hole 106. Exemplarily, the metal compounds remaining on the side wall of the through hole 106 include but are not limited to Al 2 O 3 The polymer includes a soluble polymer that is soluble in hydrogen peroxide and / or sulfuric acid. Hydrofluoric acid can remove oxides. Exemplary oxides include but are not limited to silicon dioxide.

[0061] Figure 6 FIG. 1 is a schematic diagram of a process of injecting doping elements into a protrusion in an embodiment. Figure 3 , Figure 6 As shown, in one embodiment, the doping element 108 includes a first doping element and a second doping element, and injecting the doping element 108 into the protrusion 302 includes:

[0062] S302, using a first implantation process to implant a first doping element into the protrusion.

[0063] S304, injecting a second doping element into the protruding portion using a second injection process.

[0064] The method of injecting the doping element 108 into the protrusion 302 is to ionize the doping element 108 into ions and focus it into an ion beam. The ion beam obtains extremely high kinetic energy after being accelerated in the electric field, and then is injected into a preset position in the recessed portion 302. The injection depth, injection dose, and injection number of the first doping element and the second doping element are related to the length L of the protrusion 302 in the aperture direction (Y direction) of the through hole 106 and the thickness T of the protrusion 302 in the extension direction X of the through hole 106. The etching rate that needs to be adjusted at the thickness T1 position in the protrusion 302 is set by the length L1 and the thickness T1, and then the parameters of the first injection process and the second injection process, the order of the first injection process and the second injection process, the number of the first injection process and the second injection process, the types of the first doping element and the second doping element, etc. are set to adjust the etching rate of the protrusion 302 after the overall doping, so as to achieve the purpose of completely removing the protrusion 302.

[0065] In one embodiment, the injection directions of the first injection process and the second injection process are parallel to the extension direction of the through hole 106 and perpendicular to the extension direction (Y direction) of the protrusion 302, that is, the injection angles of the first injection process and the second injection process are 0, and the injection angle is the angle between the injection direction of the doping element and the X direction perpendicular to the substrate 102.

[0066] In one embodiment, the first doping element and the second doping element are both ions that increase the etching rate of the protrusion 302. The first doping element and the second doping element may be the same ions that increase the etching rate of the protrusion 302, or the first doping element and the second doping element may be different ions that increase the etching rate of the protrusion 302. In another embodiment, the first doping element and the second doping element are both ions that reduce the etching rate of the protrusion 302. The first doping element and the second doping element may be the same ions that reduce the etching rate of the protrusion 302, or the first doping element and the second doping element may be different ions that reduce the etching rate of the protrusion 302.

[0067] In one embodiment, the first doping element is an ion that increases the etching rate of the protrusion 302, and the second doping element is an ion that reduces the etching rate of the protrusion 302. Exemplarily, the first doping element that increases the etching rate of the protrusion 302 includes an N-type element, such as phosphorus, arsenic, antimony, etc., and the second doping element that reduces the etching rate of the protrusion 302 includes a P-type element, such as boron, gallium, indium, etc. Optionally, the doping concentration of the first doping element is less than the doping concentration of the second doping element.

[0068] It is understandable that the implantation dose of the first doping element and the second doping element must be controlled within a reasonable range, otherwise the etching rate of the protrusion 302 will be excessively affected, causing the first doping element and / or the second doping element in the local area of ​​the protrusion 302 to diffuse laterally (in the aperture direction (Y direction) of the through hole 106) into the sacrificial structure 304 (non-processed area), resulting in the side wall of the through hole 106 becoming an uneven surface morphology during the subsequent etching process to remove the protrusion 302, which not only distorts the measurement value of the subsequent characteristic size of the through hole 106, but also affects the uniformity of the through hole structure subsequently formed in the through hole 106, for example, affecting the uniformity of the lower electrode of the capacitor structure formed on the inner wall of the through hole 106.

[0069] In one embodiment, the first doping element includes phosphorus, the second doping element includes boron, and the constituent material of the sacrificial layer 202 includes, but is not limited to, undoped silicon oxide, boron-doped silicon dioxide, phosphorus-doped silicon dioxide, or boron-phosphorus-doped silicon dioxide. The constituent material of the support layer 204 includes, but is not limited to, nitrides, such as silicon nitride, silicon oxynitride, and silicon carbide. Optionally, when the number of layers of the sacrificial layer 202 is greater than 1, the constituent material of each sacrificial layer 202 may be the same, the constituent material of each sacrificial layer 202 may be different, or the constituent material of each sacrificial layer 202 may be partially the same. Similarly, when the number of layers of the support layer 204 is greater than 1, the constituent material of each support layer 204 may be the same, the constituent material of each support layer 204 may be different, or the constituent material of each support layer 204 may be partially the same.

[0070] It is understandable that by increasing the doping concentration of boron and phosphorus in boron-phosphorus-doped silicon dioxide, the effect of reducing the annealing temperature of boron-phosphorus-doped silicon dioxide can be achieved. Phosphorus can capture mobile metal cations and reduce the reflow temperature of the film, and boron can reduce the reflow temperature of the film. However, after the weight ratio of boron in boron-phosphorus-doped silicon dioxide reaches a certain amount, as the boron increases, the water absorption of boron-phosphorus-doped silicon dioxide increases, and the impurity elements in boron-phosphorus-doped silicon dioxide will continue to precipitate, forming bubble defects, causing serious process problems and affecting the performance of semiconductor devices. Therefore, the total weight percentage of doping elements in the protrusion 302 is less than or equal to 10%. Exemplarily, when the protrusion 302 contains both the first doping element and the second doping element that reduce the etching rate of the protrusion 302, the sum of the weight percentage of the first doping element and the weight percentage of the second doping element in the protrusion is less than or equal to 5%; when the protrusion 302 contains both the first doping element and the second doping element that increase the etching rate of the protrusion 302, the sum of the weight percentage of the first doping element and the weight percentage of the second doping element in the protrusion 302 is less than or equal to 4.4%; when the protrusion 302 contains both the first doping element that increases the etching rate of the protrusion 302 and the second doping element that reduces the etching rate of the protrusion 302, the weight percentage of the first doping element in the protrusion 302 is less than or equal to 4.4%, and the sum of the weight percentage of the second doping element in the protrusion 302 is less than or equal to 5%. It can be understood that the doping element in the protrusion 302 can soften the protrusion 302 at the same time, so that the constituent material of the protrusion 302 flows, which is more conducive to the removal of the protrusion 302.

[0071] Table 1 is a relationship table of exemplary implantation energy (energy), implantation dose (DOSE), and ratio B / T (Bottom / Top) of the through hole top feature size to the bottom feature size. It can be seen from Table 1 that when the implantation energy of the first doping element is smaller than the implantation energy of the second doping element, and the implantation dose of the first doping element is smaller than the implantation dose of the second doping element, the removal effect of the protrusion 302 is better.

[0072] Table 1 Relationship between doping process parameters and feature sizes

[0073]

[0074] In one embodiment, etching away the doped protrusion 302 includes: removing the doped protrusion 302 by wet etching.

[0075] In one embodiment, the wet etching reagent includes a mixed etching solution of dilute sulfuric acid and hydrogen peroxide. The purpose of completely removing the protrusion 302 can be achieved by controlling the ratio of each chemical in the wet etching reagent and the wet etching time.

[0076] Figure 7 FIG. 1 is a schematic flow chart of a method for preparing a semiconductor structure in another embodiment. Figure 7 As shown, in one embodiment, after etching away the doped protrusion 302, the method further includes:

[0077] S402, detecting the through hole and obtaining actual morphological parameters of the through hole.

[0078] S404, adjusting the through hole preparation parameters corresponding to the next product wafer according to the actual morphology parameters.

[0079] After the doped protrusion 302 is etched away, the actual morphological parameters of the through hole 106 are obtained by detecting the characteristic size of the through hole 106. The actual morphological parameters include a third aperture and a fourth aperture. The third aperture is used to characterize the actual top size of the through hole 106, that is, the actual opening size D11 of the through hole 106 after the protrusion 302 is etched away. The fourth aperture is used to characterize the actual middle aperture D01 of the through hole 106 corresponding to any point O in the region where the sacrificial layer 202 is located in the extension direction X of the through hole 106 after the protrusion 302 is removed. The actual morphology of the through hole 106 can be known through the third aperture and the fourth aperture, and then the through hole preparation parameters corresponding to the next product wafer are adjusted according to the actual morphological parameters of the through hole 106. The through hole preparation parameters are process parameters for forming the through hole 106 in the stacked structure 104, so as to achieve the purpose of adjusting the difference between the third aperture and the fourth aperture, so that the difference between the top size and the bottom size of the through hole 106 is smaller, and the side wall of the through hole 106 is closer to vertical.

[0080] In one embodiment, the ratio of the actual bottom size of the through hole 106 to the actual opening size D11 of the through hole 106 is less than or equal to 1 and greater than or equal to 0.95, such as 0.96, 0.97, 0.98, 0.99, etc.

[0081] In one embodiment, the semiconductor structure includes a memory device, the through hole 106 includes a capacitor hole, and after etching to remove the doped protrusion 302, it also includes: a step of forming a capacitor structure in the through hole 106. Optionally, a shallow trench isolation structure is formed in the substrate 102, and the shallow trench isolation structure isolates a number of active areas arranged at intervals in the substrate 102, and each active area is formed with at least one transistor and at least one word line structure running through the active area, and a bit line structure is formed on the surface of the active area. Among them, the gate of each transistor is electrically connected to the word line structure, the drain of each transistor is electrically connected to the bit line structure, the stacked structure 104 is located on the active area, the through hole 106 is located above the source of the transistor, and the source of each transistor is electrically connected to the capacitor structure in the corresponding through hole 106.

[0082] Exemplarily, a capacitor contact structure is formed in the through hole 106, and the source of the transistor is electrically connected to an electrode of the capacitor structure through the capacitor contact structure. Optionally, the constituent materials of the capacitor contact structure include but are not limited to polysilicon, metal, noble metal, metal nitride, conductive metal oxide, conductive noble metal oxide, metal carbide, metal silicide or a combination thereof. For example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), aluminum (Al) tungsten nitride (WN), tungsten silicon (WSi) ruthenium (Ru), ruthenium oxide (RuO2), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, tungsten nitride / tungsten (WN / W) stack.

[0083] Exemplarily, the step of forming a capacitor structure in the through hole 106 includes: forming a first electrode layer on the inner wall of the through hole 106, the first electrode layer is electrically connected to the source of the transistor, and the inner wall of the through hole 106 includes the bottom of the through hole 106 and the side wall of the through hole 106; forming a capacitor dielectric layer on the surface of the first electrode layer; forming a second electrode layer on the surface of the capacitor dielectric layer, wherein the first electrode layer, the capacitor dielectric layer and the second electrode layer constitute a capacitor structure. Optionally, a capacitor contact structure is formed in the through hole 106, the first electrode layer covers the side wall of the through hole 106 and the surface of the capacitor contact structure away from the substrate, the first electrode layer is in contact with the capacitor contact structure, and is electrically connected to the first electrode layer through the capacitor contact structure. In some embodiments, before forming the capacitor dielectric layer on the surface of the first electrode layer, the step of removing the sacrificial layer 202 is also included; forming the capacitor dielectric layer on the surface of the first electrode layer includes: forming the capacitor dielectric layer on the inner and outer surfaces of the first electrode layer. In some embodiments, the constituent material of the first electrode layer includes, but is not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. For example, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes tungsten silicon (WSi). The constituent material of the first electrode layer may be the same as or different from the constituent material of the capacitor contact structure.

[0084] In some embodiments, the constituent material of the second electrode layer includes, but is not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. For example, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes tungsten silicon (WSi). The constituent material of the second electrode layer may be the same as or different from the constituent material of the first electrode layer and the constituent material of the capacitor contact structure.

[0085] It should be understood that although Figure 1 , Figure 5 , Figure 6 and Figure 7 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 , Figure 5 , Figure 6 and Figure 7At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0086] The embodiment of the present disclosure also provides a semiconductor structure, which is manufactured using any of the above-mentioned methods for manufacturing a semiconductor structure.

[0087] In one embodiment, a semiconductor structure includes a memory device.

[0088] The disclosed embodiments also provide an electronic device, including any of the above semiconductor structures. The electronic device may include a smart phone, a computer, a tablet computer, an artificial intelligence, a wearable device, or a smart mobile terminal. The embodiments of the present application do not impose any special restrictions on the specific form of the above electronic device.

[0089] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0090] The above embodiments only express several implementation methods of the embodiments of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the embodiments of the present application, and these all belong to the protection scope of the embodiments of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, on which a stacked structure is formed, the stacked structure comprising sacrificial layers and supporting layers alternately stacked; A through hole is formed in the stacked structure, wherein the through hole penetrates the stacked structure, the sacrificial layer comprises a protrusion, and an orthographic projection of the protrusion on the substrate partially overlaps with an orthographic projection of an opening of the through hole on the substrate; Injecting a doping element into the protrusion, wherein the doping element is used to change the etching rate of the protrusion; The doped protrusions are removed by etching.

2. The preparation method according to claim 1, characterized in that: An extending direction of the protrusion is perpendicular to an extending direction of the through hole.

3. The preparation method according to claim 2, characterized in that: The doping element includes a first doping element and a second doping element, and the step of injecting the doping element into the protrusion includes: Injecting the first doping element into the protrusion using a first injection process; The second doping element is implanted into the protrusion by a second implantation process.

4. The preparation method according to claim 3, characterized in that: The first doping element includes boron, the second doping element includes phosphorus, and the constituent material of the sacrificial layer includes silicon oxide.

5. The preparation method according to claim 4, characterized in that: The injection directions of the first injection process and the second injection process are parallel to the extension direction of the through hole and perpendicular to the extension direction of the protrusion.

6. The preparation method according to any one of claims 3 to 5, characterized in that: The doping concentration of the first doping element is greater than the doping concentration of the second doping element.

7. The preparation method according to claim 1, characterized in that: Etching and removing the doped protrusions, comprising: The doped protrusions are removed by wet etching.

8. The preparation method according to claim 7, characterized in that: The wet etching reagent includes a mixed etching solution of dilute sulfuric acid and hydrogen peroxide.

9. The preparation method according to claim 1, characterized in that: Before injecting the doping element into the protrusion, the method further comprises: A cleaning process is used to remove the residue on the inner wall of the through hole.

10. The preparation method according to claim 1, characterized in that: After etching away the doped protrusion, the method further comprises: A capacitor structure is formed in the through hole.

Images