Superconducting quantum flip chip and preparation method thereof

Abstract

The invention relates to the technical field of quantum chips, in particular to a superconducting quantum flip chip and a preparation method thereof. Comprising an upper layer substrate, a first superconducting metal layer, a second superconducting metal layer and a lower layer substrate which are stacked, and the upper layer substrate, the first superconducting metal layer, the second superconducting metal layer and the lower layer substrate form a closed cavity; the metal part is arranged on the second superconducting metal layer and is supported between the second superconducting metal layer and the first superconducting metal layer; the first superconducting metal layer comprises a first circuit layer and a Josephson junction, and the second superconducting metal layer comprises a second circuit layer; and the first circuit layer, the second circuit layer, the Josephson junction and the metal part are all located in the closed cavity. According to the invention, the metal part is only prepared on the lower substrate, the metal part does not need to be arranged on the upper top substrate, the negative influence of the metal part processing technology on the bit performance is avoided as far as possible, and the chip performance is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of quantum chips, and in particular to a superconducting quantum flip chip and a preparation method thereof. Background Art

[0002] Superconducting quantum computing is one of the most likely quantum computing solutions to be put into practical use in the near future. The number of bits developed by major teams around the world has basically exceeded 100, and the maximum number of bits developed by IBM has exceeded 1,000. It is no longer possible to integrate bits of this scale in a single plane, and advanced packaging technology is one of the effective means to solve this problem. In the current preparation process of superconducting quantum chips, when the number of bits exceeds 100, the circuit structure is generally split and arranged on multiple planes, and then the flip-chip or TSV process is used to press-weld and integrate multiple chip planes to achieve the structural integrity of the circuit.

[0003] The current method of preparing flip-chip chips for superconducting quantum is generally to prepare the circuit structure, including bits, resonant cavities and other structures, on the upper and lower substrates, then prepare the limiting layer, and finally prepare the indium pillar for pressure welding connection. In order to effectively control the pressure welding height of the indium pillar, some researchers also use the method of preparing the limiting layer on the chip for regulation, including copper pillars, SiO2 sacrificial layers and other process methods. However, the existing technical means still have the following problems: 1. Since the commonly used substrate superconducting metals such as Al, Ta, Nb are easy to form a metal oxide layer under room temperature and atmospheric environment, they cannot be directly welded with metal connecting parts (such as indium pillars) to form a superconducting connection circuit. Superconducting connection can only be achieved by mutual pressure welding between metal connecting parts. The contact area is very small, the grounding effect is poor, and the mechanical strength of the connection is low; 2. Since a limiting layer needs to be prepared separately to control the pressure welding spacing, the process is relatively cumbersome, which increases the overall risk; 3. In the process of preparing the limiting layer and the indium pillar, it is necessary to use processes such as photolithography and coating, which will have a more obvious impact on the existing bits and reduce the performance of the bits; since the indium pillars are dispersedly arranged on the entire chip surface, it is impossible to prepare the indium pillars first and then prepare the circuit structure; 4. The superconducting connection and grounding of the upper and lower films are completely realized by connecting metal connecting parts. The core circuit is still in direct contact with the external environment, and the chip performance is greatly affected by external noise.

[0004] Chinese patent CN114914355 discloses a three-dimensional packaged superconducting quantum bit device, its preparation method and equipment; the technology sets the resonant cavity, the materials of the capacitor and the electrode are all niobium-based superconducting materials, the metal pillars are indium pillars, and the connection between the niobium-based superconducting material and the indium pillars reacts to generate superconducting material Nb3In. Chinese patent CN116314095A discloses a flip-chip solder bump limiting structure and its preparation method; the technology fills and solidifies the interconnection structure formed by the substrate and the flip chip through the bottom filling glue. Chinese patent CN115968251A discloses a quantum bit component, a method for preparing a quantum bit component, a chip and equipment; the technology forms a superconducting connection with the superconducting circuit layer through the under-bump metal layer, and the material of the under-bump metal layer is metal niobium. Chinese patent CN114023733A discloses a three-dimensional packaging structure and packaging method of a superconducting quantum chip; the technology forms a first connection part on the first side of the quantum chip with a hard material copper, and forms a second connection part on the first side of the control circuit chip with a ductile material. These technologies do not solve the above-mentioned technical problems.

[0005] The prior application CN118102855 A provides a wrapped superconducting quantum flip chip and a preparation method. Although this technology avoids the influence of the preparation of metal pillars on the bit performance by preparing the metal wall first and then the circuit layer, the process of this prior art is cumbersome, and it is necessary to set up multiple grooves to control the metal wall, and it is also necessary to prepare and fill TSV through holes on the lower substrate, and prepare circuit layers on both sides of the lower substrate respectively, and the chip structure is relatively complicated; on the other hand, this technology still relies on the connection between the indium pillars of the upper and lower chips, and there are still technical problems such as small contact area between the indium pillars, poor connection strength and grounding effect.

[0006] In this context, exploring a superconducting quantum flip chip with simple process and superior performance has become a technical problem that needs to be solved urgently in this field. Summary of the invention

[0007] In view of the shortcomings of current technology, the present invention proposes a superconducting quantum flip chip and a preparation method thereof. No metal part (such as indium column) needs to be prepared on the bit chip (top sheet), which will not have a negative impact on the performance of the bit. At the same time, high-precision control of the compression height of the upper and lower chips can be achieved without separately preparing a limiting layer, thereby improving the comprehensive performance of the superconducting quantum flip chip.

[0008] A first aspect of the present invention provides a superconducting quantum flip chip, comprising: an upper substrate, a first superconducting metal layer, a second superconducting metal layer and a lower substrate which are stacked, and the upper substrate, the first superconducting metal layer, the second superconducting metal layer and the lower substrate form a closed cavity.

[0009] Also includes a metal portion, the metal portion is disposed on the second superconducting metal layer and supported between the second superconducting metal layer and the first superconducting metal layer;

[0010] The first superconducting metal layer includes a first circuit layer and a Josephson junction, and the second superconducting metal layer includes a second circuit layer;

[0011] The first circuit layer, the second circuit layer, the Josephson junction and the metal part are all located in the closed cavity.

[0012] The existing superconducting quantum flip chip makes metal parts on two chip circuit planes respectively, for example, aligning the upper and lower indium columns and welding them to achieve the connection between the upper and lower chips. However, this means that the superconducting connection can only be achieved through the contact of the metal part, and the contact area of ​​the metal part is very small, the grounding effect is poor, and the mechanical strength of the connection is low, resulting in poor performance of the flip chip. The design improvement focus of the present invention is that the metal part is only prepared on the lower bottom sheet, and there is no need to set the metal part on the upper top sheet, so as to avoid the negative impact of the metal part process on the bit performance as much as possible. And through the groove design of the lower substrate, the distance between the upper and lower chips after welding is limited by the substrate at the edge of the groove of the lower bottom sheet, and there is no need to prepare a limiting layer separately to achieve high-precision control of the compression height of the metal part, thereby improving the comprehensive performance of the flip chip.

[0013] Preferably, the first superconducting metal layer is made of TiN (titanium nitride).

[0014] Preferably, the second superconducting metal layer includes a second superconducting metal layer A and a second superconducting metal layer B; the second superconducting metal layer A is located on a side adjacent to the upper substrate; and the second superconducting metal layer B is bonded to the lower substrate.

[0015] Preferably, the material of the second superconducting metal layer A is TiN, and the thickness of the second superconducting metal layer A is greater than 0.

[0016] Preferably, the material of the second superconducting metal layer B is selected from one or more combinations of Al, Ta, Nb, NbN, and NbTiN, and the thickness of the second superconducting metal layer B is greater than or equal to 0;

[0017] Preferably, the metal portion is disposed on a surface of the second superconducting metal layer A.

[0018] Currently, commonly used base superconducting metals include aluminum (Al), tantalum (Ta), niobium (Nb), etc. These metal materials are very easy to form a metal oxide layer under room temperature and atmospheric environment, and cannot be directly welded with the metal part to form a superconducting connection circuit. The present invention preferably contacts the TiN layer at both ends of the metal part to form a good superconducting connection; the interference of the metal oxide layer on the contact point is greatly reduced, thereby achieving a significant increase in the connection strength. At the same time, the present invention uses the design of a flip-chip structure with a specifically selected superconducting metal film. When the upper and lower films are fixedly connected, the contact point is a large-area contact of the TiN layer of the upper and lower chips, which further solves the defect that the traditional superconducting connection and grounding rely entirely on the connection between the metal parts, and the connection and grounding effects are poor. While improving the connection strength, it also improves the grounding effect.

[0019] Furthermore, the second superconducting metal layer of the present invention sets the thickness of the second superconducting metal layer B to be greater than or equal to 0, and the thickness of the second superconducting metal layer A to be greater than 0; that is, the second superconducting metal layer can be a TiN layer alone, or a TiN layer and other superconducting metal film layers can be selected to be composited, and as long as both ends of the metal part are in contact with the TiN layer, a better connection effect can be achieved. Under such a concept, the structure of the bottom plate can be flexibly designed according to actual conditions, and the choice of adaptability is strong.

[0020] Preferably, the closed cavity is realized by providing a groove on the surface of the lower substrate adjacent to the upper substrate; preferably, the side wall of the groove forms a slope angle of 10-60° with the lower substrate.

[0021] Note: The slope angle is the angle between the groove slope and the horizontal plane.

[0022] A further improvement of the present invention is that the side wall of the groove is set to form a slope angle of 10-60° with the lower substrate to ensure line connectivity, thereby avoiding the second superconducting metal layer circuit structure from breaking under vertical conditions, which affects the stability of chip performance. The present invention completely encloses the core circuit area in the groove through the ingenious design of the chip structure, thereby achieving complete self-isolation of the chip circuit from the external environment and reducing the impact of external environmental noise pollution on chip performance.

[0023] Preferably, the end surface of the lower substrate close to the upper substrate covers the end surface of the upper substrate close to the lower substrate; that is, the width of the lower substrate is greater than the width of the upper substrate.

[0024] A further improvement of the present invention is the structural design of the upper and lower chips. It is necessary to ensure that part of the lower substrate is exposed after the upper and lower chips are connected, that is, the width of the lower substrate needs to be greater than the width of the upper substrate. This facilitates the subsequent use of the superconducting quantum flip chip. The exposed part of the lower substrate is only the pad area, which serves as an interface for connecting to the external circuit, so that the chip has strong connectivity with the external environment.

[0025] A second aspect of the present invention provides a method for preparing a superconducting quantum flip chip, the preparation steps comprising:

[0026] S1. Preparation of top sheet:

[0027] S1-1. Preparing a first superconducting metal layer on the surface of the upper substrate;

[0028] S1-2. Construct the first circuit layer and the Josephson junction on the first superconducting metal layer in sequence.

[0029] S2. Preparation of bottom film:

[0030] S2-1. Preparing a second superconducting metal layer on the surface of the lower substrate;

[0031] S2-2. Sequentially construct a second circuit layer and prepare a metal portion on the second superconducting metal layer;

[0032] S3. Flip the upper top sheet vertically and align it horizontally with the lower bottom sheet, so that the metal part is arranged corresponding to the first superconducting metal layer, and the metal part is supported between the second superconducting metal layer and the first superconducting metal layer, so that the upper top sheet and the lower bottom sheet are fixedly connected to obtain a flip chip product.

[0033] Preferably, in step S2-1, before preparing the second superconducting metal layer, a groove is prepared on the surface of the lower substrate to form a closed cavity, and the second superconducting metal layer is prepared on the side of the lower substrate where the groove is provided; the second circuit layer and the metal part are both arranged in the groove.

[0034] Preferably, the thickness of the metal part is 4-15 μm. The present invention controls the size of the metal part, achieves high-precision control without setting a limiting layer, and improves the overall performance of the chip.

[0035] Preferably, during the horizontal alignment in step S3, the first superconducting metal layer of the upper top sheet and the second superconducting metal layer of the lower bottom sheet are completely in contact with each other, and the components are pressed together after being aligned to achieve a fixed connection.

[0036] Further preferably, the S1 step specifically includes:

[0037] S1-1. A first superconducting metal layer is deposited on the surface of the upper substrate;

[0038] S1-2. By photolithography and etching processes, a circuit pattern is constructed on the upper substrate;

[0039] S1-3. Prepare a Josephson junction in the exposure area defined by photolithography.

[0040] In step S1-1, the upper substrate may be pre-cleaned before depositing the first superconducting metal layer; the cleaning method may be a common method in the art, such as BOE (silicon oxide) cleaning.

[0041] Preferably, the thickness of the first superconducting metal layer is 100-300 nm.

[0042] In the step S1-2, a suitable large-structure circuit pattern circuit (ie, the first circuit layer) is constructed according to actual needs.

[0043] Preferably, in the step S1-2, the exposure area defined by photolithography is etched, and the etching method is preferably dry etching; while etching, impurities adsorbed on the surface of the first superconducting metal layer or a possible slight oxide layer is removed.

[0044] Preferably, in the step S1-3, (1) ion-milling cleaning is performed in sequence in the exposure area defined by lithography to remove the oxide layer on the surface of the first superconducting metal layer, (2) Al layer is deposited, (3) oxidation, (4) Al layer is deposited, and (5) stripping and degumming cleaning are performed to prepare a Josephson junction and connect it to a large structure circuit.

[0045] Further preferably, the S2 step specifically includes:

[0046] S2-1. A groove is prepared on the surface of the lower substrate by photolithography and etching process;

[0047] S2-2. A second superconducting metal layer is deposited on one side of the lower substrate having a groove;

[0048] S2-3. Performing photolithography and etching on the surface of the second superconducting metal layer to construct a circuit pattern line;

[0049] S2-4. Depositing metal parts in the exposure areas defined by photolithography.

[0050] Preferably, the depth of the groove is 2-8 μm, more preferably 5 μm.

[0051] Preferably, in step S2-2, the lower substrate may be pre-cleaned before depositing the second superconducting metal layer; the cleaning method may be a commonly used method in the art, such as BOE (silicon oxide) cleaning.

[0052] In step S2-3, the circuit pattern line (ie, the second circuit layer) is designed according to actual needs.

[0053] Preferably, in the step S2-4, the exposure area defined by the photolithography is etched, and the etching method is preferably dry etching, such as ion-milling (ion beam milling); impurities adsorbed on the surface of the second superconducting metal layer or a possible slight oxide layer is removed; then the metal part is evaporated, and finally the glue is removed and cleaned to prepare a lower film provided with a metal part.

[0054] Preferably, the deposition thickness of the metal part is 4-15 μm; the method of depositing the metal part is not particularly limited, for example, evaporation.

[0055] Preferably, the metal part is a commonly used metal piece in the art that can achieve the purpose of connection, such as an indium (In) column.

[0056] Preferably, the pressing temperature in step S3 is 0-150°C.

[0057] In the step S3, before connecting the upper and lower chips, they can be cleaned to remove impurities adsorbed on the surface of the material or a possible slight oxide layer; the cleaning method adopts conventional technical means in the field, such as plasma cleaning.

[0058] Preferably, the S3 step specifically includes:

[0059] S3-1. Clean the top sheet and bottom sheet;

[0060] S3-2. In a nitrogen atmosphere, the upper sheet is vertically flipped and aligned with the lower sheet by a flip-chip welding device, at which time the first superconducting metal layer of the upper sheet and the second superconducting metal layer of the non-groove area of ​​the lower sheet and the upper sheet adjacent to the upper sheet are completely in contact, and the end surface of the lower substrate close to the upper substrate covers the end surface of the upper substrate close to the lower substrate;

[0061] S3-3. Under a nitrogen atmosphere, pressure is applied to the upper top sheet and the lower bottom sheet through a flip-chip device to achieve bonding connection between the upper top sheet and the lower bottom sheet.

[0062] Preferably, after bonding, the distance between the upper top sheet and the lower bottom sheet (ie, the groove depth) is 2-8 μm.

[0063] At present, when preparing flip chips, photolithography, coating and other processes are required in the process of preparing the limiting layer and the indium column. On the one hand, the process is relatively cumbersome, which increases the risk of the overall operation; more importantly, it will inevitably affect the existing bits and reduce the performance of the bits; limited by the fact that the metal parts are scattered on the entire chip surface, it is impossible to prepare the indium column first and then prepare the circuit structure. The present invention adjusts the design of the metal part from being prepared on the upper and lower chips respectively to being prepared only on the lower film, and connects through In and TiN contacts, eliminating the influence of the In preparation process on the bit performance of the upper top film. And through the design of the specific groove of the lower film, there is no need to specially set a limiting layer in the overall structure, which simplifies the structure and preparation process of the flip chip to the greatest extent, weakens the negative impact of the process operation on the bit performance, and thus improves the overall performance of the flip chip.

[0064] The present invention preferably uses pressure welding to fix the upper and lower chips. The temperature range for pressure welding is wide, and both hot pressing and cold pressing are possible. However, glue cannot be used to fix the upper and lower chips. This is because the superconducting quantum flip chip of the present invention is used in a precise environment, and organic substances or other impurities cannot be introduced. The system must be kept pure while maintaining electrical properties.

[0065] Preferably, when the second superconducting metal layer includes a second superconducting metal layer A and a second superconducting metal layer B, and the thickness of the second superconducting metal layer B is greater than 0, the step of preparing the bottom film in S2 is specifically:

[0066] S2-1. First, a groove is prepared on the surface of the lower substrate, and then a second superconducting metal layer B is prepared on one side of the lower substrate having the groove;

[0067] S2-2. Constructing a second circuit layer on the second superconducting metal layer B;

[0068] S2-3. Preparing a second superconducting metal layer A on the second superconducting metal layer B away from the substrate, and preparing a metal portion on the second superconducting metal layer A away from the second superconducting metal layer B;

[0069] The second circuit layer and the metal part are both arranged in the groove.

[0070] The design of the above scheme actually corresponds to another option of the bottom film structure, that is, the second superconducting metal layer is selected from a TiN layer or a composite structure composed of a TiN layer (second superconducting metal layer A) and at least one of an Al layer, a Ta layer, a Nb layer, a NbN layer, and a NbTiN layer (second superconducting metal layer B); it can be selected and used according to actual design needs. In this embodiment, the TiN layer does not need to be spread over a large area on the second superconducting metal layer B, and its size only needs to be slightly larger than the In column, in order to isolate the In column and the aluminum film from direct contact reactions to produce byproducts and reduce the negative impact on the chip.

[0071] In some embodiments, the process parameters of the present invention, such as the groove depth and the thickness of the superconducting metal layer, can be flexibly adjusted according to the actual circuit design requirements, with a wide selection range.

[0072] In some embodiments, the position of the groove of the present invention is not particularly limited. For example, it can be set in the middle of the lower substrate and positioned specifically in combination with circuit design requirements. In principle, the entire bit area can be included in the groove.

[0073] The present invention does not impose any particular limitation on the material of the substrate, and a substrate commonly used in the art may be used; for example, high-resistance silicon, amorphous silicon, aluminum oxide (such as sapphire), silicon carbide, aluminum nitride, zinc oxide, gallium arsenide, etc., which can be selected and used according to actual design requirements.

[0074] The present invention does not impose any particular limitation on the deposition process of the superconducting metal film, as long as the purpose of coating can be achieved; for example, magnetron sputtering deposition, ion deposition, ion beam assisted magnetron sputtering deposition, etc. may be used.

[0075] The present invention does not impose any particular limitation on the technical means for constructing circuit graphic lines, and the common process methods in the art can be used. For example, in addition to photolithography and etching, in actual applications, the construction of circuit graphic lines can also be achieved through lift-off processes such as photolithography, deposition, and stripping, and the process means can be flexibly matched according to actual design needs.

[0076] Beneficial effects:

[0077] The present invention provides a superconducting quantum flip chip and a preparation method thereof, which has the following advantages:

[0078] (1) The present invention only prepares the metal part on the lower bottom sheet, and does not need to set the metal part on the upper top sheet, thereby avoiding the negative impact of the metal part processing technology on the bit performance as much as possible.

[0079] (2) In the present invention, both ends of the metal part are preferably in contact with TiN to form a good superconducting connection; the interference of the metal oxide layer on the contact point is greatly reduced, thereby achieving a significant improvement in the connection strength.

[0080] (3) The present invention adopts the groove design of the lower substrate. The spacing between the upper and lower chips after pressure welding is limited by the edge substrate of the groove of the lower substrate. There is no need to prepare a limiting layer separately. While simplifying the process steps, high-precision control of the compression height of the metal part can be achieved, thereby improving the comprehensive performance of the flip chip.

[0081] (4) The present invention adopts the design of flip chip structure and specially selected superconducting metal film. After the upper and lower substrates are fixedly connected, the TiN film on the substrate shows a large-area contact, which solves the defect that the traditional superconducting connection and grounding are completely realized by the metal parts, and the connection and grounding effects are poor. It improves the connection strength and the grounding effect at the same time.

[0082] (5) The present invention simplifies the structure and preparation process of the flip chip to the greatest extent, is easy to operate and implement, and has good application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0083] Figure 1 . Schematic diagram of the process flow of Example 1;

[0084] Figure 2 . Schematic diagram of the process flow of Example 2;

[0085] Figure 3 .Schematic diagram of the slope angle between the groove sidewall and the underlying substrate. DETAILED DESCRIPTION

[0086] The schematic diagrams, specific numbers, materials, and process methods mentioned in the cases of the present invention are only used as examples of this technology. These cases should be understood as being used for more detailed and specific descriptions, and should not be understood as being used to limit the present invention in any form.

[0087] Example 1.

[0088] In a first aspect, the present embodiment provides a superconducting quantum flip chip, comprising: an upper substrate, a first superconducting metal layer, a second superconducting metal layer and a lower substrate arranged in layers, wherein the upper substrate, the first superconducting metal layer, the second superconducting metal layer and the lower substrate form a closed cavity;

[0089] Also includes a metal portion, the metal portion is disposed on the second superconducting metal layer and supported between the second superconducting metal layer and the first superconducting metal layer;

[0090] The first superconducting metal layer includes a first circuit layer and a Josephson junction, and the second superconducting metal layer includes a second circuit layer;

[0091] The first circuit layer, the second circuit layer, the Josephson junction and the metal part are all located in the closed cavity.

[0092] The first superconducting metal layer and the second superconducting metal layer are both made of TiN, and the thickness of the first superconducting metal layer and the second superconducting metal layer are both 100 nm.

[0093] The metal portion is an In column.

[0094] The closed cavity is realized by providing a groove on the surface of the lower substrate adjacent to the upper substrate; the side wall of the groove forms a slope angle of 45° with the lower substrate.

[0095] The end surface of the lower substrate close to the upper substrate covers the end surface of the upper substrate close to the lower substrate.

[0096] The upper substrate and the lower substrate are both high-resistance silicon.

[0097] A second aspect of this embodiment provides a method for preparing a superconducting quantum flip chip. The steps of preparing the superconducting quantum flip chip include:

[0098] S1. Prepare the top sheet;

[0099] S1-1. A first superconducting metal layer (TiN) is deposited on the surface of the upper substrate by magnetron sputtering, with a coating thickness of 100 nm;

[0100] S1-2. A large circuit pattern (ie, the first circuit layer) is constructed on the upper substrate by photolithography and etching processes;

[0101] S1-3. Prepare a Josephson junction in the exposure area defined by photolithography.

[0102] In step S1-1, the upper substrate is pre-cleaned with BOE before depositing the first superconducting metal layer. Specifically, ammonium fluoride and hydrofluoric acid with a volume ratio of 10:1 are used as a cleaning agent for cleaning for 1 minute to remove impurities and a natural oxide layer on the surface of the upper substrate.

[0103] In the step S1-2, the exposure area defined by the photolithography is etched, specifically using Cl2+BCl3 gas plasma etching to remove the first superconducting metal layer; the Cl2 gas flow rate is 35 sccm, and the BCl3 gas flow rate is 13 sccm.

[0104] In the step S1-3, in the exposure area defined by photolithography, (1) ion-milling is used to etch and remove the impurities and natural oxide layer adsorbed on the surface of the first superconducting metal layer, (2) a layer of Al film (coating thickness 30nm), (3) oxygen oxidation (oxidation conditions are 10torr, 20min), (4) another layer of Al film (coating thickness 60nm), (5) stripping, degumming and cleaning are performed in sequence to prepare a Josephson junction and connect it to a large structure circuit. The stripping, degumming and cleaning are specifically performed by immersion stripping in N-methylpyrrolidone at 85°C, and isopropyl alcohol cleaning and drying.

[0105] S2. Preparation of bottom film:

[0106] S2-1. A groove is prepared on the surface of the lower substrate by photolithography and etching process, the groove depth is 5μm, and the sidewall of the groove forms a slope angle of 45° with the lower substrate;

[0107] S2-2. A second superconducting metal layer (TiN) is deposited on one side of the lower substrate having a groove;

[0108] S2-3. Performing photolithography and etching on the surface of the second superconducting metal layer to construct a circuit pattern line;

[0109] S2-4. Evaporate In columns in the exposure areas defined by photolithography.

[0110] In step S2-2, the lower substrate is pre-cleaned before depositing the second superconducting metal layer; specifically, ammonium fluoride and hydrofluoric acid with a volume ratio of 10:1 are used as a cleaning agent for cleaning for 1 minute to remove impurities and a natural oxide layer on the surface of the lower substrate.

[0111] In step S2-3, the circuit pattern line (ie, the second circuit layer) is designed according to actual needs.

[0112] In the step S2-4, the exposure area defined by the photolithography is etched, specifically by using ion-milling to etch and remove the impurities adsorbed on the surface of the second superconducting metal layer and the natural oxide layer; then In columns are evaporated to a thickness of 10 μm; finally, the lower film with In columns evaporated is prepared by stripping, degumming and cleaning. The stripping, degumming and cleaning are specifically performed by immersion stripping in N-methylpyrrolidone at 85°C, and isopropyl alcohol cleaning and drying.

[0113] S3. Preparation of chip:

[0114] S3-1. The top sheet and the bottom sheet are cleaned by Ar plasma to remove surface adsorbed impurities and natural oxide layer;

[0115] S3-2. In a nitrogen atmosphere, the upper sheet is vertically flipped and aligned with the lower sheet by a flip-chip welding device, and the upper sheet is vertically flipped and horizontally aligned with the lower sheet, so that the first superconducting metal layer of the upper sheet and the second superconducting metal layer of the non-groove area of ​​the lower sheet and the upper sheet are completely in contact, and the In column is arranged corresponding to the first superconducting metal layer, and the In column is supported between the second superconducting metal layer and the first superconducting metal layer;

[0116] S3-3. In a nitrogen atmosphere, after alignment, the upper top sheet and the lower bottom sheet are pressure-heated to 150°C through a flip-chip device and maintained for 10 minutes to achieve bonding connection between the upper top sheet and the lower bottom sheet.

[0117] After lamination, the distance between the upper top sheet and the lower bottom sheet is equal to the groove depth, which is equal to 5 μm.

[0118] The process flow diagram of Example 1 is shown in Figure 1 .

[0119] Example 2.

[0120] In a first aspect, the present embodiment provides a superconducting quantum flip chip, comprising: an upper substrate, a first superconducting metal layer, a second superconducting metal layer and a lower substrate arranged in layers, wherein the upper substrate, the first superconducting metal layer, the second superconducting metal layer and the lower substrate form a closed cavity;

[0121] Also includes a metal portion, the metal portion is disposed on the second superconducting metal layer and supported between the second superconducting metal layer and the first superconducting metal layer;

[0122] The first superconducting metal layer includes a first circuit layer and a Josephson junction, and the second superconducting metal layer includes a second circuit layer;

[0123] The first circuit layer, the second circuit layer, the Josephson junction and the metal part are all located in the closed cavity.

[0124] The material of the first superconducting metal layer is TiN.

[0125] The second superconducting metal layer includes a second superconducting metal layer A and a second superconducting metal layer B; the second superconducting metal layer A is located on a side adjacent to the upper substrate; and the second superconducting metal layer B is bonded to the lower substrate.

[0126] The second superconducting metal layer A is made of TiN, with a thickness of 50 nm; the second superconducting metal layer B is made of Al, with a thickness of 100 nm.

[0127] The metal portion is disposed on the surface of the second superconducting metal layer A.

[0128] The metal portion is an In column.

[0129] The closed cavity is realized by providing a groove on the surface of the lower substrate adjacent to the upper substrate; the side wall of the groove forms a slope angle of 45° with the lower substrate.

[0130] The end surface of the lower substrate close to the upper substrate covers the end surface of the upper substrate close to the lower substrate.

[0131] The upper substrate and the lower substrate are both high-resistance silicon.

[0132] A second aspect of this embodiment provides a method for preparing a superconducting quantum flip chip. The steps of preparing the superconducting quantum flip chip include:

[0133] S1. Prepare the top sheet;

[0134] S1-1. A first superconducting metal layer (TiN) is deposited on the surface of the upper substrate by magnetron sputtering, with a coating thickness of 100 nm;

[0135] S1-2. A large circuit pattern (ie, the first circuit layer) is constructed on the upper substrate by photolithography and etching processes;

[0136] S1-3. Prepare a Josephson junction in the exposure area defined by photolithography.

[0137] In step S1-1, the upper substrate is pre-cleaned with BOE before depositing the first superconducting metal layer. Specifically, ammonium fluoride and hydrofluoric acid with a volume ratio of 10:1 are used as a cleaning agent for cleaning for 1 minute to remove impurities and a natural oxide layer on the surface of the upper substrate.

[0138] In the step S1-2, the exposure area defined by the photolithography is etched, specifically using Cl2+BCl3 gas plasma etching to remove the first superconducting metal layer; the Cl2 gas flow rate is 35 sccm, and the BCl3 gas flow rate is 13 sccm.

[0139] In the step S1-3, in the exposure area defined by photolithography, (1) ion-milling is used to etch and remove the impurities and natural oxide layer adsorbed on the surface of the first superconducting metal layer, (2) a layer of Al film (coating thickness 30nm), (3) oxygen oxidation (oxidation conditions are 10torr, 20min), (4) another layer of Al film (coating thickness 60nm), (5) stripping, degumming and cleaning are performed in sequence to prepare a Josephson junction and connect it to a large structure circuit. The stripping, degumming and cleaning are specifically performed by immersion stripping in N-methylpyrrolidone at 85°C, and isopropyl alcohol cleaning and drying.

[0140] S2. Preparation of bottom film:

[0141] S2-1. A groove is prepared on the surface of the lower substrate by photolithography and etching process, the groove depth is 5μm, and the sidewall of the groove forms a slope angle of 45° with the lower substrate;

[0142] S2-2. A 100 nm thick second superconducting metal layer B (Al) is deposited on one side of the lower substrate having a groove;

[0143] S2-3. Performing photolithography and etching on the surface of the second superconducting metal layer B to construct a circuit pattern line;

[0144] S2-4. A 50 nm thick second superconducting metal layer A (TiN) is deposited in the exposure area defined by photolithography, and then an In column is evaporated.

[0145] In step S2-2, the lower substrate is pre-cleaned before depositing the second superconducting metal layer A; specifically, ammonium fluoride and hydrofluoric acid with a volume ratio of 10:1 are used as a cleaning agent for cleaning for 1 minute to remove impurities and a natural oxide layer on the surface of the lower substrate.

[0146] In step S2-3, the circuit pattern line (ie, the second circuit layer) is designed according to actual needs.

[0147] In the step S2-4, the exposure area defined by the photolithography is etched, specifically by using ion-milling to etch and remove the impurities and natural oxide layer adsorbed on the surface of the second superconducting metal layer A; then In columns are evaporated to a thickness of 10 μm; finally, the lower film with In columns evaporated is stripped and cleaned to prepare the lower film. The stripping and cleaning is specifically performed by soaking and stripping in N-methylpyrrolidone at 85°C, and then cleaning and drying with isopropyl alcohol.

[0148] S3. Preparation of chip:

[0149] S3-1. The top sheet and the bottom sheet are cleaned by Ar plasma to remove surface adsorbed impurities and natural oxide layer;

[0150] S3-2. In a nitrogen atmosphere, the upper sheet is vertically flipped and aligned with the lower sheet by a flip-chip welding device, and the upper sheet is vertically flipped and horizontally aligned with the lower sheet, so that the first superconducting metal layer of the upper sheet and the second superconducting metal layer A in the non-groove area adjacent to the lower sheet and the upper sheet are completely in contact, and the In column is arranged corresponding to the first superconducting metal layer A, and the In column is supported between the second superconducting metal layer A and the first superconducting metal layer;

[0151] S3-3. In a nitrogen atmosphere, after alignment, the upper top sheet and the lower bottom sheet are pressure-heated to 150°C through a flip-chip device and maintained for 10 minutes to achieve bonding connection between the upper top sheet and the lower bottom sheet.

[0152] After lamination, the distance between the upper top sheet and the lower bottom sheet is equal to the groove depth, which is equal to 5 μm.

[0153] The process flow diagram of Example 2 is shown in Figure 2 .

[0154] The series of detailed descriptions listed in the present invention are only specific descriptions of the feasible implementation methods of this technology. They are not used to limit the protection scope of this application. Any equivalent implementation methods or changes that do not deviate from the technical spirit of this application should be included in the protection scope of this application. In addition, the relationship terms in this article (such as the first superconducting metal layer and the second superconducting metal layer, S1 step and S2 step) are only used to distinguish one entity / operation from another entity / operation, and do not necessarily require or imply that there is an actual relationship or order between these entities / operations; in the specific implementation, the operation can be carried out in accordance with the principle of meeting the actual use requirements.

Claims

1. A superconducting quantum flip chip, It is characterized in that include: An upper substrate, a first superconducting metal layer, a second superconducting metal layer and a lower substrate are stacked, and the upper substrate, the first superconducting metal layer, the second superconducting metal layer and the lower substrate form a closed cavity; Also includes a metal portion, the metal portion is disposed on the second superconducting metal layer and supported between the second superconducting metal layer and the first superconducting metal layer; The first superconducting metal layer includes a first circuit layer and a Josephson junction, and the second superconducting metal layer includes a second circuit layer; The first circuit layer, the second circuit layer, the Josephson junction and the metal part are all located in the closed cavity.

2. The superconducting quantum flip chip according to claim 1, It is characterized in that The material of the first superconducting metal layer is TiN.

3. The superconducting quantum flip chip according to claim 1, It is characterized in that The second superconducting metal layer includes a second superconducting metal layer A and a second superconducting metal layer B; the second superconducting metal layer A is located on a side adjacent to the upper substrate; the second superconducting metal layer B is bonded to the lower substrate; The material of the second superconducting metal layer A is TiN, and the thickness of the second superconducting metal layer A is greater than 0; the material of the second superconducting metal layer B is selected from a combination of one or more of Al, Ta, Nb, NbN, and NbTiN, and the thickness of the second superconducting metal layer B is greater than or equal to 0.

4. The superconducting quantum flip chip according to claim 3, It is characterized in that The metal portion is disposed on the surface of the second superconducting metal layer A.

5. The superconducting quantum flip chip according to claim 1, It is characterized in that The closed cavity is realized by providing a groove on the surface of the lower substrate adjacent to the upper substrate; The sidewall of the groove forms a slope angle of 10-60° with the underlying substrate.

6. The superconducting quantum flip chip according to claim 1, It is characterized in that The end surface of the lower substrate close to the upper substrate covers the end surface of the upper substrate close to the lower substrate.

7. A method for preparing a superconducting quantum flip chip, It is characterized in that The preparation steps include: S1. Preparation of top sheet: S1-1. Preparing a first superconducting metal layer on the surface of the upper substrate; S1-2. Construct the first circuit layer and the Josephson junction on the first superconducting metal layer in sequence. S2. Preparation of bottom film: S2-1. Preparing a second superconducting metal layer on the surface of the lower substrate; S2-2. Sequentially construct a second circuit layer and prepare a metal portion on the second superconducting metal layer; S3. Flip the upper top sheet vertically and align it horizontally with the lower bottom sheet, so that the metal part is arranged corresponding to the first superconducting metal layer, and the metal part is supported between the second superconducting metal layer and the first superconducting metal layer, so that the upper top sheet and the lower bottom sheet are fixedly connected to obtain a flip chip product.

8. The method for preparing a superconducting quantum flip chip according to claim 7, It is characterized in that In step S2-1, before preparing the second superconducting metal layer, a groove is prepared on the surface of the lower substrate to form a closed cavity, and the second superconducting metal layer is prepared on the side of the lower substrate where the groove is provided; The second circuit layer and the metal part are both arranged in the groove.

9. The method for preparing a superconducting quantum flip chip according to claim 7, It is characterized in that The second superconducting metal layer includes a second superconducting metal layer A and a second superconducting metal layer B; the thickness of the second superconducting metal layer A is greater than 0; the thickness of the second superconducting metal layer B is greater than or equal to 0; When the thickness of the second superconducting metal layer B is greater than 0, step S2 comprises: In step S2-1, a groove is first prepared on the surface of the lower substrate before preparing the second superconducting metal layer, and the second superconducting metal layer B is prepared on the side of the lower substrate where the groove is provided; S2-2. Constructing a second circuit layer on the second superconducting metal layer B; S2-3. Preparing a second superconducting metal layer A on the second superconducting metal layer B away from the substrate, and preparing a metal portion on the second superconducting metal layer A away from the second superconducting metal layer B; The second circuit layer and the metal part are both arranged in the groove.

10. The method for preparing a superconducting quantum flip chip according to claim 7 or 9, It is characterized in that The metal part is prepared to have a thickness of 4-15 μm.

11. The method for preparing a superconducting quantum flip chip according to claim 7 or 9, It is characterized in that During the horizontal alignment in step S3, the first superconducting metal layer of the top sheet and the second superconducting metal layer of the non-groove area adjacent to the bottom sheet and the top sheet are completely in contact, and the components are aligned and pressed together to achieve fixed connection.

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