Method for transferring layer from source substrate to target substrate

Abstract

The present specification designs a method of transferring a layer (15) from a source substrate (13) to a target substrate (17), comprising the steps of: a) activating a bonding surface of the layer (15) and a bonding surface of the target substrate (17) by ion etching of the bonding surface of the layer (15) and the bonding surface of the target substrate (17) or by sputtering a bonding material onto the surface; and b) after step a), placing the bonding surface of the layer (15) in contact with the bonding surface of the target substrate (17) wherein during step a) a masking ring (21) covers a peripheral portion of the bonding surface of the layer (15) and / or a masking ring (23) covers a peripheral portion of the bonding surface of the target substrate; and wherein steps a) and b) are carried out under vacuum, and the vacuum is not destroyed between the two steps.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the priority of French patent application No. 2204711 filed on May 18, 2022 and entitled “Method for transferring a layer from a source substrate to a target substrate”, which application is considered to be an integral part of this description to the extent provided by law. Technical Field

[0003] The present disclosure generally relates to methods of manufacturing microelectronic components based on semiconductor materials. More specifically, it is directed to a method of transferring a semiconductor layer from a source substrate to a target substrate. Background Art

[0004] In microelectronic component manufacturing methods, layer transfer is currently used to transfer relatively thin semiconductor layers of high crystal quality onto thicker target substrates of lower crystal quality or made of cheaper materials.

[0005] After transfer, the transferred layer can be used as a substrate for an epitaxial step. Microelectronic components can then be formed within and on top of the epitaxial layer.

[0006] It would be desirable to at least partially overcome certain disadvantages of known methods for transferring a semiconductor layer from a source substrate to a target substrate.

[0007] More particularly, consideration is given here to improving the edge quality of the transferred layer. Summary of the invention

[0008] One embodiment provides a method of transferring a layer from a source substrate to a target substrate, the method comprising the steps of:

[0009] a) activating the bonding surface of the layer and the bonding surface of the target substrate by ion etching of the bonding surface of the layer and the bonding surface of the target substrate or by sputtering a bonding material onto the surfaces; and

[0010] b) after step a), placing the bonding surface of the layer in contact with the bonding surface of a target substrate,

[0011] wherein during step a), the masking ring covers a peripheral portion of the bonding surface of the layer, and / or the masking ring covers a peripheral portion of the bonding surface of the target substrate; and

[0012] Wherein, steps a) and b) are performed under vacuum, and the vacuum is not broken between the two steps.

[0013] According to one embodiment, the target substrate and / or the source substrate key has a tapered edge spanning the first width.

[0014] According to one embodiment, the width of the masking ring is greater than or equal to the first width.

[0015] According to one embodiment, the method comprises a step c) of removing the source matrix after step b).

[0016] According to one embodiment, step c) comprises an annealing step which causes the assembly obtained at the end of step b) to break in the plane of the implanted buried layer separating said layer from the source matrix.

[0017] According to an embodiment, the layer is a semiconductor layer.

[0018] According to one embodiment, the method comprises, after step b), a step of epitaxy on top of and in contact with the surface of the layer opposite to the target substrate.

[0019] According to one embodiment, the method comprises, before step a), a step of forming a step at the periphery of the layer and / or at the periphery of the target substrate.

[0020] According to one embodiment, the step is formed by ion etching while protecting the central part of the bonding surface by means of a masking disk.

[0021] According to one embodiment, the ion etching for forming the step is carried out in the same apparatus as that used for activating the bonding surface in step a).

[0022] According to one embodiment, the method comprises a waiting period of at least 10 minutes and / or a period of applying a reactive gas between forming said step and activating the bonding surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The foregoing features and advantages, as well as other features and advantages, will be described in detail in the remainder of the disclosure of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0024] Figure 1A , Figure 1B , Figure 1C , Figure 1D and Figure 1E is a perspective view partially and schematically showing consecutive steps of an example of a method of transferring a semiconductor layer from a source substrate to a target substrate according to a first embodiment;

[0025] Figure 2A , Figure 2B , Figure 2C , Figure 2D and Figure 2Eis a cross-sectional view partially and schematically illustrating consecutive steps of an example of a method of transferring a semiconductor layer from a source substrate to a target substrate according to a second embodiment; and

[0026] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E and Figure 3F is a cross-sectional view partially and schematically illustrating consecutive steps of an example of a method of transferring a semiconductor layer from a source substrate to a target substrate according to a third embodiment. DETAILED DESCRIPTION

[0027] In the various figures, the same features are represented by the same reference numerals. In particular, common structural features and / or functional features in various embodiments may have the same reference numerals, and the same structural characteristics, dimensional characteristics and material characteristics may be provided.

[0028] For the sake of clarity, only the steps and elements that are helpful for understanding the embodiments described herein are described and shown in detail. In particular, the method of manufacturing microelectronic components based on transferred semiconductor layers is not described in detail, the described transfer method is compatible with all or most commonly used microelectronic component manufacturing methods.

[0029] In the following disclosure, when reference is made to absolute position qualifiers (such as terms "front", "back", "top", "bottom", "left", "right", etc.) or relative position qualifiers (such as terms "above", "below", "upper", "lower", etc.) or orientation qualifiers (such as "horizontal", "vertical", etc.), unless otherwise specified, the orientation of the figure shall be referred to.

[0030] Unless otherwise indicated, the expressions "about", "approximately", "substantially" and "approximately" mean within 10%, preferably within 5%.

[0031] Figure 1A , Figure 1B , Figure 1C , Figure 1D and Figure 1E is a perspective view partially and schematically illustrating consecutive steps of an example of a method of transferring a semiconductor layer from a source substrate to a target substrate according to the first embodiment.

[0032] Figure 1A On its left side, a structure 110 is shown, which includes a source substrate 13 and a semiconductor layer 15 to be transferred, and on its right side, a target substrate 17 is shown.

[0033] The semiconductor layer 15 to be transferred is arranged on the upper surface of the substrate 13 and, for example, in contact with it. For example, the semiconductor layer 15 extends continuously across the entire upper surface of the substrate 13 with a substantially uniform thickness. The semiconductor layer 15 is, for example, a single crystal layer. For example, the semiconductor layer 15 is a silicon carbide (SiC) layer, such as a single crystal of the 4H-SiC type. As a variation, the semiconductor layer 15 is made of germanium (Ge), such as a single crystal. The described embodiments are not limited to these specific examples.

[0034] The source matrix 13 is made of, for example, a semiconductor material. For example, the source matrix 13 is made of the same material as the semiconductor layer 15. However, the described embodiments are not limited to this particular case.

[0035] For example, the thickness of the layer 15 to be transferred ranges from 100 nm to 10 μm, for example from 300 nm to 2 μm.

[0036] For example, the thickness of the source matrix 13 ranges from 100 μm to 1 mm, such as between 250 μm and 800 μm, such as approximately 350 μm.

[0037] The target substrate 17 can be made of a semiconductor material or of a dielectric material. The target substrate 17 is, for example, a semiconductor wafer, for example made of silicon or of carbide polysilicon, for example of the 3C-SiC type.

[0038] For example, the target substrate 17 and the source substrate 13 have substantially the same shape and the same size in a top view. For example, in a top view, the target substrate 17 and the source substrate 13 are both circular in shape and have, for example, the same diameter.

[0039] In order to limit the risk of breakage, the target substrate 17 and / or the source substrate 13 preferably has a tapered or rounded edge and lip region, for example, across a peripheral annular band with a width ranging from 0.1 mm to 5 mm, for example, from 0.2 mm to 3 mm. In other words, the target substrate 17 and / or the source substrate 13 has at its periphery a thickness that decreases as the distance from the center of the substrate increases, for example, across a peripheral annular band with a width ranging from 0.1 mm to 5 mm, for example, from 0.2 to 3 mm.

[0040] During the transfer of the layer 15 to be transferred onto the target substrate 17, the layer 15 to be transferred is placed on Figure 1A In the orientation, the upper surface of the target substrate 17 is contacted by its upper surface.

[0041] In practice, and more specifically in the case of target substrate 17 and / or source substrate 13 with tapered edges, it can be observed that the bonding of layer 15 to target substrate 17 is not complete at the periphery of the assembly. In fact, during the transfer of layer 15 onto substrate 17, while layer 15 and substrate 17 are in good contact towards the centre of the assembly, they are not in contact or are only partially in contact at the edges of the assembly, in particular due to the peripheral tapering of the substrate and / or possible surface irregularities of the substrate.

[0042] At the end of the step of removing the source substrate 13, the peripheral portions of the layer 15 which are not bonded or poorly bonded to the target substrate 17 are broken off. Thus, a peripheral annular zone of the target substrate 17 is not covered by the layer 15 or is only partially covered by it.

[0043] In the absence of specific preventive measures, after the transfer, the edge of the layer 15 at the periphery of the assembly is irregular. This is due to the irregular bonding limits between the layer 15 and the target substrate 17. Such irregularities of the edge of the layer 15 may make it possible for defects to propagate towards the center of the layer 15 during subsequent microelectronic component manufacturing steps, for example during the step of epitaxy from the upper surface of the layer 15. Defects are particularly likely to propagate in the epitaxial layer on the layer 15.

[0044] It is desirable here to increase the regularity or sharpness of the edges of the layer 15 at the end of the transfer.

[0045] Figure 1B The step of activating the upper surface of the layer 15 (referred to as the bonding surface) and the upper surface of the target substrate 17 (referred to as the bonding surface) is shown.

[0046] This activation step is carried out by an etching or ion milling method, comprising sending an ion beam 19 or an atomic beam, such as a neutral beam, onto the surface to be activated. For example, the beam 19 is able to remove oxides that may be present at the surface of the surface to be activated and form dangling bonds that will be used to form covalent bonds in the subsequent step during contacting of the activated surfaces. This type of bonding method is generally referred to as surface activated bonding or SAB.

[0047] This step is carried out under vacuum, that is to say at a pressure lower than atmospheric pressure, for example under ultra-high vacuum, for example at a pressure lower than 10 -7 mbar (e.g. below 10 -8 mbar).

[0048] exist Figure 1BIn the example of , during the step of activating the bonding surface, the masking ring 21 covers the peripheral part of the bonding surface of the layer 15 and the masking ring 23 covers the peripheral part of the bonding surface of the target substrate 17. For example, the outer diameter of the masking ring 21 corresponds to the diameter of the source substrate 13. For example, the outer diameter of the masking ring 23 corresponds to the diameter of the target substrate 17. For example, in vertical projection, the center of the masking ring 21 coincides with the center of the source substrate 13, and the center of the masking ring 23 coincides with the center of the target substrate 17. The width of the peripheral annular zone of the layer 15 masked by the ring 21 is, for example, in the range from 0.2 mm to 5.1 mm, for example, from 0.3 mm to 3.1 mm, for example, approximately 0.5 mm. The width of the peripheral annular zone of the target substrate 17 masked by the ring 23 is, for example, in the range from 0.2 mm to 5.1 mm, for example, from 0.3 mm to 3.1 mm, for example, approximately 0.5 mm. For example, masking rings 21 and 23 are identical in the manufacturing dispersion.

[0049] The masking rings 21 and 23 are, for example, metallic and / or made of a semiconductor or insulating material. For example, during a step of activating the bonding surface by ion etching, the ring 21 is arranged on top of and in contact with the bonding surface of the semiconductor layer 15, and the ring 23 is arranged on top of and in contact with the bonding surface of the target substrate 17.

[0050] In the example shown, activation of the bonding surface of the layer 15 and activation of the bonding surface of the target substrate 17 are performed simultaneously. As a variant, activation of the bonding surface of the layer 15 and activation of the bonding surface of the target substrate 17 are performed consecutively without breaking the vacuum.

[0051] During the activation step, only the free parts of the bonding surfaces of the layer 15 to be transferred and the target substrate 17 (that is, the parts of the bonding surfaces of the layer 15 and the substrate 17 that are not covered by the masking rings 21 and 23) are activated. In particular, surface dangling bonds intended to subsequently form covalent bonds to bond the layer 15 to the target substrate 17 are formed only in the central parts of the bonding surfaces of the layer 15 and the target substrate 17 that are not covered by the masking rings 21 and 23. However, activation (in particular the formation of dangling bonds) does not occur in the peripheral parts of the bonding surfaces of the layer 15 and the target substrate 17 that are covered by the masking rings 21 and 23.

[0052] Figure 1C The structure 110 is shown at the end of the step of activating the bonding surfaces of the target substrate 17 and the layer 15 and the target substrate 17 after the removal of the masking rings 21 and 23 .

[0053] At this stage, the central portion 15' of the bonding surface of the layer 15 is activated, and the central portion 17' of the bonding surface of the target substrate 17 is activated. However, the peripheral portion 15" of the bonding surface of the layer 15 and the peripheral portion 17" of the bonding surface of the target substrate 17 remain unactivated and do not include dangling bonds that allow the formation of covalent bonds.

[0054] Figure 1D Shows the Figure 1C The structure 110 is bonded to Figure 1C During this step, the bonding surface of the layer 15 is placed in contact with the bonding surface of the target substrate 17.

[0055] When dangling bonds formed on activated portion 15 ′ of the bonding layer of layer 15 and dangling bonds formed on activated portion 17 ′ of the bonding surface of substrate 17 are placed in contact, they form covalent bonds ensuring bonding of layer 15 to substrate 17 .

[0056] For example, the bonding step is performed at a temperature ranging from 10° C. to 400° C., such as from 10° C. to 40° C., such as at room temperature.

[0057] Figure 1E The structure obtained at the end of the step of removing the source substrate 13 so as to leave only the layer 15 to be transferred on the bonding surface of the target substrate 17 is shown.

[0058] For example, the substrate 13 is made of the same semiconductor material as the layer 15 and is implanted with, for example, hydrogen ions (H + ) separates the layer 15 from the source substrate 13. For example, the structure 110 is initially a single crystalline semiconductor wafer, which is implanted with, for example, hydrogen ions from its upper surface to form a buried implant layer that separates the layer 15 to be transferred from the source substrate 13. For example, the removal of the source substrate 13 may include a step of thermal annealing, causing the structure 110 to break in the plane of the buried implant layer, so as to enable the removal of the source substrate 13 and leaving only the layer 15 on the target substrate 17.

[0059] More generally, removing the substrate 13 may be performed by any other known method for removing a source substrate during the transfer of a semiconductor layer from a source substrate to a target substrate, for example by grinding or by a laser lift-off method.

[0060] During the removal of the source substrate 13, only the central area of ​​the layer 15, which is located in front of the activated part 15' of the bonding surface, remains bonded to the active part 17' of the bonding surface of the target substrate 17. However, the non-activated peripheral part 17" of the bonding surface of the target substrate 17 remains free, that is to say not covered by the layer 15.

[0061] Therefore, in Figures 1A to 1E At the end of the method shown, the transferred layer 15 has the same Figure 1B The inner edge of the masking ring 21 installed during the activation step substantially corresponds to a sharp and regular edge.

[0062] The surface activation and bonding steps are performed without breaking the vacuum. For example, the surface activation step ( Figure 1B ) and bonding steps ( Figure 1D ) is performed in the same device, which includes, for example, Figure 1B Activation chamber and implementation of the activation step Figure 1D The bonding chamber for the bonding step.

[0063] In practice, during the bonding step ( Figure 1D ), it is desirable to align the structure so that the activated surface 15' of the layer 15 coincides with the activated surface 17' of the substrate 17. However, even if the alignment is not perfect, the solution provided enables sharp edges of the transferred layer to be obtained, since only the portions of the activated surfaces 15' and 17' that are placed in contact will adhere to each other.

[0064] It should be noted that Figure 1B In the example shown, the bonding surface of the layer 15 is activated by means of a masking ring 21 and the bonding surface of the target substrate 17 is activated by means of a masking ring 23. As a variant, the masking ring can be provided only on the bonding surface of the layer 15 or only on the bonding surface of the target substrate 17. In this case, during contacting of the bonding surfaces, bonding of the layer 15 to the semiconductor substrate 17 will not take place at the periphery of the assembly, since dangling bonds will be formed only on one of the two bonding surfaces. The advantage of this variant is that it requires less alignment accuracy.

[0065] Figure 2A , Figure 2B , Figure 2C , Figure 2D and Figure 2E is a cross-sectional view partially and schematically illustrating consecutive steps of an example of a method of transferring a semiconductor layer from a source substrate to a target substrate according to a second embodiment.

[0066] The second embodiment is similar to Figures 1A to 1E The first embodiment shown is different in that, in the second embodiment, the activation of the bonding surface is performed by depositing a thin layer of bonding material providing dangling bonds, which then enables the formation of covalent bonds during the process of placing the active surfaces in contact. Figures 1A to 1E Only the elements that are common to the methods of Figures 1A to 1E differences in methods.

[0067] Similar to Figure 1A , Figure 2AA structure 110 is shown on its left part, which includes a source substrate 13 and a semiconductor layer 15 to be transferred, and a target substrate 17 is shown on its right part.

[0068] Figure 2B The step of activating the upper surface of the layer 15 (referred to as the bonding surface) and the upper surface of the target substrate 17 (referred to as the bonding surface) is shown.

[0069] The activation step consists in depositing a thin activation layer on the surface to be activated. This enables the creation of dangling bonds which will be used to form covalent bonds in a subsequent step during the process of bringing the activation layer into contact. This bonding technique is known as atomic diffusion bonding or ADB.

[0070] For example, during this step, a beam of atoms or ions, for example of a neutral gas (for example argon), bombards a target 24 made of a material whose atoms 25 are separated and deposited uniformly in a thin layer on the surface to be activated. For example, the target is metallic, for example made of tungsten or of titanium. As a variant, the target 24 is made of a semiconductor material, for example made of silicon, germanium, etc.

[0071] This step is carried out under vacuum, that is to say at a pressure lower than atmospheric pressure, for example under ultra-high vacuum, for example at a pressure lower than 10 -7 mbar (e.g. below 10 -8 mbar).

[0072] Similar to what was described previously, during activation, the masking ring 21 covers the bonding surface of the layer 15 and the masking ring 23 covers the bonding surface of the target substrate 17 .

[0073] In the example shown, activation of the bonding surface of the layer 15 and activation of the bonding surface of the target substrate 17 are performed simultaneously. As a variant, activation of the bonding surface of the layer 15 and activation of the bonding surface of the target substrate 17 are performed consecutively without breaking the vacuum.

[0074] Similar to what has been described previously, during the activation step, only the free parts of the bonding surfaces of layer 15 and target substrate 17 (that is, the parts of the bonding surfaces of layer 15 and substrate 17 that are not covered by masking rings 21 and 23) are activated.

[0075] Figure 2C The structure 110 is shown at the end of the step of activating the bonding surfaces of the target substrate 17 and the layer 15 and the target substrate 17 after the removal of the masking rings 21 and 23 .

[0076] At this stage, the central part of the bonding surface of the layer 15 and the central part of the bonding surface of the target substrate 17 are activated, that is, the top is covered with a layer 27 made of the material of the target 24. For example, the layers 27 each have a thickness greater than 0.2 nm, for example less than 100 nm. For example, the thickness of the layer 27 is in the range from 1 nm to 20 nm.

[0077] In this example, the periphery 15 ″ of the bonding surface of layer 15 and the periphery 17 ″ of the bonding surface of the target substrate 17 are not activated, that is, they are not covered by layer 27 and therefore do not include dangling bonds allowing the creation of covalent bonds to bond layer 15 to substrate 17 .

[0078] Figure 2D Shows the Figure 2C The structure 110 is bonded to Figure 2C During this step, the bonding surface of the layer 15 is placed in contact with the bonding surface of the target substrate 17. More specifically, the layer 27 formed on the layer 15 and the layer 27 formed on the target substrate 17 are placed in contact.

[0079] The dangling bonds of layer 27 deposited on layer 15 and the dangling bonds of layer 27 deposited on substrate 17 create covalent bonds when they are placed in contact, ensuring that layer 15 is bonded to substrate 17 .

[0080] For example, the bonding step is performed at a temperature ranging from 10°C to 400°C, such as ranging from 10°C to 40°C, such as at room temperature.

[0081] For example, the interface resistivity between the layer 15 and the target substrate 17 is less than 10 -3 Ω.cm -2 , for example, less than 10 -5 Ω.cm -2 . This makes the bond electrically transparent.

[0082] Figure 2E Shown in Figure 2D The structure shown is the structure obtained at the end of the step of removing the source matrix 13 .

[0083] As previously described, during the removal of the source substrate 13, only the central area of ​​the layer 15 to be transferred, located in front of the activated part of the bonding surface, remains bonded to the target substrate 17. However, the peripheral part 17″ of the target substrate 17, located in front of the unactivated part of the bonding surface, remains free, that is, not covered by the layer 15.

[0084] Here, the bonding surface activation step ( Figure 2B ) and bonding steps ( Figure 2D) is carried out without breaking the vacuum, for example in the same apparatus, which for example includes an apparatus for implementing Figure 2B Activation chamber and implementation of the activation step Figure 2D The bonding chamber for the bonding step.

[0085] exist Figure 2B In the example shown, the bonding surface of the layer 15 is activated by means of a masking ring 21 and the bonding surface of the target substrate 17 is activated by means of a masking ring 23. As a variant, the masking ring may be provided only on the bonding surface of the layer 15 or only on the bonding surface of the target substrate 17. In this case, during the bringing into contact of the bonding surfaces, bonding of the layer 15 to the target substrate 17 will not take place at the periphery of the assembly, since dangling bonds will be formed only on one of the two bonding surfaces.

[0086] In practice, during the bonding step, it is desirable to align the structures in such a way that the activated surfaces of the two structures coincide. However, even if the alignment is not perfect, the solution provided enables sharp edges of the transferred layer to be obtained, since only the parts of the activated surfaces that are placed in contact will adhere to each other.

[0087] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E and Figure 3F is a cross-sectional view partially and schematically showing consecutive steps of an example of a method of transferring a semiconductor layer from a source substrate 13 to a target substrate 17 according to a third embodiment.

[0088] The third embodiment is similar to Figures 1A to 1E The first embodiment shown is different in that it includes a step of etching a step at the periphery of the target substrate 17 and the periphery of the layer 15 before the step of bonding the layer 15 to the substrate 17. Figures 1A to 1E Only the elements that are common to the methods of Figures 1A to 1E differences in methods.

[0089] Similar to Figure 1A , Figure 3A A structure 110 is shown on its left part, which includes a source substrate 13 and a semiconductor layer 15 to be transferred, and a target substrate 17 is shown on its right part.

[0090] Figure 3B The steps of etching a step 30 at the periphery of the upper surface of the target substrate 17 and etching a step 29 at the periphery of the upper surface of the layer 15 are shown.

[0091] The steps 29 and 30 are carried out by an etching or ion milling method, which comprises sending an ion beam 19 or an atom beam, such as a neutral beam, onto the area to be etched. This step is carried out under vacuum, that is to say under a pressure lower than atmospheric pressure, such as under an ultra-high vacuum, for example at a pressure lower than 10 -7 mbar (e.g. below 10 -8 mbar).

[0092] During the etching step, only the free parts of the upper surface of the layer 15 and of the target substrate 17 are etched, that is to say the parts of the upper surface of the target substrate 17 and of the layer 15 that are not covered by the mask.

[0093] exist Figure 3B In the example of , the central portions of the bonding surfaces are each covered with a masking disk in order to form the step 29 only at the periphery of the bonding surface of the layer 15 and the step 30 only at the periphery of the bonding surface of the target substrate 17. Thus, during the etching step, the masking disk 31 covers the central portion of the bonding surface of the layer 15 and the masking disk 33 covers the central portion of the bonding surface of the target substrate 17.

[0094] For example, in vertical projection, the center of the masking disk 31 coincides with the center of the source substrate 13, and the center of the masking disk 33 coincides with the center of the target substrate 17. For example, the diameter of the masking disk 31 is smaller than the diameter of the source substrate 13, and the diameter of the masking disk 33 is smaller than the diameter of the target substrate 17. The difference between the diameter of the source substrate 13 and the diameter of the masking disk 31 is, for example, in the range of 0.2 mm to 5 mm, such as in the range of 0.5 mm to 3 mm, such as approximately 1 mm. The difference between the diameter of the target substrate 17 and the diameter of the masking disk 33 is, for example, in the range of 0.2 mm to 5 mm, such as in the range of 0.5 mm to 3 mm, such as approximately 1 mm. For example, the masking disks 31 and 33 are identical in the manufacturing dispersion.

[0095] The masking plates 31 and 33 are, for example, metallic and / or made of a semiconductor or insulator material. For example, during the steps of etching steps 29 and 30, the masking plate 31 is arranged on top of the upper surface of the semiconductor layer 15 and is arranged in contact with the upper surface of the semiconductor, and the masking plate 33 is arranged on top of the upper surface of the target substrate 17 and is arranged in contact with the upper surface of the target substrate.

[0096] In the example shown, etching of the step 29 in the layer 15 and etching of the step 30 in the target substrate 17 are performed simultaneously. As a variant, etching of the step 29 in the layer 15 and etching of the step 30 in the target substrate 17 are performed consecutively.

[0097] For example, the depth of step 29 from the upper surface of layer 15 is greater than approximately 10 nm, such as greater than approximately 50 nm. For example, the depth of step 30 from the upper surface of substrate 17 is greater than approximately 10 nm, such as greater than approximately 50 nm. For example, due to the different properties of layer 15 and substrate 17, step 29 and step 30 do not have the same depth.

[0098] At the end of this step, the masking disks 31 and 33 are removed.

[0099] Figure 3C The step of activating the bonding surfaces of the target substrate 17 and the layer 15 is shown.

[0100] The method implemented during this step is an etching or ion milling method similar to the method implemented during the formation of steps 29 and 30. However, the etching energy and / or etching time are lower than the etching energy and / or etching time implemented during the formation of steps 29 and 30, so as to activate the exposed surface without etching the significant thickness of layer 15 and substrate 17. During this step, the ion beam 19 or atomic beam (e.g., neutral beam) sent to the surface to be activated makes it possible to remove possible oxides present at the surface of the surface to be activated, while leaving dangling bonds, which will be used to form covalent bonds in the process of placing the activated surface in contact in the subsequent steps. For example, during this step, the material removed from the surface to be activated is less than a few nanometers, for example, less than 5nm. In any case, the thickness of the material removed during this activation step is less than the thickness removed during the formation of steps 29 and 30.

[0101] For example, relative to Figure 3B The steps shown in Figure 3C During the steps shown, the surface exposure time is, for example, reduced and / or the power of the ion beam 19 is, for example, lowered.

[0102] Similar to the previous Figure 1B As depicted, during activation, masking ring 21 covers the bonding surface of layer 15 and masking ring 23 covers the bonding surface of target substrate 17 .

[0103] In the example shown, activation of the bonding surface of layer 15 and activation of the bonding matrix of target layer 17 are performed simultaneously. Activation of the bonding surface of layer 15 and activation of the bonding surface of target layer 17 are performed consecutively without breaking the vacuum.

[0104] Analogously to what has been described previously, during the activation step only the free parts of the bonding surfaces of layer 15 and target substrate 17 are activated, that is to say the parts of the bonding surfaces of layer 15 and substrate 17 which are not covered by the masking ring 21 .

[0105] For example, the inner diameter of masking disk 21 is greater than or equal to the diameter of disk 31. Similarly, the inner diameter of masking disk 23 is greater than or equal to the diameter of disk 33. Thus, layer 15 comprises a free portion in step 29, and substrate 17 comprises a free portion in step 30. These free portions in steps 29 and 30 are then activated during this step.

[0106] For example, the step of etching steps 29 and 30 ( Figure 3B ) and a step of activating the bonding surface by masking the ring ( Figure 3C ) for a few minutes, for example at least fifteen minutes, to reduce Figure 3B The waiting period can be implemented between the two steps without breaking the vacuum. As a variant, the waiting period can be replaced by a period in which the chamber or a part of the chamber is put back, for example using a loading port, for example at a higher pressure, for example at atmospheric pressure, for example in an atmosphere containing a reactive gas such as nitrogen or oxygen. Here again, this makes it possible to reduce the activation of the etched ring, that is to say to neutralize the dangling bonds on the surface of the etched ring.

[0107] Figure 3D The structure 110 is shown at the end of the step of activating the target substrate 17 and the upper surface of the layer 15 , and the target substrate 17 after the removal of the masking rings 21 and 23 .

[0108] At this stage, a central portion 15' of the bonding surface of the layer 15 extending further in the step 29 and a central portion 17' of the bonding surface of the target substrate 17 extending further in the step 30 are activated. However, a peripheral portion 15" of the bonding surface of the layer 15 and a peripheral portion 17" of the bonding surface of the target substrate 17 remain inactive and do not include dangling bonds allowing the formation of covalent bonds. For example, the peripheral portions 15" and 17" are located in the steps 29 and 30, respectively. For example, the peripheral portion 15" extends over a width that is smaller than the width of the step 29, and similarly, the peripheral portion 17" extends over a width that is, for example, smaller than the width of the step 30.

[0109] Figure 3E The step of bonding the structure 110 to the target substrate 17 is shown. During this step, the bonding surface of the layer 15 is placed in contact with the bonding surface of the target substrate 17. Figure 1D The bonding steps shown are different, in Figure 3E In this embodiment, only the central region of the bonding surface of the layer 15 delimited by the step 29 is placed in contact with the central region of the bonding surface of the substrate 17 delimited by the step 30 .

[0110] When dangling bonds formed on activated portion 15 ′ of the bonding surface of layer 15 and dangling bonds formed on activated portion 17 ′ of the bonding surface of substrate 17 are placed in contact, they form covalent bonds, ensuring that layer 15 is bonded to substrate 17 .

[0111] For example, the bonding step is performed at a temperature ranging from 10° C. to 400° C., such as from 10° C. to 40° C., such as at ambient temperature.

[0112] Figure 3F Shown in Figure 3E The structure shown is the structure obtained at the end of the step of removing the source matrix 13 .

[0113] During the removal of the source substrate 13, only the central area of ​​the layer 15 to be transferred, located in front of the activated part of the bonding surface and outside the steps 29 and 31, remains bonded to the target substrate 17. However, the peripheral part of the target substrate 17, located in front of the steps 29 and 30, remains free, that is, not covered by the layer 15.

[0114] Here, the activation step of the bonding surface ( Figure 3C ) and bonding steps ( Figure 3E ) is carried out without breaking the vacuum, for example in the same apparatus, which for example includes an apparatus for implementing Figure 3B The etching steps and Figure 3C The activation chamber and the activation step of the activation are implemented Figure 3E The bonding chamber for the bonding step.

[0115] exist Figure 3B In the example shown, etching of the layer 15 is performed through the masking disk 31 to form the step 29 in the layer 15, and etching of the target substrate 17 is performed through the masking disk 33 to form the step 30 in the target substrate 17. As a variant, the masking disk may be provided only on the layer 15 or only on the target substrate 17 to form a step on a single bonding surface of the two bonding surfaces.

[0116] In addition, Figure 3C In the example shown, the bonding surface of the layer 15 is activated by means of a masking ring 21 and the bonding surface of the target substrate 17 is activated by means of a masking ring 23. As a variant, the masking ring may be provided only on the bonding surface of the layer 15 or only on the bonding surface of the target substrate 17. In this case, during the bringing into contact of the bonding surfaces, bonding of the layer 15 to the target substrate 17 will not take place at the periphery of the assembly, since dangling bonds will be formed only on one of the two bonding surfaces.

[0117] FIG. 3A to FIG. 3FThe advantage of the method is that the etching of the steps 29 and / or 30 makes it possible to improve the sharpness of the boundary between the bonded central area and the non-bonded peripheral area of ​​the layer 15. However, due to the definition of the bonding surface by the masking rings 21 and / or 23, the steps 29 and / or 30 may be relatively shallow, for example, less than 500 nm in depth, and preferably less than 100 nm in depth.

[0118] We will now describe FIG. 2A to FIG. 2E A more detailed example of an embodiment of the method of is provided. In this example, it is provided that a single crystalline layer of 4H-SiC of a 4H-SiC source substrate is transferred to a target substrate corresponding to a multicrystalline silicon 3C-SiC wafer. In this example, a buried layer is implanted in the 4H-SiC wafer with hydrogen ions, the buried layer defining the layer to be transferred to the target substrate. For example, the implantation step is performed at approximately 5.10 16 at / cm 2 The implantation step is carried out with a dose of about 95 keV and an energy of about 95 keV. Still in this example, after the implantation step, the 4H-SiC wafer and the 3C-SiC wafer are subjected to a cleaning step, which allows the surface contamination to be removed. After the cleaning step, the two wafers are introduced into the deposition chamber of the ADB device, in which they each see their upper surface coated with a silicon film deposited through an annular mask that masks its peripheral portion across a width of about 1 mm. In this example, the annular mask is made of molten silicon dioxide. This step is carried out at ambient temperature at a temperature corresponding to about 10 -6 Pa (i.e. 10 -8 mbar) pressure. At the end of this step, the upper surface of each of the two 4H-SiC and 3C-SiC wafers is covered with a silicon film having a thickness greater than 1nm and less than 20nm, spanning its entire upper surface, excluding a ring having a width of approximately 1mm at the edge of the wafer. Without breaking the vacuum, and in another bonding chamber, the two wafers are bonded by noting that the silicon film formed on each of the two 4H-SiC and 3C-SiC wafers is contacted. Then, the bonded assembly is heat treated to cause a break at the level of the buried layer in the 4H-SiC wafer between the layer to be transferred and the source substrate, and thus remove the source substrate. For example, the heat treatment is performed at approximately 900°C for approximately 30 minutes. Before the structure formed by the target substrate and the layer to be transferred is subjected to a new annealing of approximately 1700°C for approximately 30 minutes, a polishing and / or cleaning step can be provided.

[0119] We will now describe FIG. 3A to FIG. 3F A more detailed example of an embodiment of the method of is provided. In this example, it is provided that a germanium film is transferred from a source substrate corresponding to a germanium wafer to a target substrate corresponding to a silicon wafer. In this example, a buried layer is implanted in the germanium wafer with hydrogen ions, the buried layer defining the layer to be transferred to the target substrate. The implantation step is performed at approximately 5.5.1016 at / cm 2 In this example, after the implantation step, the silicon wafer and the germanium wafer are placed in an ultra-high vacuum (i.e., less than 10 -7 mbar) are introduced into the activation chamber of the SAB equipment, in which their upper surfaces are etched by a disk made of silicon with a diameter smaller than the wafer diameter by approximately 3mm. Etching is performed while the wafer is rotating (for example, at a speed of approximately 70rpm). Etching is performed for approximately 10 minutes under an argon flow with an energy of approximately 200eV and an intensity of approximately 150mA. At the end of the etching step, the two wafers enter the loading port, where the pressure rises to 500mbar due to the nitrogen flow, and then falls back under ultra-high vacuum due to the purging of an argon flow of 500mbar. Then, the wafer returns to the activation chamber under ultra-high vacuum. Then, argon atoms with an energy of approximately 200eV and an intensity of approximately 150mA are used to mask the peripheral portion of the upper surfaces of the two wafers across a width of approximately 2.5mm through an annular mask made of silicon, and the upper surfaces of the two wafers are activated for one minute each. Without breaking the vacuum, and in another bonding chamber, the two wafers are bonded by taking care to place the activated surface of each of the two germanium and silicon wafers in contact. The bonding step is carried out at a temperature of approximately 250°C under ultra-high vacuum. The bonded assembly is then subjected to a heat treatment to cause a break in the germanium wafer at the level of the buried layer between the layer to be transferred and the source matrix, and thus remove the source matrix. For example, the heat treatment is performed at approximately 330°C for approximately 10 hours. In this example, a germanium film of approximately 800nm ​​is transferred to silicon.

[0120] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and those skilled in the art will appreciate other variations. In particular, the described embodiments are not limited to the examples of materials and dimensions mentioned in this disclosure.

[0121] also, FIG. 2A to FIG. 2E and FIG. 3A to FIG. 3F The embodiments of can be combined. More specifically, in Figure 3C During the steps shown, the activation of the surface can be based on Figure 2B The activation method described was performed.

[0122] Furthermore, the embodiments have been described with respect to circular source and target substrates, but they may have different shapes.

[0123] Furthermore, although the provided methods are advantageous for transferring semiconductor layers from a source substrate to a target substrate, they can also be implemented to transfer layers of a different nature, such as metal layers or dielectric layers, from a source substrate to a target substrate.

[0124] Furthermore, in the described embodiments, the masking ring may be replaced by a frame or an oval ring. Furthermore, the edge of the masking ring may be corrugated rather than having a rounded shape.

[0125] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art.

Claims

1. A method for transferring a layer (15) from a source substrate (13) to a target substrate (17), comprising the following steps: a) activating the bonding surface of the layer (15) and the bonding surface of the target substrate (17) by ion etching of the bonding surface of the layer (15) and the bonding surface of the target substrate (17) or by sputtering a bonding material (27) onto the surfaces; and b) after step a), placing the bonding surface of the layer (15) in contact with the bonding surface of the target substrate (17), wherein during step a), a masking ring (21) covers a peripheral portion (15") of the bonding surface of the layer (15), and / or a masking ring (23) covers a peripheral portion (17") of the bonding surface of the target substrate (17); and Wherein, steps a) and b) are performed under vacuum, and the vacuum is not broken between the two steps.

2. The method according to claim 1, wherein: The target substrate (17) and / or the source substrate (13) has a tapered edge spanning a first width.

3. The method according to claim 2, wherein: The width of the masking ring is greater than or equal to the first width.

4. Method according to any one of claims 1 to 3, comprising a step c) of removing the source matrix (13) after step b).

5. The method according to claim 4, wherein: Step c) comprises an annealing step which causes the assembly obtained in step b) to break in the plane of the implanted buried layer separating said layer (15) from said source matrix (13).

6. The method according to any one of claims 1 to 5, wherein: The layer (15) is a semiconductor layer.

7. Method according to claim 6 as appended to claim 4, comprising, after step c), a step of epitaxy on top of and in contact with the surface of the layer (15) opposite to the target substrate (17).

8. The method according to any one of claims 1 to 7, comprising the step of forming steps (29, 30) at the periphery of the layer (15) and / or at the periphery of the target substrate (17) before step a).

9. The method according to claim 8, wherein: The steps (29, 30) are formed by ion etching, with the central portion of the bonding surface being protected by means of a masking disk.

10. The method according to claim 9, wherein: The ion etching for forming the steps (29, 30) is carried out in the same apparatus as that used in step a) for activating the bonding surface.

11. Method according to claim 10, comprising a waiting period of at least 10 minutes and / or a period of applying a reactive gas between forming the step (29, 30) and activating the bonding surface.

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