Integrated circuit layout of process monitor and chip including process monitor

Abstract

The present disclosure relates to an integrated circuit layout of a process monitor, including: a signal line; the oscillator module comprises at least one group of oscillator units, each group of oscillator units comprises a first oscillator and a second oscillator which have the same circuit structure, and the first oscillator and the second oscillator are in mirror symmetry relative to a center line between the positions of the first oscillator and the second oscillator in the integrated circuit layout; and the logic module is coupled to the oscillator module through a signal line and enables the first oscillator and disables the second oscillator in a chip aging test mode so as to determine the aging degree of the chip. At least one group of oscillators are arranged in a mirror symmetry manner, so that the circuit matching degree is improved, the performance difference is reduced, circuit parameters are balanced, a stable direct current working point is maintained, and the accuracy of a chip aging test is improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit design, and more particularly, to an integrated circuit layout of a process monitor, a chip, and a method for the integrated circuit layout of the process monitor. Background Art

[0002] Process detectors (PDs) play an important role in system-on-chip (SoC) and integrated circuits (IC). First, PDs can monitor process parameters in real time to ensure that they are within the predetermined safety and performance range, which is essential for maintaining chip stability and reliability. Second, PDs can trigger protection mechanisms to prevent damage or failure by detecting potential abnormal conditions (such as overheating or overvoltage), thereby improving the safety of the entire system. Third, PDs help optimize energy use, reduce power consumption and extend the life of equipment by monitoring and adjusting power supply. Fourth, in SoC design, PDs can be integrated with other functional modules (such as CPU, GPU, memory, etc.) to form a highly integrated system for more efficient data processing and system management. Fifth, PDs can be used for fault analysis and diagnosis. By detecting abnormal signals, they help engineers quickly locate the source of the problem and accelerate the repair and maintenance process. Sixth, in applications such as high-performance computing and graphics processing, PDs can monitor key parameters to ensure that the system operates in the best condition and improve overall performance.

[0003] However, traditional process monitors do not have the function of chip aging testing, so they cannot effectively test the degree of chip aging when the chip continues to work under extreme conditions, nor is it easy to determine the service life of the circuit in the chip. Summary of the invention

[0004] In response to the above technical problems, the solution of the present disclosure improves the matching degree of the oscillator circuit, reduces the performance differences caused by process deviations or design non-uniformities, helps balance parameters such as parasitic capacitance and parasitic inductance, maintains a stable DC operating point, and thus improves the accuracy of the process monitor in performing chip aging tests by arranging at least one group of oscillators in a mirror-symmetrical manner in the integrated circuit layout of the process monitor for chip aging test comparison. Due to the mirror-symmetrical design, the device parameter mismatch caused by process changes is reduced, and it also helps to reduce the non-uniformity in the signal path, thereby improving signal integrity and simplifying design and debugging. In addition, this layout helps to distribute heat more evenly, so that the power distribution and heat flow path are more balanced in the symmetrical structure, and the heat dissipation efficiency is improved.

[0005] To this end, according to a first aspect of the present disclosure, an integrated circuit layout of a process monitor is provided, wherein the process monitor is used for aging testing of a chip, and the integrated circuit layout comprises: a signal line; an oscillator module, which comprises at least one group of oscillator units, each group of oscillator units comprises a first oscillator and a corresponding second oscillator having the same circuit structure, and at least one of the first oscillator and the corresponding second oscillator are mirror-symmetric relative to a center line between their positions in the integrated circuit layout; and a logic module, which is coupled to the oscillator module via the signal line and is configured to enable the first oscillator and disable the second oscillator in a chip aging test mode, thereby determining the degree of chip aging.

[0006] According to the above technical concept, the embodiments of the present disclosure may further include any one or more of the following optional forms.

[0007] In some embodiments, the logic module includes at least one group of mode control units corresponding to the at least one group of oscillator units respectively, each group of mode control units includes an OR logic unit coupled to the first oscillator and an AND logic unit coupled to the second oscillator, wherein positions of the OR logic unit and the AND logic unit in the integrated circuit layout are symmetrical relative to the center line.

[0008] In some embodiments, the OR logic unit is coupled to the first oscillator at a side of the first oscillator close to the center line, and the AND logic unit is coupled to the second oscillator at a side of the second oscillator close to the center line.

[0009] In some embodiments, at least one group of oscillator units includes a plurality of groups of oscillator units, and the plurality of groups of oscillator units are arranged sequentially along the direction of the center line in the integrated circuit layout.

[0010] In some embodiments, two oscillators in the same group of oscillator units include semiconductor devices of the same type and process, and multiple oscillators in different groups of oscillator units include semiconductor devices of different types and processes.

[0011] In some embodiments, the integrated circuit layout further includes: a power line and a ground line; a power supply module, which is coupled to the oscillator module and the logic module via the power line and the ground line, and is configured to power the oscillator module and the logic module via an external power supply.

[0012] In some embodiments, the power supply module includes a first power supply submodule and a second power supply submodule, the first power supply submodule is configured to power at least the first oscillator via the external power supply, and the second power supply submodule is configured to power at least the second oscillator via the external power supply, wherein the first power supply submodule and the second power supply submodule have the same layout structure and are mirror-symmetric relative to the center line in the integrated circuit layout.

[0013] In some embodiments, the first power supply submodule is located on a side of the first oscillator away from the center line in the integrated circuit layout, and the second power supply submodule is located on a side of the second oscillator away from the center line in the integrated circuit layout.

[0014] In some embodiments, the power lines and the ground lines are at least partially arranged in a grid pattern in the integrated circuit layout.

[0015] In some embodiments, the integrated circuit layout further includes: a buffer module, which is coupled to the oscillator module via the signal line and is configured to buffer the clock signal output by the oscillator module, the buffer module includes at least one group of buffer units corresponding to the at least one group of oscillator units respectively, each group of buffer units includes a first buffer coupled to the first oscillator and a second buffer coupled to the second oscillator, wherein the first buffer and the second buffer have the same structure and are mirror-symmetric relative to the center line in the integrated circuit layout.

[0016] In some embodiments, the first buffer is located on a side of the first oscillator close to the center line in the integrated circuit layout, and the second buffer is located on a side of the second oscillator close to the center line in the integrated circuit layout.

[0017] In some embodiments, the integrated circuit layout further includes: a divider module, which is coupled to the oscillator module via the signal line and is configured to perform frequency division processing on the clock signal output by the oscillator module, and the coverage area of ​​the divider module in the integrated circuit layout intersects with the extension line of the center line.

[0018] In some embodiments, the integrated circuit layout further includes: a decoder module, which is coupled to the logic circuit via the signal line and is configured to output a selection signal; a multiplexer module, which is coupled to the decoder module and the oscillator module via the signal line; and a counter module, which is coupled to the multiplexer module via the signal line; wherein, in the chip aging test mode, the oscillator module outputs at least one clock signal to the multiplexer module, and the multiplexer module outputs one of the at least one clock signal to the counter module according to the selection signal, and the counter module counts one of the at least one clock signal to output a counting result corresponding to the chip aging degree.

[0019] According to a second aspect of the present disclosure, a chip is provided, comprising: a process monitor used for aging test of the chip, wherein the process monitor has an integrated circuit layout according to any one embodiment of the first aspect.

[0020] According to a third aspect of the present disclosure, a method for integrated circuit layout for a process monitor is provided, comprising: arranging an oscillator module in the integrated circuit layout, the oscillator module comprising at least one group of oscillator units, each group of oscillator units comprising a first oscillator and a second oscillator having the same circuit structure, wherein the first oscillator and the second oscillator are arranged in the integrated circuit layout to be mirror-symmetrical relative to a center line between their positions; and arranging a logic module in the integrated circuit layout and coupling it to the oscillator module via a signal line, the logic module being configured to enable the first oscillator and disable the second oscillator in a chip aging test mode to determine the degree of chip aging.

[0021] The integrated circuit layout, chip and integrated circuit layout method for a process monitor provided by the present disclosure improve the matching degree of the oscillator circuit by arranging at least one group of oscillators for chip aging test comparison in a mirror-symmetrical manner in the integrated circuit layout of the process monitor, reduce the performance difference caused by process deviation or design non-uniformity, help balance parameters such as parasitic capacitance and parasitic inductance, maintain a stable DC operating point, and thus improve the accuracy of the process monitor in performing chip aging tests. Due to the mirror-symmetrical design, the device parameter mismatch caused by process changes is reduced, and it also helps to reduce the non-uniformity in the signal path, thereby improving signal integrity and simplifying design and debugging. In addition, this layout helps to distribute heat more evenly, so that the power distribution and heat flow path are more balanced in the symmetrical structure, and the heat dissipation efficiency is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The features, advantages and other aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings, in which several embodiments of the present disclosure are shown in an exemplary and non-limiting manner. In the accompanying drawings: Figure 1 An integrated circuit layout of a process monitor according to an embodiment of the present disclosure is shown; Figure 2 Another integrated circuit layout of a process monitor according to an embodiment of the present disclosure is shown; Figure 3 Another integrated circuit layout of a process monitor according to an embodiment of the present disclosure is shown; Figure 4 A flow chart of a method for integrated circuit layout for a process monitor according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0023] The various exemplary embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. Although the exemplary methods and devices described below include software and / or firmware executed on hardware among other components, it should be noted that these examples are merely illustrative and should not be considered restrictive. For example, it is considered that any or all hardware, software, and firmware components can be implemented exclusively in hardware, exclusively in software, or in any combination of hardware and software. Therefore, although exemplary methods and devices have been described below, it should be readily understood by those skilled in the art that the examples provided are not intended to limit the manner in which these methods and devices are implemented.

[0024] In addition, the flowcharts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the methods and systems according to the various embodiments of the present disclosure. It should be noted that the functions marked in the boxes may also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession may actually be executed substantially in parallel, or they may sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the flowchart and / or block diagram, and the combination of boxes in the flowchart and / or block diagram, may be implemented using a dedicated hardware-based system that performs a specified function or operation, or may be implemented using a combination of dedicated hardware and computer instructions.

[0025] The terms "including", "comprising" and similar terms used in this disclosure are open terms, i.e., "including / including but not limited to", indicating that other contents may also be included. The term "based on" means "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one other embodiment", etc.

[0026] In the present disclosure, the terms "first", "second", etc. are not used to limit the order of precedence and the number of components, unless otherwise specified.

[0027] In the present disclosure, terms such as "upper", "lower", "front", "back", "left", "right", etc., indicating directions or positional relationships are merely for the convenience and simplification of description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operate in a specific direction, and therefore should not be understood as a limitation on the present disclosure.

[0028] In the present disclosure, the term "connection" or "coupling" and similar terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "A", "a group" or "an" and similar words do not indicate a quantity limitation, but indicate the presence of at least one.

[0029] In this disclosure, the term "mirror symmetry" means that two circuits or modules are mirror images about a center line between them in an integrated circuit layout, that is, one side is a reflection of the other side. When two circuits or modules are mirror symmetric, they have the same structure and are reflections of each other, and are equidistant from the center line between them.

[0030] In the present disclosure, the term "layout" refers to the physical information of the hardware units in the circuit and the semiconductor devices included therein on the chip, including but not limited to the device type, device size, relative position and connection relationship between devices, etc. The integrated circuit layout includes not only the layout structure of the chip during the design process, but also the actual physical structure of the chip after manufacturing.

[0031] In this disclosure, the term "aging" refers to the performance degradation of a semiconductor device or an entire circuit over time. This degradation is usually caused by a variety of physical and chemical processes that change the electrical characteristics of the circuit.

[0032] As mentioned above, the process monitor in the prior art does not have the function of chip aging test, so it is impossible to effectively test the degree of chip aging when the chip continues to work under extreme conditions, and it is not easy to judge the service life of the circuit in the chip. In response to such technical status and corresponding technical problems, the solution of the present disclosure improves the matching degree of the oscillator circuit by arranging at least one group of oscillators in a mirror-symmetrical manner in the integrated circuit layout of the process monitor for chip aging test comparison, reduces the performance difference caused by process deviation or design non-uniformity, helps to balance parameters such as parasitic capacitance and parasitic inductance, maintains a stable DC operating point, and thus improves the accuracy of the process monitor in chip aging testing. In addition, this layout helps to distribute heat more evenly, so that the power distribution and heat flow path are more balanced in the symmetrical structure, and the heat dissipation efficiency is improved.

[0033] The technical solution according to the present disclosure is described in detail below according to several embodiments. First, several integrated circuit layouts of the process monitor according to the embodiments of the present disclosure are introduced. The specific working principle of the process monitor can refer to the patent previously authorized by the applicant with the authorization announcement number CN117805594B. The entire content of the patent is incorporated herein by reference.

[0034] First reference Figure 1 , Figure 1 An integrated circuit layout of a process monitor according to an embodiment of the present disclosure is shown.

[0035] exist Figure 1 In the embodiment, the integrated circuit layout 100 of the process monitor includes an oscillator module 10, a logic module 11 and a signal line 12. The oscillator module 10 includes at least one group of oscillator units, each group of oscillator units includes a first oscillator 101 and a corresponding second oscillator 102 having the same circuit structure. The first oscillator 101 and the second oscillator 102 are mirror-symmetric relative to the center line A-A' between their positions in the integrated circuit layout 100. That is, the first oscillator 101 and the second oscillator 102 are reflections of each other relative to the center line A-A'. Not only do they have the same structure, but the routing, line length, line width, and distance relative to the center line A-A' in the integrated circuit layout 100 are also the same. The logic module 11 is coupled to the oscillator module 10 via the signal line 12. In the chip aging test mode, the logic module 11 outputs a control signal to enable the first oscillator 101 and disable the second oscillator 102, so that the first oscillator 101 continues to oscillate and outputs a clock signal, and the second oscillator 102 does not oscillate. After the test is completed, the oscillation frequency of the first oscillator 101 is compared with the oscillation frequency of the second oscillator 102 , so that the aging degree of the chip can be specifically quantified.

[0036] Despite Figure 1Only the integrated circuit layout 100 of the process monitor is shown to include several modules, but those skilled in the art will understand that this is only for the convenience of illustration, and the integrated circuit layout 100 may also include other modules and / or semiconductor devices to implement other functions of the process monitor.

[0037] In addition, despite the Figure 1 Only one group of oscillator units is shown in the figure, but those skilled in the art will appreciate that the oscillator module 10 may include more than one group of oscillator units and / or may also include one or more separate oscillators for implementing other functions of the process monitor.

[0038] In addition, despite the Figure 1 It is shown that the first oscillator 101 and the second oscillator 102 are arranged in the horizontal direction, and the center line A-A' between their positions is located in the vertical direction, but those skilled in the art can understand that the first oscillator 101 and the second oscillator 102 can also be arranged in the vertical direction, and the center line A-A' between their positions can be located in the horizontal direction.

[0039] In addition, despite the Figure 1 It is shown in FIG. 1 that the logic module 11 is located above the first oscillator 101 , but those skilled in the art will appreciate that this is only an example, and the logic module 11 may be located at other locations in the integrated circuit layout 100 of the process monitor.

[0040] In the above embodiment, since the first oscillator 101 and the second oscillator 102 in the same group of oscillator units are mirror-symmetrical with respect to the center line A-A', their parameters such as parasitic capacitance and parasitic inductance tend to have similar values ​​and distributions, thereby reducing the negative impact on circuit performance, balancing various DC effects in the circuit, and maintaining a stable DC working flow. Due to the mirror-symmetrical design, the device parameter mismatch caused by process changes is reduced, and it is also helpful to reduce the non-uniformity in the signal path, thereby improving signal integrity and simplifying design and debugging. In addition, in the mirror-symmetrical integrated circuit layout, the power distribution and heat flow path are more balanced, which helps to improve the heat dissipation efficiency.

[0041] In some embodiments, the oscillator module 10 includes a plurality of groups of oscillator units, each group of oscillator units being arranged in sequence along the direction of the center line AA' in the integrated circuit layout 100. In each group of oscillator units, the first oscillator 101 and the second oscillator 102 are mirror-symmetric with respect to the center line AA'. For example, if the center line AA' is Figure 1As shown in the vertical direction, the plurality of first oscillators 101 are arranged on the left side of the center line AA', and the corresponding plurality of second oscillators 102 are arranged on the right side of the center line AA'. The logic module 11 can output a plurality of control signals to independently control each oscillator, so as to start at least one of the plurality of first oscillators 101 and disable at least one of the plurality of second oscillators 102 in the chip aging test mode. In these embodiments, the aging test can be selectively performed on semiconductor devices with different processes and / or types according to specific needs, and the accuracy of the aging test can be improved due to the mirror-symmetric design.

[0042] In some embodiments, the oscillator module 10 includes a plurality of groups of oscillator units, and some groups, but not all, of the oscillator units are arranged in sequence along the direction of the center line A-A' in the integrated circuit layout 100. In the plurality of groups of oscillator units, the first oscillator 101 and the second oscillator 102 are mirror-symmetrical with respect to the center line A-A', while other groups of oscillator units are arranged in other ways. The logic module 11 can output a plurality of control signals to independently control each oscillator, so as to start at least one of the plurality of first oscillators 101 and disable at least one of the plurality of second oscillators 102 in the chip aging test mode. In these embodiments, the aging test can be selectively performed on semiconductor devices with different processes and / or types according to specific needs, and the accuracy of the aging test can be improved due to the mirror-symmetrical design.

[0043] In some embodiments, the oscillator module 10 includes a plurality of groups of oscillator units, each group of oscillator units includes two oscillators. The oscillator module 10 may include oscillators. Two oscillators in the same group of oscillator units include semiconductor devices of the same type and process, while multiple oscillators in different groups of oscillator units include semiconductor devices of different types and processes. That is to say, for the same group of oscillator units, in order to compare the oscillation frequency after the chip aging test, the circuit structure, type and process of the semiconductor device of the two oscillators are the same. On the other hand, in order to perform an aging test on a chip including semiconductor devices of different types and processes, different groups of oscillator units can include semiconductor devices of different types and processes. For example, the oscillator module 10 may include nine groups of oscillator units, each of which includes two oscillators. The first to third groups of oscillator units adopt an 8nm process, the first group of oscillator units include SVT type transistors, the second group of oscillator units include LVT type transistors, and the third group of oscillator units include ULVT type transistors; the fourth to sixth groups of oscillator units adopt an 11nm process, the fourth group of oscillator units include SVT type transistors, the fifth group of oscillator units include LVT type transistors, and the sixth group of oscillator units include ULVT type transistors; the seventh to ninth groups of oscillator units adopt an 8nm process, the seventh group of oscillator units include SVT type transistors, the eighth group of oscillator units include LVT type transistors, and the ninth group of oscillator units include ULVT type transistors. The oscillators in the first to sixth groups of oscillator units have the same circuit structure, and the oscillators in the seventh to ninth groups of oscillator units have the same circuit structure, but the circuit structure is different from that of the oscillators in the first to sixth groups of oscillator units.

[0044] In some embodiments, the integrated circuit layout 100 further includes a power line, a ground line, and a power supply module. The power supply module is coupled to the oscillator module 10 and the logic module 11 via the power line and the ground line, and supplies power to the oscillator module 10 and the logic module 11 via an external power supply. The power supply module can be located at any position near the oscillator module 10 and the logic module 11 in the integrated circuit layout 100, for example, on the left side of the oscillator module 10.

[0045] In some embodiments, the power supply module includes a first power supply submodule and a second power supply submodule. The first power supply submodule is located on the side of the first oscillator 101 away from the center line A-A' in the integrated circuit layout 100, and at least the first oscillator 101 is powered via an external power supply. The second power supply submodule is located on the side of the second oscillator 102 away from the center line A-A' in the integrated circuit layout 100, and at least the second oscillator 102 is powered via an external power supply. The first power supply submodule and the second power supply submodule have the same layout structure and are mirror-symmetrical with respect to the center line A-A' in the integrated circuit layout 100. That is, the first power supply submodule and the second power supply submodule are reflections of each other with respect to the center line A-A'. In these embodiments, in addition to the oscillator unit, the power supply module is also arranged in a mirror-symmetrical manner, which further improves the accuracy of the aging test.

[0046] Figure 2 Another integrated circuit layout of a process monitor according to an embodiment of the present disclosure is shown.

[0047] In the present embodiment, the oscillator module 20 includes three groups of oscillator units, each group of oscillator units includes a first oscillator and a second oscillator arranged in mirror symmetry with respect to the center line A-A', for example, the first oscillator 201a and the second oscillator 202a are mirror symmetric with respect to the center line A-A', the first oscillator 201b and the second oscillator 202b are mirror symmetric with respect to the center line A-A', and the first oscillator 201c and the second oscillator 202c are mirror symmetric with respect to the center line A-A'. The first oscillator and the second oscillator in each group of oscillator units may include semiconductor devices of the same type and process, and the first oscillator and the second oscillator in different groups of oscillator units may include semiconductor devices of different types and processes. The logic module 21 is coupled to each oscillator via a signal line 23, respectively.

[0048] In addition, in the present embodiment, the integrated circuit layout 200 of the process monitor further includes a decoder module 26, a multiplexer module 27 and a counter module 28. The power supply module 22 supplies power to the oscillator module 20, the logic module 21, the decoder module 26, the multiplexer module 27 and the counter module 28 via the power line 24 and the ground line 25. The decoder module 26 is coupled to the logic module 21 via the signal line 23. The multiplexer module 27 is coupled to the decoder module 26 and the oscillator module 20 via the signal line 23. The counter module 28 is coupled to the multiplexer module 27 via the signal line 23.

[0049] In this embodiment, the decoder module 26 may receive a decoder enable signal and a register signal. The register signal is a binary input signal externally provided to the process monitor for controlling the selection of the oscillator. The decoder module 26 generates a selection signal according to the received register signal and provides it to the logic module 21 and the multiplexer module 27. The selection signal may have data of bits equal to the number of oscillators for selecting the corresponding oscillator. The logic module 21 generates a control signal according to the selection signal and the aging test enable signal to control the corresponding oscillator. For example, in the chip aging test mode, the control signal generated by the logic module 21 may enable at least one of the first oscillators 201a-201c to output at least one clock signal to the multiplexer module 27, and disable the second oscillators 202a-202c. In the process monitoring mode, the control signal generated by the logic module 21 may enable at least one of the second oscillators 202a-202c to output at least one clock signal to the multiplexer module 27, and disable the first oscillator 201a-201c. The multiplexer module 27 selects one of the at least one clock signal according to the selection signal and outputs it to the counter module 28. Specifically, the multiplexer module includes a plurality of switch units corresponding to the plurality of oscillators respectively, and controls the corresponding switch units to be turned on or off according to the selection signal to output the corresponding clock signal. The counter module 28 counts one of the at least one clock signal and outputs a counting result corresponding to the degree of chip aging. For example, in the chip aging test mode, the logic module 21 enables the first oscillator 201a-201c and disables the second oscillator 202a-202c through the control signal, the multiplexer module 27 selects the clock signal output by the first oscillator 201a according to the selection signal, and the counter module 28 counts the clock signal and outputs the counting result; in the process monitoring mode, the logic module 21 enables the first oscillator 201a-201c and the second oscillator 202a-202c through the control signal, the multiplexer module 27 can select the clock signal output by one of them according to the selection signal, and the counter module 28 counts the clock signal and outputs the counting result. By comparing the counting result of the clock signal output by the first oscillator that has undergone the chip aging test with the counting result of the clock signal output by the corresponding second oscillator, the aging degree of the chip can be determined.

[0050] Despite Figure 2 Only several modules are shown, but those skilled in the art will appreciate that this is only for the sake of illustration, and the integrated circuit layout 200 may further include other modules and / or semiconductor devices to implement other functions of the process monitor.

[0051] In addition, despite the Figure 2It is shown that in each group of oscillator units, the first oscillator and the second oscillator are arranged in the horizontal direction, and the center line A-A' between their positions is located in the vertical direction, but those skilled in the art can understand that the first oscillator and the second oscillator can also be arranged in the vertical direction, and the center line A-A' between their positions can be located in the horizontal direction.

[0052] In addition, despite Figure 2 Only three groups of oscillator units are shown in the figure. Those skilled in the art will appreciate that the integrated circuit layout 200 may include other numbers of oscillator units, and each group of oscillator units may be arranged in a mirror-symmetrical manner with respect to the center line AA′.

[0053] also, Figure 2 The locations of the logic module 21 , the power supply module 22 , the decoder module 26 , the multiplexer module 27 and the counter module 28 in the integrated circuit layout 200 shown in FIG. 2 are merely an example, and they may be located at other locations in the integrated circuit layout 200 .

[0054] Figure 3 Another integrated circuit layout of a process monitor according to an embodiment of the present disclosure is shown. Figure 3 In the embodiment of FIG. 1 , only the layout of each module is shown, and the signal lines, power lines and / or ground lines between them are omitted.

[0055] In this embodiment, the oscillator module includes three groups of oscillator units. Each group of oscillator units includes a first oscillator and a second oscillator arranged in mirror symmetry with respect to a center line A-A', for example, the first oscillator 301a and the second oscillator 302a are mirror symmetric with respect to the center line A-A', the first oscillator 301b and the second oscillator 302b are mirror symmetric with respect to the center line A-A', and the first oscillator 301c and the second oscillator 302c are mirror symmetric with respect to the center line A-A'. The first oscillator and the second oscillator in each group of oscillator units may include semiconductor devices of the same type and process, and the first oscillator and the second oscillator in different groups of oscillator units may include semiconductor devices of different types and processes.

[0056] In this embodiment, the logic module includes three groups of mode control units corresponding to the three groups of oscillator units respectively. Each group of mode control units includes an OR logic unit and an AND logic unit. The OR logic units 310a-310c are respectively coupled to the first oscillators 301a-301c via signal lines on the side of the first oscillators 301a-301c close to the center line A-A'. The AND logic units 311a-311c are coupled to the second oscillators 302a-302c on the side of the second oscillators 302a-302c close to the center line A-A' via signal lines. In each group of mode control units, the positions of the OR logic unit and the AND logic unit in the integrated circuit layout 300 are symmetrical relative to the center line A-A'. For example, the OR logic unit 310a and the AND logic unit 311a are symmetrical relative to the center line A-A', the OR logic unit 310b and the AND logic unit 311b are symmetrical relative to the center line A-A', and the OR logic unit 310c and the AND logic unit 311c are symmetrical relative to the center line A-A'. That is to say, although the layout structures of the OR logic unit and the AND logic unit are different, in each group of mode control units, the distances between their positions relative to the center line A-A' are equal. However, it can be understood by those skilled in the art that in other embodiments, the OR logic unit and the AND logic unit can also be arranged at other positions in the integrated circuit layout 300, for example, respectively arranged on the side of the first oscillator and the second oscillator away from the center line A-A'. Alternatively, the logic module can also include other types of logic units. The symmetrical arrangement of the OR logic unit and the AND logic unit can further reduce the parasitic effects in the circuit, reduce the circuit mismatch, improve the circuit stability and signal integrity, and thus improve the accuracy of the aging test.

[0057] In this embodiment, the power supply module includes a first power supply submodule 320 and a second power supply submodule 321. The first power supply submodule 320 is located on the side of the first oscillator 301a-301c away from the center line A-A' in the integrated circuit layout 300, and is coupled to the module on the left side of the center line A-A' through the power line and the ground line, and supplies power to the module on the left side of the center line A-A' via an external power supply. The module on the left side of the center line A-A' includes, for example, the first oscillator 301a-301c, or the logic unit 310a-310c and the first buffer 360a-360c. The second power supply submodule 321 is located on the side of the second oscillator 302a-302c away from the center line A-A' in the integrated circuit layout 300, and is coupled to the module on the right side of the center line A-A' through the power line and the ground line, and supplies power to the module on the right side of the center line A-A' via an external power supply. The module on the right side of the center line AA' includes, for example, a second oscillator 302a-302c, a logic unit 311a-311c, and a second buffer 361a-361c. The power line and the ground line can be at least partially arranged in a grid shape in the integrated circuit layout 300, so as to reduce the mismatch caused by uneven current distribution. The first power supply submodule 320 and the second power supply submodule 321 have the same layout structure, the line width can be about 0.5μm, and are mirror-symmetric relative to the center line AA' in the integrated circuit layout 300. That is, the first power supply submodule 320 and the second power supply submodule 321 are reflections of each other relative to the center line AA'. Not only do they have the same structure, but the routing, line length, line width, and distance relative to the center line AA' in the integrated circuit layout 300 are also the same. Arranging the first power supply submodule 320 and the second power supply submodule 321 on the outside in a mirror-symmetrical manner can ensure that the power supply environment on the left and right sides is as consistent as possible, providing the same power supply environment for the devices that need to be matched, and effectively reducing the line resistance and the voltage drop (IR Drop) on the power line and the ground line, thereby further improving the accuracy of the aging test.

[0058] In this embodiment, the integrated circuit layout 300 of the process monitor may further include a buffer module, which is coupled to the oscillator module via a signal line and is used to buffer the clock signal output by the oscillator module. Figure 3In the embodiment of the present invention, the buffer module includes three groups of buffer units corresponding to the three groups of oscillator units respectively. Each group of buffer units includes a first buffer coupled to the first oscillator and a second buffer coupled to the second oscillator. The first buffers 360a-360c are respectively coupled to the first oscillators 301a-301c via signal lines on the side of the first oscillators 301a-301c close to the center line AA'. The second buffers 361a-361c are coupled to the second oscillators 302a-302c via signal lines on the side of the second oscillators 302a-302c close to the center line AA'. In each group of buffer units, the first buffer and the second buffer have the same structure and are mirror-symmetric with respect to the center line AA' in the integrated circuit layout 300. That is, in each group of buffer units, the first buffer and the second buffer are reflections of each other with respect to the center line AA'. They not only have the same structure, but also have the same routing, line length, line width, and distance relative to the center line AA' in the integrated circuit layout 300. Arranging the buffers in mirror symmetry can further reduce parasitic effects in the circuit, reduce circuit mismatch, improve circuit stability and signal integrity, and thus improve the accuracy of aging testing.

[0059] In addition, in this embodiment, the integrated circuit layout 300 of the process monitor may further include a frequency divider module 37, which is coupled to the oscillator module via a signal line and is used to perform frequency division processing on the clock signal output by the oscillator module to reduce the frequency of the clock signal for subsequent counting. Figure 3 In the embodiment of the present invention, the divider module 37 is located above the oscillator module, the logic module and the buffer module in the integrated circuit layout 300, and its coverage area in the integrated circuit layout 300 intersects with the extension line of the center line A-A'. Such an arrangement of the divider module 37 can reduce the impact on the modules arranged in mirror symmetry below, further improving the accuracy of the aging test. However, it can be understood by those skilled in the art that in other embodiments, the divider module 37 can also be arranged at other positions in the integrated circuit layout 300, for example, below the oscillator module, the logic module and the buffer module.

[0060] although Figure 3 In this embodiment, the integrated circuit layout 300 may further include a decoder module, a multiplexer module and a counter module. The connection relationship and functions between them and other modules can be referred to in Figure 2 The described embodiments will not be described in detail here.

[0061] The following briefly describes the working principle of the OR logic unit and the AND logic unit. For example, Figure 3The first oscillator 301a shown in is the Mth oscillator in the oscillator module, and the second oscillator 302a is the Kth oscillator in the oscillator module. The first input end of the OR logic unit 310a receives the aging test enable signal, and the second input end receives the data Sel_M of the Mth bit of the selection signal (corresponding to the Mth oscillator). The first input end of the AND logic unit 311a receives the inverted signal of the aging test enable signal, and the second input end receives the data of the Kth bit of the selection signal. When the process monitor executes the chip aging test mode, the logic value of the aging test enable signal is "1", and the logic value of its inverted signal is "0". Regardless of the logic value of Sel_M, the OR logic unit 310a outputs a control signal with a logic value of "1" to the first oscillator 301a to enable the first oscillator 301a to continue oscillating and output a clock signal. At the same time, the multiplexer module receives the data Sel_M of the Mth bit of the selection signal. When the logic value of Sel_M is "1", the corresponding switch unit is turned on to output the clock signal to the counter module. The counter module counts the clock signal and outputs the counting result. Since the logic value of the inverted signal of the aging test enable signal is "0", regardless of the logic value of Sel_K, the logic unit 311a outputs a control signal with a logic value of "0" to the second oscillator 302a to disable the second oscillator 302a. When the process monitor executes the process monitoring mode, the logic value of the aging test enable signal is "0" and the logic value of its inverted signal is "1". When the logic value of Sel_M is "1", the logic unit 310a outputs a control signal with a logic value of "1" to the first oscillator 301a to enable the first oscillator 301a to continue oscillating and output the clock signal. At the same time, the multiplexer module receives the data Sel_M of the Mth bit of the selection signal. When the logic value of Sel_M is "1", the corresponding switch unit is turned on so that the clock signal is output to the counter module. The counter module counts the clock signal and outputs the counting result. When the logic value of Sel_K is "1", the logic unit 311a outputs a control signal with a logic value of "1" to the second oscillator 302a to enable the second oscillator 302a to continuously oscillate and output the clock signal. At the same time, the multiplexer module receives the data Sel_K of the Kth bit of the selection signal. When the logic value of Sel_K is "1", the corresponding switch unit is turned on so that the clock signal is output to the counter module. The counter module counts the clock signal and outputs the counting result. By comparing the counting result of the clock signal output by the first oscillator 301a after the chip aging test with the counting result of the clock signal output by the second oscillator 302a, the aging degree of the chip can be determined.

[0062] The present disclosure also proposes a method for integrated circuit layout for a process monitor. Figure 4 A flow chart of a method for integrated circuit layout of a process monitor according to an embodiment of the present disclosure is shown. The method can be executed by a controller, a microprocessor or other computing device, for example, by a processor when automatically designing an integrated circuit layout.

[0063] In method 400, step 401 includes arranging an oscillator module in an integrated circuit layout, the oscillator module includes at least one group of oscillator units, each group of oscillator units includes a first oscillator and a corresponding second oscillator having the same circuit structure, wherein at least one first oscillator and the corresponding second oscillator are arranged in the integrated circuit layout to be mirror-symmetrical relative to a center line between their positions. The modules included in the integrated circuit layout and their functions can be referred to Figure 1-Figure 3 The contents described will not be repeated here.

[0064] Step 402 includes placing a logic module in an integrated circuit layout and coupling it to an oscillator module through a signal line, wherein the logic module is configured to enable a first oscillator and disable a second oscillator in a chip aging test mode to determine a chip aging degree.

[0065] Those skilled in the art will appreciate that the functions marked in the boxes may also occur in a different order than that marked in the drawings. For example, the oscillator module, the logic module, and the power supply module may be first arranged in the integrated circuit layout, and then connected through signal lines, power lines, and ground lines, respectively.

[0066] In addition, computer-readable program instructions or computer program products for executing the above-mentioned methods can also be stored in the cloud. When needed, users can access the computer-readable program instructions for executing the above-mentioned embodiments of the present disclosure stored in the cloud through mobile Internet, fixed network or other networks, thereby implementing the technical solutions disclosed in multiple embodiments of the present disclosure.

[0067] The present disclosure also proposes a chip, which includes a process monitor. The process monitor is used for aging test of the chip. The integrated circuit layout of the process monitor is, for example, the integrated circuit layout described in the above embodiments, which includes: a signal line; an oscillator module, which includes at least one group of oscillator units, each group of oscillator units includes a first oscillator and a corresponding second oscillator with the same circuit structure, and at least one first oscillator and a corresponding second oscillator are mirror-symmetric relative to the center line between their positions in the integrated circuit layout; and a logic module, which is coupled to the oscillator module via a signal line and is configured to enable the first oscillator and disable the second oscillator in the chip aging test mode to determine the degree of chip aging.

[0068] In some embodiments, the logic module includes at least one group of mode control units corresponding to the at least one group of oscillator units respectively, each group of mode control units includes an OR logic unit coupled to the first oscillator and an AND logic unit coupled to the second oscillator, wherein positions of the OR logic unit and the AND logic unit in the integrated circuit layout are symmetrical relative to the center line.

[0069] In some embodiments, the OR logic unit is coupled to the first oscillator at a side of the first oscillator close to the center line, and the AND logic unit is coupled to the second oscillator at a side of the second oscillator close to the center line.

[0070] In some embodiments, the at least one group of oscillator units includes a plurality of groups of oscillator units, and the plurality of groups of oscillator units are sequentially arranged along a center line in the integrated circuit layout.

[0071] In some embodiments, two oscillators in the same group of oscillator units include semiconductor devices of the same type and process, and multiple oscillators in different groups of oscillator units include semiconductor devices of different types and processes.

[0072] In some embodiments, the integrated circuit layout further includes: a power line and a ground line; a power supply module, which is coupled to the oscillator module and the logic module via the power line and the ground line and is configured to power the oscillator module and the logic module via an external power supply.

[0073] In some embodiments, the power supply module includes a first power supply submodule and a second power supply submodule, the first power supply submodule is configured to power at least the first oscillator via an external power supply, and the second power supply submodule is configured to power at least the second oscillator via an external power supply, wherein the first power supply submodule and the second power supply submodule have the same layout structure and are mirror-symmetric relative to the center line in the integrated circuit layout.

[0074] In some embodiments, the first power supply submodule is located on a side of the first oscillator away from the center line in the integrated circuit layout, and the second power supply submodule is located on a side of the second oscillator away from the center line in the integrated circuit layout.

[0075] In some embodiments, the power lines and the ground lines are at least partially arranged in a grid pattern in the integrated circuit layout.

[0076] In some embodiments, the integrated circuit layout further includes: a buffer module, which is coupled to the oscillator module via a signal line and is configured to buffer the clock signal output by the oscillator module. The buffer module includes at least one group of buffer units corresponding to at least one group of oscillator units, each group of buffer units includes a first buffer coupled to the first oscillator and a second buffer coupled to the second oscillator, wherein the first buffer and the second buffer have the same structure and are mirror-symmetric relative to the center line in the integrated circuit layout.

[0077] In some embodiments, the first buffer is located on a side of the first oscillator close to the center line in the integrated circuit layout, and the second buffer is located on a side of the second oscillator close to the center line in the integrated circuit layout.

[0078] Although the embodiments of the present disclosure have been described with reference to several specific embodiments, it should be understood that the embodiments of the present disclosure are not limited to the specific embodiments of the disclosure. The embodiments of the present disclosure are intended to cover various modifications and equivalent arrangements included in the spirit and scope of the appended claims. The scope of the claims is consistent with the broadest interpretation, thereby including all such modifications and equivalent structures and functions.

Claims

1. An integrated circuit layout of a process monitor, wherein the process monitor is used for aging testing of a chip, the integrated circuit layout comprising: Signal line; An oscillator module, comprising at least one group of oscillator units, each group of oscillator units comprising a first oscillator and a corresponding second oscillator having the same circuit structure, at least one of the first oscillator and the corresponding second oscillator being mirror-symmetric relative to a center line between their positions in the integrated circuit layout; as well as A logic module is coupled to the oscillator module via the signal line and is configured to enable the first oscillator and disable the second oscillator in a chip aging test mode, thereby determining a chip aging degree.

2. The integrated circuit layout according to claim 1, wherein: The logic module includes at least one group of mode control units corresponding to the at least one group of oscillator units respectively, each group of mode control units includes an OR logic unit coupled to the first oscillator and an AND logic unit coupled to the second oscillator, wherein the positions of the OR logic unit and the AND logic unit in the integrated circuit layout are symmetrical relative to the center line.

3. The integrated circuit layout according to claim 2, wherein: The OR logic unit is coupled to the first oscillator at a side of the first oscillator close to the center line, and the AND logic unit is coupled to the second oscillator at a side of the second oscillator close to the center line.

4. The integrated circuit arrangement according to any one of claims 1 to 3, wherein: The at least one group of oscillator units includes a plurality of groups of oscillator units, and the plurality of groups of oscillator units are arranged in sequence along the direction of the center line in the integrated circuit layout.

5. The integrated circuit layout according to claim 4, wherein: The two oscillators in the same group of oscillator units include semiconductor devices of the same type and process, and the multiple oscillators in different groups of oscillator units include semiconductor devices of different types and processes.

6. The integrated circuit layout according to claim 1, wherein: The integrated circuit layout further comprises: Power and ground wires; The power supply module is coupled to the oscillator module and the logic module via the power line and the ground line, and is configured to supply power to the oscillator module and the logic module via an external power supply.

7. The integrated circuit layout according to claim 6, wherein: The power supply module includes a first power supply submodule and a second power supply submodule, wherein the first power supply submodule is configured to supply power to at least the first oscillator via the external power supply, and the second power supply submodule is configured to supply power to at least the second oscillator via the external power supply, wherein the first power supply submodule and the second power supply submodule have the same layout structure and are mirror-symmetric relative to the center line in the integrated circuit layout.

8. The integrated circuit layout according to claim 7, wherein: The first power supply submodule is located on a side of the first oscillator away from the center line in the integrated circuit layout, and the second power supply submodule is located on a side of the second oscillator away from the center line in the integrated circuit layout.

9. The integrated circuit layout according to claim 6, wherein: The power lines and the ground lines are at least partially arranged in a grid shape in the integrated circuit layout.

10. The integrated circuit layout of claim 1 , further comprising: A buffer module is coupled to the oscillator module via the signal line and is configured to buffer the clock signal output by the oscillator module, the buffer module includes at least one group of buffer units corresponding to the at least one group of oscillator units respectively, each group of buffer units includes a first buffer coupled to the first oscillator and a second buffer coupled to the second oscillator, wherein the first buffer and the second buffer have the same structure and are mirror-symmetric relative to the center line in the integrated circuit layout.

11. The integrated circuit layout according to claim 10, wherein: The first buffer is located on a side of the first oscillator close to the center line in the integrated circuit layout, and the second buffer is located on a side of the second oscillator close to the center line in the integrated circuit layout.

12. The integrated circuit layout of claim 1 , further comprising: A frequency divider module is coupled to the oscillator module via the signal line and is configured to perform frequency division processing on a clock signal output by the oscillator module. The coverage area of ​​the frequency divider module in the integrated circuit layout intersects with an extension line of the center line.

13. The integrated circuit layout of claim 1 , further comprising: a decoder module coupled to the logic module via the signal line and configured to output a selection signal; a multiplexer module coupled to the decoder module and the oscillator module via the signal line; a counter module coupled to the multiplexer module via the signal line; Among them, in the chip aging test mode, the oscillator module outputs at least one clock signal to the multiplexer module, and the multiplexer module outputs one of the at least one clock signal to the counter module according to the selection signal, and the counter module counts one of the at least one clock signal to output a counting result corresponding to the chip aging degree.

14. A chip, comprising: A process monitor, used for burn-in test of the chip, wherein the process monitor has an integrated circuit layout according to any one of claims 1-13.

15. A method for integrated circuit layout for a process monitor, comprising: Arranging an oscillator module in the integrated circuit layout, the oscillator module comprising at least one group of oscillator units, each group of oscillator units comprising a first oscillator and a corresponding second oscillator having the same circuit structure, wherein at least one of the first oscillator and the corresponding second oscillator are arranged in the integrated circuit layout to be mirror-symmetrical with respect to a center line between their positions; and A logic module is arranged in the integrated circuit layout and coupled to the oscillator module through a signal line, wherein the logic module is configured to enable the first oscillator and disable the second oscillator in a chip aging test mode to determine the chip aging degree.

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