Floating point multiplier-adder, processor and electronic equipment

Abstract

The invention provides a floating point multiplier-adder, a processor and electronic equipment. The floating point multiplier-adder comprises a control module, a receiving module, a splitting module, an index operation module, a multiplication module, an order matching module and an addition module. The receiving module receives all of the first, second and third operands or only the first and third operands for operation. The splitting module splits the operands received by the receiving module into sign bits, indexes and mantissas. The addition module performs first addition processing on the order result and the multiplication operation result based on the mantissa when the multiplication operation is performed, or performs second addition processing on the order result and the first mantissa of the first operand based on the mantissa when the addition operation is performed. The control module controls the splitting module, the index operation module, the addition module and the multiplication array module according to operation types. The floating-point multiply-add device can reduce power consumption loss when the floating-point multiply-add device executes additive operation.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a floating-point multiplier-adder, a processor, and an electronic device. Background Art

[0002] The floating-point multiplier and adder (FMA) is a commonly used computing unit in modern high-performance processors. It can execute floating-point multiplication and addition instructions to complete the multiplication and addition operation of A*B+C, where A, B, and C are floating-point operands involved in the multiplication and addition operation. The floating-point multiplier and adder can also execute floating-point addition instructions and floating-point multiplication instructions. For example, when the floating-point multiplier and adder executes a floating-point multiplication instruction, the operand C can be set to 0, which is equivalent to executing the multiplication operation of A*B. When the floating-point multiplier and adder executes a floating-point addition instruction, the operand B can be set to 1, which is equivalent to executing the addition operation of A+C. Summary of the invention

[0003] At least one embodiment of the present disclosure provides a floating-point multiplier and adder, comprising: a control module, a receiving module, a splitting module, an exponential operation module, a multiplication array module, an order module and an addition module, wherein the receiving module is configured to receive all or only the first operand and the third operand of a first operand, a second operand and a third operand for operation, wherein the operation includes a multiplication-addition operation or an addition operation; the splitting module is configured to split the operand received by the receiving module into a sign bit, an exponent and a mantissa respectively; the exponential operation module is configured to perform an exponential operation on the exponent obtained by splitting the splitting module to obtain an exponential operation result; the multiplication array module is configured to, when performing the multiplication-addition operation, perform an exponential operation on the first mantissa of the first operand The multiplication operation is performed on the third operand and the second mantissa of the second operand to obtain a multiplication operation result; the exponentiation module is configured to perform an exponentiation shift on the third mantissa of the third operand according to the exponentiation result to obtain a mantissa exponentiation result; the addition module is configured to, when performing the multiplication and addition operation, obtain a first addition result based on performing a first addition process on the mantissa exponentiation result and the multiplication operation result, or, when performing the addition operation, obtain a second addition result based on performing a second addition process on the mantissa exponentiation result and the first mantissa of the first operand; and the control module is configured to control the operations of the splitting module, the exponentiation module, the addition module and the multiplication array module according to the type of the operation.

[0004] The floating-point multiplier and adder provided by at least one embodiment of the present disclosure further includes a selection module, wherein the selection module is coupled to the splitting module, the exponential operation module and the addition module, and is configured to select the exponent and mantissa obtained by the splitting from the splitting module according to the control instruction provided by the control module, and send the exponent and mantissa obtained by the splitting to the exponential operation module and the addition module according to the multiplication and addition operation or the addition operation mode.

[0005] At least one embodiment of the present disclosure provides a floating-point multiplier and adder, wherein the selection module includes multiple selectors, and the multiple selectors include a first selector; the first selector is coupled to the split module and the exponential operation module, and is configured to receive an exponent offset value and a second exponent of the second operand from the split module, and when the operation is the multiplication operation, select the second exponent to be output to the exponential operation module, or, when the operation is the addition operation, select the exponent offset value to be output to the exponential operation module.

[0006] At least one embodiment of the present disclosure provides a floating-point multiplier, wherein the addition module includes a carry-save adder and an addition leading zero prediction module, the carry-save adder is coupled to the order module, and is configured to perform compression processing on the mantissa order result, the received first addend, and the received second addend to obtain first compressed data and second compressed data; the addition leading zero prediction module is configured to, when the operation is the multiplication operation, perform the first addition processing on the received third addend and the fourth addend to obtain the first addition processing result, or when the operation is the addition operation, perform the second addition processing on the received third addend and the fourth addend to obtain the second addition processing result, and is configured to calculate the number of leading zeros in the first addition processing result or the second addition processing result.

[0007] At least one embodiment of the present disclosure provides a floating-point multiplier, wherein the multiple selectors include a second selector and a third selector, the addition leading zero prediction module is coupled to the carry-save adder, and the third addend and the fourth addend are the first compressed data and the second compressed data, respectively; the second selector is configured to, when the operation is the multiplication operation, select the first result of the multiplication operation to be provided to the carry-save adder as the first addend, or, when the operation is the addition operation, select zero to be provided to the carry-save adder as the first addend; the third selector is configured to, when the operation is the multiplication operation, select the second result of the multiplication operation to be provided to the carry-save adder as the second addend, or, when the operation is the addition operation, select the first mantissa obtained by splitting the splitting module to be provided to the carry-save adder as the second addend.

[0008] At least one embodiment of the present disclosure provides a floating-point multiplier / adder, wherein the splitting module is further configured to, when the operation is the addition operation, perform bit width expansion processing on the first mantissa of the first operand, and provide the expanded first mantissa to the third selector, wherein the expanded first mantissa is the same as the bit width of the second result.

[0009] At least one embodiment of the present disclosure provides a floating-point multiplier and adder, wherein the multiple selectors include a second selector and a third selector, the first addend and the second addend are respectively the first result and the second result of the multiplication operation result; the second selector is configured to, when the operation is the multiplication operation, select to provide the first compressed data to the addition leading zero prediction module as the third addend, or, when the operation is the addition operation, select to provide the mantissa order result obtained by the order module to the addition leading zero prediction module as the third addend; the third selector is configured to, when the operation is the multiplication operation, select to provide the second compressed data to the addition leading zero prediction module as the fourth addend, or, when the operation is the addition operation, select to provide the first mantissa obtained by splitting the splitting module to the addition leading zero prediction module as the fourth addend.

[0010] In at least one embodiment of the present disclosure, a floating-point multiplier and adder is provided, wherein the receiving module includes a first register, a second register and a third register, wherein the first register, the second register and the third register are respectively configured to store the first operand, the second operand and the third operand.

[0011] In at least one embodiment of the present disclosure, a floating-point multiplier is provided, wherein the receiving module further includes the fourth register, and the fourth register is configured to, when the operation is the addition operation, store the first operand, and provide the first operand to the splitting module to obtain the first mantissa used for the addition operation and provided to the addition module.

[0012] At least one embodiment of the present disclosure provides a floating-point multiplier, further comprising: a normalization shift module, configured to perform a logical shift on the first addition processing result or the second addition processing result to obtain a normalized result, wherein the number of bits of the logical shift is equal to the number of leading zeros; and a rounding module, configured to round the normalized result.

[0013] At least one embodiment of the present disclosure further provides a processor, which includes the floating-point multiplier and adder provided by any of the above embodiments.

[0014] At least one embodiment of the present disclosure further provides an electronic device, which includes the floating-point multiplier and adder provided by any of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0016] Figure 1 A schematic diagram of the structure of a traditional floating-point multiplier-adder is shown;

[0017] Figure 2 A schematic diagram of the structure of a floating-point multiplier and adder provided by at least one embodiment of the present disclosure is shown;

[0018] Figure 3 A schematic diagram of performing bit width expansion processing provided by at least one embodiment of the present disclosure is shown;

[0019] Figure 4 A schematic diagram showing the structure of another floating-point multiplier-adder provided by at least one embodiment of the present disclosure is shown; and

[0020] Figure 5 A schematic structural diagram of an electronic device provided by at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0022] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0023] Floating point numbers are used to represent real numbers in computers. They represent data where the decimal point can float. They are usually expressed as N = M × R. E , including a sign bit, an exponent field E and a mantissa M, where R is the base (base) of the order (for example, 2, 8, 16, etc.).

[0024] For example, in the IEEE 754 standard, a single-precision floating-point number (such as FP32) has a total of 32 bits, including 1 sign bit, 8-bit exponent and 23-bit mantissa (that is, the sign bit occupies 1 bit, the exponent part occupies 8 bits, and the mantissa part occupies 23 bits); a double-precision floating-point number (such as FP64) has a total of 64 bits, including 1 sign bit, 11-bit exponent part and 52-bit mantissa part.

[0025] The sign bit is used to indicate the sign of the operand, for example, 0 represents a positive number and 1 represents a negative number. The exponent part is used to store the exponent value, and the exponent part determines the position of the decimal point relative to the mantissa part. The mantissa part represents the decimal part of the operand, for example, the mantissa is a binary decimal, for example, it can be assumed that there is a hidden highest bit "1" (the highest bit may not be explicitly saved when stored to save storage space). In binary floating point numbers, these bits represent the digits after the binary decimal point.

[0026] Floating-point addition refers to the process of adding two or more values ​​encoded in floating-point representation. This process is not just a simple addition of the mantissa part, because the decimal point position of the floating-point number is not fixed, but is determined by the exponent. Generally, floating-point addition can include the following steps: alignment operation, mantissa addition, overflow processing, rounding processing, normalization processing, and special processing.

[0027] Alignment operation (i.e., aligning exponents or exponent operations) means that before performing floating-point addition operations, it is necessary to ensure that the decimal point positions of all floating-point operands (also referred to as "floating-point operands") participating in the addition are the same. The exponent part of the floating-point operands should be adjusted to the same level. If the exponents of the two addends are different, alignment is achieved by moving the mantissa corresponding to the addend with the smaller exponent value. For example, if the exponent of one operand is larger, the mantissa of the other smaller operand needs to be right-shifted so that the exponent of the operand with the smaller exponent is aligned with the exponent of the operand with the larger exponent. Mantissa addition means that when the exponent parts of all floating-point operands participating in the addition have been aligned, the mantissa parts of the aligned adjusted operands can be added. This process can be similar to ordinary integer addition, but because it is performed in binary and is limited by the number of significant digits of the mantissa, it may involve additional carries and subsequent rounding operations (described below).

[0028] In addition, floating-point multiplication refers to the process of multiplying two or more values ​​encoded in floating-point representation. For example, the multiplication of floating-point numbers follows the IEEE 754 standard (the standard used by most modern computers), including sign bit calculation, exponent calculation (also known as "exponent calculation"), mantissa calculation, normalization and rounding, overflow checking, etc.

[0029] Sign calculation involves first determining the sign of the result; if the sign bits of the two operands are the same (both positive or both negative), then the sign bit of the result is 0 (positive); if the sign bits are different, the sign bit of the result is 1 (negative). Exponent calculation involves calculating the exponent of the result, where, since this is a multiplication, the exponent of the result is equal to the sum of the exponents of the two operands, minus any offset (if an exponent representation with an offset is used). For example, in single-precision floating point numbers, the exponent has 8 bits and a bias value of 127. Mantissa calculation involves multiplying the mantissas of the two operands. The mantissa after multiplication may exceed the normalization range, so it is necessary to normalize it, that is, adjust the mantissa and exponent to ensure that the mantissa is between 1.0 and 2.0 (for normalized floating point numbers). Normalization and rounding involve: if the mantissa after multiplication exceeds the normalization range, it may be necessary to perform a right shift (mantissa) and increase (exponent) operation to renormalize the result. During normalization, the mantissa may also need to be rounded to meet the precision requirements of the floating point number. Rounding rules can be rounding to the nearest, rounding to zero, rounding up, or rounding down. Overflow and underflow checks include checking whether the exponent exceeds the representation range, which may cause overflow (the value is too large) or underflow (the value is too small to be accurately represented). In the case of overflow, the result may be set to infinity (Infinity), and in the case of underflow, it may be set to zero or a smaller non-zero number.

[0030] As mentioned above, a floating-point multiplier-adder (FMA) can perform multiplication and addition operations. In the design of a floating-point multiplier-adder, the length of the pipeline and the operation logic of the floating-point multiplier-adder are usually divided according to the operating frequency of each functional module of the floating-point multiplier-adder (e.g., multiplier, adder, register, etc.), so as to ensure that the floating-point multiplier-adder can operate efficiently at different operating frequencies.

[0031] For example, Figure 1 A structural schematic diagram of a floating-point multiplier-adder is shown.

[0032] like Figure 1 As shown, a floating-point multiplier and adder with a delay of 4 beats (e.g., 4 clock cycles) is used as an example for explanation, that is, the floating-point multiplier and adder includes a four-stage pipeline, each stage of the pipeline corresponds to a clock cycle, and the floating-point multiplier and adder performs a part of the calculation task in each clock cycle. Based on the duration limit of the clock cycle, the alignment shift operation performed by the alignment module 130 is divided into alignment Align_1 operation and alignment Align_2 operation, the multiplication operation of the multiplication array module 140 is divided into multiplication operation Mult_1 and multiplication operation Mult_2, and the shift operation of the normalization shift module 160 is divided into Norm_1 operation and Norm_2 operation, which are respectively executed in different pipeline stages.

[0033] like Figure 1 As shown, the first-stage pipeline includes a split module 110, an exponential operation module 120, an alignment module 130, and a multiplication array module 140. Three floating-point operands (e.g., A, B, and C) are written into three registers 101-103. The split module 110 splits each operand to obtain the sign bit, exponent, and mantissa corresponding to each operand. For example, the split module 110 splits operand A into the sign bit SA, exponent EA, and mantissa MA corresponding to operand A. The exponential operation module 120 calculates the exponential operation result according to the exponents EA, EB, and EC of operands A, B, and C, respectively. The alignment module 130 performs an alignment operation Align_1 on the received exponential operation result and the mantissa MC of operand C. The multiplication array module 140 performs a multiplication operation Mult_1 on the mantissas MA and MB of operands A and B.

[0034] like Figure 1 As shown, the second-stage pipeline includes an alignment module 130, a multiplication array module 140, and a carry-save adder 151. The alignment module 130 performs an alignment operation Align_2 to obtain a mantissa alignment result, and inputs the mantissa alignment result to the carry-save adder 151 for processing. The multiplication array module 140 performs a multiplication operation Mult_2 to obtain a multiplication operation result, and inputs the multiplication operation result to the carry-save adder 151 for processing. The processing result generated by the carry-save adder 151 is input to the sum leading zero prediction module 152.

[0035] like Figure 1 As shown, the third-stage pipeline includes a sum leading zero prediction module 152 and a normalization shift module 160. The sum leading zero prediction module 152 performs addition processing on the processing result generated by the carry-save adder 151 and calculates the number of leading zeros, and outputs the generated processing result and the calculated number of leading zeros to the normalization shift module 160, so that the normalization shift module 160 performs the Norm_1 operation in the third-stage pipeline.

[0036] like Figure 1 As shown, the fourth-stage pipeline includes a normalization shift module 160 and a rounding module 170. The normalization shift module 160 performs a Norm_2 operation and obtains a normalized result. The rounding module 170 performs rounding processing on the normalized result.

[0037] When the floating-point multiplier and adder performs a multiplication operation, the operand C can be set to 0 to perform a multiplication and addition operation of A*B+0. When the floating-point multiplier and adder performs an addition operation, the operand B can be set to 1 to perform a multiplication and addition operation of A*1+C.

[0038] The inventor of the present disclosure has noticed that the above-mentioned floating-point multiplier and adder includes a multiplication array module to perform multiplication operations, and the multiplication array module occupies a large area. When the floating-point multiplier and adder is used to perform addition operations, the multiplication array module will continue to work, resulting in unnecessary power consumption losses of the floating-point multiplier and adder. For this problem, for example, a separate floating-point adder can generally be set in the floating-point multiplier and adder to replace the floating-point multiplier and adder to perform addition operations. Although this method can avoid unnecessary power consumption losses of the floating-point multiplier and adder, the floating-point adder set will also increase the area overhead and static power consumption losses of the chip, and this solution cannot solve the above-mentioned problem well.

[0039] One or more embodiments of the present disclosure provide a floating-point multiplier and adder. The floating-point multiplier and adder includes a control module, a receiving module, a splitting module, an exponential operation module, a multiplication array module, an order module and an addition module. The receiving module is configured to receive all or only the first operand and the third operand of the first operand, the second operand and the third operand for operation, wherein the operation includes a multiplication and addition operation or an addition operation. The splitting module is configured to split the operand received by the receiving module into a sign bit, an exponent and a mantissa respectively. The exponential operation module is configured to perform an exponential operation on the exponent obtained by splitting the splitting module to obtain an exponential operation result. The multiplication array module is configured to perform a multiplication operation on the first mantissa of the first operand and the second mantissa of the second operand when performing a multiplication and addition operation to obtain a multiplication operation result. The order module is configured to perform an order shift on the third mantissa of the third operand according to the exponential operation result to obtain a mantissa order result. The addition module is configured to, when performing a multiplication-addition operation, obtain a first addition result based on a first addition process on a mantissa pair order result and a multiplication operation result, or, when performing an addition operation, obtain a second addition result based on a second addition process on a mantissa pair order result and a first mantissa of a first operand. The control module is configured to control the operation of the split module, the exponential operation module, the addition module, and the multiplication array module according to the type of operation. When the floating-point multiplier and adder provided in the embodiment of the present disclosure executes a floating-point addition instruction, based on the operation of the control module, the multiplication array module can be bypassed, thereby reducing the power consumption loss of the floating-point multiplier and adder when performing an addition operation.

[0040] The present disclosure is described below through several specific embodiments. In order to keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components may be omitted. When any component of the embodiments of the present disclosure appears in more than one figure, the component is represented by the same or similar reference numeral in each figure.

[0041] Some embodiments and examples of the present disclosure are described in detail below with reference to the accompanying drawings.

[0042] Figure 2A schematic diagram of the structure of a floating-point multiplier and adder provided by at least one embodiment of the present disclosure is shown.

[0043] like Figure 2 As shown, the floating-point multiplier and adder includes a control module ( Figure 2 ), receiving module 200, splitting module 210, exponential operation module 220, multiplication array module 240, rank module 230 and addition module 250.

[0044] For example, the pipeline of the floating-point multiplier-adder can be divided into a four-stage pipeline, that is, the operation process of the floating-point multiplier-adder is divided into four stages. The specific division method is the same as the above Figure 1 However, in the embodiments of the present disclosure, the division mode of the pipeline of the floating-point multiplier-adder can be determined according to the operating frequency of each functional module or component in the floating-point multiplier-adder, and the embodiments of the present disclosure are not limited to this.

[0045] In this embodiment, the receiving module 200 is configured to receive floating-point operands for operation, including all or only operands A and C among operands A, B and C, and correspondingly, the operation performed includes a multiplication and addition operation A*B+C or an addition operation A+C. The splitting module 210 is configured to split the operands (A, B and C, or A and C) received by the receiving module 200 into respective corresponding sign bits, exponents and mantissas. The exponential operation module 220 is configured to perform exponential operation on the exponents split by the splitting module 210 to obtain exponential operation results.

[0046] For example, in at least one example, the receiving module 200 may include registers 201-203, wherein the registers 201-203 are respectively configured to store operands A, B, and C. For example, in other examples, the receiving module may further include a register 204. The register 204 is configured to store the operand D when the floating-point multiplier performs an addition operation, and provide the operand D to the splitting module 210 to obtain the corresponding sign bit SD, exponent ED, and mantissa MD, and the operand D is a copy of the operand A so as to be used in the addition operation, thereby simplifying the control during the addition operation.

[0047] It should be noted that in order to facilitate the distinction between “operand A” used for addition operation and “operand A” used for multiplication operation, one or more embodiments of the present disclosure use “operand D” (stored in register 204) to represent “operand A” used for addition operation.

[0048] When the floating-point multiplier-adder performs a multiplication-addition operation A*B+C, the multiplication array module 240 is configured to perform a multiplication operation on the mantissa MA of the operand A and the mantissa MB of the operand B. That is, the multiplication array module 240 performs a multiplication operation Mult_1 on the first-stage pipeline, and then performs a multiplication operation Mult_2 on the second-stage pipeline, and obtains a multiplication operation result. The multiplication operation result includes a first result Carry and a second result Sum.

[0049] The alignment module 230 is configured to perform an alignment shift on the mantissa MC of the operand C according to the result of the exponential operation, that is, the alignment module 230 performs the alignment_1 operation in the alignment shift operation on the first stage pipeline, and then performs the alignment_2 operation in the alignment shift operation on the second stage pipeline, and obtains the mantissa alignment result MC_Align.

[0050] When the floating-point multiplier adder performs a multiplication-addition operation A*B+C, the addition module 250 is configured to perform a first addition process on the mantissa alignment result MC_Align and the multiplication result to obtain a first addition process result. Alternatively, when the floating-point multiplier adder performs an addition operation A+C (that is, D+C), the addition module 250 is configured to perform a second addition process on the mantissa alignment result MC_Align and the mantissa MD of the operand D to obtain a second addition process result.

[0051] Control Module( Figure 2 The control module 210 (not shown) is configured to control the operation of the split module 210, the exponential operation module 220, the addition module 250 and the multiplication array module 240 according to the type of operation, so as to realize different operations; for example, the control module determines the type of operation according to the received operation instruction, and thus sends a corresponding control signal. For example, the control module can be realized by a logic processing circuit (such as microprogram control) or by hard wiring, and the embodiments of the present disclosure are not limited to this.

[0052] For example, when the floating-point multiplier and adder receives a floating-point addition instruction, the control module can turn off the clocks of registers 201, 202, and register 206 that may exist in the multiplication array module 240, wherein register 206 is used to store the intermediate result Mult_Tmp during the multiplication operation. By turning off the clocks of registers 201, 202, and 206, it is possible to prevent the data in registers 201, 202, and 206 from being updated or overwritten as the clock signal changes, thereby preventing the splitting module from splitting the operands A and B in registers 201 and 202, thereby bypassing the multiplication array module 240 when the floating-point multiplier and adder performs an addition operation, thereby avoiding unnecessary power consumption loss caused by the multiplication array module 240 participating in the addition operation. That is, during the process of the floating-point multiplier and adder performing an addition operation, Figure 2 The grayed-out modules (registers 201, 202, 206 and multiplication array module 240) do not participate in the addition operation, and the modules not grayed-out (such as registers 203, 204, etc.) are still in normal working state, thereby reducing the power consumption of the floating-point multiplier when performing addition operations.

[0053] The floating-point multiplier and adder provided by one or more embodiments of the present disclosure may further include a selection module. The selection module is coupled to the splitting module, the exponential operation module and the addition module. The selection module is configured to select the exponent and mantissa obtained by splitting from the splitting module according to the control instruction provided by the control module, and send the exponent and mantissa obtained by splitting to the exponential operation module and the addition module according to the multiplication and addition operation or the addition operation mode.

[0054] For example, the selection module may include multiple selectors. Figure 2 In the embodiment shown, multiple selectors ( Figure 2 The selector 2802 (denoted by "MUX" in FIG. 2 ) includes a selector 2802, a selector 2803, and a selector 2804. The selector 2802 is coupled to the split module 210 and the exponent operation module 220, and is configured to receive the exponent offset value Bias and the exponent EB of the operand B received from the split module 210. When the floating-point multiplier and adder perform a multiplication operation, the selector 2802 selects to output the exponent EB to the exponent operation module 220, or, when the floating-point multiplier and adder perform an addition operation, the selector 2802 selects to output the exponent offset value Bias to the exponent operation module 220. For example, the exponent offset value Bias can be determined according to the IEEE 754 standard and the data format of the floating-point operand, that is, the exponent offset value Bias=2 (n-1) -1, where n is the number of exponent bits of the floating point number. For example, in the IEEE 754 standard, a single-precision floating point number includes an 8-bit exponent, so the Bias for single-precision floating point numbers is 2. (8-1)-1 = 127, double-precision floating point numbers include an 11-bit exponent, so the Bias used for double-precision floating point numbers is 2 (11-1) -1=1023. The connection mode and function of the selector 2803 and the selector 2804 will be introduced below and will not be described here in detail.

[0055] For example, when the receiving module includes the register 204, the plurality of selectors may further include the selector 2801. Figure 2 As shown, the selector 2801 is coupled to the split module 210 and the exponent operation module 220, and is configured to receive the exponent EA of the operand A stored in the register 201 and the exponent ED of the operand D stored in the register 204 from the split module 210. When the floating-point multiplier and adder performs a multiplication operation, the selector 2801 selects to output the exponent EA to the exponent operation module 220, or, when the floating-point multiplier and adder performs an addition operation, the selector 2801 selects to output the exponent ED to the exponent operation module 220.

[0056] In one example of the present disclosure, when the floating-point multiplier and adder performs a multiplication operation, the exponential operation module receives exponents EA, EB and EC, and the exponential operation result obtained can be expressed as E=EC-(EA+EB)+Bias0; when the floating-point multiplier and adder performs an addition operation, the exponential operation module receives exponent EA, exponent ED and exponent offset value Bias, and the exponential operation result obtained can be expressed as E=EC-(ED+Bias)+Bias0=EC-ED, wherein Bias0 is the initial exponent offset value for exponential operation set in advance in the exponential operation module, and the values ​​of Bias0 and Bias are the same.

[0057] For example, in the floating-point multiplier adder provided by one or more embodiments of the present disclosure, the addition module includes a carry-save adder and an addition leading zero prediction module.

[0058] The Carry Save Adder (CSA) is an efficient adder design suitable for performing addition operations on multiple numbers. During the calculation process, the carry-save adder does not immediately process the carry generated by the low bit, but saves the carry generated for subsequent processing. This method helps to reduce the delay in the addition operation and increase the operation speed.

[0059] like Figure 2As shown, since the carry-save adder 251 has three input terminals and two output terminals, the carry-save adder 251 is also called a "3:2 compressor", which is used to compress the sum of three input data (for example, A1+A2+A3) into the sum of two output data (for example, PS+PC), wherein the three input data and the two output data satisfy the following relationship: PS=A1⊕A2⊕A3, PC=(A1·A2)+(A1·A3)+(A2·A3), "⊕" represents an exclusive OR operation (XOR), and "·" represents an AND operation (AND). The floating-point multiplier in the present disclosure can also choose to use a 4:2 compressor, a 5:2 compressor, etc. according to actual needs, and the present disclosure does not limit this.

[0060] like Figure 2 As shown, the carry-preserve adder 251 is coupled to the output end of the alignment module 230, and is configured to compress the mantissa alignment result MC_Align, the received first addend, and the received second addend to obtain compressed data PS and PC, wherein the first addend and the second addend are used to describe that the carry-preserve adder 251 receives two data other than the mantissa alignment result MC_Align. The compressed data PS represents the sum of the alignment result MC_Align, the first addend, and the second addend when the carry is not considered, also known as the "partial sum (Partial Sum)"; the compressed data PD (Propagate Carry) represents the carry generated in the process of adding the alignment result MC_Align, the first addend, and the second addend.

[0061] The summing leading zero prediction module 252 is configured to perform a first addition process on the received third addend and fourth addend when the floating-point multiplier performs a multiplication operation to obtain a first addition process result, or to perform a second addition process on the received third addend and fourth addend when the floating-point multiplier performs an addition operation to obtain a second addition process result. The summing leading zero prediction module 252 is also configured to calculate the number of leading zeros in the first addition process result or the second addition process result. Here, "third addend" and "fourth addend" are used to describe the data received at the two input ends of the summing leading zero prediction module 252, and the "first addition process" and "second addition process" have the same addition process steps.

[0062] In one embodiment of the present disclosure, Figure 2 As shown, the selector 2803 is coupled to the output end of the multiplication array module 240 and the input end of the carry-save adder 251 , and the selector 2804 is coupled to the multiplication array module 240 , the carry-save adder 251 and the split module 210 .

[0063] For example, when the floating-point multiplier and adder performs a multiplication operation, the selector 2803 selects to provide the first result Carry in the multiplication operation result to the carry-save adder 251 as the first addend, and the selector 2804 selects to provide the second result Sum in the multiplication operation result to the carry-save adder 251 as the second addend. Then, the carry-save adder 251 compresses the mantissa alignment result MC_Align, the first result Carry, and the second result Sum at the second pipeline stage to obtain compressed data PS and PC.

[0064] For example, when the floating-point multiplier performs an addition operation, the selector 2803 selects to provide 0 (i.e., corresponding to the case of no carry) to the carry-save adder 251 as the first addend, and the selector 2804 selects to provide the mantissa MD obtained by the splitting module 210 to the carry-save adder 251 as the second addend. Then, the carry-save adder 251 compresses the mantissa alignment result MC_Align, 0, and the mantissa MD at the second pipeline stage to obtain compressed data PS and PC.

[0065] Following the above embodiment, the sum leading zero prediction module 252 is coupled to the carry-save adder 251, and the compressed data PS and PC generated by the carry-save adder 251 are directly provided to the sum leading zero prediction module 252. In the third-stage pipeline, the sum leading zero prediction module 252 first performs addition processing on the compressed data PS and PC to obtain an addition processing result, and then calculates the number of leading zeros in the addition processing result.

[0066] It should be noted that when the floating-point multiplier performs addition operations, Figure 2 The mantissa MD received by the selector 2804 in the operation is actually the mantissa MD_d1 obtained after the expansion operation. On the first-stage pipeline, the split module 210 performs a bit width expansion process on the mantissa MD of the operand D, and provides the expanded mantissa MD_d1 to the selector 2804, wherein the expanded mantissa MD_d1 has the same bit width as the second result Sum. The expanded mantissa MD_d1 can be stored in the register 205, which is coupled to the selector 2804 so that the selector 2804 reads the mantissa MD_d1.

[0067] Figure 3 A schematic diagram of performing bit width expansion processing provided by at least one embodiment of the present disclosure is shown.

[0068] like Figure 3As shown, the bit width of the mantissa MD is W, and the bit width of the second result Sum in the multiplication operation result is 2W. When the mantissa MD is subjected to bit width expansion processing, since the bit width of the second result Sum is greater than the bit width of the mantissa MD, the bit width expansion processing belongs to positive number expansion, and 1 bit of data 0 is added to the high bit of the mantissa MD, and then (W-1) bits of data 0 are added to the low bit of the mantissa MD, and finally the mantissa MD_d1 with a bit width of 2W is obtained. The highest bit of the expanded mantissa MD_d1 is 0, the last (W-1) bits are all 0, and the middle W bits are the mantissa MD.

[0069] In at least one embodiment of the present disclosure, by expanding the bit width of the mantissa (also referred to as "bit width alignment"), it is possible to ensure that data can be correctly processed and calculated inside the floating-point multiplier, thereby improving calculation efficiency and ensuring compatibility with hardware design.

[0070] For example, the floating-point multiplier and adder provided by one or more embodiments of the present disclosure further includes a normalization shift module and a rounding module.

[0071] like Figure 2 As shown, the normalization shift module 260 is configured to perform a logical shift on the first addition processing result or the second addition processing result output by the addition module 250 to obtain a normalized result, wherein the number of bits of the logical shift is equal to the number of leading zeros in the first addition processing result or the second addition processing result. The logical shift operation is divided into two parts, namely, the Norm_1 operation performed on the third-stage pipeline and the Norm_2 operation performed on the fourth-stage pipeline. The rounding module 270 is configured to perform rounding processing on the normalized result generated by the normalization shift module 260 on the fourth-stage pipeline.

[0072] It should be noted that Figure 2 The floating-point multiplier and adder shown omits a sign bit prediction module that operates on the split sign bit. The sign bit prediction module can determine the sign of the final operation result based on the exponential operation result, that is, determine whether the sign of the final operation result is positive or negative. The specific determination method is relatively conventional and will not be repeated here.

[0073] Compared to Figure 2In another embodiment, the register 201 is used to directly provide the operand A for addition calculation, instead of the register 204. In this case, the word number EA and the mantissa MA obtained by splitting the operand A need to be selectively provided directly to the exponent operation module 220 (the selector 2801 is not needed in this case) and the selector 2804 (and then further provided to the addition operation module 250). For example, another selector is provided to selectively connect the split module corresponding to the operand A to the multiplication array module 240. For example, in the case of performing multiplication and addition operations, the split module corresponding to the operand A is connected to the multiplication array module 240, and in the case of performing addition operations, the split module corresponding to the operand A is disconnected from the multiplication array module 240. For other connections and operations of this embodiment, please refer to the above. Figure 2 The situation shown will not be repeated here.

[0074] Figure 4 A schematic diagram of the structure of another floating-point multiplier-adder provided by at least one embodiment of the present disclosure is shown.

[0075] Figure 4 The floating-point multiplier and adder in the embodiment shown also includes a control module, a receiving module, a splitting module, an exponential operation module, a normalization shift module, a rounding module, etc. The connection mode and functions of these modules can refer to the above Figure 2 The floating-point multiplier and adder shown in the figure will not be described in detail here. Figure 4 Examples and Figure 2 The differences between the embodiments are described below.

[0076] like Figure 4 As shown, the carry-save adder 451 is a 3:2 compressor, and the three input terminals of the carry-save adder 451 are respectively coupled to the output terminal of the alignment module 430 and the two output terminals of the multiplication array module. The carry-save adder 451 is configured to compress the mantissa alignment result MC_Align, the first result Carry of the multiplication operation result, and the second result Sum to obtain compressed data PS and PC, and provide the compressed data PS and PC to the selectors 4803 and 4804 respectively.

[0077] like Figure 4 As shown, the selector 4803 is coupled to the alignment module 430 and the carry-preserved adder 451 respectively to receive the mantissa alignment result MC_Align and the compressed data PS. The selector 4804 is coupled to the carry-preserved adder 451 and the register 405 to receive the compressed data PC and the extended mantissa MD_d1. The method for generating the extended mantissa MD_d1 can refer to the above Figure 3 The bit width expansion processing method shown is not repeated here.

[0078] For example, when the floating-point multiplier performs a multiplication operation, the selector 2803 selects to provide the compressed data PS to the addition and leading zero prediction module 452 as the third addend, and the selector 4804 selects to provide the compressed data PC to the addition and leading zero prediction module 452 as the fourth addend. The leading zero prediction module 452 first performs a first addition process on the compressed data PS and PC to obtain a first addition process result, and then calculates the number of leading zeros in the first addition process result. For example, when the floating-point multiplier provided in the embodiment performs an addition operation, the selector 4803 selects to provide the mantissa alignment result MC_Align to the addition leading zero prediction module 452 as the third addend, and the selector 4804 selects to provide the extended mantissa MD_d1 to the addition leading zero prediction module 252 as the fourth addend. The leading zero prediction module 452 first performs a second addition process on the mantissa alignment result MC_Align and the extended mantissa MD_d1 to obtain a second addition process result, and then calculates the number of leading zeros in the second addition process result.

[0079] One or more embodiments of the present disclosure further provide a processor, which includes a floating-point multiplier and adder provided in any of the above embodiments. The processor may be, for example, a central processing unit (CPU) or a coprocessor, and the coprocessor may be, for example, a graphics processing unit (GPU), a general-purpose graphics processing unit (GPGPU), an AI accelerator (such as a tensor processor, etc.), etc., which is not limited by the embodiments of the present disclosure; and the embodiments of the present disclosure do not limit the specific architecture of the processor, the applicable instruction set, etc.

[0080] One or more embodiments of the present disclosure also provide an electronic device, which includes the processor provided by any of the above embodiments.

[0081] For example, Figure 5 A schematic structural diagram of an electronic device provided by at least one embodiment of the present disclosure is shown.

[0082] The electronic devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc., and may also be used to implement various types of servers.

[0083] For example, Figure 5As shown, in some examples, the electronic device 500 includes a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 501, which may include a floating-point multiplier and adder provided by at least one embodiment of the present disclosure, and the processing device 501 may perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 502 or a program loaded from a storage device 508 to a random access memory (RAM) 503. In the RAM 503, various programs and data required for the operation of the computer system are also stored. The processing device 501, the ROM 502, and the RAM 503 are connected to each other via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0084] For example, the following components may be connected to the I / O interface 505: an input device 506 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 507 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 508 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 509 which may also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 509 may allow the electronic device 500 to communicate with other devices wirelessly or by wire to exchange data, and perform communication processing via a network such as the Internet. The drive 510 is also connected to the I / O interface 505 as needed. Removable media 511, such as magnetic disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive 510 as needed, so that the computer programs read therefrom are installed into the storage device 508 as needed. Although Figure 5 The electronic device 500 is shown to include various devices, but it should be understood that it is not required to implement or include all the devices shown. More or fewer devices may be implemented or included instead.

[0085] For example, the electronic device 500 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 509 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular phone network, a wireless local area network (LAN) and / or a metropolitan area network (MAN). Wireless communication may use any of a variety of communication standards, protocols, and techniques, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging and / or Short Message Service (SMS), or any other suitable communication protocol.

[0086] In addition to the above exemplary descriptions, there are a few points that need to be explained:

[0087] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0088] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0089] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A floating-point multiplier-accumulator, include: A control module, a receiving module, a splitting module, an exponential operation module, a multiplication array module, an order module and an addition module, wherein: The receiving module is configured to receive all or only the first operand and the third operand of a first operand, a second operand and a third operand for operation, wherein the operation includes a multiplication and addition operation or an addition operation; The splitting module is configured to split the operand received by the receiving module into a sign bit, an exponent and a mantissa respectively; The exponential operation module is configured to perform exponential operation on the exponent obtained by the splitting module to obtain an exponential operation result; The multiplication array module is configured to, when performing the multiplication-addition operation, perform the multiplication operation on the first mantissa of the first operand and the second mantissa of the second operand to obtain a multiplication operation result; The alignment module is configured to perform an alignment shift on the third mantissa of the third operand according to the exponential operation result to obtain a mantissa alignment result; The addition module is configured to, when performing the multiplication-addition operation, obtain a first addition result based on performing a first addition process on the mantissa pair order result and the multiplication result, or, when performing the addition operation, obtain a second addition result based on performing a second addition process on the mantissa pair order result and the first mantissa of the first operand; and The control module is configured to control the operations of the split module, the exponential operation module, the addition module and the multiplication array module according to the type of the operation.

2. The floating-point multiplier-adder as claimed in claim 1 further comprising a selection module, in, The selection module is coupled to the splitting module, the exponential operation module and the addition module, and is configured to select the exponent and mantissa obtained by the splitting from the splitting module according to the control instruction provided by the control module, and send the exponent and mantissa obtained by the splitting to the exponential operation module and the addition module according to the multiplication and addition operation mode or the addition operation mode.

3. The floating-point multiplier-adder as claimed in claim 2, in, The selection module includes a plurality of selectors, and the plurality of selectors includes a first selector; The first selector is coupled to the splitting module and the exponential operation module, and is configured to receive an exponent offset value and a second exponent of the second operand from the splitting module, and select the second exponent to be output to the exponential operation module when the operation is the multiplication operation, or select the exponent offset value to be output to the exponential operation module when the operation is the addition operation.

4. The floating-point multiplier-adder as claimed in claim 3, in, The addition module includes a carry-save adder and a leading zero prediction module. The carry-save adder is coupled to the alignment module and is configured to compress the mantissa alignment result, the received first addend and the received second addend to obtain first compressed data and second compressed data; The addition leading zero prediction module is configured to, when the operation is the multiplication operation, perform the first addition processing on the received third addend and the fourth addend to obtain the first addition processing result, or when the operation is the addition operation, perform the second addition processing on the received third addend and the fourth addend to obtain the second addition processing result, and is configured to calculate the number of leading zeros in the first addition processing result or the second addition processing result.

5. The floating-point multiplier-adder as claimed in claim 4, in, The plurality of selectors include a second selector and a third selector, the sum leading zero prediction module is coupled to the carry-save adder, the third addend and the fourth addend are the first compressed data and the second compressed data, respectively; The second selector is configured to, when the operation is the multiplication operation, select to provide a first result of the multiplication operation results to the carry-save adder as the first addend, or, when the operation is the addition operation, select to provide zero to the carry-save adder as the first addend; The third selector is configured to, when the operation is the multiplication operation, select to provide the second result of the multiplication operation to the carry-save adder as the second addend, or, when the operation is the addition operation, select to provide the first mantissa obtained by splitting the splitting module to the carry-save adder as the second addend.

6. The floating-point multiplier-adder as claimed in claim 5, in, The splitting module is also configured to, when the operation is the addition operation, perform bit width expansion processing on the first mantissa of the first operand and provide the expanded first mantissa to the third selector, wherein the expanded first mantissa has the same bit width as the second result.

7. The floating-point multiplier-adder according to claim 4, in, The plurality of selectors include a second selector and a third selector, the first addend and the second addend are respectively a first result and a second result of the multiplication operation result; The second selector is configured to, when the operation is the multiplication operation, select to provide the first compressed data to the addition leading zero prediction module as the third addend, or, when the operation is the addition operation, select to provide the mantissa alignment result obtained by the alignment module to the addition leading zero prediction module as the third addend; The third selector is configured to, when the operation is the multiplication operation, select to provide the second compressed data to the addition leading zero prediction module as the fourth addend, or, when the operation is the addition operation, select to provide the first mantissa obtained by splitting the splitting module to the addition leading zero prediction module as the fourth addend.

8. The floating-point multiplier-adder according to claim 1, in, The receiving module includes a first register, a second register and a third register, wherein the first register, the second register and the third register are configured to store the first operand, the second operand and the third operand respectively.

9. The floating-point multiplier-adder as claimed in claim 8, in, The receiving module further includes the fourth register, The fourth register is configured to, when the operation is the addition operation, store the first operand and provide the first operand to the split module to obtain the first mantissa used for the addition operation and provided to the addition module.

10. The floating-point multiplier-adder according to claim 1, further comprising: include: a normalization shift module configured to perform a logical shift on the first addition processing result or the second addition processing result to obtain a normalized result, wherein the number of bits of the logical shift is equal to the number of the leading zeros; and The rounding module is configured to round the normalized result.

11. A processor, include: A floating-point multiplier-adder as claimed in any one of claims 1 to 10.

12. An electronic device comprising the processor according to claim 11.

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