Mainboard state monitoring circuit and mainboard

Abstract

The invention relates to a mainboard state monitoring circuit and a mainboard, an MCU, and a state acquisition circuit, a crystal oscillator circuit and an information reading circuit which are connected with the MCU are arranged in the mainboard state monitoring circuit, and the state acquisition circuit can acquire state information of a monitored mainboard. The MCU can record the state information of the monitored mainboard according to the clock signal provided by the crystal oscillator circuit, and the state information recorded by the MCU can be read out through the information reading circuit. The mainboard state monitoring circuit is internally provided with the first power supply circuit and the second power supply circuit, and the second power supply circuit is provided with the standby power supply independent of the power supply of the monitored mainboard, so that the standby power supply can still supply power to the MCU under the condition that the power supply of the monitored mainboard cannot supply power due to a fault; the MCU is maintained in a basic state monitoring working state, so that no matter how the power supply state of the monitored mainboard is, the mainboard state monitoring circuit can collect and record the state information of the monitored mainboard.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a mainboard status monitoring circuit and a mainboard. Background Art

[0002] The motherboard, also known as the main board, system board or motherboard, is one of the most basic and important components of the computer. All components in the computer host are connected through the motherboard. When the computer is running normally, the control of the system memory, storage devices and other I / O devices must be completed through the motherboard. It can be seen that the state of the motherboard determines the operating state of the computer. There are also monitoring schemes for the motherboard state in the relevant technology. For example, the Chinese patent application with application number 202410451627.2 and the name of "A DDR5 motherboard onboard processor operation state AI monitoring method" records the monitoring scheme for the DDR5 motherboard onboard processor operation state; for example, the Chinese patent application with application number 200410080121.8 and the name of "A computer motherboard fault monitoring and diagnosis device" provides a monitoring and diagnosis scheme for computer motherboard faults. However, these schemes basically rely on software programs to implement. Once the motherboard is powered off or the CPU fails, these monitoring schemes cannot be implemented normally. Therefore, the monitoring scenarios of the existing motherboard state monitoring schemes are limited, and it is difficult to fully monitor the motherboard state. Summary of the invention

[0003] In order to solve the problem that the monitoring scenarios of existing motherboard status monitoring solutions are limited and it is difficult to comprehensively monitor the status of the motherboard in various scenarios, the present application provides a motherboard status monitoring circuit and a mainboard.

[0004] In a first aspect, the present application provides a mainboard status monitoring circuit, the mainboard status monitoring circuit comprising: MCU, the MCU includes a crystal oscillator connection pin, a first power pin, a second power pin, a status acquisition pin and an information reading pin, the MCU has a first function and a second function, the second function includes monitoring the status of a monitored motherboard, the monitored motherboard includes a CPU and a power supply; A crystal oscillator circuit connected to the crystal oscillator connection pin; a first power supply circuit connected to the first power pin, the other end of the first power supply circuit being connected to the power supply, and the first power supply circuit being used to support the MCU to implement a first function; a second power supply circuit connected to the second power supply pin, the other end of the second power supply circuit being connected to a backup power supply, the backup power supply being independent of the power supply, and the second power supply circuit being used to support the MCU to implement a second function; A state acquisition circuit corresponding to the state acquisition pins one by one, wherein one end of the state acquisition circuit is connected to the state acquisition pins, and the other end of the state acquisition circuit is connected to a monitoring point on the monitored motherboard; and The input end is connected to the information reading pin to read the information reading circuit in the MCU. The information in the MCU includes the state information collected by the state acquisition circuit recorded by the MCU according to the clock signal provided by the crystal oscillator circuit, and the acquisition time of the state information.

[0005] By adopting the above technical scheme, an MCU and a state acquisition circuit, a crystal oscillator circuit, and an information reading circuit connected to the MCU are set in the motherboard state monitoring circuit. The state acquisition circuit can collect the state information of the monitored motherboard, and the MCU can record the state information of the monitored motherboard according to the clock signal provided by the crystal oscillator circuit, and the state information recorded by the MCU can be read out by the information reading circuit. The implementation of the motherboard state monitoring scheme does not depend on the state of the CPU on the monitored motherboard. Even if the CPU fails, the state information including the CPU failure can be collected normally; at the same time, the motherboard state monitoring circuit is provided with a first power supply circuit and a second power supply circuit, and the second power supply circuit has a backup power supply independent of the power supply of the monitored motherboard. Therefore, when the power supply of the monitored motherboard cannot supply power due to a fault, the backup power supply can still supply power to the MCU, and the MCU is maintained in the basic state monitoring working state. Therefore, no matter what the power supply state of the monitored motherboard is, the motherboard state monitoring circuit can realize the collection and recording of the state information of the monitored motherboard. The monitoring function of the motherboard state monitoring circuit is not affected by the CPU and power supply state of the monitored motherboard, and the state monitoring of the monitored motherboard is more comprehensive, which is conducive to the engineering personnel to accurately locate the cause of the fault according to the monitored state information and determine the fault elimination plan. In addition, the cost of the motherboard status monitoring circuit is low, which is conducive to the popularization and application of the motherboard status monitoring solution.

[0006] Optionally, the crystal oscillator connecting pin includes a first crystal oscillator connecting pin and a second crystal oscillator connecting pin, and the crystal oscillator circuit includes: a first crystal oscillator circuit connected to the first crystal oscillator connection pin; A second crystal oscillator circuit is connected to the second crystal oscillator connection pin, and the crystal oscillator frequency of the second crystal oscillator circuit is lower than the crystal oscillator frequency of the first crystal oscillator circuit, and the second crystal oscillator circuit is powered by the second power supply circuit.

[0007] Optionally, the voltage of the backup power supply is lower than the voltage of the power supply, and the second power supply circuit further includes: a first diode; a first resistor connected between the backup power supply and the anode of the first diode; A second diode; a second resistor connected between the power supply and the anode of the second diode; and A first capacitor, wherein a first end of the first capacitor is connected to the cathode of the first diode and the cathode of the second diode at the same time, a second end is grounded, and the first end is connected to the second power pin.

[0008] By adopting the above technical solution, in addition to supplying power to the MCU through the backup power supply, the second power supply circuit can also supply power to the MCU through the power supply of the monitored mainboard, and because the voltage of the backup power supply is lower than the voltage of the power supply, based on the structure of the first diode and the second diode, it can be ensured that when the power supply of the monitored mainboard is normal, the second power supply circuit supplies power to the MCU through the power supply, and the backup power supply does not supply power. The backup power supply starts supplying power only when the power supply of the monitored mainboard is abnormal. This can save the electric energy of the backup power supply and extend the service life of the backup power supply.

[0009] Optionally, the first power supply circuit includes: a third diode, wherein an anode of the third diode is connected to the power supply; a fourth diode having an anode connected to a cathode of the third diode, wherein the cathode of the fourth diode is connected to the first power supply pin; and A second capacitor is connected between the cathode of the third diode and ground.

[0010] By adopting the above technical solution, the first power supply circuit can supply power to the MCU through the third diode and the fourth diode using the power supply of the monitored mainboard, and can charge the second capacitor while supplying power. When the power supply fails and cannot supply power normally, the second capacitor can be discharged to maintain the normal operation of the MCU in a short time, so that the MCU switches from the normal working state to the basic working state.

[0011] Optionally, the first power supply circuit further includes: A fifth diode, wherein an anode of the fifth diode is connected to the anode of the third diode, and a cathode of the fifth diode is connected to the cathode of the fourth diode.

[0012] By adopting the above technical solution, a fifth diode connected in parallel with the series branch of the third diode and the fourth diode is also provided in the first power supply circuit. The power supply can also supply power to the MCU through the branch where the fifth diode is located, and the power supply speed of the power supply through the branch where the fifth diode is located is not affected by the charging speed of the second capacitor, which is beneficial to improving the startup speed of the MCU.

[0013] Optionally, the state acquisition circuit includes at least one of the following: A first acquisition circuit is configured to acquire the power-on voltage of the monitored mainboard; A second acquisition circuit is configured to acquire the bridge chip power supply voltage of the monitored mainboard; A third acquisition circuit is configured to acquire the operating voltage of the CPU after it is turned on; A fourth acquisition circuit is configured to acquire an S3 indication signal indicating that the monitored mainboard enters a sleep state; A fifth acquisition circuit is configured to acquire an S4 indication signal indicating that the monitored mainboard enters a dormant state; A sixth acquisition circuit is configured to acquire a reset wake-up signal indicating that the bridge chip power supply voltage of the monitored mainboard is normal; The seventh state acquisition circuit is configured to acquire a platform reset signal indicating that the CPU has met the initialization condition.

[0014] Optionally, the output end of the information reading circuit is connected to the CPU, and the information reading circuit also includes a reading control end, which is configured to control the connectivity between the input end and the output end of the information reading circuit according to an MCU effective signal, so that the CPU can read information from the MCU.

[0015] By adopting the above technical solution, the output end of the information reading circuit is connected to the CPU. Therefore, when engineers need to obtain the status information recorded in the MCU, they do not need to connect a special external reading device or disassemble the main chassis, which facilitates the reading of status information and is beneficial to improving the efficiency of mainboard fault location and fault analysis.

[0016] Optionally, the MCU also includes an information write pin; the mainboard status monitoring circuit also includes an information write circuit, the information write circuit includes a write control end, an input end connected to the CPU, and an output end connected to the information write pin, and the write control end is configured to write the information sent by the CPU into the MCU according to the MCU valid signal.

[0017] Optionally, the monitored mainboard further includes a peripheral device reading circuit and a peripheral device writing circuit, the peripheral device reading circuit and the information reading circuit are connected to the same reading pin of the CPU, and the peripheral device writing circuit and the information writing pin are connected to the same writing pin of the CPU; the peripheral device reading circuit includes a reading control terminal, configured to read the information in the peripheral device to the CPU according to the peripheral device valid signal input to the reading control terminal; the peripheral device writing circuit includes a writing control terminal, configured to write the information sent by the CPU to the peripheral device according to the peripheral device valid signal input to the writing control terminal; the mainboard status monitoring circuit further includes a selection circuit, and the selection circuit includes: A first output terminal, wherein the first output terminal is connected to the read control terminal and the write control terminal at the same time; a second output terminal, the second output terminal being connected to the read control terminal and the write control terminal at the same time; and A selection control terminal connected to the CPU; The selection circuit is configured to control the first output terminal to output an MCU valid signal and control the second output terminal to output a peripheral invalid signal according to a first control signal output by the CPU to the selection control terminal; the selection circuit is also configured to control the second output terminal to output a peripheral valid signal and control the first output terminal to output an MCU invalid signal according to a second control signal output by the CPU to the selection control terminal.

[0018] By adopting the above technical solution, the information reading circuit of the mainboard status monitoring circuit shares the CPU reading pin with the peripheral reading circuit on the monitored mainboard, and the information writing circuit of the mainboard status monitoring circuit shares the CPU writing pin with the peripheral writing circuit. At the same time, the CPU data reading and writing path can be switched by selecting the circuit, and the MCU and the peripheral are isolated, avoiding writing the status information in the MCU into the peripheral, and avoiding writing the information in the peripheral into the MCU. The information interaction between the MCU and the CPU can be realized when there is no interaction requirement between the peripheral and the CPU, which not only simplifies the external connection circuit structure of the CPU, but also ensures the data receiving and sending function between the CPU and the peripheral and the MCU.

[0019] In a second aspect, the present application provides a motherboard, comprising: A mainboard, the mainboard comprising a mainboard body, a CPU and a power supply arranged on the mainboard body, the power supply being used to supply power to the CPU; As described in any one of the aforementioned first aspects, the mainboard status monitoring circuit is configured to perform status monitoring on the mainboard.

[0020] By adopting the above technical solution, a motherboard status monitoring circuit is set in the mainboard, and the status acquisition circuit of the motherboard status monitoring circuit can collect the status information of the monitored motherboard, and the MCU can record the status information of the monitored motherboard according to the clock signal provided by the crystal oscillator circuit, and the status information recorded by the MCU can be read out through the information reading circuit. The implementation of the motherboard status monitoring scheme does not depend on the status of the CPU on the monitored motherboard. Even if the CPU fails, the status information including the CPU failure can be collected normally; at the same time, the motherboard status monitoring circuit is set with a first power supply circuit and a second power supply circuit, and the second power supply circuit has a backup power supply independent of the power supply of the monitored motherboard. Therefore, when the power supply of the monitored motherboard cannot supply power due to a fault, the backup power supply can still supply power to the MCU, and the MCU is maintained in the basic status monitoring working state. Therefore, no matter what the power supply state of the monitored motherboard is, the motherboard status monitoring circuit can realize the collection and recording of the status information of the monitored motherboard. The monitoring function of the motherboard status monitoring circuit is not affected by the CPU and power supply state of the monitored motherboard, and the status monitoring of the monitored motherboard is more comprehensive, which is conducive to the engineering personnel to accurately locate the cause of the fault according to the monitored status information and determine the fault elimination plan.

[0021] In summary, this application at least includes the following beneficial technical effects: 1. The monitoring function of the motherboard status monitoring circuit is not affected by the CPU and power supply status on the monitored motherboard. It can monitor the status of the monitored motherboard more comprehensively, which is beneficial for engineering personnel to accurately locate the cause of the fault and determine the fault elimination plan based on the monitored status information.

[0022] 2. The cost of the motherboard status monitoring circuit is low, which is conducive to the popularization and application of the motherboard status monitoring solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of a circuit principle of a mainboard status monitoring circuit provided in an embodiment of the present application; Figure 2 A chip schematic diagram of an MCU provided in an embodiment of the present application; Figure 3 A schematic diagram of a circuit principle of a first crystal oscillator circuit provided in an embodiment of the present application; Figure 4 A schematic diagram of a circuit principle of a second crystal oscillator circuit provided in an embodiment of the present application; Figure 5 A schematic diagram of a circuit principle of a second power supply circuit provided in an embodiment of the present application; Figure 6 A schematic diagram of a circuit principle of a first power supply circuit provided in an embodiment of the present application; Figure 7 Another schematic diagram of a circuit principle of a first power supply circuit provided in an embodiment of the present application; Figure 8 A schematic diagram of a circuit principle of a first acquisition circuit provided in an embodiment of the present application; Fig. 9 A schematic diagram of a circuit principle of a second acquisition circuit provided in an embodiment of the present application; Fig.10 A schematic diagram of a circuit principle of a third acquisition circuit provided in an embodiment of the present application; Fig.11 A schematic diagram of the circuit principles of a fourth acquisition circuit, a fifth acquisition circuit, a sixth acquisition circuit, and a seventh acquisition circuit provided in an embodiment of the present application; Fig.12 A schematic diagram of a circuit principle of an information reading circuit provided in an embodiment of the present application; Fig.13 A schematic diagram of a circuit principle of an information writing circuit provided in an embodiment of the present application; Fig.14 A schematic diagram of a circuit principle of a selection circuit provided in an embodiment of the present application.

[0024] Description of reference numerals: 100-mainboard status monitoring circuit; 20-MCU; 30-crystal oscillator circuit; 31-first crystal oscillator circuit; 32-second crystal oscillator circuit; 40-first power supply circuit; 50-second power supply circuit; 60-status acquisition circuit; 70-information reading circuit; 80-selection circuit; 81-first output terminal; 82-second output terminal; 83-selection control terminal; D1-first diode; D2-second diode; D3-third diode; D4-fourth diode; D5-fifth diode; R1-first resistor; R2-second resistor; R3-third resistor; R4-fourth resistor; R5-fifth resistor; R6-sixth resistor; R7-seventh resistor; R8-eighth resistor; R9-ninth resistor; R10-tenth resistor; R11-eleventh resistor; C1-first capacitor; C2-second capacitor; C3-third capacitor; C4-fourth capacitor; C5-fifth capacitor. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0026] The terms used in the following embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to be used as limitations to the present application. As used in the specification and the appended claims of the present application, the singular expressions "one", "a kind of", "said", "above", "the" and "this" are intended to also include plural expressions, unless there is a clear contrary indication in its context. It should also be understood that the term "and / or" used in the present application refers to and includes any or all possible combinations of one or more listed items. The term "exemplary" means "used as an example, embodiment or illustrative", and any embodiment described as "exemplary" here does not need to be interpreted as being superior to or better than other embodiments. The terms "first" and "second" are only used for descriptive purposes, and cannot be understood as implying or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first" and "second" can expressly or implicitly include one or more of these features, and in the description of the embodiments of the present application, unless otherwise specified, the meaning of "multiple" is two or more.

[0027] Industrial computers, or industrial control computers, are computer systems designed specifically for industrial environments. Compared with ordinary commercial computers, industrial computers have stronger stability, durability, anti-interference capabilities, and the ability to adapt to harsh environments. Industrial computers are usually used in industrial automation fields such as automated production lines, industrial robots, power systems, and traffic control.

[0028] The mainboard of an industrial computer may fail due to various reasons during long-term operation. In order to troubleshoot, engineers often need to understand the status of the mainboard before and when the failure occurs, so it is very important to monitor the status of the mainboard. However, if the mainboard CPU runs a monitoring program to monitor the status of the mainboard, it is necessary to ensure that the mainboard CPU works normally. Once a failure occurs that affects the normal operation of the CPU, the monitoring work will naturally be unable to continue. In this regard, the embodiment of the present application provides a solution: First, the embodiment provides a mainboard status monitoring circuit 100, see Figure 1 The schematic diagram of the mainboard status monitoring circuit 100 is shown as follows: The mainboard status monitoring circuit 100 includes an MCU 20 , a crystal oscillator circuit 30 , a first power supply circuit 40 , a second power supply circuit 50 , a status acquisition circuit 60 and an information reading circuit 70 .

[0029] Those skilled in the art may understand that, in some other examples of the present embodiment, names such as “crystal oscillator circuit”, “first power supply circuit”, “second power supply circuit”, “status acquisition circuit” and “information reading circuit” may also be replaced with “crystal oscillator module”, “first power supply module”, “second power supply module”, “status acquisition module” and “information reading module”, or “circuit” may be replaced with “unit”.

[0030] MCU20 has a crystal oscillator connection pin, a first power supply pin, a second power supply pin, a status acquisition pin and an information reading pin, which are respectively used to connect to the crystal oscillator circuit 30, the first power supply circuit 40, the second power supply circuit 50, the status acquisition circuit 60 and the information reading circuit 70.

[0031] The crystal oscillator circuit 30 is used to provide a clock signal to the MCU 20 , and the MCU 20 can perform timing and task processing according to the clock signal provided by the crystal oscillator circuit 30 .

[0032] One end of the state acquisition circuit 60 is connected to the state acquisition pin of the MCU20, and the other end is connected to the monitoring point on the monitored mainboard. The state acquisition circuit 60 is used to transmit the electrical signal at the monitored point to the MCU20, so that the MCU20 can convert the analog electrical signal into digital state information and store it. It is undoubted that the monitored mainboard includes a CPU, but in addition to the CPU, the monitored mainboard also includes many other components, such as memory, power management chip, sensor, input / output interface, hard disk interface, basic input / output system (BIOS) chip, etc. In this embodiment, when recording the state information of the monitored mainboard, the MCU20 will record the acquisition time of the state information according to the clock signal provided by the crystal oscillator circuit 30. It can be understood by those skilled in the art that the acquisition time recorded by the MCU20 can be time. For example, after the industrial computer is started, the monitored mainboard synchronizes the real-time time to the MCU20, and the MCU20 subsequently determines the time based on the time synchronized by the monitored mainboard and the clock signal of the crystal oscillator circuit 30.

[0033] The information reading circuit 70 is used to read information from the MCU20. In some examples of the present embodiment, the output end of the information reading circuit 70 can be connected to an external reading device, so that the external reading device can be used to read information from the MCU20 via the information reading circuit 70. In other examples of the present embodiment, the output end of the information reading circuit 70 is connected to the CPU of the monitored mainboard. When the engineering personnel need to read the information in the MCU20, for example, after the mainboard of the industrial computer fails, the engineering personnel need to trace the state of the monitored mainboard in the past period of time. This is because the engineering personnel can directly read the required information from the MCU20 through the CPU of the industrial computer and display the read information through the display screen of the industrial computer. It can be understood by those skilled in the art that, compared with the solution in which the output end of the information reading circuit 70 is connected to the external reading device, in the solution in which the information is read directly through the CPU, there is no need to set up a special interface for connecting the external reading device, nor is there a need to disassemble the industrial computer, and the information reading process is simple and easy.

[0034] The first power supply circuit 40 and the second power supply circuit 50 are both used to supply power to the MCU 20. One end of the first power supply circuit 40 is connected to the power supply of the monitored mainboard, and the other end is connected to the first power pin of the MCU 20, and is used to supply power to the MCU 20 through the power supply. One end of the second power supply circuit 50 is connected to the backup power supply, and the other end supplies power to the MCU 20 through the second power pin. The backup power supply is independent of the power supply of the monitored mainboard, that is, the ability of the backup power supply to provide electrical energy does not depend on the normal operation of the power supply on the monitored mainboard. In some examples of the present embodiment, the backup power supply can be a battery, such as a button battery, a small photovoltaic battery, etc.

[0035] In this embodiment, MCU20 has a first function and a second function, wherein the second function includes a basic status monitoring function, which refers to a function of collecting and recording the status information of the monitored motherboard. The first power supply circuit 40 is used to support MCU20 to implement the first function, and the second power supply circuit 50 is used to support MCU20 to implement the second function, so the basic status monitoring function of MCU20 is powered by the second power supply circuit 50. Since the second power supply circuit 50 is connected to the backup power supply, whether the CPU on the monitored motherboard fails or the power supply is cut off, it will not affect the status monitoring of the monitored motherboard by MCU20. MCU20 can obtain the status information of the monitored motherboard in all scenarios (including the monitored motherboard power supply failure scenario and the monitored motherboard CPU failure scenario), which is conducive to the comprehensive monitoring of the monitored motherboard.

[0036] exist Figure 2FIG. 1 shows a schematic diagram of a chip of MCU 20, which has 48 pins. It is obvious that if other types of MCU 20 are selected in other examples, the schematic diagram of the corresponding MCU 20 can be the same as FIG. Figure 2 Since different parts of the motherboard status monitoring circuit 100 may be presented through different drawings, in order to facilitate the connection relationship between the MCU20 and other circuits in the motherboard status monitoring circuit 100, in this embodiment, the pin number of the MCU20 is "an", and the terminal of other circuits that cooperates with the an pin in the MCU20 is "bn", where the value of n is a natural number between 1 and 48.

[0037] In some examples of this embodiment, the crystal oscillator circuit 30 includes a first crystal oscillator circuit 31 and a second crystal oscillator circuit 32, see Figure 3 and Figure 4 ,in, Figure 3 FIG. 4 is a schematic diagram showing the circuit structure of the first crystal oscillator circuit 31. Figure 4 The circuit structure diagram of the second crystal oscillator circuit 32 is shown. Correspondingly, the MCU 20 has a first crystal oscillator connection pin (eg Figure 2 a3 and a4 in the figure), and a second crystal oscillator connection pin (for example Figure 2 a5 and a6 in the figure). Normally, one of the first crystal oscillator circuit 31 and the second crystal oscillator circuit 32 is used for timing by MCU20, and the other is used for task processing by MCU20 under normal working conditions. For example, in one example, the second crystal oscillator circuit 32 is used to provide a clock signal for timing to MCU20. It can be understood that the realization of the timing function of MCU20 is a necessary condition for the realization of the basic status monitoring function. Therefore, the second crystal oscillator circuit 32 used to help MCU20 realize timing is powered by the second power supply circuit 50, so that it can be ensured that when the power supply of the monitored mainboard cannot be supplied normally, MCU20 can still obtain the clock signal normally for timing. In some examples of this embodiment, the crystal oscillator frequency of the second crystal oscillator circuit 32 is lower than the crystal oscillator frequency of the first crystal oscillator circuit 31. For example, an 8MHz crystal oscillator is used in the first crystal oscillator circuit 31, and a 32KHz crystal oscillator is used in the second crystal oscillator circuit 32.

[0038] Combine the following Figure 5 The second power supply circuit 50 is introduced. Figure 5A circuit diagram of the second power supply circuit 50 shown: the second power supply circuit 50 includes a first diode D1, a second diode D2, a first resistor R1, a second resistor R2 and a first capacitor C1. One end of the first resistor R1 is configured to connect to a backup power supply, and the other end is connected to the anode of the first diode D1. One end of the second resistor R2 is configured to be connected to the power supply of the monitored motherboard, and the other end is connected to the anode of the second diode D2. The cathode of the first diode D1 and the cathode of the second diode D2 are both connected to the first end b1 of the first capacitor C1, and the second end of the first capacitor C1 is grounded. In this embodiment, the first end b1 of the first capacitor C1 is connected to the second power pin a1 of the MCU20. In some examples, the specification of the first capacitor C1 is 1uF / 6.3V.

[0039] according to Figure 5 It can be seen from the provided circuit diagram that in this example, the second power supply circuit 50 has two power supplies, one is the power supply of the monitored mainboard, and the other is the backup power supply. The backup power supply supplies power to MCU20 through the first branch where the first resistor R1 and the first diode D1 are located; the power supply supplies power to MCU20 through the second branch where the second resistor R2 and the second diode D2 are located. Since the voltage of the backup power supply is lower than the voltage of the power supply, when the power supply normally supplies power to MCU20 through the second branch, the power of the backup power supply cannot be output through the first branch. In this way, when the power supply is normal, the power of the backup power supply will not be consumed, which can save the power of the backup power supply and extend the use time of the backup power supply. In some examples of this embodiment, the resistance of the first resistor R1 is higher than the resistance of the second resistor R2. For example, in one example, the voltage of the power supply is 3.3V, the voltage of the backup power supply is lower than 3.3V, the resistance of the first resistor R1 is 1KΩ, and the resistance of the second resistor R2 is almost 0.

[0040] In some examples of this embodiment, the first diode D1 and the second diode D2 may be packaged in one device, for example Figure 5 As shown in the dotted box in , the packaged device has two input terminals and one output terminal, the two input terminals correspond to the anode of the first diode D1 and the anode of the second diode D2, respectively, and the output terminal corresponds to the cathode of the first diode D1 and the second diode D2.

[0041] See below Figure 6A circuit diagram of a first power supply circuit 40 is shown: the first power supply circuit 40 includes a third diode D3, a fourth diode D4 and a second capacitor C2, the third diode D3 and the fourth diode D4 are connected in series, that is, the cathode of the third diode D3 is connected to the anode of the fourth diode D4, one end of the second capacitor C2 is connected between the third diode D3 and the fourth diode D4, and the other end is grounded. The anode of the third diode D3 is connected to the power supply of the monitored motherboard, and the cathode b9 of the fourth diode D4 is connected to the first power pin a9 of MCU20. The first power supply circuit 40 uses the power supply to supply power to MCU20 through the third diode D3 and the fourth diode D4 in sequence. It can be understood that due to the presence of the second capacitor C2, when the power supply starts to supply power to MCU20 through the first power supply circuit 40, the second capacitor C2 needs to be charged first. After the second capacitor C2 is fully charged, the power supply can be supplied to MCU20 through the fourth diode D4. This may affect the startup speed of MCU20 when the motherboard status monitoring circuit 100 is just powered on. In this regard, the present embodiment also provides another first power supply circuit 40, such as Figure 7 As shown, the first power supply circuit 40 is Figure 6 The fifth diode D5 is also included on the basis of the first power supply circuit 40, the anode of the fifth diode D5 is connected to the anode of the third diode D3, and the cathode is connected to the cathode of the fourth diode D4, that is, the fifth diode D5 is connected in parallel with the branch formed by the third diode D3 and the fourth diode D4. In this first power supply circuit 40, when the motherboard status monitoring circuit 100 is powered on, the power supply can directly supply power to the MCU 20 through the branch where the fifth diode D5 is located, and at the same time, the power supply can charge the second capacitor C2 through the third diode D3, and the charging of the second capacitor C2 will not affect the power-on speed of the MCU 20.

[0042] In some examples of this embodiment, the specification of the second capacitor C2 is 560uF / 6.3V, and in some other examples of this embodiment, the second capacitor C2 may also have other specifications. It can be understood by those skilled in the art that when the power supply of the monitored motherboard fails and cannot be powered normally, the electric energy stored in the second capacitor C2 can be released to MCU20, providing a short-term power supply to MCU20, so that MCU20 can switch from the normal working mode to the mode of maintaining only the basic status monitoring function.

[0043] The state acquisition circuit 60 corresponds one-to-one to the state acquisition pin of MCU20, that is, one state acquisition circuit 60 corresponds to one state acquisition pin on MCU20. In this embodiment, the state acquisition circuit 60 can collect at least part of the following state information of the monitored motherboard: the power-on voltage (V12AL) ​​of the monitored motherboard, the bridge chip power supply voltage (V3.3AL), the working voltage of the CPU after power-on (V3.3S), the S3 indication signal indicating that the monitored motherboard enters the sleep state, the S4 indication signal indicating that the monitored motherboard enters the hibernation state, the reset wake-up signal (RSMRST#) indicating that the bridge chip power supply voltage of the monitored motherboard is normal, and the platform reset signal (PLT_RST#) indicating that the CPU has the initialization conditions.

[0044] In some examples, the state acquisition circuit 60 includes a first acquisition circuit, which is used to acquire the power-on voltage of the monitored mainboard, and the MCU 20 has a first acquisition pin a27 corresponding to the first acquisition circuit. Figure 8 The first acquisition circuit includes a third resistor R3, a fourth resistor R4 and a third capacitor C3. The first end of the third resistor R3 is connected to the monitoring point on the monitored motherboard. The fourth resistor R4 is connected in parallel with the third capacitor C3 and connected to the second end b27 of the third resistor R3. The other ends of the fourth resistor R4 and the third capacitor C3 are both grounded. In an example, the resistance of the third resistor R3 is 5.1K, the resistance of the fourth resistor R4 is 1K, and the specification of the third capacitor C3 is 0.1uF / 50V.

[0045] In some examples, the state acquisition circuit 60 includes a second acquisition circuit, which is used to acquire the bridge chip power supply voltage of the monitored motherboard, and the MCU 20 has a second acquisition pin a28 corresponding to the second acquisition circuit. Fig. 9 The second acquisition circuit includes a fifth resistor R5 and a fourth capacitor C4, a first end of the fifth resistor R5 is connected to a monitoring point on the monitored motherboard, a second end b28 is grounded through the fourth capacitor C4, and a second end b28 of the fifth resistor R5 is connected to a second acquisition pin a28 on the MCU20. In an example, the resistance of the fifth resistor R5 is 10K, and the specification of the fourth capacitor C4 is 0.1uF / 16V.

[0046] In some examples, the state acquisition circuit 60 includes a third acquisition circuit for acquiring the working voltage of the CPU after it is powered on, and one end of the third acquisition circuit is connected to the third acquisition pin a29 on the MCU20. Fig.10As shown, the third acquisition circuit includes a sixth resistor R6 and a first MOS tube Q1, one end of the sixth resistor R6 is connected to the monitoring point on the monitored mainboard, the other end is connected to the gate of the first MOS tube Q1, the source of the first MOS tube Q1 is grounded, and the drain b29 is connected to the third acquisition pin a29. In some examples, the third acquisition circuit also includes a seventh resistor R7 and a fifth capacitor C5, the seventh resistor R7 is connected in series with the fifth capacitor C5, the other end of the seventh resistor R7 is connected to MCU20 to power MCU20, the other end of the fifth capacitor C5 is grounded, and the drain b29 of the first MOS tube Q1 is connected between the seventh resistor R7 and the fifth capacitor C5. In one example, the resistance of the sixth resistor R6 is 4.7K, the resistance of the seventh resistor R7 is 5.1K, and the specification of the fifth capacitor C5 is 0.1UF / 50V.

[0047] It can be understood that for the fourth acquisition circuit for collecting the S3 indication signal, there is a corresponding fourth acquisition pin a36 on MCU20; for the fifth acquisition circuit for collecting the S4 indication signal, there is a corresponding fifth acquisition pin a35 on MCU20; similarly, if the state acquisition circuit 60 includes a sixth acquisition circuit for collecting the reset wake-up signal, then there is also a sixth acquisition pin a34 corresponding to the sixth acquisition circuit on MCU20; if the state acquisition circuit 60 includes a seventh acquisition circuit for collecting the platform reset signal, then there is also a seventh acquisition pin a33 corresponding to the seventh acquisition circuit on MCU20. In some examples of this embodiment, the fourth acquisition circuit, the fifth acquisition circuit, the sixth acquisition circuit and the seventh acquisition circuit each include a resistor (respectively the eighth resistor R8, the ninth resistor R9, the tenth resistor R10 and the eleventh resistor R11), one end of these resistors is connected to the monitoring point on the monitored motherboard, and the other end (b36, b35, b34, b33) is respectively connected to the corresponding state acquisition pins on MCU20, such as Fig.11 shown.

[0048] In some examples, the information reading circuit 70 has an input terminal b13 connected to the information reading pin a13 on the MCU20 and an output terminal connected to the CPU, and also has a reading control terminal, which is used to control the input terminal b13 to be connected to the output terminal according to an input valid control signal, so that the CPU can read information from the MCU20. Fig.12 The information reading circuit 70 shown: the information reading circuit 70 includes two MOS tubes, the sources of the two MOS tubes are connected together, the two gates are used as reading control terminals, and one of the two drains is used as the input terminal b13 of the information reading circuit 70, connected to the information reading pin a13 on the MCU20, and the other drain is used as the output terminal of the information reading circuit 70, connected to the CPU.

[0049] In some examples, the motherboard status monitoring circuit 100 further includes an information writing circuit, see Fig.13 As shown, the information writing circuit is used for the CPU to write information into the MCU20. The input end of the information writing circuit is connected to the CPU, and the output end b12 is connected to the information writing pin a12 of the MCU20. The information writing circuit also includes a writing control end, which can control the on-off between the input end and the output end b12 of the information writing circuit according to the input control signal. When the writing control end receives a valid control signal, the input end is connected to the output end b12, and the information sent by the CPU can be written into the MCU20 normally. In some examples, the circuit structure of the information writing circuit is similar to that of the information reading circuit 70: the information reading and writing circuit includes two MOS tubes, the sources of the two MOS tubes are connected together, and the two gates are used as the writing control end, and one of the two drains is used as the output end b12 of the information reading circuit, which is connected to the information writing pin a12 on the MCU20, and the other drain is used as the input end of the information writing circuit and connected to the CPU.

[0050] Normally, in addition to MCU20, peripherals are also connected to the CPU, and information is exchanged between the peripherals and the CPU. From the perspective of the CPU, the CPU may need to write information to the peripherals, or may need to read information from the peripherals. Therefore, in some examples, the monitored mainboard also includes a peripheral read circuit and a peripheral write circuit. The peripheral read circuit includes a read control terminal, which can control the on-off between the input terminal and the output terminal of the peripheral read circuit according to the input control signal. When the input control signal is a valid signal, the input terminal and the output terminal are connected to read the information in the peripheral to the CPU. The peripheral write circuit also includes a write control terminal, which is configured to control the on-off between the input terminal and the output terminal of the peripheral write circuit according to the control signal of the input write control terminal. When the input terminal and the output terminal of the peripheral write circuit are connected, the information sent by the CPU can be written into the peripheral. In this embodiment, the circuit structure of the peripheral write circuit is similar to the circuit structure of the information write circuit, that is, similar to Fig.13 ; The circuit structure of the peripheral reading circuit is similar to the circuit structure of the information reading structure, that is, similar to Fig.12 Therefore, the circuit structure diagram of the peripheral reading circuit and the peripheral writing circuit is not specifically shown here.

[0051] In some examples of this embodiment, the pins corresponding to the information reading circuit 70 between MCU20 and CPU on the CPU are independent of the pins corresponding to the peripheral reading circuit and the peripheral writing circuit on the CPU. In this way, the peripheral information will not be written into MCU20, nor will the information in MCU20 be read into the peripheral. However, it can be understood that in this case, four independent pins are needed on the CPU, corresponding to the information reading circuit 70, the information writing circuit, the peripheral reading circuit, and the peripheral writing circuit, respectively.

[0052] In other examples, the peripheral read circuit and the information read circuit are connected to the same read pin of the CPU, and the peripheral write circuit and the information write pin are connected to the same write pin of the CPU. In this case, only two independent pins are needed on the CPU, namely a read pin and a write pin, to achieve the connection with the information read circuit 70, the information write circuit, the peripheral read circuit, and the peripheral write circuit. It can be understood by those skilled in the art that in this case, there may be a situation where the information of MCU20 is read into the peripheral, or the information in the peripheral is read into MCU20, resulting in interference between MCU20 and the peripheral.

[0053] In order to avoid the problem of information interference between the MCU 20 and the peripherals, in some examples of this embodiment, the mainboard status monitoring circuit 100 further includes a selection circuit 80. Fig.14 As shown, the selection circuit 80 includes a first output terminal 81, a second output terminal 82 and a selection control terminal 83, wherein the first output terminal 81 is simultaneously connected to the read control terminal of the information reading circuit 70 and the write control terminal of the information writing circuit, and the second output terminal 83 is simultaneously connected to the read control terminal of the peripheral reading circuit and the write control terminal of the peripheral writing circuit. The selection control terminal 83 is connected to the CPU for receiving a control signal from the CPU.

[0054] If the CPU outputs the first control signal to the selection control terminal 83, the first output terminal 81 will output the MCU valid signal, and the second output terminal 82 will output the peripheral invalid signal. At this time, the read control terminal of the information reading circuit 70 and the write control terminal of the information writing circuit both receive the MCU valid signal, so the input terminal and the output terminal of the information reading circuit 70 will be connected, and the input terminal and the output terminal of the information writing circuit will also be connected. In this case, the CPU can read information from the MCU20 through the information reading circuit 70, including the state information collected by the state acquisition circuit 60 and the acquisition time of the state information. In addition, the CPU can also write the information that needs to be written into the MCU20 into the MCU20 through the information writing circuit. Since the second output terminal 82 of the selection circuit 80 outputs a peripheral invalid signal, the read control terminal of the peripheral read circuit and the write control terminal of the peripheral write circuit connected to the second output terminal 82 both receive the peripheral invalid signal, and the input terminal and the output terminal of the peripheral read circuit will not be connected, and the input terminal and the output terminal of the peripheral write circuit will not be connected. Therefore, although the information read circuit 70 is connected to the peripheral read circuit and the information write circuit is connected to the peripheral write circuit, there will be no interference between the peripheral and MCU20.

[0055] If the CPU outputs a second control signal to the selection control terminal 83, the first output terminal 81 will output an MCU invalid signal, and the second output terminal 82 will output a peripheral valid signal. The read control terminal of the peripheral read circuit and the write control terminal of the peripheral write circuit both receive peripheral valid signals. Therefore, the peripheral read circuit will connect its input terminal and output terminal according to the peripheral valid signal, so that the CPU can read information from the peripheral; the peripheral write circuit will also connect its input terminal and output terminal according to the peripheral valid signal, so that the CPU can write information to the peripheral. On the other hand, in MCU20, since the first output terminal 81 of the selection circuit 80 outputs an MCU invalid signal to the read control terminal of the information read circuit 70 and the write control terminal of the information write circuit, the input terminal and output terminal of the information read circuit 70 will not be connected, and the input terminal and output terminal of the information write circuit will not be connected. Therefore, although the information read circuit 70 and the peripheral read circuit share the read pin on the CPU, and the information write circuit and the peripheral write circuit share the write pin on the CPU, information will not be transmitted between MCU20 and the peripheral.

[0056] In some examples, the first control signal is a high level signal (represented by "1" in this embodiment), and the second control signal is a low level signal (represented by "0" in this embodiment). When the CPU outputs a high level 1 to the selection circuit 80, the first output terminal 81 outputs a high level 1, and the second output terminal 82 outputs a low level 0. The high level 1 of the first output terminal 81 connects the input terminal and the output terminal of the information reading circuit 70, and connects the input terminal and the output terminal of the information writing circuit; the low level 0 of the second output terminal 82 prohibits the input terminal and the output terminal of the peripheral reading circuit from being connected, and prohibits the input terminal and the output terminal of the peripheral writing circuit from being connected. When the CPU outputs a low level 0 to the selection circuit 80, the first output terminal 81 outputs a low level 0, and the second output terminal 82 outputs a high level 1. The high level 1 of the second output terminal 82 connects the input terminal and the output terminal of the peripheral reading circuit, and connects the input terminal and the output terminal of the peripheral writing circuit; at the same time, the low level 0 of the first output terminal 81 prohibits the input terminal and the output terminal of the information reading circuit 70 from being connected, and prohibits the input terminal and the output terminal of the information writing circuit from being connected.

[0057] This embodiment also provides a motherboard, which includes a mainboard and a mainboard status monitoring circuit 100 provided in any of the above examples, and the mainboard is used as a monitored mainboard, and the mainboard status monitoring circuit 100 performs status monitoring. The mainboard includes a mainboard body and a CPU, a memory, a hard disk interface, etc. arranged on the mainboard body.

[0058] In some examples of this embodiment, the motherboard status monitoring circuit 100 is disposed on the motherboard body and is also carried by the motherboard body. In other examples, the motherboard status monitoring circuit 100 can also be disposed on a separate small substrate, which can be fixed to the motherboard body by means of clamping, screwing or even bonding.

[0059] In some examples, the mainboard status monitoring circuit 100 has its own backup power supply. A battery mounting slot is provided on the small substrate of the mainboard status monitoring circuit 100. A button battery is installed in the battery mounting slot as a backup power supply. When the button battery is low on power, a new button battery can be replaced and installed.

[0060] The motherboard status monitoring circuit 100 and the motherboard including the motherboard status monitoring circuit 100 provided in the embodiment of the present application are low-cost, and at the same time, the status monitoring is more comprehensive and the monitoring function is more stable and reliable.

[0061] As described above, the above embodiments are only used to introduce the technical solution of the present application in detail, but the description of the above embodiments is only used to help understand the method and core idea of ​​the present application and should not be understood as limiting the present application. Any changes or substitutions that can be easily thought of by technicians in this technical field within the technical scope disclosed in the present application should be included in the protection scope of the present application.

Claims

1. A motherboard status monitoring circuit, characterized in that: The mainboard status monitoring circuit comprises: MCU, the MCU includes a crystal oscillator connection pin, a first power pin, a second power pin, a status acquisition pin and an information reading pin, the MCU has a first function and a second function, the second function includes monitoring the status of a monitored motherboard, the monitored motherboard includes a CPU and a power supply; A crystal oscillator circuit connected to the crystal oscillator connection pin; a first power supply circuit connected to the first power pin, the other end of the first power supply circuit being connected to the power supply, and the first power supply circuit being used to support the MCU to implement a first function; a second power supply circuit connected to the second power supply pin, the other end of the second power supply circuit being connected to a backup power supply, the backup power supply being independent of the power supply, and the second power supply circuit being used to support the MCU to implement a second function; A state acquisition circuit corresponding to the state acquisition pins one by one, wherein one end of the state acquisition circuit is connected to the state acquisition pins, and the other end of the state acquisition circuit is connected to a monitoring point on the monitored motherboard; and The input end is connected to the information reading pin to read the information reading circuit in the MCU. The information in the MCU includes the state information collected by the state acquisition circuit recorded by the MCU according to the clock signal provided by the crystal oscillator circuit, and the acquisition time of the state information.

2. The motherboard status monitoring circuit according to claim 1, characterized in that: The crystal oscillator connecting pins include a first crystal oscillator connecting pin and a second crystal oscillator connecting pin, and the crystal oscillator circuit includes: a first crystal oscillator circuit connected to the first crystal oscillator connection pin; A second crystal oscillator circuit is connected to the second crystal oscillator connection pin, and the crystal oscillator frequency of the second crystal oscillator circuit is lower than the crystal oscillator frequency of the first crystal oscillator circuit, and the second crystal oscillator circuit is powered by the second power supply circuit.

3. The motherboard status monitoring circuit according to claim 1, characterized in that: The voltage of the backup power supply is lower than the voltage of the power supply, and the second power supply circuit comprises: a first diode; a first resistor connected between the backup power supply and the anode of the first diode; A second diode; a second resistor connected between the power supply and the anode of the second diode; and A first capacitor, wherein a first end of the first capacitor is connected to the cathode of the first diode and the cathode of the second diode at the same time, a second end is grounded, and the first end is connected to the second power supply pin.

4. The motherboard status monitoring circuit according to claim 1, characterized in that: The first power supply circuit comprises: a third diode, wherein an anode of the third diode is connected to the power supply; a fourth diode having an anode connected to a cathode of the third diode, wherein the cathode of the fourth diode is connected to the first power supply pin; and A second capacitor is connected between the cathode of the third diode and ground.

5. The motherboard status monitoring circuit according to claim 4, characterized in that: The first power supply circuit further includes: A fifth diode, wherein an anode of the fifth diode is connected to the anode of the third diode, and a cathode of the fifth diode is connected to the cathode of the fourth diode.

6. The motherboard status monitoring circuit according to claim 1, characterized in that: The state acquisition circuit includes at least one of the following: A first acquisition circuit is configured to acquire the power-on voltage of the monitored mainboard; A second acquisition circuit is configured to acquire the bridge chip power supply voltage of the monitored mainboard; A third acquisition circuit is configured to acquire the operating voltage of the CPU after it is turned on; A fourth acquisition circuit is configured to acquire an S3 indication signal indicating that the monitored mainboard enters a sleep state; A fifth acquisition circuit is configured to acquire an S4 indication signal indicating that the monitored mainboard enters a dormant state; A sixth acquisition circuit is configured to acquire a reset wake-up signal indicating that the bridge chip power supply voltage of the monitored mainboard is normal; The seventh state acquisition circuit is configured to acquire a platform reset signal indicating that the CPU has met the initialization condition.

7. The motherboard status monitoring circuit according to any one of claims 1 to 6, characterized in that: The output end of the information reading circuit is connected to the CPU, and the information reading circuit also includes a reading control end, which is configured to control the connection between the input end and the output end of the information reading circuit according to the MCU effective signal, so that the CPU can read information from the MCU.

8. The motherboard status monitoring circuit according to claim 7, characterized in that: The MCU also includes an information write pin; the mainboard status monitoring circuit also includes an information write circuit, the information write circuit includes a write control end, an input end connected to the CPU, and an output end connected to the information write pin, and the write control end is configured to write the information sent by the CPU into the MCU according to the MCU valid signal.

9. The motherboard status monitoring circuit according to claim 8, characterized in that: The monitored motherboard further comprises a peripheral device reading circuit and a peripheral device writing circuit, wherein the peripheral device reading circuit and the information reading circuit are connected to the same reading pin of the CPU, and the peripheral device writing circuit and the information writing pin are connected to the same writing pin of the CPU; the peripheral device reading circuit comprises a reading control terminal, configured to read the information in the peripheral device to the CPU according to the peripheral device valid signal input to the reading control terminal; the peripheral device writing circuit comprises a writing control terminal, configured to write the information sent by the CPU to the peripheral device according to the peripheral device valid signal input to the writing control terminal; The mainboard status monitoring circuit further includes a selection circuit, and the selection circuit includes: A first output terminal, wherein the first output terminal is connected to the read control terminal and the write control terminal at the same time; a second output terminal, the second output terminal being connected to the read control terminal and the write control terminal at the same time; and A selection control terminal connected to the CPU; The selection circuit is configured to control the first output terminal to output an MCU valid signal and control the second output terminal to output a peripheral invalid signal according to a first control signal output by the CPU to the selection control terminal; the selection circuit is also configured to control the second output terminal to output a peripheral valid signal and control the first output terminal to output an MCU invalid signal according to a second control signal output by the CPU to the selection control terminal.

10. A motherboard, characterized in that: include: A mainboard, the mainboard comprising a mainboard body, a CPU and a power supply arranged on the mainboard body, the power supply being used to supply power to the CPU; The mainboard status monitoring circuit according to any one of claims 1 to 9, wherein the mainboard status monitoring circuit is configured to perform status monitoring on the mainboard.

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