A dual-code partition security method, device and chip based on multi-block configuration

Abstract

The present application provides a chip security configuration method, device and chip based on multiple blocks, including: allocating on-chip security resources to corresponding security partitions through dedicated security OTPs, each dedicated security OTP includes multiple blocks, and each block stores security configuration attributes of on-chip security resources; determining valid blocks from multiple blocks of the corresponding security partition through block link pointers in each dedicated security OTP to determine valid security configuration attributes; loading its valid security configuration attributes into a dual-code security controller through each dedicated security OTP, and providing corresponding security configuration information to the on-chip security resources and the main core processor through the dual-code security controller to control chip operation; based on the flexible configuration of on-chip security resources, the present application can also select the valid configuration of each security partition through the block link pointer, thereby realizing flexible configuration of security mode and greatly improving the utilization rate of on-chip security resources.

Description

Technical Field

[0001] The present application relates to the technical field of chip partition design, and in particular to a chip security configuration method, device and chip based on multiple blocks. Background Art

[0002] Chips are widely used in various fields, including computers, communications, consumer electronics, medical treatment, Internet of Things, and industrial control. Chips include many security resources. In order to protect the security resources in the chip (such as data, programs, or other security devices in the memory) from being accessed by unauthorized personnel, the chip usually sets part of the memory or other security devices as special security resources separately, which cannot be accessed by unauthorized personnel.

[0003] In practice, different users have different requirements for the security resources to be protected. If fixed memory space or other security devices on a chip are allocated as special security resources, it cannot flexibly meet the needs of users and will cause a waste of security resource space. Summary of the invention

[0004] The present application provides a chip security configuration method, device, electronic device and storage medium based on multiple block areas. On the basis of flexibly configuring the on-chip security resources through two security partitions, the effective security attribute configuration of each security partition can be selected through the block area link pointer, which not only meets the user's usage needs, but also realizes the flexible configuration of the security mode, greatly improving the utilization rate of the on-chip security resources.

[0005] In a first aspect, an embodiment of the present application provides a chip security configuration method based on multiple blocks, which is applied to a dual-code partition security device, wherein the dual-code partition security device includes a dual-code security controller, a one-time programmable OTP, a main core processor, and an on-chip security resource; the OTP, the main core processor, and the on-chip security resource are respectively communicated with the dual-code security controller; the chip includes two security partitions and each security partition corresponds to a dedicated security OTP; the method includes:

[0006] The on-chip security resources are allocated to the corresponding security partitions through the dedicated security OTP, and the security configuration attributes for the on-chip security resources in each security partition are obtained; wherein the on-chip security resources allocated to different security partitions are different, and the security configuration attributes of each security partition are stored in the dedicated security OTP of the security partition; each dedicated security OTP includes a plurality of blocks, and each block stores the security configuration attributes of the on-chip security resources; the dedicated security OTP of each security partition also includes a block link pointer exclusive to the security partition;

[0007] By configuring the block link pointer of each security partition, a valid block is selected from a plurality of blocks of the corresponding security partition, and a valid security configuration attribute is determined through the valid block;

[0008] Each dedicated security OTP is used to load the effective security configuration attributes of its corresponding security partition into the dual-code security controller, and the dual-code security controller and the effective security configuration attributes of each security partition loaded therein are used to provide corresponding security configuration information for the on-chip security resources and the main core processor, respectively, and control the operation of the chip based on the security configuration information.

[0009] In a possible implementation, the on-chip security resources include an on-chip host, an on-chip slave, and a memory, and the memory is pre-divided into a plurality of memory spaces;

[0010] The security configuration attributes include at least a partition password, partition attributes of the on-chip security resources, and an execute-only protection function configuration for the memory space in the memory; wherein, when any memory space enables the execute-only protection function configuration, data in the memory space is not allowed to be read or written, but data in the memory space is allowed to be read and written by a specified security code program; the specified security code program is a code program that is pre-configured for the security partition where the memory space is located and stored in the read-only memory ROM of the security partition.

[0011] In a possible implementation, when the on-chip security resource is allocated to any security partition, the on-chip security resource is encrypted based on a partition password of the security partition;

[0012] The chip is also used to connect to a debugger and debug the chip through the debugger; the encrypted on-chip security resources in the security partition are configured to be read accessed according to a specified security access configuration: when the chip is connected to the debugger, if the encrypted on-chip security resources in the security partition are not semi-decrypted, data access and instruction fetch access to the on-chip security resources in the security partition are not allowed, and the debugger's debugging connection to the chip is interrupted.

[0013] In a possible implementation, the partition password in each secure partition further includes a semi-decrypted password; and the method further includes:

[0014] Semi-decrypting each security partition using the semi-decryption password of the security partition; wherein after the semi-decryption, the encrypted on-chip security resources in each security partition are configured to be read-accessed according to the specified security access configuration: the specified security access configuration of the encrypted on-chip security resources in each security partition is the same as the encryption state when the debugger is not connected;

[0015] At the same time, after semi-decryption, the debugger's reading and writing of the encrypted on-chip slave or memory space in the secure partition is invalid, and the debugger's debugging connection to the chip is maintained when the security protection condition is not triggered; when the triggering of the security protection condition is detected, the debugger's debugging connection to the chip is interrupted; wherein the triggering of the security protection condition at least includes: the program running in the secure partition is stopped.

[0016] In a possible implementation, corresponding security configuration information is provided for the on-chip security resources and the main core processor respectively through the dual-code security controller and the effective security configuration attributes of each security partition loaded therein, including:

[0017] Generate, by the dual-code security controller, security configuration information corresponding to the on-chip security resources and the main core processor based on the security configuration attributes of each security partition loaded by the dual-code security controller, and send the security configuration information to the on-chip security resources and the main core processor respectively;

[0018] The security configuration information of the main core processor and the on-chip host includes: security partition information of each on-chip slave and on-chip memory space, and the partition information of each on-chip slave and on-chip memory space is composed of two bits;

[0019] The security configuration information of the memory includes: security partition information of each memory space and execution-only protection function attribute enabling information; the security partition information of each memory space and execution-only protection function attribute enabling information are composed of three bits;

[0020] The security configuration information of the on-chip slave includes security partition information of the on-chip slave, and the security partition information of the on-chip slave consists of two bits.

[0021] In a possible implementation, configuring a block link pointer of each security partition, selecting a valid block from a plurality of blocks of the corresponding security partition, and determining a valid security configuration attribute through the valid block include:

[0022] The mapping relationship between the block link pointer of each security partition and the multiple blocks in the security partition is configured in the dual-code security controller; wherein each group of OTP mapping addresses in the dedicated security OTP corresponds to a block, and each block stores a security configuration attribute of a security resource within a piece;

[0023] By configuring the block link pointer of each security partition and combining the mapping relationship, a valid block is determined from multiple blocks of the security partition, and a valid security configuration attribute is determined through the valid block.

[0024] In one possible implementation, each dedicated secure OTP includes a plurality of block link pointers, the plurality of block link pointers corresponding to a plurality of values, the plurality of values ​​using bit-by-bit voting logic to form a final value of a hardware parsing pointer, and the valid block is determined by combining the final value with the mapping relationship; wherein, when the values ​​of the plurality of block link pointers are different, an error status prompt is given in a status register.

[0025] In one possible implementation, based on the characteristic that the dedicated security OTP is all 1s in the default state and the number of blocks in the corresponding security partition, the number of bits of the block link pointer is defined and the valid block is specified from multiple blocks by the position of the highest 0 bit in the block link pointer.

[0026] In a possible implementation manner, the dual-code security controller and the dedicated security OTP are connected using a private bus, so as to complete the loading of data from the dedicated security OTP to the dual-code security controller in an invisible condition.

[0027] In a possible implementation, the method further includes:

[0028] A preset loading mechanism is configured for the dual-code security controller, so that the dual-code security controller loads the security configuration information in the on-chip security resources and the main core processor based on the preset loading mechanism, and after the loading is completed, controls the operation of the chip based on the security configuration information; the preset loading mechanism includes the loading order of each area and the corresponding processing method;

[0029] Among them, after the chip is powered on, the loading is carried out according to the loading order of each area in the preset loading mechanism and the loading completion signal is in an invalid state. When the previous area loading data completion indication signal is valid, it is determined whether the current data loading is completed according to the private bus loading address of the dedicated security OTP and the address of this area; for the first block area link pointer of the first security partition loaded by the first loading address, the previous area loading data completion indication signal is always in a valid state; wherein, compared with the public area loading, the block area loading has an additional set of valid address selection logic.

[0030] In a possible implementation, the method further includes:

[0031] Resetting the block link pointer through the dual code security controller to switch the valid block to a new valid block, and causing the dual code security controller to load the on-chip security resources and the security configuration information in the main core processor based on a security loading mechanism;

[0032] When the dual-code security controller hardware is implemented, when completing the last step of the security loading process, the specified configuration information in the security configuration information is synchronously loaded; the specified configuration information includes: the password visible configuration of each of the two security partitions, the other security configurations of each of the two security partitions, the execution-only configuration of each of the two security partitions, and the partition attributes of each of the two security partitions.

[0033] In a possible implementation, the security configuration attributes of each security partition are burned into a dedicated security OTP of each security partition, and each dedicated security OTP is decrypted based on a partition password of the corresponding security partition before burning.

[0034] In a possible implementation manner, the dual-code security controller decrypts the security partition in the following manner:

[0035] For each security partition, the dual code security controller loads multiple block link pointers of the security partition based on its private bus connected to the dedicated security OTP of the security partition;

[0036] Calculate the valid block area of ​​the security partition based on the multiple block area link pointers by the dual code security controller;

[0037] Loading the partition password of the security partition based on the private bus through the dual-code security controller;

[0038] By writing a decryption password to a decryption register in the dual code security controller;

[0039] Determine whether the decryption password of the decryption register is the same as the partition password of the security partition; if they are the same, complete the decryption; if they are different, return to the step of writing the decryption password to the dual-code security controller until the decryption is completed or the decryption function is exited;

[0040] The fully decrypted partition password is 128 bits; the semi-decrypted password is a part of the partition password and is 64 bits.

[0041] In a second aspect, an embodiment of the present application further provides a chip security configuration device based on multiple blocks, including a dual-code security controller, a one-time programmable OTP, a main core processor, and an on-chip security resource; the OTP, the main core processor, and the on-chip security resource are respectively connected to the dual-code security controller for communication;

[0042] The dual-code partition security device is used to execute the chip security configuration method based on multiple blocks as described in any one of the first aspects.

[0043] In the third aspect, an embodiment of the present application also provides a chip, including a dual-code partition security device, the dual-code partition security device includes a dual-code security controller, a one-time programmable OTP, a main core processor and on-chip security resources; the OTP, the main core processor and the on-chip security resources are respectively communicated and connected with the dual-code security controller; the chip includes two security partitions and each security partition corresponds to a dedicated security OTP; the chip executes the chip security configuration method based on multiple blocks described in any one of the first aspects through the dual-code partition security device.

[0044] The embodiment of the present application provides the above-mentioned chip security configuration method, device and chip based on multiple blocks. The method includes: the chip includes two security partitions and each security partition corresponds to a dedicated security OTP, and the dedicated security OTP is used to allocate on-chip security resources to the corresponding security partition to obtain the security configuration attributes of each security partition; because the dedicated security OTP of each security partition is configured with an exclusive block link pointer, the block link pointer of each security partition can determine the valid block from the multiple blocks of the corresponding security partition, and determine the valid security configuration attributes through the valid block; then, the valid security configuration attributes of the corresponding security partition are loaded into the dual-code security controller through each dedicated security OTP, and the dual-code security controller and the valid security configuration attributes of each security partition loaded by it provide corresponding security configuration information for the on-chip security resources and the main core processor, respectively, and control the operation of the chip based on the security configuration information. In this way, on the basis of flexibly configuring the on-chip security resources through two security partitions, the effective security attribute configuration of each security partition can also be selected through the block link pointer, which not only meets the user's usage needs, but also realizes the flexible configuration of the security mode, greatly improving the utilization rate of the on-chip security resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0046] Figure 1 A flowchart of a chip security configuration method based on multiple blocks provided in an embodiment of the present application is shown;

[0047] Figure 2 A schematic diagram of a distributed implementation of a dual-code partition security device is shown;

[0048] Figure 3A schematic diagram of the security configuration architecture within a dedicated secure OTP is shown;

[0049] Figure 4 A logic flow chart of secure partition decryption / semi-decryption is shown;

[0050] Figure 5 The overall logic diagram of the decryption process is shown;

[0051] Figure 6 A valid schematic diagram of a disconnected simulation link is shown. DETAILED DESCRIPTION

[0052] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of explanation and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn in real proportion. The flowchart used in this application shows the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowchart can be implemented out of sequence, and the steps without logical context can be reversed in order or implemented simultaneously. In addition, those skilled in the art can add one or more other operations to the flowchart under the guidance of the content of the present application, or remove one or more operations from the flowchart.

[0053] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0054] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.

[0055] Chips are widely used in various fields, including computers, communications, consumer electronics, medical treatment, the Internet of Things, and industrial control. The chip includes many security resources, and different users have different security resource requirements to be protected. If fixed memory space or other security devices on the chip are allocated as special security resources, it cannot flexibly meet the needs of users and will cause a waste of security resource space. Based on this, the embodiment of the present application provides a chip security configuration method, device, and chip based on multiple blocks, which can flexibly configure security resources on the chip through two security partitions, which can not only meet the needs of users, but also improve the utilization rate of security resources on the chip.

[0056] like Figure 1 As shown, the embodiment of the present application provides a chip security configuration method based on multiple blocks, which is applied to a dual-code partition security device, wherein the dual-code partition security device includes a dual-code security controller, a one-time programmable OTP, a main core processor, and an on-chip security resource; the OTP, the main core processor, and the on-chip security resource are respectively connected to the dual-code security controller in communication; the chip includes two security partitions and each security partition corresponds to a dedicated security OTP; the method includes:

[0057] S101, allocating the on-chip security resources to the corresponding security partitions through the dedicated security OTP, and obtaining security configuration attributes for the on-chip security resources in each security partition; wherein different security partitions are allocated different on-chip security resources, and the security configuration attributes of each security partition are stored in the dedicated security OTP of the security partition; each dedicated security OTP includes a plurality of blocks, and each block stores the security configuration attributes of the on-chip security resources; the dedicated security OTP of each security partition also includes a block link pointer exclusive to the security partition;

[0058] S102, by configuring the block link pointer of each security partition, selecting a valid block from multiple blocks of the corresponding security partition, and determining a valid security configuration attribute through the valid block;

[0059] S103. Load the effective security configuration attributes of the corresponding security partition into the dual-code security controller through each dedicated security OTP, and provide corresponding security configuration information for the on-chip security resources and the main core processor respectively through the dual-code security controller and the effective security configuration attributes of each security partition loaded therein, and control the operation of the chip based on the security configuration information.

[0060] In the above-mentioned chip security configuration method based on multiple blocks, on-chip security resources are allocated to the corresponding security partitions through a dedicated security OTP to obtain the security configuration attributes of each security partition; since the dedicated security OTP of each security partition is configured with an exclusive block link pointer, the block link pointer of each security partition can determine the valid block from the multiple blocks of the corresponding security partition, and determine the valid security configuration attributes through the valid block; then, the valid security configuration attributes of its corresponding security partition are loaded into the dual-code security controller through each dedicated security OTP, and the dual-code security controller and the valid security configuration attributes of each security partition loaded thereon are used to provide corresponding security configuration information for the on-chip security resources and the main core processor, respectively, and the chip operation is controlled based on the security configuration information. In this way, on the basis of flexibly configuring the on-chip security resources through two security partitions, the effective security attribute configuration of each security partition can also be selected through the block link pointer, which not only meets the user's usage needs, but also realizes the flexible configuration of the security mode, greatly improving the utilization rate of the on-chip security resources.

[0061] The following is an example of a chip security configuration method based on multiple blocks:

[0062] In the present application, the above-mentioned chip security configuration method based on multiple blocks is applied to a dual-code partition security device, which includes a dual-code security controller, OTP (One Time Programmable), a main core processor and on-chip security resources; the OTP, the main core processor and the on-chip security resources are respectively communicated with the dual-code security controller; in addition, the chip is also used to connect to a debugger, and when it is connected to the debugger, the chip is debugged (i.e., simulated) through the debugger.

[0063] Specifically, the dual-code partition security device in this application is a security function device in the chip, which prevents unauthorized personnel from accessing and viewing the on-chip security resources on the chip (also referred to as on-chip), and can also prevent the copying and reverse engineering of patent codes. Security partition encryption means that access to on-chip security resources on the chip (such as on-chip security memory) is restricted, and security partition decryption or configuration of on-chip security resources (such as on-chip security memory) as non-security partitions means that access is allowed (the contents of the memory can be read in any way).

[0064] Dual-code partitioning means that if configured as a secure mode, the on-chip secure resources can be set to partition 1 and partition 2; in addition, the on-chip secure resources can also be set to a non-secure mode. The on-chip secure resources include an on-chip host, an on-chip slave (where the device initiating access is the on-chip host, and the device being accessed is the on-chip slave) and memory; the memory includes: Flash memory, SRAM memory, etc. Among them, the above memory is pre-divided into multiple memory spaces. Specifically, the memory can be divided into multiple memory spaces by access address, and each memory space can independently configure its security attributes.

[0065] Here, the configurable security permission devices (i.e. the above-mentioned on-chip security resources) include: on-chip host, on-chip slave and memory (the memory space of each memory can independently define security partitions). In a multi-core chip architecture, the on-chip host can be a slave core or other master device; in a multi-core processor, the master core is the main processor and the slave core is other processors; the master core and the debugging device do not have the configuration attributes of the security partition, and their access to the on-chip security resources depends on the configuration of the dual-code partition security device on the on-chip security resources.

[0066] The dual code security mechanism provides protection for two security partitions, namely security partition 1 and security partition 2. The security mechanism of the two security partitions is the same. Each security partition has its own dedicated security resources (including dedicated security OTP and allocated on-chip security resources). The following 1-4 are the different security resources available on-chip in each security partition:

[0067] 1. One-time programmable storage (OTP): According to the two security partitions pre-configured in the chip, a dedicated security OTP is allocated to each security partition, and each security partition corresponds to a dedicated security OTP. Each dedicated security OTP contains the security configuration attributes of the security partition to which it belongs. If the on-chip security resource configuration belongs to a certain security partition (security partition 1 or security partition 2), the content of the OTP (including the security partition password) can only be accessed when the partition password of the security partition is used to unlock the security partition. Specifically, the on-chip security resources are allocated to the corresponding security partition through the dedicated security OTP, and the security configuration attributes for the on-chip security resources in each security partition are obtained; wherein the security configuration attributes of each security partition are stored in the dedicated security OTP of the security partition, and the security configuration attributes at least include the partition password and the partition attributes of the on-chip security resources; wherein, the on-chip security resources allocated to different security partitions are different, which can also be understood as that the same on-chip security resource cannot be allocated to two security partitions at the same time. After obtaining the security configuration attributes of each security partition, the security configuration attributes of its corresponding security partition are loaded into the dual-code security controller through each dedicated security OTP.

[0068] The dedicated secure OTP for each secure partition contains:

[0069] 1) Block link pointer for each security partition; wherein each dedicated security OTP includes multiple blocks, each of which stores security configuration attributes of a security resource within a chip; each dedicated security OTP for a security partition also includes a block link pointer exclusive to the security partition, and by configuring the block link pointer for each security partition, a valid block is selected from multiple blocks of the corresponding security partition, and the valid security configuration attributes are determined through the valid block; then, the valid security configuration attributes of the corresponding security partition are loaded into the dual-code security controller through each dedicated security OTP, and the dual-code security controller and the valid security configuration attributes of each security partition loaded thereon provide corresponding security configuration information for the security resources within the chip and the main core processor, respectively, and the chip operation is controlled based on the security configuration information;

[0070] 2) Security configuration attributes of on-chip security resources, including partition passwords and partition attribute settings of each security resource;

[0071] 3) Execute-only mode setting (i.e., execution-only protection function configuration for the memory space in the memory).

[0072] 2. On-chip host: The on-chip host has security resource attributes (that is, it has security configuration attributes). In a multi-core processor chip, it is usually an additional core. The user can divide the on-chip host into any security partition by editing the dedicated security OTP.

[0073] 3. On-chip memory: usually includes flash and ram, which can be divided into multiple memory spaces. Each memory space has its own configuration bit in the dedicated security OTP of the corresponding security partition. Users can divide each memory space into different security partitions by editing the dedicated security OTP.

[0074] 4. On-chip slave: The on-chip slave has security resource attributes (that is, it has security configuration attributes). Users can divide the on-chip slave into any security partition by editing the dedicated security OTP.

[0075] Specifically, the security protection configuration based on the above dual-code partition security device includes the following 1-2:

[0076] 1. Partition configuration:

[0077] For the on-chip host, on-chip memory, and on-chip slave, each on-chip security resource can be edited by the user to divide the security partition; the on-chip security resource is described by two bits in the corresponding security partition. That is, in each security partition, there are two bits describing the security configuration of the on-chip resource in this security partition:

[0078] Bit 00: inaccessible;

[0079] Bit 01: belongs to the security partition;

[0080] Bit 10 / 11: does not belong to this security partition;

[0081] After the dedicated security OTP in security partition 1 or security partition 2 is configured, the partition division of each security resource is shown in Table 1:

[0082] .

[0083] In the above Table 1, XX represents any two special data. Here, it should be noted that when the configurations of the security partition 1 and the security partition 2 are both 01, it is an invalid configuration.

[0084] 2. Execute configuration only:

[0085] This configuration is only valid for on-chip memory: here, the memory configured with the "execution protection function only attribute" is a secure memory, and the data stored in the secure memory is the instruction code of the processor (the instruction code can also be understood as a program or code). When any memory space of the above-mentioned secure memory enables the execution protection function only configuration, the data in the memory space is not allowed to be read or written, but the data in the memory space is allowed to be read and written by a designated security code program; the designated security code program is a code program that is pre-configured in the security partition where the memory space is located and stored in the read-only memory ROM of the security partition.

[0086] Specifically, in order to achieve a higher level of security in the memory space storing critical user code (i.e., the instruction code of the above-mentioned processor), an execute-only protection function is provided. When execute-only protection is enabled for any of the above-mentioned memory spaces, no code (even security code) is allowed to read or write the data of the flash sector or RAM block. There is only one exception, that is, the contents of this memory space can be read and written when and only when the user uses the specified security code (i.e., the security code program) to read and write it; here, code copying of the security code program can also be understood as the security code program's data access to the secure memory configured with the "execute-only protection function attribute". Each security partition has its own security code program, which is stored in the read-only memory ROM of the security partition.

[0087] The memory space is described by one bit as having an execute-only protection function in the corresponding security partition; specifically, in each security partition, each memory space has one bit describing its execute-only protection function attribute in the security partition:

[0088] Bit 0: only the protection function attribute is enabled;

[0089] Bit 1: The execution protection function attribute is disabled.

[0090] The following describes the security policy for each security zone:

[0091] 1. Protect permissions in the secure partition when the device is encrypted:

[0092] The security of each region (i.e., secure partition) is protected by its own 128-bit (four 32-bit words) password. The partition password for each secure partition is stored in a dedicated secure OTP for that secure partition. The partition can be decrypted by executing the password unlock process. There are three types of access: data access, instruction fetch access, and debugger access.

[0093] In an embodiment of the present application, when on-chip security resources are allocated to any security partition, the on-chip security resources are encrypted based on the partition password of the security partition; wherein the partition password of each security partition is stored in a dedicated security OTP of the security partition and is a 128-bit password pre-configured for the security partition.

[0094] The encrypted on-chip security resources in the security partition are configured to be read and accessed according to a specified security access configuration; wherein the encrypted on-chip security resources can be decrypted by a partition password corresponding to the security partition, and after decryption, are not subject to the constraints of the specified security access configuration.

[0095] In the chip, the on-chip slaves and memory space can be read accessed, and the encrypted on-chip security resources in the security partition are configured for read access according to the specified security access configuration, as follows:

[0096] First, when encrypting:

[0097] 1. Access to data:

[0098] 1) If the memory space is divided into security partitions:

[0099] a. When the execute-only protection function attribute of the memory space is not enabled, only data access operations initiated by programs in the memory space in the same security partition are allowed.

[0100] b. Otherwise, only data access operations from the specified security code program in the same security partition are allowed. The specified security code program is a code program pre-configured in the security partition where the memory space is located and stored in the read-only memory ROM of the security partition; that is, the content of this memory space can only be read when the read-only memory (ROM) of the security code program used by the user and the accessed memory are from the same partition.

[0101] 2) If the on-chip slaves are divided into security partitions, only data access operations initiated by programs in the memory space in the same security partition are allowed.

[0102] In the chip, the on-chip host and the main core processor can fetch instructions in the instruction memory, and the on-chip host and the main core processor can also access the on-chip slave and the memory space. Among them, the encrypted on-chip security resources in the security partition are configured to be read accessed according to the specified security access configuration, and also include:

[0103] 2. For instruction fetch access:

[0104] a. Instruction fetch access to the main core processor: instruction fetch access to the main core processor is allowed; that is, instruction fetching of the main core processor will never be blocked.

[0105] b. Instruction fetch access of the on-chip host: whether the instruction fetch access of the on-chip host is allowed depends on whether it belongs to the same security partition as the instruction memory being accessed (that is, if the memory space is divided into security partitions, whether the program access of the on-chip host is blocked depends on whether it belongs to the same security partition as the instruction memory); wherein, when belonging to the same security partition, the instruction fetch access of the on-chip host is allowed.

[0106] 3. The chip is also used to connect to a debugger and debug the chip through the debugger; accordingly, the encrypted on-chip security resources in the security partition are configured to be read and accessed according to the specified security access configuration, which also includes: when the chip is connected to the debugger, if the encrypted on-chip security resources in the security partition are not semi-decrypted, data access and instruction fetch access in the on-chip security resources in the security partition are not allowed, and the debugger's debugging connection to the chip is interrupted.

[0107] Second, protect permissions in the semi-decrypted state of the device in the secure partition:

[0108] The security partition is semi-decrypted by the semi-decryption password of each security partition; wherein, after semi-decryption, the encrypted on-chip security resources in each security partition are configured for read access according to the specified security access configuration; for example, the on-chip slave or memory space is configured for read access according to the specified security access configuration: Specifically, each area also implements the simulation code security logic using a 64-bit password (part of the partition password) to prevent unauthorized users from single-stepping the security code. When the emulator is connected, the security code pause will interrupt the simulation connection. In order to allow simulation of security code while maintaining protection for reading from devices and memories within the security partition, the user must use the correct 64 bits for semi-decryption. When the decryption password matches the password value stored in the secure OTP, this security partition will be in a semi-decrypted state.

[0109] At the same time, after semi-decryption, the debugger's reading and writing of the encrypted on-chip slave or memory space in the secure partition is invalid, and the debugger's debugging connection to the chip is maintained when the security protection condition is not triggered; when the triggering of the security protection condition is detected, the debugger's debugging connection to the chip is interrupted; wherein the triggering of the security protection condition at least includes: the program running in the secure partition is stopped.

[0110] That is, after semi-decryption, the access security policy of the encrypted on-chip host, on-chip slave or memory space in each secure partition is consistent with the encryption state; when connecting the debugger, if the security protection condition is not triggered, the security code pause will not interrupt the simulation connection, and the debugging state can continue to be maintained, but the debugger's reading and writing of the on-chip slave or memory space will be invalid (of course, if the debugger needs to control the main core processor or the on-chip host, it will also be invalid). In other words, in the semi-decrypted state, the debugger can continue to connect to the chip but cannot read and write secure resource data; and when the security protection condition is triggered, that is, the program running in the secure partition stops, the debugger's debugging connection to the chip must be interrupted to ensure that the chip status is not obtained by the debugger.

[0111] The following is a summary of the dual-code partition security solution and the security strategy of the device:

[0112] After decrypting the secure partition by executing the password unlocking process, or the on-chip secure resources themselves are configured in the non-secure area, it is in a non-secure state, otherwise it is in a secure state. The security permissions of the main core processor, on-chip host, and debugger are described in Table 2.

[0113]

[0114] .

[0115] Third, partition password visibility configuration for secure partitions.

[0116] Here, the partition password of each security partition can be configured for visibility. When this configuration is valid, the password in the dedicated security OTP can be read by the user regardless of whether the corresponding security partition is unlocked or not. This design facilitates customer debugging to prevent mis-encryption operations due to unfamiliar configuration. When this configuration is valid, because the password is permanently readable, even if the user accidentally encrypts the security partition due to misoperation, it can be decrypted again by reading the partition password. When this configuration is invalid, the password is unreadable when the security partition is encrypted.

[0117] In the embodiments of the present application, Figure 2 As shown, the implementation of the dual-code partition security device is as follows:

[0118] The dual-code partition security device adopts a distributed layout, distributed in the main core processor, dual-code partition security controller and on-chip security resources (on-chip host, on-chip slave, on-chip memory, dedicated security OTP).

[0119] As described above, the security configuration of the dual-code partition security device and the configuration of the dedicated OTP are explained, and after the security configuration attributes of the corresponding security partition are configured in each dedicated OTP, the security configuration attributes of the corresponding security partition are loaded into the dual-code security controller through each dedicated security OTP; then, through the dual-code security controller and the security configuration attributes of each security partition in each dedicated security OTP loaded therein, corresponding security configuration information is provided for the on-chip security resources and the main core processor respectively, and the chip operation is controlled based on the security configuration information.

[0120] Among them, the main functions of the dual-code safety controller are as follows:

[0121] a. Provide security configuration information for the main core processor and on-chip security resources (on-chip host, on-chip slave, on-chip memory).

[0122] b. Through the block link pointer setting, formulate the chip's effective dedicated security OTP configuration according to user needs.

[0123] c. Ensure security permissions within the chip to prevent unauthorized users from bypassing the security configuration logic and performing unauthorized operations.

[0124] d. Encryption and decryption functions of each security partition.

[0125] The above functions a to d are described in detail below:

[0126] Function a: The dual-code security controller provides security configuration information for the main core processor and on-chip security resources (on-chip host, on-chip slave, on-chip memory) and the implementation method is as follows:

[0127] a1. Generate security configuration information corresponding to the on-chip security resources and the main core processor respectively based on the security configuration attributes of each security partition in each dedicated security OTP loaded by the dual-code security controller, and send the security configuration information to the on-chip security resources and the main core processor respectively;

[0128] The security configuration information of the main core processor and the on-chip host includes: security partition information of each on-chip slave and on-chip memory space, and the partition information of each on-chip slave and on-chip memory space is composed of two bits;

[0129] Here, the master device (including the main core processor and the on-chip host) performs an instruction fetch operation. The instruction fetch instruction needs to be sent out and carries the partition information: according to the configuration in the dedicated secure OTP, the partition information of each on-chip slave and on-chip memory space is provided to the main core processor and the on-chip host (slave core). The partition information of each on-chip slave and on-chip memory space consists of two bits. The secure OTP configuration of the slave device and the on-chip memory space and its partition information decoding logic in the master device are shown in Table 3;

[0130] .

[0131] Here: For other configuration combinations, although the partition information at the master device is a non-secure area, the actual inaccessible logic control occurs in the control logic of the on-chip slave and on-chip memory space. These combinations cannot generate access logic for the on-chip slave and on-chip memory space.

[0132] a2. The security configuration information of the memory includes: security partition information of each memory space and execution-only protection function attribute enabling information; the security partition information of each memory space and execution-only protection function attribute enabling information are composed of three bits;

[0133] Memory: Provide each memory space with its own secure configuration partition and execute-only protection attribute enable information according to the configuration in the secure OTP. The decoding logic of the secure OTP configuration of the on-chip memory space is shown in Table 4.

[0134] .

[0135] Note: In the above Table 4, X means don't care about the configuration of this bit.

[0136] a3. The security configuration information of the on-chip slave includes the security partition information of the on-chip slave, and the security partition information of the on-chip slave consists of two bits.

[0137] Slave device: Provide each slave device with its own secure configuration partition according to the configuration in the secure OTP. Each slave device secure partition information consists of two bits. The decoded code of the secure OTP configuration of the slave device is shown in Table 5.

[0138] .

[0139] Function b: Through the block link pointer setting, formulate the effective security OTP configuration of the chip according to user needs. Because OTP is a one-time programmable memory and cannot be edited repeatedly, if the security configuration information of all security resources in the chip can only be edited once, this will greatly limit the flexibility of chip use, and if a configuration error occurs during debugging, it will not be able to be changed, affecting the use and increasing the cost of use. This device maps the effective security-related configuration information to multiple groups of OTP address space through the block link pointer, so that users can use chips with dual-code partition security devices more flexibly.

[0140] Specifically, each dedicated security OTP is divided into multiple blocks, each dedicated security OTP includes multiple blocks, and each block stores security configuration attributes of security resources within a slice; the dedicated security OTP of each security partition also includes a block link pointer exclusive to the security partition; by configuring the block link pointer of each security partition, a valid block is selected from the multiple blocks of the corresponding security partition, and the valid security configuration attributes are determined through the valid block.

[0141] The above-mentioned selecting a valid block from a plurality of blocks of the corresponding security partition by configuring the block link pointer of each security partition and determining the valid security configuration attribute through the valid block includes:

[0142] The mapping relationship between the block link pointer of each security partition and the multiple block areas in the security partition is configured in the dual-code security controller; wherein each group of OTP mapping addresses in the dedicated security OTP corresponds to a block area, and each block area stores a security configuration attribute of a security resource within a chip; by configuring the block link pointer of each security partition and combining the mapping relationship, a valid block area is determined from the multiple block areas of the security partition, and the valid security configuration attribute is determined through the valid block area.

[0143] Specifically, the dual-code partition security device (hereinafter referred to as the device) uses a block link pointer to divide each secure OTP available address area into 30 blocks. The corresponding relationship between the block link pointer and the secure partition is shown in Table 6. The reasons for designing the block link pointer are as follows:

[0144] Reason 1: The block link pointer of each security partition must be configured in its own dedicated security OTP to prevent unauthorized users from modifying the block link pointer without decrypting the security partition and thus bypassing the security protection of this device.

[0145] Reason 2: Because the block link pointer is in the OTP, it can only be programmed once and cannot be edited repeatedly. Therefore, it is necessary to reasonably set the block link pointer mapping logic to ensure that the block link pointer can be mapped to each available block when the user uses it. In the embodiment of the present application, based on the characteristics that the dedicated security OTP is all 1 in the default state and the number of blocks in the corresponding security partition, the number of bits of the block link pointer is defined and the valid block is specified from multiple blocks through the position of the highest 0 bit in the block link pointer. Specifically, because OTP is all 1 in the default state, we define the block link pointer as 29 bits, and use = to specify the valid OTP block through the position of the highest 0 bit.

[0146] Reason 3: Each security partition has its own block link pointer, which is independent of each other.

[0147] .

[0148] Note: In the above Table 6, x represents configuration information that is not of concern.

[0149] Among them, each block has its own address space, so that the user can specify the valid block through the block link pointer to determine or switch the security configuration information of the on-chip security resources (here, the security configuration information is obtained through the security configuration attributes).

[0150] In the embodiment of the present application, the security configuration architecture in the secure OTP is as follows: Figure 3 As shown, Figure 3 It is a security configuration architecture within a dedicated secure OTP. The secure OTP is divided into a public area and a block area. The block area link pointer can specify a valid block area to provide security configuration information, while the public area has only one set, which is independent of the configuration of the block area link pointer.

[0151] Because the block link pointer determines the use of the block partition, if the OTP fails and causes data abnormality, this will affect the security configuration of the chip. Therefore, the present device defines multiple block link pointers, and each dedicated security OTP includes multiple block link pointers. The multiple block link pointers correspond to multiple values. The multiple values ​​use bit-by-bit voting logic to form the final value of the hardware parsing pointer, and the valid block is determined by the final value combined with the mapping relationship; wherein, when the values ​​of the multiple block link pointers are different, an error status prompt is given in the status register.

[0152] In the embodiment of the present application, three block area link pointers are used, and the three block area link pointers correspond to three values. The three values ​​adopt the logic of bit-by-bit voting to form the final value of the hardware parsing pointer, and the valid block area is determined by combining the final value with the mapping relationship. If the values ​​of the three block area link pointers are different, the device will have an error state in the status register.

[0153] Function c: Ensure security permissions within the chip to prevent unauthorized users from bypassing the security configuration logic and performing unauthorized operations.

[0154] First, in order to ensure data communication between the security OTP and the dual-code partition security controller, a private bus is used to ensure that data loading of the security OTP to the dual-code partition security controller is completed under the condition that it is invisible to the user.

[0155] Second, after the chip is powered on, in order to ensure the smooth loading of the security configuration, the dual-code partition security controller has designed a preset loading mechanism. Before the preset loading mechanism is completed, all security resources in the chip cannot be accessed. The above preset loading mechanism includes the loading order of each area and the corresponding processing method. The loading order of each area is as follows:

[0156] 1. Load secure partition 1 block link pointer 1 / 2 / 3;

[0157] 2. Load secure partition 2 block link pointer 1 / 2 / 3;

[0158] 3. Load the password visible configuration of secure partition 1;

[0159] 4. Load other security configurations of security partition 1;

[0160] 5. Load the password visible configuration of secure partition 2;

[0161] 6. Load other security configurations of security partition 2;

[0162] At this time, according to the link pointer of the secure partition 1 block, the corresponding valid block is parsed;

[0163] 7. Load secure partition 1 to execute configuration only;

[0164] 8. Load the partition configuration of security partition 1;

[0165] 9. Load the security partition 1 protection password;

[0166] At this time, according to the link pointer of the secure partition 2 block, the corresponding valid block is parsed;

[0167] 10. Load secure partition 2 to execute configuration only;

[0168] 11. Load the security partition 2 partition configuration;

[0169] 12. Load the security partition 1 protection password.

[0170] Among them, the public area loads the initialization protection logic. After the chip is powered on, the loading completion signal is in an invalid state. Only when the previous area loading data completion indication signal is valid, the data loading is determined to be completed according to the secure OTP private bus loading address and the address of this area. For the first block link pointer of the first security partition loaded by the first loading address (in this embodiment of the application, the first security partition is security partition 1, and the first block link pointer is block link pointer 1), the previous area loading data completion indication signal is always in a valid state. The previous area loading data completion indication signal is always in a valid state.

[0171] Among them, the block area loading initialization protection logic, after the chip is powered on, the loading completion signal is in an invalid state. Compared with the public area security logic, because the valid block area is determined by the block area link pointer, the block area security logic has an additional set of valid address selection logic compared to the public area security logic.

[0172] According to the preset loading mechanism of the dual-code partition security controller, the security protection logic of each area adopts a cascade structure to ensure that only by loading the logic according to the specified security area can the initialization be successfully completed, thereby accessing the on-chip security resources. The loading mechanism ensures that users cannot bypass the effective security configuration to access the on-chip security resources.

[0173] Third, the online update security information loading protection of the dual-code controller. When the user switches blocks during use, because the loading of partition security information is completed serially by address, if it is not protected, it will also cause usage errors, as shown in Table 1. For example: after the user switches blocks, in the process of loading other security information, when the configuration of security partition 1 has been loaded, but the configuration of security partition 2 has not been loaded, invalid data may be generated in the middle, resulting in the inaccessibility of on-chip security resources. If the program happens to be stored in the affected security resources, it will cause the program to be locked and cannot be recovered. For this problem, the dual-code partition security controller solves it in a way similar to the initialization process. The security loading process needs to be executed to complete the online loading and updating of security information.

[0174] Resetting the block link pointer through the dual code security controller to switch the valid block to a new valid block, and causing the dual code security controller to load the on-chip security resources and the security configuration information in the main core processor based on a security loading mechanism;

[0175] The above-mentioned safe loading mechanism includes:

[0176] 1) Load secure partition 1 block link pointer 1 / 2 / 3;

[0177] 2) Load secure partition 2 block link pointer 1 / 2 / 3;

[0178] 3) Load the password visible configuration of secure partition 1;

[0179] 4) Load other security configurations of security partition 1;

[0180] 5) Load the password visible configuration of secure partition 2;

[0181] 6) Load other security configurations of security partition 2.

[0182] At this time, according to the link pointer of the secure partition 1 block, the corresponding valid block is parsed;

[0183] 7) Load secure partition 1 to execute configuration only;

[0184] 8) Load the partition configuration of security partition 1;

[0185] At this time, according to the link pointer of the secure partition 2 block, the corresponding valid block is parsed;

[0186] 9) Load secure partition 2 to execute configuration only;

[0187] 10) Load the security partition 2 partition configuration.

[0188] Among them, when the dual-code security controller hardware is implemented, when completing the last step of the security loading process, the specified configuration information in the security configuration information is synchronously loaded; the specified configuration information includes: security partition 1 password visible configuration / security partition 1 other security configuration / security partition 2 password visible configuration / full partition 2 other security configuration / security partition 1 execution only configuration / security partition 1 partition configuration / security partition 2 execution configuration / security partition 2 zone configuration these security information.

[0189] Specifically, when the dual-code partition security controller hardware is implemented, the security information such as security partition 1 password visible configuration / security partition 1 other security configuration / security partition 2 password visible configuration / full partition 2 other security configuration / security partition 1 execution only configuration / security partition 1 partition configuration / security partition 2 execution configuration / security partition 2 zone configuration will be loaded synchronously only when the last step of the security loading process is completed. The update of the block link pointer is real-time to correctly identify the corresponding valid block.

[0190] In addition, the security configuration attributes of each security partition are burned in the dedicated security OTP of each security partition, and each dedicated security OTP is decrypted based on the partition password of the corresponding security partition before burning; specifically, if the user attempts to burn the security OTP of security zone 1 or security zone 2, the corresponding security zone must be decrypted first, thereby preventing unauthorized users from attempting to bypass the security information protection logic of the dual-code partition security controller by burning the security OTP.

[0191] Similarly, the security information loading and refreshing logic is different for the public area and the block area. The difference between the online update loading protection logic of the public area and the block area and their respective loading initialization protection logic is that there is an additional security information loading completion handshake input. When the loading is completed, the loading completion indication signal of each area is reset for use during the next online update loading.

[0192] Function d: Implementation of encryption, decryption and semi-decryption functions of the security partition.

[0193] For encryption, the encryption function of security zone 1 and security zone 2 can be realized by writing the corresponding control bits to the decryption register of the dual-code partition security controller.

[0194] For decryption and semi-decryption, the process is as follows Figure 4 As shown. The dual-code security controller decrypts the security partition in the following manner: for each security partition, the dual-code security controller loads multiple block link pointers of the security partition based on the private bus connected to the dedicated security OTP of the security partition; the dual-code security controller calculates the valid block of the security partition based on the multiple block link pointers; the dual-code security controller loads the partition password of the security partition based on the private bus; writes the decryption password to the decryption register in the dual-code security controller; determines whether the decryption password of the decryption register is the same as the partition password of the security partition; if they are the same, complete the decryption; if they are different, return to the step of writing the decryption password to the dual-code security controller until the decryption is completed or the decryption function is exited; wherein, the partition password of the full decryption is 128 bits; the semi-decryption password is a part of the partition password and is 64 bits. Here, the difference between decryption and semi-decryption is that the decryption password is protected by the 128-bit security zone protection password, and the semi-decryption password is protected by the 64-bit security zone protection password.

[0195] In the implementation, the overall logic of the decryption process is as follows Figure 5 As shown, only after all the block pointers of the partition are loaded, the action of writing the decryption password to the decryption register of the dual-code partition security controller is effective. After the decryption is successful, the decryption success indication signal will be sent back to the block pointer decryption protection register to complete the handshake with it and prepare for the next decryption operation.

[0196] The block pointer decryption protection register logic, after the corresponding block pointer is loaded, the loading completion flag signal is valid, after the decryption is successful, the loading completion flag signal is invalid, preparing for the next decryption.

[0197] The decryption register logic of the dual-code partition security controller is that after the encryption setting is valid, the decryption status valid signal is invalid. When the block pointer is loaded and the decryption password is the same as the block valid protection password, the decryption status is valid.

[0198] The main core processor and the on-chip host dual-code security logic are described below. The main functions of the main core processor and the on-chip host dual-code security logic are as follows:

[0199] a. Provide access types for on-chip security resources (secure OTP, on-chip slaves, on-chip processors).

[0200] b. When the debugger is linked, the control code determines whether to disconnect the simulation link based on the semi-decrypted state and the security partition of the memory where the program is located.

[0201] c. Control whether the main core processor and the on-chip host should monitor the program based on the decryption status and the security partition of the memory where the program is located.

[0202] The above functions a to c are described below respectively:

[0203] Function a: Provides access type implementation for on-chip security resources (secure OTP, on-chip slave, on-chip processor).

[0204] The processor or on-chip host can encode the current execution program according to the access type, instruction fetch address and security configuration information provided by the dual-code security controller (see Table 3), indicating the status of the current execution program. According to different states, the dual-code security logic in the on-chip memory and the on-chip slave determines what access state is open for the current execution program.

[0205] The on-chip bus of this device will represent the current transmission status, and the current execution program status mapping of the main core processor and the on-chip main device is shown in Table 7.

[0206] .

[0207] The X in the above Table 7 can be any value.

[0208] The implementation logic is as follows:

[0209] a. The main core processor or the on-chip host initiates the access, so according to the access type, if the access type is instruction fetch access, PROT[0] is 0, otherwise it is 1.

[0210] b. If it is data access, because of the security configuration information provided by the dual-code security controller, the security information corresponding to the instruction fetch address can be determined based on the instruction fetch address (see Table 3), thereby determining which security partition the program comes from, namely PROT[2] and PROT[1].

[0211] c. Based on the instruction fetch address, it is also possible to determine whether the program comes from ROM, thereby determining PROT[3].

[0212] Function b: When the debugger is linked, control whether to disconnect the simulation link according to the semi-decrypted state and the security partition of the memory where the program is located.

[0213] Implementation method: Figure 6 As shown, when the pause valid signal arrives, the security partition information of the current program is obtained according to the program instruction address and the security configuration information provided by the dual-code security controller (see Table 3). If the current program is in security partition 1, then if the semi-decryption signal of security partition 1 is invalid, the disconnect simulation link valid logic of the main core processor or the security master device will send a reset signal, thereby disconnecting the interrupt and resetting the chip to ensure that when the debugger is linked and the security partition is not semi-decrypted, the code cannot be paused in the memory of the security partition.

[0214] Function c: Control whether the main core processor and the on-chip host monitor the program according to the decryption status and the security partition of the memory where the program is located.

[0215] This function is implemented as follows: In the monitoring logic of the main core processor and the on-chip host, the security partition where the current program is running can be obtained by fetching the instruction address and the security configuration information provided by the dual-code security controller (see Table 3).

[0216] If the program runs in a non-secure partition, the program monitoring enable is not controlled by the secure partition unlock signal provided by the dual-code security controller.

[0217] If the program runs in security partition 1, program monitoring cannot be enabled when the dual-code safety controller provides an invalid unlock signal control for security partition 1.

[0218] If the program runs in security partition 2, program monitoring cannot be enabled when the dual-code safety controller provides an invalid unlock signal control for security partition 1.

[0219] The following is an explanation of the dedicated security OTP, memory and on-chip slave dual-code security logic. Specifically, the main functions of the dedicated security OTP, memory and on-chip slave dual-code security logic are as follows:

[0220] a. Determine whether the device is accessible based on the access device, the access type provided by the access device, the device security configuration information provided by the dual-code security controller (see Table 4), and the encryption and decryption status.

[0221] b. Determine whether the device is accessible based on the connection status and semi-decryption status of the debugging device.

[0222] The above functions a and b are explained below:

[0223] Function a: Determine whether the device is accessible based on the access device, the access type provided by the access device, the device security configuration information provided by the dual-code security controller (see Table 4) and the encryption and decryption status.

[0224] Secure OTP, memory and on-chip slaves are all accessed slave devices in the access transaction. Therefore, the access to the device is protected according to the type of access master device (main core processor or on-chip host), the type of access (instruction access or data access), and combined with their own configuration information and encryption and decryption status.

[0225] This function is implemented as follows: In an access transaction, the access device type and access type are provided by the bus and are dynamic signals. Each access will change according to the main device and access type of this access. The security configuration information of this device provided by the dual-code security controller will not change after the configuration is completed, and the encryption and decryption status will only change after the encryption and decryption operation. They are all quasi-static signals.

[0226] 1. Storage device security logic:

[0227] 1. If the device is configured in a non-secure partition:

[0228] 1) When the access device is the main core processor, the access status is released and no protection is performed.

[0229] 2) When the access device is an on-chip host: If the on-chip host is configured as a secure zone and the access type is instruction fetch access, the access is prohibited by the security logic;

[0230] 2. If the device is divided into a safe zone:

[0231] 1) When the security logic is unlocked: any access is not restricted and is always valid.

[0232] 2) When the access device is the main core processor:

[0233] If the access type is an instruction fetch access, the access is always valid.

[0234] If the access type is data access, the data can be accessed only when the program from the same security zone is accessed (see Table 7). When the execution-only mode setting provided by the dual-code security controller is in effect, although the memory can be accessed, the user cannot read the data of this access. Unless the program comes from the secure ROM (see Table 7).

[0235] 3) When the access device is an on-chip host

[0236] If the access type is instruction fetch access, the master device security partition must be consistent with the memory partition configuration, otherwise the access will be blocked by the security logic.

[0237] If the access type is data access, the security logic is the same as that when the main core processor accesses.

[0238] 2. Secure OTP and on-chip slave security logic:

[0239] Because there is no access type for instruction fetch operations in these two devices, then:

[0240] 1. If the device is configured in a non-secure partition, any access is not restricted and is always valid.

[0241] 2. If the device is divided into a safe zone:

[0242] When the security logic is unlocked: any access is unlimited and always valid.

[0243] When the security logic is not unlocked: the data can be accessed if and only if the access is from a program in the same security zone (see Table 7).

[0244] Function b: Determine whether the device is accessible based on the connection status and semi-decryption status of the debugging device.

[0245] When the secure OTP, memory, and on-chip slave detect that the debugger is in a linked state, if the semi-decryption indication signal provided by the dual-code security controller is invalid, the access is blocked by the security protection logic.

[0246] The present application can flexibly configure the on-chip security resources through two security partitions, which not only meets the needs of users but also improves the utilization rate of the on-chip security resources.

[0247] An embodiment of the present application also provides a chip security configuration device based on multiple block areas, including a dual-code security controller, a one-time programmable OTP, a main core processor and on-chip security resources; the OTP, the main core processor and the on-chip security resources are respectively communicated with the dual-code security controller; the above-mentioned dual-code partition security device is used to execute the above-mentioned chip security configuration method based on multiple block areas.

[0248] In addition, the chip can also be connected to a debugger to debug the chip. Similarly, the chip security configuration device based on multiple blocks is still based on the chip security configuration method based on multiple blocks.

[0249] The above-mentioned chip security configuration device based on multiple blocks, on the basis of flexibly configuring the on-chip security resources through two security partitions, can also select the effective security attribute configuration of each security partition through the block link pointer, which not only meets the user's usage needs, but also realizes the flexible configuration of the security mode, greatly improving the utilization rate of the on-chip security resources.

[0250] An embodiment of the present application also provides a chip, including a dual-code partition security device, the dual-code partition security device includes a dual-code security controller, a one-time programmable OTP, a main core processor and on-chip security resources; the OTP, the main core processor and the on-chip security resources are respectively communicated and connected with the dual-code security controller; the chip includes two security partitions and each security partition corresponds to a dedicated security OTP; the chip executes the above-mentioned dual-code partition security method through the dual-code partition security device.

[0251] In addition, the chip can also be connected to a debugger to debug the chip. Similarly, the chip security configuration device based on multiple blocks is still based on the features of the chip security configuration method based on multiple blocks.

[0252] The above-mentioned chip, based on the flexible configuration of on-chip security resources through two security partitions, can also select the effective security attribute configuration of each security partition through the block link pointer, which not only meets the user's usage needs, but also realizes the flexible configuration of the security mode, greatly improving the utilization rate of on-chip security resources.

[0253] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the method embodiment, and will not be repeated in this application. In the several embodiments provided in this application, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0254] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0255] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0256] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard drives, ROM, RAM, magnetic disks, or optical disks.

[0257] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip security configuration method based on multiple blocks, characterized in that: Applied to a dual-code partition security device, the dual-code partition security device comprises a dual-code security controller, a one-time programmable OTP, a main core processor and an on-chip security resource; the OTP, the main core processor and the on-chip security resource are respectively connected to the dual-code security controller for communication; The chip includes two security partitions and each security partition corresponds to a dedicated security OTP; the method includes: The on-chip security resources are allocated to the corresponding security partitions through the dedicated security OTP, and the security configuration attributes for the on-chip security resources in each security partition are obtained; wherein the on-chip security resources allocated to different security partitions are different, and the security configuration attributes of each security partition are stored in the dedicated security OTP of the security partition; each dedicated security OTP includes a plurality of blocks, and each block stores the security configuration attributes of the on-chip security resources; the dedicated security OTP of each security partition also includes a block link pointer exclusive to the security partition; By configuring the block link pointer of each security partition, a valid block is selected from a plurality of blocks of the corresponding security partition, and a valid security configuration attribute is determined through the valid block; Each dedicated security OTP is used to load the effective security configuration attributes of its corresponding security partition into the dual-code security controller, and the dual-code security controller and the effective security configuration attributes of each security partition loaded therein are used to provide corresponding security configuration information for the on-chip security resources and the main core processor, respectively, and control the operation of the chip based on the security configuration information.

2. The chip security configuration method based on multiple blocks according to claim 1, characterized in that: The on-chip security resources include an on-chip host, an on-chip slave, and a memory, and the memory is pre-divided into a plurality of memory spaces; The security configuration attributes include at least a partition password, partition attributes of the on-chip security resources, and an execute-only protection function configuration for the memory space in the memory; wherein, when any memory space enables the execute-only protection function configuration, data in the memory space is not allowed to be read or written, but data in the memory space is allowed to be read and written by a specified security code program; the specified security code program is a code program that is pre-configured for the security partition where the memory space is located and stored in the read-only memory ROM of the security partition.

3. The chip security configuration method based on multiple blocks according to claim 2, characterized in that: When the on-chip security resource is allocated to any security partition, the on-chip security resource is encrypted based on the partition password of the security partition; The chip is also used to connect to a debugger and debug the chip through the debugger; the encrypted on-chip security resources in the security partition are configured to be read accessed according to a specified security access configuration: when the chip is connected to the debugger, if the encrypted on-chip security resources in the security partition are not semi-decrypted, data access and instruction fetch access to the on-chip security resources in the security partition are not allowed, and the debugger's debugging connection to the chip is interrupted.

4. The chip security configuration method based on multiple blocks according to claim 3 is characterized in that: The partition password in each secure partition also includes a semi-decrypted password; the method further includes: Semi-decrypting each security partition using the semi-decryption password of the security partition; wherein after the semi-decryption, the encrypted on-chip security resources in each security partition are configured to be read-accessed according to the specified security access configuration: the specified security access configuration of the encrypted on-chip security resources in each security partition is the same as the encryption state when the debugger is not connected; At the same time, after semi-decryption, the debugger's reading and writing of the encrypted on-chip slave or memory space in the secure partition is invalid, and the debugger's debugging connection to the chip is maintained when the security protection condition is not triggered; when the triggering of the security protection condition is detected, the debugger's debugging connection to the chip is interrupted; wherein the triggering of the security protection condition at least includes: the program running in the secure partition is stopped.

5. The chip security configuration method based on multiple blocks according to claim 2, characterized in that: Through the dual-code security controller and the valid security configuration attributes of each security partition loaded therein, corresponding security configuration information is provided for the on-chip security resources and the main core processor, including: Generate, by the dual-code security controller, security configuration information corresponding to the on-chip security resources and the main core processor based on the security configuration attributes of each security partition loaded by the dual-code security controller, and send the security configuration information to the on-chip security resources and the main core processor respectively; The security configuration information of the main core processor and the on-chip host includes: security partition information of each on-chip slave and on-chip memory space, and the partition information of each on-chip slave and on-chip memory space is composed of two bits; The security configuration information of the memory includes: security partition information of each memory space and execution-only protection function attribute enabling information; the security partition information of each memory space and execution-only protection function attribute enabling information are composed of three bits; The security configuration information of the on-chip slave includes security partition information of the on-chip slave, and the security partition information of the on-chip slave consists of two bits.

6. The chip security configuration method based on multiple blocks according to claim 1, characterized in that: The method of configuring a block link pointer of each security partition, selecting a valid block from a plurality of blocks of the corresponding security partition, and determining a valid security configuration attribute through the valid block includes: The mapping relationship between the block link pointer of each security partition and the multiple blocks in the security partition is configured in the dual-code security controller; wherein each group of OTP mapping addresses in the dedicated security OTP corresponds to a block, and each block stores a security configuration attribute of a security resource within a piece; By configuring the block link pointer of each security partition and combining the mapping relationship, a valid block is determined from multiple blocks of the security partition, and a valid security configuration attribute is determined through the valid block.

7. The chip security configuration method based on multiple blocks according to claim 6, characterized in that: Each dedicated secure OTP includes a plurality of block link pointers, and the plurality of block link pointers correspond to a plurality of values. The plurality of values ​​adopt a bit-by-bit voting logic to form a final value of a hardware parsing pointer, and the valid block is determined by combining the final value with the mapping relationship; wherein, when the values ​​of the plurality of block link pointers are different, an error status prompt is given in the status register.

8. The chip security configuration method based on multiple blocks according to claim 6, characterized in that: Based on the characteristic that the dedicated security OTP is all 1s in the default state and the number of blocks in the corresponding security partition, the number of bits of the block link pointer is defined and the valid block is specified from multiple blocks by the position of the highest 0 bit in the block link pointer.

9. The chip security configuration method based on multiple blocks according to claim 1, characterized in that: The dual-code security controller and the dedicated security OTP are connected by a private bus, so as to complete the loading of data from the dedicated security OTP to the dual-code security controller in an invisible condition.

10. The chip security configuration method based on multiple blocks according to claim 4, characterized in that: The method further comprises: A preset loading mechanism is configured for the dual-code security controller, so that the dual-code security controller loads the security configuration information in the on-chip security resources and the main core processor based on the preset loading mechanism, and after the loading is completed, controls the operation of the chip based on the security configuration information; the preset loading mechanism includes the loading order of each area and the corresponding processing method; Among them, after the chip is powered on, the loading is carried out according to the loading order of each area in the preset loading mechanism and the loading completion signal is in an invalid state. When the previous area loading data completion indication signal is valid, it is determined whether the current data loading is completed according to the private bus loading address of the dedicated security OTP and the address of this area; for the first block area link pointer of the first security partition loaded by the first loading address, the previous area loading data completion indication signal is always in a valid state; wherein, compared with the public area loading, the block area loading has an additional set of valid address selection logic.

11. The chip security configuration method based on multiple blocks according to claim 10, characterized in that: The method further comprises: Resetting the block link pointer through the dual code security controller to switch the valid block to a new valid block, and causing the dual code security controller to load the on-chip security resources and the security configuration information in the main core processor based on a security loading mechanism; When the dual-code security controller hardware is implemented, when completing the last step of the security loading process, the specified configuration information in the security configuration information is synchronously loaded; the specified configuration information includes: the password visible configuration of each of the two security partitions, the other security configurations of each of the two security partitions, the execution-only configuration of each of the two security partitions, and the partition attributes of each of the two security partitions.

12. The chip security configuration method based on multiple blocks according to claim 11, characterized in that: in, The security configuration attributes of each security partition are burned into the dedicated security OTP of each security partition, and each dedicated security OTP is decrypted based on the partition password of the corresponding security partition before burning.

13. The chip security configuration method based on multiple blocks according to claim 11, characterized in that: The dual-code security controller decrypts the security partition in the following manner: For each security partition, the dual code security controller loads multiple block link pointers of the security partition based on its private bus connected to the dedicated security OTP of the security partition; Calculate the valid block area of ​​the security partition based on the multiple block area link pointers by the dual code security controller; Loading the partition password of the security partition based on the private bus through the dual-code security controller; By writing a decryption password to a decryption register in the dual code security controller; Determine whether the decryption password of the decryption register is the same as the partition password of the security partition; if they are the same, complete the decryption; if they are different, return to the step of writing the decryption password to the dual-code security controller until the decryption is completed or the decryption function is exited; The fully decrypted partition password is 128 bits; the semi-decrypted password is a part of the partition password and is 64 bits.

14. A chip security configuration device based on multiple blocks, characterized in that: It includes a dual-code security controller, a one-time programmable OTP, a main core processor and on-chip security resources; the OTP, the main core processor and the on-chip security resources are respectively connected to the dual-code security controller for communication; The dual-code partition security device is used to execute the chip security configuration method based on multiple blocks as described in any one of claims 1-13.

15. A chip, characterized in that: It comprises a dual-code partition security device, which comprises a dual-code security controller, a one-time programmable OTP, a main core processor and on-chip security resources; the OTP, the main core processor and the on-chip security resources are respectively communicated with the dual-code security controller; the chip comprises two security partitions and each security partition corresponds to a dedicated security OTP; the chip executes the chip security configuration method based on multiple blocks as described in any one of claims 1 to 13 through the dual-code partition security device.

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