Display device

Abstract

A display device according to the present invention includes a display panel including a plurality of pixels and a plurality of data lines, a source driving circuit outputting a data signal, and a selection circuit disposed between the plurality of data lines and the source driving circuit and selectively connecting the source driving circuit to a portion of the plurality of data lines. The source driving circuit includes a first latch that generates line image data, a second latch that receives the line image data from the first latch and outputs the line image data in response to a first latch control signal, and a third latch receiving the line image data from the second latch and outputting the line image data in response to the second latch control signal. A period of the first latch control signal is constant, and a period of the second latch control signal is variable.

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly, to a display device capable of improving image quality. Background Art

[0002] Among display devices, a light-emitting display device displays images using a light-emitting diode (LED) that generates light through the recombination of electrons and holes. Such a light-emitting display device has the advantages of having a fast response speed and being driven with low power consumption.

[0003] The light-emitting display device has a display panel on which pixels connected to data lines and scan lines are arranged. The pixel generally includes a light-emitting diode and a pixel circuit unit for controlling the amount of current flowing to the light-emitting diode. The pixel circuit unit controls the amount of current flowing through the light-emitting diode in response to a data signal. At this time, light of a predetermined brightness is generated in response to the amount of current flowing through the light-emitting diode. Summary of the invention

[0004] An object of the present invention is to provide a display device capable of sufficiently ensuring an active period of a scanning signal while reducing the number of channels of a source driving circuit.

[0005] According to one feature of the present invention, a display device includes a display panel including a plurality of pixels and a plurality of data lines connected to the plurality of pixels, a source driving circuit outputting data signals to the plurality of data lines, and a selection circuit arranged between the plurality of data lines and the source driving circuit and selectively connecting the source driving circuit to a portion of the plurality of data lines.

[0006] The source driving circuit includes a first latch that sequentially stores image data in response to a data clock signal and generates line image data, a second latch that receives the line image data from the first latch and outputs the line image data in response to a first latch control signal, and a third latch that receives the line image data from the second latch and outputs the line image data in response to a second latch control signal. The period of the first latch control signal is constant, and the period of the second latch control signal is variable.

[0007] According to one feature of the present invention, a display device includes a display panel including a plurality of pixels and a plurality of data lines connected to the plurality of pixels, a source driver circuit that outputs data signals, and a selection circuit that is arranged between the plurality of data lines and the source driver circuit and selectively connects the source driver circuit to a portion of the plurality of data lines.

[0008] The source driving circuit includes a first latch and a second latch. The first latch sequentially stores image data in response to a data clock signal and generates line image data. The second latch includes a first sub-latch and a second sub-latch, and alternately stores the line image data received from the first latch in the first sub-latch and the second sub-latch. The second latch outputs the first line image data of the first sub-latch in response to a first sub-latch control signal, and outputs the second line image data of the second sub-latch in response to a second sub-latch control signal.

[0009] A start time point of the second sub-output interval of the second sub-latch control signal precedes a 1 / 2 point of the first sub-output interval of the first sub-latch control signal.

[0010] According to the present invention, when a third latch is added to the source driving circuit, the width of the active interval of the scanning signal can be increased by ensuring that the period of the second output interval is larger than the period of the first output interval. As a result, even if a selective driving method for selectively driving the data line is adopted, the active interval of the scanning signal can be fully ensured, thereby improving the image quality problem caused by insufficient data charging time of each pixel. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a perspective view of a display device according to an embodiment of the present invention.

[0012] Figure 2 is an exploded perspective view of a display device according to an embodiment of the present invention.

[0013] Figure 3 is a block diagram of a display device according to an embodiment of the present invention.

[0014] Figure 4 Detailed description is a block diagram showing the connection relationship between a source driving circuit and a selection circuit according to an embodiment of the present invention.

[0015] Figure 5 is a block diagram of a source driving circuit according to an embodiment of the present invention.

[0016] Figure 6 It is shown Figure 5 Waveform diagram of the first latch control signal and the second latch control signal shown in .

[0017] Figure 7 is a waveform diagram showing a first selection signal and a second selection signal, a second latch control signal, and a scan signal according to an embodiment of the present invention.

[0018] Figure 8Detailed description is a block diagram showing the connection relationship between a source driving circuit and a selection circuit according to an embodiment of the present invention.

[0019] Fig. 9 is a waveform diagram showing a first selection signal, a second selection signal, and a third selection signal, a second latch control signal, and a scan signal according to an embodiment of the present invention.

[0020] Fig.10 is a block diagram of a source driving circuit according to an embodiment of the present invention.

[0021] Fig.11 1 is a waveform diagram showing first and second selection signals, first and second sub-latch control signals, and scan signals according to an embodiment of the present invention.

[0022] Description of Reference Numerals

[0023] DD: Display device DP: Display panel

[0024] DIC: driver chip 100: driver controller

[0025] 200: Source driving circuit 250: Selection circuit

[0026] 300: Scanning driving circuit 400: Voltage generator

[0027] 251, 251a: first switch circuit 253, 253a: second switch circuit

[0028] 255a: third switch circuit 221: first latch

[0029] 222, 225: second latch 223: third latch

[0030] 225a: first sub-latch 225b: second sub-latch

[0031] CH1 to CHk: Channels FL1 to FLk: Fan-out lines

[0032] CS_L1: first latch control signal CS_L2: second latch control signal

[0033] TP0: Reference output interval TP1: First output interval

[0034] TP2: Second output interval CLA: First selection signal

[0035] CLB: second selection signal SP1: first selection interval

[0036] SP2: Second selected interval AP, APa: Active interval DETAILED DESCRIPTION

[0037] In this specification, when a certain constituent element (or region, layer, part, etc.) is mentioned as being "on", "connected to" or "bonded to" another constituent element, it means that it can be directly arranged on / directly connected to / directly bonded to another constituent element, or a third constituent element may be arranged between them.

[0038] The same reference numerals indicate the same constituent elements. In addition, in order to effectively illustrate the technical content, the thickness, proportion and size of the constituent elements in the drawings are exaggerated. "And / or" can define all of more than one combination of related constituent elements.

[0039] Although the terms of first, second, etc. are used to illustrate a variety of constituent elements, the constituent elements are not limited by the terms. The terms are used only for the purpose of distinguishing one constituent element from another constituent element. For example, without departing from the scope of the present invention, the first constituent element may be named as the second constituent element, and similarly, the second constituent element may also be named as the first constituent element. Unless clearly indicated differently in the context, a singular expression includes a plural expression.

[0040] In addition, terms such as "lower", "lower side", "upper", and "upper side" are used to explain the relationship between components shown in the drawings. These terms are relative concepts and are explained based on the directions indicated in the drawings.

[0041] It should be understood that terms such as “including” or “having” are intended to specify the presence of features, numbers, steps, operations, constituent elements, parts, or combinations thereof recorded in the specification, without excluding in advance the presence or possibility of adding one or more other features, numbers, steps, operations, constituent elements, parts, or combinations thereof.

[0042] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this specification have the same meaning as those commonly understood by practitioners in the technical field to which the present invention belongs. In addition, terms such as those defined in commonly used dictionaries should be interpreted as having the same meaning as that in the context of the relevant technology, and unless clearly defined herein, should not be interpreted as too ideal or too formal.

[0043] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0044] Figure 1 is a perspective view of a display device according to an embodiment of the present invention, and Figure 2 is an exploded perspective view of a display device according to an embodiment of the present invention.

[0045] Reference Figure 1 and Figure 2 , the display device DD may be a device activated according to an electrical signal. The display device DD according to the present invention may be a large display device such as a television, a monitor, etc., and a small or medium-sized display device such as a mobile phone, a tablet computer, a notebook computer, a car navigation, a game console, etc. These are merely suggested as examples, and the display device DD may also be implemented in other forms without departing from the concept of the present invention. The display device DD has a rectangular shape including a long side in a first direction DR1 and a short side in a second direction DR2 intersecting the first direction DR1. However, the shape of the display device DD is not limited thereto, and a display device DD of various shapes may be provided. The display device DD may display an image IM toward a third direction DR3 on a display surface IS parallel to each of the first direction DR1 and the second direction DR2. The display surface IS displaying the image IM may correspond to the front surface (front surface) of the display device DD.

[0046] In this embodiment, the front side (or top) and the back side (or bottom) of each component are defined based on the direction of displaying the image IM. The front side and the back side may be opposite to each other in the third direction DR3, and the normal direction of each of the front side and the back side may be parallel to the third direction DR3.

[0047] The spacing distance between the front and back surfaces in the third direction DR3 may correspond to the thickness of the display device DD in the third direction DR3. In addition, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative concepts and may be converted into other directions.

[0048] The display device DD can sense external input applied from the outside. The external input may include various forms of input provided from the outside of the display device DD. The display device DD according to an embodiment of the present invention can sense external input of a user applied from the outside. The external input of the user may be any one or a combination of various forms of external input such as a part of the user's body, light, heat, sight or pressure. In addition, the display device DD may also sense the external input of the user applied to the side or back of the display device DD according to the structure of the display device DD, and is not limited to any one embodiment. As an example of the present invention, the external input may also include input according to an input device (for example, a stylus, an active pen, a touch pen, an electronic pen, an e-pen, etc.), etc.

[0049] The display surface IS of the display device DD can be divided into a display area DA and a non-display area NDA. The display area DA can be an area where an image IM is displayed. A user observes the image IM through the display area DA. In the present embodiment, the display area DA is shown as a quadrilateral with rounded vertices. However, this is shown by way of example, and the display area DA can have a variety of shapes and is not limited to any one embodiment.

[0050] The non-display area NDA is adjacent to the display area DA. The non-display area NDA may have a predetermined color. The non-display area NDA may surround the display area DA. Thus, the shape of the display area DA may be substantially defined by the non-display area NDA. However, this is shown exemplarily, and the non-display area NDA may also be arranged to be adjacent to only one side of the display area DA, and may also be omitted. The display device DD according to an embodiment of the present invention may include a variety of embodiments and is not limited to any one embodiment.

[0051] like Figure 2 As shown in , the display device DD may include a display module DM and a window WM arranged on the display module DM. The display module DM may include a display panel DP and an input sensing layer ISP.

[0052] The display panel DP according to an embodiment of the present invention may be a light-emitting display panel. As an example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting substance. The light-emitting layer of the inorganic light-emitting display panel may include an inorganic light-emitting substance. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots and quantum rods, etc.

[0053] The display panel DP may output an image IM, and the output image IM may be displayed through the display surface IS.

[0054] The input sensing layer ISP may be arranged on the display panel DP and sense external input. The input sensing layer ISP may be arranged directly on the display panel DP. According to an embodiment of the present invention, the input sensing layer ISP may be formed on the display panel DP by a continuous process. That is, in the case where the input sensing layer ISP is arranged directly on the display panel DP, an internal adhesive film (not shown) is not arranged between the input sensing layer ISP and the display panel DP. However, an internal adhesive film may be arranged between the input sensing layer ISP and the display panel DP. In this case, the input sensing layer ISP is not manufactured by a process continuous with the display panel DP, and may be fixed on the upper surface of the display panel DP by an internal adhesive film after being manufactured by an additional process with the display panel DP.

[0055] The window WM may be made of a transparent substance that allows the image IM to be emitted. For example, the window WM may be made of glass, sapphire, plastic, etc. Although the window WM is shown as a single layer, it is not limited thereto and may include a plurality of layers.

[0056] In addition, although not shown, the non-display area NDA of the display device DD described above may be substantially provided as an area in which a substance containing a predetermined color is printed in an area of ​​the window WM. As an example of the present invention, the window WM may include a shading pattern for defining the non-display area NDA. The shading pattern is a colored organic film, for example, which may be formed by coating.

[0057] The window WM may be bonded to the display module DM via an adhesive film. As an example of the present invention, the adhesive film may include an optically clear adhesive film (OCA). However, the adhesive film is not limited thereto and may include a common adhesive or bonding agent. For example, the adhesive film may include an optically clear adhesive resin (OCR) or a pressure sensitive adhesive film (PSA).

[0058] An anti-reflection layer may also be arranged between the window WM and the display module DM. The anti-reflection layer reduces the reflectivity of external light incident from the upper side of the window WM. The anti-reflection layer according to an embodiment of the present invention may include a phase retarder and a polarizer. The phase retarder may be a film type or a liquid crystal coating type, and may include a λ / 2 phase retarder and / or a λ / 4 phase retarder. The polarizer may also be a film type or a liquid crystal coating type. The film type may include an extended synthetic resin film, and the liquid crystal coating type may include liquid crystals arranged in a predetermined arrangement. The phase retarder and the polarizer may be implemented as one polarizing film.

[0059] As an example of the present invention, the anti-reflection layer may also include a color filter. Figure 3 ) to determine the arrangement of the color filters. In this case, the anti-reflection layer may further include a light shielding pattern arranged between the color filters.

[0060] The display module DM may display an image IM according to an electrical signal, and may receive / transmit information for external input. The display module DM may be defined as an active area AA and a non-active area NAA. The active area AA may be defined as an area for the image IM to be emitted from the display panel DP (i.e., an area for displaying the image IM). In addition, the active area AA may also be defined as an area for the input sensing layer ISP to sense an external input applied from the outside. According to an embodiment, the active area AA of the display module DM may correspond to (or overlap) at least a portion of the display area DA.

[0061] The non-active area NAA is adjacent to the active area AA. The non-active area NAA may be an area that does not substantially display the image IM. For example, the non-active area NAA may surround the active area AA. However, this is shown exemplarily, and the non-active area NAA may be defined as a variety of shapes and is not limited to any one embodiment. According to one embodiment, the non-active area NAA of the display module DM may correspond to (or overlap) at least a portion of the non-display area NDA.

[0062] The display device DD may further include a plurality of flexible films FF connected to the display panel DP. A driving chip DIC may be mounted on each of the flexible films FF. As an example of the present invention, the source driving circuit 200 (see Figure 3 ) can be composed of multiple driving chips DIC, and the multiple driving chips DIC can be respectively mounted on multiple flexible films FF.

[0063] The display device DD may further include at least one circuit board PCB combined with a plurality of flexible films FF. As an example of the present invention, although two circuit boards PCB are provided in the display device DD, the number of circuit boards PCB is not limited thereto. Two adjacent circuit boards PCB in the circuit boards PCB may be electrically connected to each other through the connecting film CF. In addition, at least one of the circuit boards PCB may be electrically connected to the main board. A driving controller 100 (see Figure 3 ) and voltage generator 400 (refer to Figure 3 )wait.

[0064] Although in Figure 2 , the structure in which the driving chips DIC are respectively mounted on the flexible films FF is shown, but the present invention is not limited thereto. For example, the driving chip DIC may be directly mounted on the display panel DP. In this case, the portion of the display panel DP on which the driving chip DIC is mounted may be bent and arranged on the rear of the display module DM.

[0065] The input sensing layer ISP may be electrically connected to the circuit board PCB through the flexible film FF. However, the embodiments of the present invention are not limited thereto. That is, the display module DM may additionally include an additional flexible film for electrically connecting the input sensing layer ISP to the circuit board PCB.

[0066] The display device DD also includes a housing EDC that accommodates the display module DM. The housing EDC may be combined with the window WM to define the appearance of the display device DD. The housing EDC absorbs impacts applied from the outside and prevents foreign matter / moisture, etc. from penetrating into the display module DM to protect the structure accommodated in the housing EDC. In addition, as an example of the present invention, the housing EDC may be provided in a form in which a plurality of accommodating components are combined.

[0067] According to one embodiment, the display device DD may also include an electronic module including various functional modules for operating the display module DM, a power supply module (e.g., a battery) for supplying power required for the overall operation of the display device DD, a bracket combined with the display module DM and / or the housing EDC to divide the internal space of the display device DD, and the like.

[0068] Figure 3 is a block diagram of a display device according to an embodiment of the present invention.

[0069] Reference Figure 3 The display device DD includes a driving controller 100, a source driving circuit 200, a selection circuit 250, a scanning driving circuit 300, a voltage generator 400 and a display panel DP. As an example of the present invention, the source driving circuit 200 may include a data driver and a sensing driver.

[0070] The display panel DP includes driving scan lines SCL1 to SCLn, sensing scan lines SSL1 to SSLn, data lines DL1 to DLm, and pixels PX. Here, n and m are integers greater than 1. The display panel DP may be divided into an active area AA and a non-active area NAA. The pixels PX may be arranged in the active area AA, and the scan driving circuit 300 may be arranged in the non-active area NAA.

[0071] The driving scan lines SCL1 to SCLn and the sensing scan lines SSL1 to SSLn extend in parallel with the first direction DR1 and are arranged to be spaced apart from each other in the second direction DR2. The second direction DR2 may be a direction crossing the first direction DR1. The data lines DL1 to DLm extend from the selection circuit 250 in parallel with the second direction DR2 and are arranged to be spaced apart from each other in the first direction DR1.

[0072] The plurality of pixels PX are electrically connected to the driving scan lines SCL1 to SCLn, the sensing scan lines SSL1 to SSLn, and the data lines DL1 to DLm, respectively. Each of the plurality of pixels PX may be electrically connected to two scan lines. However, the number of scan lines connected to each pixel PX is not limited thereto. For example, each of the plurality of pixels PX may be electrically connected to one or three scan lines. The display panel DP may further include sensing lines extending in the second direction DR2 and arranged in the first direction DR1. In this case, the plurality of pixels PX may be connected to the sensing lines.

[0073] Each of the plurality of pixels PX includes a light emitting device and a pixel circuit portion for controlling light emission of the light emitting device. The light emitting device may include an organic light emitting diode. The pixel circuit portion may include a plurality of transistors and at least one capacitor.

[0074] The driving controller 100 receives an input image signal RGB and a control signal CTRL from a main controller (eg, a microcontroller or a graphic controller). The driving controller 100 may convert the input image signal RGB to generate image data DATA.

[0075] The driving controller 100 generates a scanning control signal GCS and a source control signal DCS based on a control signal CTRL. The source driving circuit 200 receives the source control signal DCS and the image data DATA from the driving controller 100, and converts the image data DATA into a data signal in response to the source control signal DCS. The source driving circuit 200 outputs the data signal to a plurality of data lines DL1 to DLm. The data signal may be an analog voltage corresponding to the grayscale value of the image data DATA.

[0076] Alternatively, the source driving circuit 200 may also be connected to a plurality of sensing lines. In this case, the source driving circuit 200 may also receive a sensing control signal from the driving controller 100, and may sense the characteristics of the devices included in each pixel PX of the display panel DP in response to the sensing control signal.

[0077] As an example of the present invention, the source driver circuit 200 may be formed in at least one chip form. For example, the source driver circuit 200 may be arranged in Figure 2 The driver chip shown in DIC.

[0078] The selection circuit 250 may be arranged between the data lines DL1 to DLm and the source driving circuit 200. The source driving circuit 200 may be connected to the selection circuit 250 through the fan-out lines FL1 to FLk. Here, k is an integer greater than 1 and less than m. As an example of the present invention, the number k of the fan-out lines FL1 to FLk may be 1 / 2, 1 / 3, or 1 / 4 of the number m of the data lines DL1 to DLm. In the case where the number k of the fan-out lines FL1 to FLk is 1 / 2 of the number m of the data lines DL1 to DLm, the data lines DL1 to DLm may be divided into two groups (i.e., a first data line group and a second data line group). The selection circuit 250 is in the first selection interval SP1 (refer to Figure 7 ) during which a portion of the data lines DL1 to DLm (eg, the first data line group) is electrically connected to the source driving circuit 200, and in the second selection interval SP2 (refer to Figure 7 ) during which a portion of the data lines DL1 to DLm (eg, the second data line group) is electrically connected to the source driving circuit 200.

[0079] As an example of the present invention, the selection circuit 250 may be arranged in the non-active area NAA of the display panel DP. In particular, the selection circuit 250 may be formed in the non-active area NAA by the same process as the pixel circuit portion of each pixel PX. The selection circuit 250 is used to selectively drive the data lines DL1 to DLm, thereby reducing the number of channels CH1 to CHk of the source driving circuit 200 as a whole (refer to Figure 4 ) and the number of fan-out lines FL1 to FLk.

[0080] The scan driving circuit 300 receives a scan control signal GCS from the driving controller 100. The scan driving circuit 300 may output a scan signal in response to the scan control signal GCS. The scan driving circuit 300 may be built in the display panel DP. In the case where the scan driving circuit 300 is built in the display panel DP, the scan driving circuit 300 may include a transistor formed by the same process as the pixel circuit part of each pixel PX. Although the scan driving circuit 300 may be arranged in the non-active area NAA of the display panel DP, the present invention is not limited thereto. The scan driving circuit 300 may overlap with the active area AA of the display panel DP.

[0081] The scan driving circuit 300 may generate a plurality of driving scan signals and a plurality of sensing scan signals in response to the scan control signal GCS. The plurality of driving scan signals are applied to the driving scan lines SCL1 to SCLn, and the plurality of sensing scan signals are applied to the sensing scan lines SSL1 to SSLn.

[0082] As an example of the present invention, the scan driving circuit 300 includes a first scan driving circuit 310 and a second scan driving circuit 320. The first scan driving circuit 310 is arranged at the left side with the active area AA as a reference, and the second scan driving circuit 320 is arranged at the right side with the active area AA as a reference. The first scan driving circuit 310 receives a first scan control signal GCS1 from the driving controller 100, and the second scan driving circuit 320 receives a second scan control signal GCS2 from the driving controller 100. The first scan driving circuit 310 may generate a plurality of drive scan signals and a plurality of sense scan signals in response to the first scan control signal GCS1. The second scan driving circuit 320 may generate a plurality of drive scan signals and a plurality of sense scan signals in response to the second scan control signal GCS2.

[0083] Although in Figure 3 3 shows a structure in which the first scan driving circuit 310 and the second scan driving circuit 320 are respectively arranged at the left and right sides of the active area AA, but the present invention is not limited thereto. The scan driving circuit 300 may include only one of the first scan driving circuit 310 and the second scan driving circuit 320.

[0084] Each of the plurality of pixels PX may receive a first driving voltage ELVSS and a second driving voltage ELVDD.

[0085] The voltage generator 400 generates voltages required for the operation of the display panel DP. In one embodiment of the present invention, the voltage generator 400 generates a first driving voltage ELVSS and a second driving voltage ELVDD required for the operation of the display panel DP. The first driving voltage ELVSS and the second driving voltage ELVDD may be provided to the display panel DP through a first driving voltage line VL1 and a second driving voltage line VL2.

[0086] The voltage generator 400 can not only generate the first driving voltage ELVSS and the second driving voltage ELVDD, but also generate various voltages required for the operation of the source driving circuit 200 and the scan driving circuit 300 (for example, a gamma reference voltage, a data driving voltage, a gate-on voltage, a gate-off voltage, etc.).

[0087] Figure 4 Detailed description is a block diagram showing the connection relationship between a source driving circuit and a selection circuit according to an embodiment of the present invention.

[0088] Reference Figure 4, the source driving circuit 200 may be connected to the selection circuit 250 through the fan-out lines FL1 to FLk. The source driving circuit 200 may include a plurality of channels CH1, CH2, CH3, CH4, CH5, CH6 to CHk-2, CHk-1, CHk respectively connected to the fan-out lines FL1 to FLk. The fan-out lines FL1 to FLk may be selectively connected to corresponding data lines among the data lines DL1 to DLm through the selection circuit 250. As an example of the present invention, the number k of the fan-out lines FL1 to FLk may be 1 / 2 of the number m of the data lines DL1 to DLm.

[0089] The selection circuit 250 may include a plurality of switch circuits. As an example of the present invention, the selection circuit 250 includes a first switch circuit 251 and a second switch circuit 253. The first switch circuit 251 and the second switch circuit 253 may be activated alternately with each other. The interval in which the first switch circuit 251 is activated is referred to as a first selection interval SP1 (refer to Figure 7 ), and the interval in which the second switch circuit 253 is activated is called the second selection interval SP2 (refer to Figure 7 ). The first switch circuit 251 is activated during the first selection interval SP1 to electrically connect the fan-out lines FL1 to FLk to a portion (e.g., a first data line group) of the data lines DL1 to DLm. The second switch circuit 253 is activated during the second selection interval SP2 to electrically connect the fan-out lines FL1 to FLk to a portion (e.g., a second data line group) of the data lines DL1 to DLm.

[0090] The first switch circuit 251 includes a plurality of first switch transistors TS11 to TS1k, and the second switch circuit 253 includes a plurality of second switch transistors TS21 to TS2k. The plurality of first switch transistors TS11 to TS1k are connected between the first data line group and the fan-out lines FL1 to FLk, and the plurality of second switch transistors TS21 to TS2k are connected between the second data line group and the fan-out lines FL1 to FLk.

[0091] The 1-1st switching transistor TS11 among the plurality of first switching transistors TS11 to TS1k includes an input electrode connected to a first fan-out line FL1 among the fan-out lines FL1 to FLk, an output electrode connected to a first data line DL1 among the data lines DL1 to DLm, and a control electrode receiving a first selection signal CLA. The 1-2nd switching transistor TS12 among the plurality of first switching transistors TS11 to TS1k includes an input electrode connected to a second fan-out line FL2 among the fan-out lines FL1 to FLk, an output electrode connected to a second data line DL2 among the data lines DL1 to DLm, and a control electrode receiving a first selection signal CLA. The 1-3rd switching transistor TS13 among the plurality of first switching transistors TS11 to TS1k includes an input electrode connected to a third fan-out line FL3 among the fan-out lines FL1 to FLk, an output electrode connected to a third data line DL3 among the data lines DL1 to DLm, and a control electrode receiving a first selection signal CLA.

[0092] As an example of the present invention, the first, second and third data lines DL1, DL2 and DL3 may be connected to the first, second and third pixels PXR1, PXG1 and PXB1, respectively. The first, second and third pixels PXR1, PXG1 and PXB1 may output different color lights from each other.

[0093] The 2-1st switching transistor TS21 among the plurality of second switching transistors TS21 to TS2k includes an input electrode connected to the first fan-out line FL1 among the fan-out lines FL1 to FLk, an output electrode connected to the fourth data line DL4 among the data lines DL1 to DLm, and a control electrode receiving the second selection signal CLB. The 2-2nd switching transistor TS22 among the plurality of second switching transistors TS21 to TS2k includes an input electrode connected to the second fan-out line FL2 among the fan-out lines FL1 to FLk, an output electrode connected to the fifth data line DL5 among the data lines DL1 to DLm, and a control electrode receiving the second selection signal CLB. The 2-3rd switching transistor TS23 among the plurality of second switching transistors TS21 to TS2k includes an input electrode connected to the third fan-out line FL3 among the fan-out lines FL1 to FLk, an output electrode connected to the sixth data line DL6 among the data lines DL1 to DLm, and a control electrode receiving the second selection signal CLB.

[0094] As an example of the present invention, the fourth data line DL4, the fifth data line DL5, and the sixth data line DL6 may be connected to the fourth pixel PXR2, the fifth pixel PXG2, and the sixth pixel PXB2, respectively. The fourth pixel PXR2, the fifth pixel PXG2, and the sixth pixel PXB2 may output color lights different from each other. The first pixel PXR1 and the fourth pixel PXR2 may output a first color light (e.g., red light), the second pixel PXG1 and the fifth pixel PXG2 may output a second color light (e.g., green light), and the third pixel PXB1 and the sixth pixel PXB2 may output a third color light (e.g., blue light).

[0095] When the first selection signal CLA is activated during the first selection interval SP1, the first switching transistors TS11 to TS1k may be turned on, and the data signals provided to the fan-out lines FL1 to FLk may be applied to the first data line group through the first switching transistors TS11 to TS1k. When the second selection signal CLB is activated during the second selection interval SP2, the second switching transistors TS21 to TS2k may be turned on, and the data signals provided to the fan-out lines FL1 to FLk may be applied to the second data line group through the second switching transistors TS21 to TS2k.

[0096] In one embodiment, each of the first switch transistors TS11 to TS1k and the second switch transistors TS21 to TS2k may be configured as a P-type transistor. However, this is not limited thereto, and each of the first switch transistors TS11 to TS1k and the second switch transistors TS21 to TS2k may be configured as an N-type transistor. When each of the first switch transistors TS11 to TS1k and the second switch transistors TS21 to TS2k is configured as a P-type transistor, the first selection signal CLA and the second selection signal CLB may have a low level during the first selection interval SP1 and the second selection interval SP2. On the contrary, when each of the first switch transistors TS11 to TS1k and the second switch transistors TS21 to TS2k is configured as an N-type transistor, the first selection signal CLA and the second selection signal CLB may have a high level during the first selection interval SP1 and the second selection interval SP2.

[0097] Figure 5 is a block diagram of a source driving circuit according to an embodiment of the present invention. Figure 6 It is shown Figure 5 Waveform diagram of the first latch control signal and the second latch control signal shown in . Figure 7 is a waveform diagram showing a first selection signal and a second selection signal, a second latch control signal, and a scan signal according to an embodiment of the present invention.

[0098] Reference Figure 5The source driving circuit 200 includes a shift register 210 , a first latch 221 , a second latch 222 , a third latch 223 , a digital-to-analog converter 230 , and an output buffer 240 .

[0099] The shift register 210 may start operating in response to the horizontal start signal STH and sequentially output the data clock signal CLK. The horizontal start signal STH may be included in the slave driving controller 100 (refer to Figure 3 ) provides a source control signal DCS (refer to Figure 3 ) in the signal.

[0100] The data clock signal CLK output from the shift register 210 may be provided to the first latch 221. The first latch 221 receives the image data DATA from the driving controller 100 and sequentially stores the image data DATA in response to the data clock signal CLK. The first latch 221 may store k image data DATA corresponding to the k channels CH1 to CHk of the source driving circuit 200, respectively. Hereinafter, for convenience of explanation, the k image data DATA may be referred to as line image data.

[0101] The first latch 221 may output line image data in parallel and provide it to the second latch 222. That is, the first latch 221 may receive the image data in a serial form and output it in a parallel form when outputting it. Here, receiving in a serial form means sequentially receiving a plurality of image data DATA corresponding to a plurality of pixels, and outputting in a parallel form means simultaneously outputting a plurality of image data DATA corresponding to a plurality of pixels.

[0102] The second latch 222 receives the line image data from the first latch 221 and outputs the line image data in response to the first latch control signal CS_L1. The first latch control signal CS_L1 may be included in the slave driving controller 100 (refer to Figure 3 ) provides a source control signal DCS (refer to Figure 3 The first latch control signal CS_L1 may include a reference output interval TP0 (refer to Figure 6 ).like Figure 6 As shown in , the reference period of the first latch control signal CS_L1 may be constant, but not variable.

[0103] The third latch 223 receives the line image data from the second latch 222 and outputs the line image data in response to the second latch control signal CS_L2. The second latch control signal CS_L2 may be included in the slave driving controller 100 (refer to Figure 3 ) provides a source control signal DCS (refer to Figure 3 ) in the signal. Figure 6 As shown in , the period of the second latch control signal CS_L2 may be variable rather than constant. As an example of the present invention, the second latch control signal CS_L2 may include a first output interval TP1 and a second output interval TP2. The period of the first output interval TP1 may be different from the period of the second output interval TP2. For example, the period of the first output interval TP1 may be smaller than the reference period of the reference output interval TP0, and the period of the second output interval TP2 may be larger than the reference period of the reference output interval TP0. Although the period of the reference output interval TP0 of the first latch control signal CS_L1 is fixed to be constant, when a third latch 223 is added to the source drive circuit 200, the period of the first output interval TP1 and the second output interval TP2 of the second latch control signal CS_L2 can be freely adjusted. In particular, by combining the first output interval TP1 and the second output interval TP2 with the scan signal SC (reference Figure 7 ) of the active interval AP (refer to Figure 7 ) The period of the second output interval TP2 overlapped with the first output interval TP1 is ensured to be greater than the period of the first output interval TP1, and the scanning signal SC can be increased (refer to Figure 7 ) of the active interval AP (refer to Figure 7 )’s width.

[0104] The DAC 230 receives the line image data from the third latch 223. The line image data is in digital form, and the DAC 230 converts the line image data into a data signal in analog form. The DAC 230 may receive the gamma reference voltage VGM, and may convert the line image data into a data signal based on the gamma reference voltage VGM.

[0105] The data signal generated from the digital-to-analog converter 230 is provided to the output buffer 240. The output buffer 240 may output the data through the channels CH1 to CHk (refer to Figure 4 ) output data signal. The output enable signal OE may be included in the slave drive controller 100 (refer to Figure 3 ) provides a source control signal DCS (refer to Figure 3 ) in the signal.

[0106] Reference Figures 5 to 7 , the second latch control signal CS_L2 includes a first output interval TP1 and a second output interval TP2. The start time point t1 of the first output interval TP1 precedes the start time point t3 of the first selection interval SP1, and the start time point t2 of the second output interval TP2 precedes the start time point t4 of the second selection interval SP2. The start time point t2 of the second output interval TP2 may be later than the end time point of the first selection interval SP1. Therefore, the second output interval TP2 does not overlap with the first selection interval SP1.

[0107] The third latch 223 may output the first data signal group O_DATA during the first output interval TP1, and may output the second data signal group E_DATA during the second output interval TP2. The first data signal group O_DATA is applied to the first data line group through the first switch circuit 251 activated during the first selection interval SP1, and the second data signal group E_DATA is applied to the second data line group through the second switch circuit 253 activated during the second selection interval SP2.

[0108] The duration of the first selection interval SP1 may be the same as the duration of the second selection interval SP2. The first selection interval SP1 and the second selection interval SP2 may not overlap with each other.

[0109] Figure 3 A scan signal SC is applied to each of the plurality of scan lines (e.g., drive scan lines SCL1 to SCLn) shown in . The active interval AP of each of the scan signals SC may overlap with the second selection interval SP2, and may not overlap with the first selection interval SP1. As an example of the present invention, the active interval AP of each of the scan signals SC may be a low level interval, and the inactive interval may be a high level interval. However, the present invention is not limited thereto. For example, in the case where the active interval AP of each of the scan signals SC is a high level interval, the inactive interval may be a low level interval.

[0110] As an example of the present invention, the period of the second output interval TP2 is greater than the period of the first output interval TP1. In this way, when the third latch 223 is added to the source driving circuit 200, the width of the active interval AP of the scanning signal SC can be increased by ensuring that the period of the second output interval TP2 is greater than the period of the first output interval TP1. As a result, even if a selective driving method of selectively driving the data lines DL1 to DLm is adopted, the active interval AP of the scanning signal SC can be fully ensured, thereby improving the image quality problem caused by insufficient data charging time of each pixel PX.

[0111] Figure 8 Detailed description is a block diagram showing the connection relationship between a source driving circuit and a selection circuit according to an embodiment of the present invention. Fig. 9 is a waveform diagram showing a first selection signal, a second selection signal, a third selection signal, a second latch control signal, and a scan signal according to an embodiment of the present invention. Figure 8 and Fig. 9 The components shown in Figure 4 and Figure 7 The same constituent elements as those shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

[0112] Reference Figure 8 and Fig. 9 , the source driving circuit 200a may be connected to the selection circuit 250a through the fan-out lines FL1 to FLk. The source driving circuit 200a may include a plurality of channels CH1, CH2, CH3 to CHk-2, CHk-1, CHk respectively connected to the fan-out lines FL1 to FLk. The fan-out lines FL1 to FLk may be selectively connected to corresponding data lines among the data lines DL1 to DLm through the selection circuit 250a. As an example of the present invention, the number k of the fan-out lines FL1 to FLk may be 1 / 3 of the number m of the data lines DL1 to DLm.

[0113] The selection circuit 250a may include a plurality of switch circuits. As an example of the present invention, the selection circuit 250a includes a first switch circuit 251a, a second switch circuit 253a, and a third switch circuit 255a. The first switch circuit 251a, the second switch circuit 253a, and the third switch circuit 255a may be activated alternately with each other. The interval in which the first switch circuit 251a is activated is referred to as a first selection interval SPa, and the interval in which the second switch circuit 253a is activated is referred to as a second selection interval SPb, and the interval in which the third switch circuit 255a is activated is referred to as a third selection interval SPc. The first switch circuit 251a is activated during the first selection interval SPa to electrically connect the fan-out lines FL1 to FLk to a portion of the data lines DL1 to DLm (e.g., a first data line group). The second switch circuit 253a is activated during the second selection interval SPb to electrically connect the fan-out lines FL1 to FLk to a portion of the data lines DL1 to DLm (e.g., a second data line group). The third switch circuit 255a is activated during the third selection interval SPc to electrically connect the fan-out lines FL1 to FLk to a portion (eg, a third data line group) of the data lines DL1 to DLm.

[0114] The first switch circuit 251a includes a plurality of first switch transistors TS11 to TS1k, the second switch circuit 253a includes a plurality of second switch transistors TS21 to TS2k, and the third switch circuit 255a includes a plurality of third switch transistors TS31 to TS3k. The plurality of first switch transistors TS11 to TS1k are connected between the first data line group and the fan-out lines FL1 to FLk, and the plurality of second switch transistors TS21 to TS2k are connected between the second data line group and the fan-out lines FL1 to FLk. The plurality of third switch transistors TS31 to TS3k are connected between the third data line group and the fan-out lines FL1 to FLk.

[0115] The 1-1st switching transistor TS11 among the plurality of first switching transistors TS11 to TS1k includes an input electrode connected to a first fan-out line FL1 among the fan-out lines FL1 to FLk, an output electrode connected to a first data line DL1 among the data lines DL1 to DLm, and a control electrode receiving a first selection signal CLA. The 1-2nd switching transistor TS12 among the plurality of first switching transistors TS11 to TS1k includes an input electrode connected to a second fan-out line FL2 among the fan-out lines FL1 to FLk, an output electrode connected to a second data line DL2 among the data lines DL1 to DLm, and a control electrode receiving a first selection signal CLA. The 1-3rd switching transistor TS13 among the plurality of first switching transistors TS11 to TS1k includes an input electrode connected to a third fan-out line FL3 among the fan-out lines FL1 to FLk, an output electrode connected to a third data line DL3 among the data lines DL1 to DLm, and a control electrode receiving a first selection signal CLA.

[0116] The 2-1st switching transistor TS21 among the plurality of second switching transistors TS21 to TS2k includes an input electrode connected to the first fan-out line FL1 among the fan-out lines FL1 to FLk, an output electrode connected to the fourth data line DL4 among the data lines DL1 to DLm, and a control electrode receiving the second selection signal CLB. The 2-2nd switching transistor TS22 among the plurality of second switching transistors TS21 to TS2k includes an input electrode connected to the second fan-out line FL2 among the fan-out lines FL1 to FLk, an output electrode connected to the fifth data line DL5 among the data lines DL1 to DLm, and a control electrode receiving the second selection signal CLB. The 2-3rd switching transistor TS23 among the plurality of second switching transistors TS21 to TS2k includes an input electrode connected to the third fan-out line FL3 among the fan-out lines FL1 to FLk, an output electrode connected to the sixth data line DL6 among the data lines DL1 to DLm, and a control electrode receiving the second selection signal CLB.

[0117] The 3-1st switching transistor TS31 among the plurality of third switching transistors TS31 to TS3k includes an input electrode connected to the first fan-out line FL1 among the fan-out lines FL1 to FLk, an output electrode connected to the seventh data line DL7 among the data lines DL1 to DLm, and a control electrode receiving the third selection signal CLC. The 3-2nd switching transistor TS32 among the plurality of third switching transistors TS31 to TS3k includes an input electrode connected to the second fan-out line FL2 among the fan-out lines FL1 to FLk, an output electrode connected to the eighth data line DL8 among the data lines DL1 to DLm, and a control electrode receiving the third selection signal CLC. The 3-3rd switching transistor TS33 among the plurality of third switching transistors TS31 to TS3k includes an input electrode connected to the third fan-out line FL3 among the fan-out lines FL1 to FLk, an output electrode connected to the ninth data line DL9 among the data lines DL1 to DLm, and a control electrode receiving the third selection signal CLC.

[0118] When the first selection signal CLA is activated during the first selection interval SPa, the first switching transistors TS11 to TS1k may be turned on, and the data signals provided to the fan-out lines FL1 to FLk may be applied to the first data line group through the first switching transistors TS11 to TS1k. When the second selection signal CLB is activated during the second selection interval SPb, the second switching transistors TS21 to TS2k may be turned on, and the data signals provided to the fan-out lines FL1 to FLk may be applied to the second data line group through the second switching transistors TS21 to TS2k. When the third selection signal CLC is activated during the third selection interval SPc, the third switching transistors TS31 to TS3k may be turned on, and the data signals provided to the fan-out lines FL1 to FLk may be applied to the third data line group through the third switching transistors TS31 to TS3k.

[0119] Reference Fig. 9 , the period of the second latch control signal CS_L2a may be variable, not constant. The second latch control signal CS_L2a may include a first output interval TPa, a second output interval TPb, and a third output interval TPc. The period of the first output interval TPa may be the same as the period of the second output interval TPb, and the period of the third output interval TPc may be different from the period of the first output interval TPa and the period of the second output interval TPb. The period of the third output interval TPc may be greater than the period of the first output interval TPa and the period of the second output interval TPb.

[0120] The start time point of the first output interval TPa precedes the start time point of the first selection interval SPa, and the start time point of the second output interval TPb precedes the start time point of the second selection interval SPb. The start time point of the third output interval TPc precedes the start time point of the third selection interval SPc. The start time point of the second output interval TPb may be later than the end time point of the first selection interval SPa, and the start time point of the third output interval TPc may be later than the end time point of the second selection interval SPb. Therefore, the second output interval TPb does not overlap with the first selection interval SPa, and the third output interval TPc does not overlap with the second selection interval SPb.

[0121] The first selection interval SPa precedes the second selection interval SPb, and the second selection interval SPb precedes the third selection interval SPc. The duration of the first selection interval SPa may be the same as the duration of the second selection interval SPb and the duration of the third selection interval SPc. The first selection interval SPa, the second selection interval SPb, and the third selection interval SPc may not overlap with each other.

[0122] The first selection interval SPa of the first selection signal CLA overlaps with the first output interval TPa of the second latch control signal CS_L2a, and the second selection interval SPb of the second selection signal CLB overlaps with the second output interval TPb of the second latch control signal CS_L2a. The third selection interval SPc of the third selection signal CLC overlaps with the third output interval TPc of the second latch control signal CS_L2a.

[0123] The third latch 223 (see Figure 5 ) can output a first data signal group during a first output interval TPa, can output a second data signal group during a second output interval TPb, and can output a third data signal group during a third output interval TPc. The first data signal group is applied to the first data line group through a first switch circuit 251a activated during a first selection interval SPa, and the second data signal group is applied to the second data line group through a second switch circuit 253a activated during a second selection interval SPb. The third data signal group is applied to the third data line group through a third switch circuit 255a activated during a third selection interval SPc.

[0124] Figure 3A scan signal SC is applied to each of the plurality of scan lines (e.g., drive scan lines SCL1 to SCLn) shown in . The active interval APa of each of the scan signals SC may overlap with the third selection interval SPc, and may not overlap with the first selection interval SPa and the second selection interval SPb. As an example of the present invention, the active interval APa of each of the scan signals SC may be a low level interval, and the inactive interval may be a high level interval.

[0125] In this way, even if the number of channels CH1 to CHk and the number of fan-out lines FL1 to FLk are reduced to 1 / 3 or 1 / 4 of the number of data lines DL1 to DLm, etc., when the third latch 223 is added to the source driving circuit 200, the period of the output interval (i.e., the third output interval TPc) overlapping with the active interval APa of the scanning signal SC can be set to be larger than the period of the output interval (i.e., the first output interval TPa and the second output interval TPb) that does not overlap with the active interval APa. Therefore, the active interval AP of the scanning signal SC can be fully ensured, and as a result, the image quality problem caused by insufficient data charging time of each pixel PX can be improved.

[0126] Fig.10 is a block diagram of a data driver according to an embodiment of the present invention. Fig.11 2 is a waveform diagram showing the first selection signal and the second selection signal, the first sub-latch control signal and the second sub-latch control signal, and the scan signal according to an embodiment of the present invention. Fig.10 and Fig.11 The components shown in Figure 5 and Figure 7 The same constituent elements as those shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

[0127] Reference Fig.10 The source driving circuit 200 b includes a shift register 210 , a first latch 221 , a second latch 225 , a digital-to-analog converter 230 , and an output buffer 240 .

[0128] The second latch 225 includes a first sub-latch 225a and a second sub-latch 225b. The second latch 225 receives line image data from the first latch 221 and stores the line image data alternately in the first sub-latch 225a and the second sub-latch 225b. The second latch 225 outputs the first line image data of the first sub-latch 225a in response to the first sub-latch control signal CS_SL1, and outputs the second line image data of the second sub-latch 225b in response to the second sub-latch control signal CS_SL2. The first sub-latch control signal CS_SL1 and the second sub-latch control signal CS_SL2 may be included in the slave driving controller 100 (refer to Figure 3 ) provides a source control signal DCS (refer to Figure 3 ) in the signal.

[0129] The first sub-latch control signal CS_SL1 includes a first sub-output interval STP1, and the second sub-latch control signal CS_SL2 includes a second sub-output interval STP2. The period of the first sub-output interval STP1 may be the same as the period of the second sub-output interval STP2. In the case where the second latch 225 has more than two sub-latches (for example, the first sub-latch 225a and the second sub-latch 225b), the starting time point of the sub-output interval can be variably set. As an example of the present invention, the starting time point st1 of the first sub-output interval STP1 may precede the starting time point st2 of the second sub-output interval STP2. The starting time point st2 of the second sub-output interval STP2 may precede the 1 / 2 point ht1 of the first sub-output interval STP1.

[0130] The start time point st1 of the first sub-output interval STP1 precedes the start time point t3 of the first selection interval SP1, and the start time point st2 of the second sub-output interval STP2 precedes the start time point t4 of the second selection interval SP2. The start time point st2 of the second sub-output interval STP2 may be later than the end time point of the first selection interval SP1. Therefore, the second sub-output interval STP2 does not overlap with the first selection interval SP1. The start time point t4 of the second selection interval SP2 may be earlier than the 1 / 2 point ht1 of the first sub-output interval STP1.

[0131] The first sub-latch 225a may output the first data signal group O_DATA during the first sub-output interval STP1, and the second sub-latch 225b may output the second data signal group E_DATA during the second sub-output interval STP2. The first data signal group O_DATA is applied to the first data line group through the first switch circuit 251 activated during the first selection interval SP1, and the second data signal group E_DATA is applied to the second data line group through the second switch circuit 253 activated during the second selection interval SP2.

[0132] The duration of the first selection interval SP1 may be the same as the duration of the second selection interval SP2. The first selection interval SP1 and the second selection interval SP2 may not overlap with each other.

[0133] Figure 3A scan signal SC is applied to each of the plurality of scan lines (e.g., drive scan lines SCL1 to SCLn) shown in . The active interval AP of each of the scan signals SC may overlap with the second selection interval SP2, and may not overlap with the first selection interval SP1. As an example of the present invention, the active interval AP of each of the scan signals SC may be a low level interval, and the inactive interval may be a high level interval. However, the present invention is not limited thereto. For example, in the case where the active interval AP of each of the scan signals SC is a high level interval, the inactive interval may be a low level interval.

[0134] In the case where the second latch 225 has two or more sub-latches (for example, the first sub-latch 225a and the second sub-latch 225b), the start time point st2 of the second sub-output interval STP2 related to the active interval AP of each scanning signal SC can be sufficiently advanced. Therefore, even if a selective driving method of selectively driving the data lines DL1 to DLm is adopted, the active interval AP of the scanning signal SC can be sufficiently ensured, and thus the image quality problem caused by insufficient data charging time of each pixel PX can be improved.

[0135] Although the above description is made with reference to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art or those of ordinary skill in the art that various modifications and changes can be made to the present invention without departing from the scope of the concept and technical field of the present invention as recorded in the attached claims. Therefore, the technical scope of the present invention shall be limited only by the claims, and not by the contents recorded in the detailed description of the specification.

Claims

1. A display device, include: A display panel, the display panel comprising a plurality of pixels and a plurality of data lines connected to the plurality of pixels; a source driving circuit, wherein the source driving circuit outputs a data signal to the plurality of data lines; as well as a selection circuit, the selection circuit being arranged between the plurality of data lines and the source driving circuit and selectively connecting the source driving circuit to a portion of the plurality of data lines, The source driving circuit comprises: a first latch that sequentially stores image data in response to a data clock signal and generates line image data; a second latch receiving the line image data from the first latch and outputting the line image data in response to a first latch control signal; and a third latch that receives the line image data from the second latch and outputs the line image data in response to a second latch control signal, A period of the first latch control signal is constant, and a period of the second latch control signal is variable.

2. The display device according to claim 1, in, The selection circuit comprises: a first switching circuit that is activated during a first selection interval; and a second switching circuit, the second switching circuit being activated during a second selection interval, The second latch control signal includes a first output interval that starts before a start time point of the first selection interval, and a second output interval that starts before a start time point of the second selection interval. A period of the first output interval is different from a period of the second output interval.

3. The display device according to claim 2, in, The first selection interval precedes the second selection interval, The period of the second output interval is greater than the period of the first output interval.

4. The display device according to claim 3, in, The display panel further includes: a plurality of scan lines, wherein the plurality of scan lines are connected to the plurality of pixels, An active interval of a scan signal applied to each of the plurality of scan lines overlaps the second selection interval.

5. The display device according to claim 2, in, The duration of the first selection interval is the same as the duration of the second selection interval.

6. The display device according to claim 2, in, The plurality of data lines include: a first data line group, the first data line group being connected to the source driving circuit through the first switch circuit during the first selection interval; and A second data line group, wherein the second data line group is connected to the source driving circuit through the second switch circuit during the second selection interval.

7. The display device according to claim 1, in, The selection circuit comprises: a first switch circuit, the first switch circuit being activated during a first selection interval; a second switch circuit that is activated during a second selection interval; and a third switching circuit, the third switching circuit being activated during a third selection interval, The second latch control signal includes a first output interval that starts before the start time point of the first selection interval, a second output interval that starts before the start time point of the second selection interval, and a third output interval that starts before the start time point of the third selection interval. The period of the first output interval and the period of the second output interval are different from the period of the third output interval.

8. The display device according to claim 7, in, The first selection interval precedes the second selection interval, and the second selection interval precedes the third selection interval, The period of the third output interval is greater than the period of the first output interval and the period of the second output interval.

9. The display device according to claim 8, in, The display panel further includes: a plurality of scan lines, wherein the plurality of scan lines are connected to the plurality of pixels, An active interval of a scan signal applied to each of the plurality of scan lines overlaps the third selection interval.

10. The display device according to claim 7, in, Durations of the first selection interval to the third selection interval are the same as each other.

11. The display device according to claim 7, in, The plurality of data lines include a first data line group, the first data line group being connected to the source driving circuit through the first switch circuit during the first selection interval; a second data line group, the second data line group being connected to the source driving circuit through the second switch circuit during the second selection interval; as well as A third data line group is connected to the source driving circuit through the third switch circuit during the third selection interval.

12. The display device according to claim 1, in, The source driving circuit further includes: a shift register, the shift register generating the data clock signal; a digital-to-analog converter that receives the line image data from the third latch and converts the line image data into the data signal; and An output buffer outputs the data signal in response to an output enable signal.

13. The display device according to claim 1, further comprising: include: A driving controller provides the image data, the first latch control signal, and the second latch control signal to the source driving circuit.

14. A display device, include: A display panel, the display panel comprising a plurality of pixels and a plurality of data lines connected to the plurality of pixels; A source driving circuit, wherein the source driving circuit outputs a data signal; as well as a selection circuit, the selection circuit being arranged between the plurality of data lines and the source driving circuit and selectively connecting the source driving circuit to a portion of the plurality of data lines, The source driving circuit comprises: a first latch that sequentially stores image data in response to a data clock signal and generates line image data; as well as a second latch, the second latch including a first sub-latch and a second sub-latch, alternately storing the line image data received from the first latch in the first sub-latch and the second sub-latch, outputting the first line image data of the first sub-latch in response to a first sub-latch control signal, and outputting the second line image data of the second sub-latch in response to a second sub-latch control signal, A start time point of a second sub-output interval of the second sub-latch control signal precedes a 1 / 2 point of a first sub-output interval of the first sub-latch control signal.

15. The display device according to claim 14, in, A period of the first sub-latch control signal is the same as a period of the second sub-latch control signal.

16. The display device according to claim 14, in, The selection circuit comprises: a first switching circuit that is activated during a first selection interval; and a second switching circuit, the second switching circuit being activated during a second selection interval, The start time point of the first sub-output interval is earlier than the start time point of the first selection interval, The start time point of the second sub-output interval precedes the start time point of the second selection interval.

17. The display device according to claim 16, in, The duration of the first selection interval is the same as the duration of the second selection interval, and the first selection interval precedes the second selection interval, The start time point of the second selection interval precedes the 1 / 2 point of the first sub-output interval.

18. The display device according to claim 17, in, The display panel further includes: a plurality of scan lines, wherein the plurality of scan lines are connected to the plurality of pixels, An active interval of a scan signal applied to each of the plurality of scan lines overlaps the second selection interval.

19. The display device according to claim 16, in, The plurality of data lines include: a first data line group, the first data line group being connected to the source driving circuit through the first switch circuit during the first selection interval; and A second data line group, wherein the second data line group is connected to the source driving circuit through the second switch circuit during the second selection interval.

20. The display device according to claim 14, in, The source driving circuit further includes: a shift register, the shift register generating the data clock signal; a digital-to-analog converter that receives the first line image data or the second line image data from the second latch and converts the first line image data or the second line image data into the data signal; and An output buffer outputs the data signal in response to an output enable signal.

Images