Novel reading circuit

Abstract

The invention discloses a novel reading circuit. The novel reading circuit comprises a storage unit, a pre-charging module, a reading module, a bit line and a bit negative line, the storage unit is used for storing data; the pre-charging module is used for pre-charging according to the CTRLPC signal; the reading module is used for reading storage data of the storage unit; comprising a fifth PMOS tube, an NAND gate and an inverter. The storage unit, the pre-charging module and the reading module are connected pairwise through a bit line and a bit negative line. The reading circuit provided by the invention is only a pure logic gate combination, and does not need to consider too much circuit performance. In the aspect of cost, the reading circuit only needs seven MOS devices, and compared with a traditional SA, the number of the devices is greatly reduced, and the chip cost is also greatly reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of chip circuit design, and in particular relates to a novel reading circuit. Background Art

[0002] At present, memory chips are generally divided into three parts: word line selector, bit line selector, memory array, read circuit and register, such as Figure 1 shown.

[0003] The word line selector is generally completed through a decoder, used for addressing, and generates a word line WL; the bit line selector is generally combined with the bit line to define the storage cell of the storage array. The storage array is used to store data, and the size of the storage array determines the capacity of the chip. The size of the storage array is determined by the word line (WL) bit width and the bit line (BL) bit width, that is, the storage capacity is determined by the WL bit width * BL bit width. If the WL bit width is 7bis and the BL bit width is 8bits, the storage capacity is 1024bits. A specific word line WL and a specific bit line BL correspond to a specific storage cell in the storage array.

[0004] If the data of the storage unit is to be obtained, a readout circuit is required. Currently, the readout circuit is completed by a sensitive amplifier (SA). In general, the data output of the memory chip is divided into single-bit width output or multi-bit width output. Once the capacity of a memory chip is determined, the storage array area is basically fixed. If the storage capacity of a chip is X bits, and the time required for the output data bit width of 1 bit is t0, then it takes time X / t0 to output all the data; when the output data bit width is N bits, the time required is X / (N*t0), which is N times shorter than 1 bit. That is to say, the transmission efficiency of the output data when the bit width is N bits is 1 / N times that of the output of 1 bit, which greatly improves the transmission efficiency.

[0005] At present, the simplest architecture of the sense amplifier consists of a bias current circuit IBIAS, a five-tube comparator and a driver stage Driver, such as Figure 2 The bit line selector sends the selected BL / BLN to the two input terminals of the five-tube comparator. When the comparator starts working, it amplifies the differential voltage signal of BL and BLN and outputs it to node Node1. Node1 outputs the data correctly after passing through the driver stage.

[0006] The above-mentioned traditional SA architecture needs to consider the sensitivity, gain and power consumption of the comparator, as well as the design of the driver stage and bias current circuit. This not only requires more devices to implement, but also needs to consider the performance of the circuit. In addition, there is a trade-off between data transmission efficiency and cost. When the bit width of the output data is 1 bit, a Figure 2When the bit width of the output data is N bits, the chip will have N built-in sensitive amplifiers to ensure data transmission efficiency. Figure 2 Sensitive amplifier, but the area of ​​the chip SA will increase N times. Therefore, how to reduce the area cost of the chip while ensuring data transmission efficiency has become a problem that technicians in this field need to solve. Summary of the invention

[0007] In order to solve the above technical problems, the present invention proposes a novel reading circuit to solve the above problems existing in the prior art.

[0008] To achieve the above object, the present invention provides a novel reading circuit, comprising:

[0009] Storage unit, precharge module, read module, bit line, bit negative line;

[0010] The storage unit is used to store data;

[0011] The pre-charging module is used to perform pre-charging according to the CTRL_PC signal;

[0012] The reading module is used to read the storage data of the storage unit; it includes a fifth PMOS tube, a NAND gate, and an inverter;

[0013] The storage unit, the pre-charge module and the read module are connected in pairs through a bit line and a bit negative line.

[0014] Optionally, the storage unit includes a first PMOS tube, a sixth PMOS tube, a first NMOS tube, a third NMOS tube, a word line, a second NMOS tube, and a fourth NMOS tube;

[0015] The gate of the first PMOS tube is respectively connected to the drain of the sixth PMOS tube and the third NMOS tube and connected to the gate of the first NMOS tube; the drain of the first PMOS tube is respectively connected to the gate of the sixth PMOS tube, the gate of the third NMOS tube and the drain of the first NMOS tube;

[0016] The drain of the sixth PMOS tube is also connected to the drain of the third NMOS tube, and the gate of the first NMOS tube is connected to the drain of the fourth NMOS tube; the gate of the sixth PMOS tube is connected to the drain of the second NMOS tube, the gate of the third NMOS tube, and the drain of the first NMOS tube;

[0017] The gate of the first NMOS tube is connected to the drain of the third NMOS tube and the drain of the fourth NMOS tube respectively; the drain of the first NMOS tube is connected to the drain of the second NMOS tube and the gate of the third NMOS tube;

[0018] The gate of the third NMOS tube is connected to the drain of the second NMOS tube, and the drain of the third NMOS tube is connected to the drain of the fourth NMOS tube;

[0019] The sources of the second NMOS tube and the fourth NMOS tube are connected to the bit line and the bit negative line respectively; the gates of the second NMOS tube and the fourth NMOS tube are connected to the word line respectively.

[0020] Optionally, a BL line parasitic capacitor also exists on the bit line, and a BLN line parasitic capacitor also exists on the bit negative line.

[0021] Optionally, the pre-charging module includes a second PMOS tube, a third NMOS tube, and a fourth PMOS tube;

[0022] Among them, the storage unit is connected to the pre-charging module through the CTRL_PC signal control, the source of the second PMOS tube and the fourth PMOS tube is connected to the source of the first NMOS tube and the third NMOS tube; the gate of the second PMOS tube, the fourth PMOS tube and the gate of the third PMOS tube are connected in pairs; the drain of the second PMOS tube and the fourth PMOS tube are connected to the bit line and the bit negative line respectively; the drain of the second PMOS tube is also connected to the drain of the fifth PMOS tube and the input end of the NAND gate; the source of the third PMOS tube is connected to the bit line and the drain of the second PMOS tube, and the drain of the third PMOS tube is connected to the bit negative line and the drain of the fourth PMOS tube.

[0023] Optionally, the source of the fifth PMOS tube is connected to a power supply; the drain of the fifth PMOS tube is respectively connected to a bit line and an input of a NAND gate, the gate of the fifth PMOS tube is connected to the output of the NAND gate and the input of the inverter; the input of the inverter is also connected to the output of the NAND gate.

[0024] Optionally, the NAND gate includes two input terminals, one input terminal is connected to the bit line, and the other input terminal is connected to the read enable signal RD.

[0025] Compared with the prior art, the present invention has the following advantages and technical effects:

[0026] The reading module in the present invention includes a feedback tube MP5, a NAND gate and an inverter, a total of seven MOS devices. When the bit width of the output data is N bits, only N groups of MP5, NAND gates and inverters are needed. The NAND gates and inverters can also drive the next level through fan-out and fan-in, solving the driving problem in traditional circuits. The reading circuit provided by the present invention is just a simple combination of logic gates, and there is no need to consider too much circuit performance. In terms of cost, the reading module of the present invention only requires seven MOS devices. Compared with traditional SA, the number of devices is greatly reduced, and the chip cost is also greatly reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0028] Figure 1 A memory chip circuit architecture diagram of the background technology of the present invention;

[0029] Figure 2 A simple sensitive amplifier architecture diagram of the background technology of the present invention;

[0030] Figure 3 A circuit diagram of a read circuit and a read path according to an embodiment of the present invention;

[0031] Figure 4 A diagram showing the read timing and voltage variation of an embodiment of the present invention;

[0032] Figure 5 It is a schematic diagram of simulation results of simulation curves with and without MP5 tubes in an embodiment of the present invention;

[0033] Description of the drawings: MP1, first PMOS tube; MP2, second PMOS tube; MP3, third PMOS tube; MP4, fourth PMOS tube; MP5, fifth PMOS tube; MP1', sixth PMOS tube; MN1, first NMOS tube, MN2, second NMOS tube; MN1', third NMOS tube; MN2', fourth NMOS tube; INV1, inverter; BL, bit line; BLN, bit negative line; WL, word line; NAND1, NAND gate; C_BL, BL line parasitic capacitance, C_BLN, BLN line parasitic capacitance; CTRL_PC, pre-charge signal; CTRL_FB, feedback signal; RD, read enable signal. DETAILED DESCRIPTION

[0034] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0035] It should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and that, although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0036] Embodiment 1

[0037] like Figure 3-5 As shown, this embodiment provides a novel reading circuit, including:

[0038] Storage unit, precharge module, read module, bit line, bit negative line;

[0039] The storage unit is used to store data;

[0040] The pre-charging module is used to perform pre-charging according to the CTRL_PC signal;

[0041] The reading module is used to read the storage data of the storage unit; it includes a fifth PMOS tube MP5, a NAND gate NAND1, and an inverter INV1;

[0042] The storage unit, the pre-charge module and the read module are connected in pairs through a bit line and a bit negative line.

[0043] Specifically, the storage unit includes a first PMOS tube MP1, a sixth PMOS tube MP1', a first NMOS tube MN1, a third NMOS tube MN1', a word line, a second NMOS tube MN2, and a fourth NMOS tube MN2';

[0044] The gate of the first PMOS transistor MP1 is connected to the drain of the sixth PMOS transistor MP1', the drain of the third NMOS transistor MN1' and the gate of the first NMOS transistor MN1 respectively; the drain of the first PMOS transistor MP1 is connected to the gate of the sixth PMOS transistor MP1', the gate of the third NMOS transistor MN1' and the drain of the first NMOS transistor MN1 respectively;

[0045] The drain of the sixth PMOS transistor MP1' is also connected to the drain of the third NMOS transistor MN1', the gate of the first NMOS transistor MN1 and the drain of the fourth NMOS transistor MN2'; the gate of the sixth PMOS transistor MP1' is connected to the drain of the second NMOS transistor MN2, the gate of the third NMOS transistor MN1' and the drain of the first NMOS transistor MN1;

[0046] The gate of the first NMOS transistor MN1 is connected to the drain of the third NMOS transistor MN1' and the drain of the fourth NMOS transistor MN2' respectively; the drain of the first NMOS transistor MN1 is connected to the drain of the second NMOS transistor MN2 and the gate of the third NMOS transistor MN1';

[0047] The gate of the third NMOS transistor MN1' is connected to the drain of the second NMOS transistor MN2, and the drain of the third NMOS transistor MN1' is connected to the drain of the fourth NMOS transistor MN2';

[0048] The sources of the second NMOS transistor MN2 and the fourth NMOS transistor MN2' are connected to the bit line and the bit negative line respectively; the gates of the second NMOS transistor MN2 and the fourth NMOS transistor MN2' are connected to the word line respectively.

[0049] Specifically, there is a BL line parasitic capacitor on the bit line, and there is a BLN line parasitic capacitor on the bit negative line.

[0050] Specifically, the pre-charging module includes a second PMOS tube MP2, a third NMOS tube MN1', and a fourth PMOS tube MP4;

[0051] The storage unit is connected to the pre-charge module through the CTRL_PC signal control, the source of the second PMOS tube MP2 and the fourth PMOS tube MP4 are connected to the source of the first NMOS tube MN1 and the third NMOS tube MN1'; the gate of the second PMOS tube MP2, the fourth PMOS tube MP4 and the third PMOS tube MP3 are connected in pairs; the drain of the second PMOS tube MP2 and the fourth PMOS tube MP4 are connected to the bit line and the bit negative line respectively; the drain of the second PMOS tube MP2 is also connected to the drain of the fifth PMOS tube MP5 and the input end of the NAND gate NAND1; the source of the third PMOS tube MP3 is connected to the bit line and the drain of the second PMOS tube MP2, and the drain of the third PMOS tube MP3 is connected to the bit negative line and the drain of the fourth PMOS tube MP4.

[0052] Specifically, the source of the fifth PMOS tube MP5 is connected to the power supply; the drain of the fifth PMOS tube MP5 is respectively connected to the bit line and the input end of the NAND gate NAND1, the gate of the fifth PMOS tube MP5 is connected to the output end of the NAND gate NAND1 and the input end of the inverter INV1; the input end of the inverter INV1 is also connected to the output end of the NAND gate NAND1.

[0053] Specifically, the NAND gate NAND1 includes two input terminals, one input terminal is connected to the bit line, and the other input terminal is connected to the read enable signal RD.

[0054] Simulation:

[0055] Will be like Figure 3 The storage unit Bitcell, the precharge module Percharge control and the read circuit Readpath shown are analyzed together. The storage unit Bitcell is used to store data. The figure shows a typical 6T storage unit architecture of SRAM; the precharge module Percharge control is used to precharge BL and BLN, which is also a relatively common architecture; the read circuit Readpath is a read circuit used to read the data of the storage unit bitcell, which is also a new read circuit of the present invention. The three modules are connected through the bit line BL and the bit negative line BLN, as follows: the source end of the second NMOS tube MN2 in the Bitcell is connected to the drain end of the second PMOS tube MP2 in the precharge control module, and is also connected to the input end Node1 of the NAND gate NAND1 in the Readpath, and both are connected to the bit line BL. The source end of the fourth NMOS tube MN2' in the Bitcell and the drain end of the fourth PMOS tube MP4 in the precharge control module are both connected to the bit negative line BLN.

[0056] The SRAM storage unit is two inverters connected end to end. Due to its positive feedback characteristics, when Q is 1, QN must be 0; when Q is 0, QN must be 1. Therefore, ideally, if the written data is correct and the read operation is performed, the correct data can be read; but in fact, when the written data is correct, there are many reasons for reading errors, such as short circuit / open circuit of the storage unit connection caused by the production process, etc., which causes abnormal reading function.

[0057] Assume that the data pre-written to Q and QN is Q=1, QN=0, that is, the potential at point Q is the power supply voltage VDD, and the potential at point QN is the reference ground level 0V. When a read operation is performed, that is, after the RD signal in the Readpath is high, the pre-charge module starts to work. When the pre-charge module starts to work, the pre-charge signal CTRL_PC will be pulled low, and the three PMOS tubes used for pre-charging, namely the second PMOS tube MP2, the third PMOS tube MP3 and the fourth PMOS tube MP4, will be turned on, and the bit line BL / bit negative line BLN will be charged to the power supply voltage VDD. On the contrary, the pre-charge signal CTRL_PC is pulled high to the power supply voltage VDD, the pre-charge tube is turned off, and the pre-charge module stops working. At the same time, the voltage of the word line WL is VDD, and WL is turned on. At this time, because the tubes connected to the WL signal are the second NMOS tube MN2 and the fourth NMOS tube MN2', the gate voltages of these two NMOS tubes are VDD, so the second NMOS tube MN2 is turned on. Since the data written in advance to Q and QN are 1 and 0, the potentials of Q and QN will be the power supply voltage VDD and the ground potential 0. At the moment when the second NMOS tube MN2 and the fourth NMOS tube MN2' are turned on, the potentials of the bit line BL and the bit negative line BLN will be pulled to VDD due to precharging. At this time, MN2 and MN2' are turned on, and the analysis is conducted for the two cases of no MP5 tube and with MP5 tube.

[0058] When the fifth PMOS tube does not exist, the second NMOS tube MN2 is connected to the bit line BL. The bit line BL in the memory chip is connected to many memory cells, so there will be a parasitic capacitor C_BL on BL. When the second NMOS tube MN2 is turned on, it is possible to cause the Q point to charge the parasitic capacitor C_BL, so that the potential of the Q point drops, causing data misreading. Second, the potential of the Q point is the power supply voltage 5V, and the gate voltage of the first PMOS tube is 0V. When the word line WL signal is high, the bit line BL voltage is the Q point voltage, but at this time, for the NAND gate NAND1 in the Readpath, the Node1 and RD voltages are also high, that is, the two NMOS tubes in the NAND gate NAND1 are turned on, and the NAND gate NAND1 includes two NMOS tubes and two PMOS tubes. Therefore, in this process, a path is formed from the power supply VDD to the ground of the NAND gate NAND1. If there is a path, there will be current, so there will be a voltage difference from the Q point to the node Node1. If the voltage difference is V0, the Node1 voltage is VDD-V0. The above timing description is as follows Figure 4As shown. The voltage is transmitted to the Node1 node of the read circuit Readpath. The voltage passes through the NAND gate and the inverter, and the output terminal OUT outputs the power supply voltage VDD, that is, the output data 1. However, this solution has a risk. From the Readpath input terminal Node1 to the Readpath output terminal OUT is a digital logic gate. For digital circuits, the voltage of each node in the circuit is either 0 or 1. At this time, the Node1 voltage (the same as the bit line BL voltage) is VDD-V0, which is neither the power supply voltage VDD nor the ground voltage 0V. Although the voltage VDD-V0 passes through two stages of inversion (NAND gate NAND1 and inverter INV1), the data read from the output OUT terminal is likely to be consistent with the written data and are both 1, but this situation is risky, and the situation where the voltage is an intermediate value in digital circuits must be avoided.

[0059] In this embodiment, a fifth PMOS tube MP5 is added to the Readpath circuit. Since the fifth PMOS tube MP5 is a positive feedback, the Node1 voltage (BL voltage) is VDD-V0, and the Node2 node voltage is 0 after NAND1. MP5 is a PMOS tube, so the Node1 voltage (BL voltage) will be pulled to the power supply voltage VDD. In summary, the existence of the MP5 tube can effectively solve the intermediate voltage problem at the above node. In addition, due to the positive feedback generated by the introduction of MP5, the flipping process of the path from Node1 to Node2 will be accelerated. Figure 5 These are the simulation curves with and without the MP5 tube. From top to bottom, the curves are the power supply voltage VDD, the pre-charge signal CTRL_PC word line signal WL, the bit line signal with the fifth PMOS tube MP5 added, and the bit line signal without the fifth PMOS tube. It can be seen that when WL is turned on, the BL voltage without the MP5 tube is 2.77V, which is not the power supply voltage 3V, while the BL voltage with the MP5 tube is 3V, which is the power supply voltage. Therefore, with the existence of the MP5 tube, when the data pre-written to the Q point is 1, the Readpath is recognized as a logic high level. The above analysis completes the process of reading 1, and the following analysis is about the process of reading 0. When the data written to Q and QN are 0 and 1, the WL tube is turned on after the pre-charge is completed, and the data 0 pre-written to the Q point is transmitted to the input of the NAND gate. Therefore, the output end OUT will be recognized as 0, that is, the pre-written data 0 is successfully read.

[0060] The above are only preferred specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A novel reading circuit, characterized in that: include: Storage unit, precharge module, read module, bit line, bit negative line; The storage unit is used to store data; The pre-charging module is used for pre-charging according to the CTRL_PC signal; The reading module is used to read the storage data of the storage unit; It includes a fifth PMOS tube, a NAND gate, and an inverter; The storage unit, the pre-charge module and the read module are connected in pairs through a bit line and a bit negative line.

2. The novel readout circuit according to claim 1, characterized in that: The storage unit includes a first PMOS tube, a sixth PMOS tube, a first NMOS tube, a third NMOS tube, a word line, a second NMOS tube, and a fourth NMOS tube; The gate of the first PMOS tube is respectively connected to the drain of the sixth PMOS tube and the third NMOS tube and connected to the gate of the first NMOS tube; the drain of the first PMOS tube is respectively connected to the gate of the sixth PMOS tube, the gate of the third NMOS tube and the drain of the first NMOS tube; The drain of the sixth PMOS tube is also connected to the drain of the third NMOS tube, and the gate of the first NMOS tube is connected to the drain of the fourth NMOS tube; the gate of the sixth PMOS tube is connected to the drain of the second NMOS tube, the gate of the third NMOS tube, and the drain of the first NMOS tube; The gate of the first NMOS tube is connected to the drain of the third NMOS tube and the drain of the fourth NMOS tube respectively; the drain of the first NMOS tube is connected to the drain of the second NMOS tube and the gate of the third NMOS tube; The gate of the third NMOS tube is connected to the drain of the second NMOS tube, and the drain of the third NMOS tube is connected to the drain of the fourth NMOS tube; The sources of the second NMOS tube and the fourth NMOS tube are connected to the bit line and the bit negative line respectively; the gates of the second NMOS tube and the fourth NMOS tube are connected to the word line respectively.

3. The novel readout circuit according to claim 1, characterized in that: There is also a BL line parasitic capacitance on the bit line, and there is also a BLN line parasitic capacitance on the bit negative line.

4. The novel reading circuit according to claim 2, characterized in that: The pre-charging module includes a second PMOS tube, a third NMOS tube, and a fourth PMOS tube; Among them, the storage unit is connected to the pre-charging module through the CTRL_PC signal control, the source of the second PMOS tube and the fourth PMOS tube is connected to the source of the first NMOS tube and the third NMOS tube; the gate of the second PMOS tube, the fourth PMOS tube and the gate of the third PMOS tube are connected in pairs; the drain of the second PMOS tube and the fourth PMOS tube are connected to the bit line and the bit negative line respectively; the drain of the second PMOS tube is also connected to the drain of the fifth PMOS tube and the input end of the NAND gate; the source of the third PMOS tube is connected to the bit line and the drain of the second PMOS tube, and the drain of the third PMOS tube is connected to the bit negative line and the drain of the fourth PMOS tube.

5. The novel readout circuit according to claim 4, characterized in that: The source of the fifth PMOS tube is connected to a power supply; the drain of the fifth PMOS tube is respectively connected to a bit line and an input end of a NAND gate; the gate of the fifth PMOS tube is connected to an output end of the NAND gate and an input end of the inverter; and the input end of the inverter is also connected to an output end of the NAND gate.

6. The novel readout circuit according to claim 1, characterized in that: The NAND gate includes two input terminals, one input terminal is connected to the bit line, and the other input terminal is connected to the read enable signal RD.

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