Deep trench manufacturing method, semiconductor structure, chip and circuit

Abstract

The present invention provides a method for fabricating a deep trench, a semiconductor structure, a chip and a circuit, relating to the field of semiconductor technology. The fabrication method includes: forming a hard mask layer with an etching window on the upper surface of a substrate; performing at least one substrate etching on the substrate by using the etching window to form a target deep trench; the step of substrate etching includes: performing multiple ion implantations on the substrate through the etching window to form a modified region; the designed size of the modified region is the same as the designed size of a sub-target trench; the ion implantation angle gradually increases; etching the modified region to form a sub-target trench; if the depth of the sub-target trench is less than the depth of the target deep trench, performing the next substrate etching; the substrate etching intensity gradually increases; if the depth of the sub-target trench is equal to the depth of the target deep trench, using this sub-target trench as the target deep trench. Through the present invention, the wall inclination of the deep trench can be reduced, the etching uniformity of the deep trench can be improved, the morphology of the deep trench can be improved, and the device performance and reliability can be enhanced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more particularly, to a method for fabricating a deep trench, a semiconductor structure, a chip, and a circuit. Background Art

[0002] Deep trenches (the ratio of whose height to width is usually greater than 4) are widely used in the field of semiconductor integrated circuits. For example, they are used in the manufacturing processes of high voltage (HV) devices, CMOS contact image sensor (CIS) devices, and Bi-CMOS devices (i.e., complementary metal oxide semiconductor (CMOS) devices and bipolar junction transistor (BJT) devices integrated on the same chip).

[0003] In the deep trench etching process, due to the long etching time and deep etching depth of the deep trench etching process, the masking layer will be damaged and its morphology will change due to the action of etching ions during the etching process, resulting in the inclination of the sidewalls of the etched deep trench. The difference between the bottom width and the top width of the deep trench gradually increases with time, affecting the product performance.

[0004] Therefore, how to improve the etching uniformity of deep trenches is a technical problem that urgently needs to be solved at present. Summary of the Invention

[0005] Aiming at the technical problems of the inclination of the sidewalls of the deep trenches formed in the prior art and poor etching uniformity, the present invention provides a method for fabricating a deep trench, a semiconductor structure, a chip, and a circuit. By using the method for fabricating a deep trench, the inclination of the sidewalls of the deep trench can be reduced, the gap between the bottom width and the top width of the deep trench can be decreased, the etching uniformity of the deep trench can be improved, the morphology of the deep trench can be improved, and the device performance and reliability can be enhanced.

[0006] To achieve the above object, a first aspect of the present invention provides a method for fabricating a deep trench, which includes: providing a substrate and forming a hard mask layer with an etching window on the upper surface of the substrate; performing at least one substrate etching on the substrate by using the etching window of the hard mask layer to form a target deep trench; wherein, each step of substrate etching includes: performing multiple ion implantations on the substrate through the etching window of the hard mask layer to form a modified region; wherein, the size of the modified region is the same as the designed size of the sub-target trench to be formed by this substrate etching; the angle of the next ion implantation is greater than the angle of the previous ion implantation; using an etching process to remove the modified region to form the sub-target trench of this substrate etching; if it is determined that the depth of the sub-target trench formed by this substrate etching is less than the depth of the target deep trench, perform the next substrate etching; wherein, the etching intensity used to remove the modified region by the etching process during the next substrate etching is greater than the etching intensity used to remove the modified region by the etching process during the previous substrate etching; if it is determined that the depth of the sub-target trench formed by this substrate etching is equal to the depth of the target deep trench, stop this substrate etching; taking the trench formed by the substrate etching as the target deep trench.

[0007] Further, forming a hard mask layer with an etching window on the upper surface of the substrate includes: sequentially forming a substrate layer, an initial hard mask layer, and a patterning layer on the upper surface of the substrate; forming an etching window in the patterning layer; using the patterning layer as a mask to etch the initial hard mask layer through the etching window of the patterning layer to form a hard mask layer with an etching window.

[0008] Further, before performing at least one substrate etching on the substrate by using the etching window of the hard mask layer, the method further includes: etching the substrate through the etching window of the hard mask layer to obtain an initial trench; wherein, the depth of the initial trench is less than the depth of the target deep trench; performing at least one substrate etching on the substrate at the bottom of the initial trench through the etching window of the hard mask layer to form the target deep trench.

[0009] Further, the depth of the initial trench is between 0.3um - 5um.

[0010] Further, performing multiple ion implantations on the substrate through the etching window of the hard mask layer to form a modified region includes: performing at least three ion implantations on the substrate through the etching window of the hard mask layer to form a modified region; wherein, the angle of the first ion implantation is 0°, the angle of the second ion implantation is 5°, and the angle of the third ion implantation is 10°.

[0011] Further, the energy of the ion implantation is between 1Kev - 5000Kev, and the ion implantation dose is between 10 12 cm -2 -10 15 cm-2 。

[0012] Further, the implanted element includes one or more of germanium, silicon, and arsenic elements.

[0013] Further, the modified region is removed by a dry etching process; the etching gas used in the dry etching process includes CHF3, HBr, and Ar; wherein, the flow rate of CHF3 ranges from 10 sccm to 1000 sccm, the flow rate of HBr ranges from 10 sccm to 1000 sccm, and the flow rate of Ar ranges from 10 sccm to 1000 sccm.

[0014] Further, the modified region is removed by a wet etching process; the etching solution used in the wet etching process includes tetramethylammonium hydroxide solution; wherein, the volume percentage of the tetramethylammonium hydroxide solution ranges from 10% to 80%; the wet etching temperature ranges from 20°C to 80°C.

[0015] Further, the aspect ratio of the target deep trench ranges from 10:1 to 30:1.

[0016] The second aspect of the present invention provides a semiconductor structure, which includes a target deep trench formed by the deep trench manufacturing method described above.

[0017] The third aspect of the present invention provides a chip, which includes the semiconductor structure described above.

[0018] The fourth aspect of the present invention provides a circuit, which includes the semiconductor structure described above.

[0019] Through the technical solution provided by the present invention, the present invention has at least the following technical effects:

[0020] In the deep trench manufacturing method of the present invention, a hard mask layer with an etching window is first formed on the upper surface of the substrate, and then the substrate is etched at least once through the etching window of the hard mask layer to form a target deep trench. Each step of substrate etching includes: implanting ions into the substrate through the etching window of the hard mask layer to form a modified region, and the designed size of the modified region is equal to the designed size of the sub-target trench to be formed in this substrate etching. The modified region is removed by an etching process to form the sub-target trench of this substrate etching. If the depth of the sub-target trench formed in this substrate etching is less than the depth of the target deep trench, the next substrate etching is cycled. If the depth of the sub-target trench formed in this substrate etching is equal to the depth of the target deep trench, the etching is stopped, and the trench formed by substrate etching is used as the target deep trench. Through the present invention, the trench wall inclination of the deep trench can be reduced, the gap between the bottom width and the top width of the deep trench can be reduced, the etching uniformity of the deep trench can be improved, the morphology of the deep trench can be improved, and the device performance and reliability can be enhanced.

[0021] Other features and advantages of the present invention will be described in detail in the following specific implementation section. Description of the Drawings

[0022] The drawings are used to provide a further understanding of the embodiments of the present invention, and constitute a part of the specification. Together with the following specific implementation, they are used to explain the embodiments of the present invention, but do not constitute a limitation to the embodiments of the present invention. In the drawings:

[0023] Figure 1 It is a schematic structural diagram of a deep trench formed in the prior art;

[0024] Figure 2 It is a schematic structural diagram of a patterned layer and an initial hard mask layer formed in the deep trench manufacturing method provided by the embodiment of the present invention;

[0025] Figure 3 It is a schematic structural diagram of a hard mask layer and an etching window formed in the deep trench manufacturing method provided by the embodiment of the present invention;

[0026] Figure 4 It is a schematic structural diagram of an initial trench formed in the deep trench manufacturing method provided by the embodiment of the present invention;

[0027] Figure 5 It is a schematic structural diagram of a first modified region formed in the deep trench manufacturing method provided by the embodiment of the present invention;

[0028] Figure 6 It is a schematic structural diagram of a first sub-target trench formed in the deep trench manufacturing method provided by the embodiment of the present invention;

[0029] Figure 7 It is a schematic structural diagram of a second modified region formed in the deep trench manufacturing method provided by the embodiment of the present invention;

[0030] Figure 8 It is a schematic structural diagram of a second sub-target trench formed in the deep trench manufacturing method provided by the embodiment of the present invention;

[0031] Figure 9 It is a flowchart of the deep trench manufacturing method provided by the embodiment of the present invention.

[0032] Description of the Reference Numerals

[0033] 100 - Substrate; 101 - Oxide layer; 102 - Deep trench; 103 - Patterned layer; 200 - Substrate; 201 - Substrate cushion layer; 202 - Initial hard mask layer; 203 - Patterned layer; 204 - Hard mask layer; 205 - Etching window; 206 - Initial trench; 207 - First modified region; 208 - First sub-target trench; 209 - Second modified region; 210 - Second sub-target trench. Detailed Embodiments

[0034] The following will describe in detail the specific embodiments of the embodiments of the present invention with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining and illustrating the embodiments of the present invention, and are not used to limit the embodiments of the present invention.

[0035] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other.

[0036] In the present invention, unless otherwise stated, the orientation terms such as "upper, lower, top, bottom" are usually in terms of the direction shown in the accompanying drawings or in terms of the vertical, perpendicular or gravitational direction for describing the relative positional relationship of each component.

[0037] As in the background art, the performance of the existing semiconductor structure is poor. The following will be specifically described with reference to the accompanying drawings.

[0038] Please refer to Figure 1 , a substrate 100 is provided; an oxide layer 101 is formed on the surface of the substrate 100; a patterned layer 103 is formed on the surface of the oxide layer 101; using the patterned layer 103 as a mask, the oxide layer 101 and a part of the thickness of the substrate 100 are etched to form a deep trench 102 in the substrate 100.

[0039] However, in the process of forming the above semiconductor structure, the deep trench 102 is usually etched by plasma dry etching. Due to the directionality of plasma etching, the etching ability of the trench sidewall is weak, and the trench sidewall is inclined. Since the depth of the deep trench 102 is relatively large, as the etching depth and etching duration increase, the gap between the bottom dimension d2 (Bottom CD) and the top dimension d1 (Top CD) of the deep trench 102 becomes larger and larger, thereby reducing the quality of the finally formed deep trench.

[0040] On this basis, the present invention provides a method for manufacturing a deep trench. A substrate is provided, and a hard mask layer with an etching window is formed on the surface of the substrate. Then, the substrate is etched at least once using the etching window to form a target deep trench. Each time the substrate is etched, ion implantation is performed on the substrate through the etching window of the hard mask layer according to the designed dimension of the sub-target trench to be formed in this substrate etching, so as to form a modified region. By ion implantation, the substrate structure is damaged, so that when the modified region is removed by an etching process, the modified region is more easily etched, and only the modified region is etched without etching the substrate. In this way, the formed sub-target trench matches its designed dimension, the trench wall does not tilt, the gap between the bottom width and the top width of the deep trench can be reduced, the etching uniformity of the deep trench can be improved, the morphology of the deep trench can be improved, and the device performance and reliability can be enhanced.

[0041] The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0042] Please refer to Figure 9 , a method for fabricating a deep trench according to a first aspect of an embodiment of the present invention includes: S101: providing a substrate 200 and forming a hard mask layer 204 having an etching window 205 on the upper surface of the substrate 200; S102: performing at least one substrate etching on the substrate 200 by using the etching window 205 of the hard mask layer 204 to form a target deep trench; wherein, each step of substrate etching includes: performing multiple ion implantations on the substrate 200 through the etching window 205 of the hard mask layer 204 to form a modified region; wherein, the size of the modified region is the same as the designed size of the sub-target trench to be formed by this substrate etching; the angle of the next ion implantation is greater than the angle of the previous ion implantation; using an etching process to remove the modified region to form the sub-target trench of this substrate etching; if it is determined that the depth of the sub-target trench formed by this substrate etching is less than the depth of the target deep trench, performing the next substrate etching; wherein, the etching intensity used to remove the modified region by the etching process during the next substrate etching is greater than the etching intensity used to remove the modified region by the etching process during the previous substrate etching; if it is determined that the depth of the sub-target trench formed by this substrate etching is equal to the depth of the target deep trench, stopping this substrate etching; taking the trench formed by the substrate etching as the target deep trench.

[0043] First, step S101 is executed: providing a substrate 200 and forming a hard mask layer 204 having an etching window 205 on the upper surface of the substrate 200.

[0044] Specifically, in the embodiment of the present invention, the provided Figure 2 substrate 200 as shown, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate 200 may also be germanium, silicon germanide, silicon carbide, gallium arsenide or indium gallium; in other embodiments, the substrate 200 may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. Then, a hard mask layer 204 having an etching window 205 is formed on the upper surface of the substrate 200.

[0045] Further, forming the hard mask layer 204 having the etching window 205 on the upper surface of the substrate 200 includes: sequentially forming a substrate layer 201, an initial hard mask layer 202 and a patterned layer 203 on the upper surface of the substrate 200; forming an etching window in the patterned layer 203; using the patterned layer 203 as a mask to etch the initial hard mask layer 202 through the etching window of the patterned layer 203 to form the hard mask layer 204 having the etching window 205.

[0046] Specifically, in the embodiment of the present invention, a liner layer 201 is formed on the upper surface of the substrate 200. In this embodiment, the liner layer 201 is a single-layer structure. In other embodiments, the liner layer 201 is also a stacked structure. In this embodiment, the material of the liner layer 201 is silicon oxide. In other embodiments, the material of the liner layer 201 can also be a combination of silicon oxynitride and silicon oxide.

[0047] In this embodiment, the forming method of the liner layer 201 is a thermal oxidation growth process. The thermal oxidation process is carried out in a thermal oxidation furnace tube, and the silicon exposed on the surface will be oxidized into silicon oxide. Preferably, the thermal oxidation uses a dry oxygen process, and the oxidation temperature is greater than 1050 °C. Among them, the thickness of the grown silicon oxide is controlled by controlling the time of the thermal oxidation process. In other embodiments, the forming method of the liner layer 201 can also be a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, etc.

[0048] Next, an initial hard mask layer 202 is formed on the upper surface of the liner layer 201. In this embodiment, the material of the initial hard mask layer 202 is silicon nitride. In other embodiments, the material of the initial hard mask layer 202 can also be one or a combination of silicon carbide, silicon oxynitride, silicon oxide, and silicon nitride. In this embodiment, the initial hard mask layer 202 is a single-layer structure. In other embodiments, the initial hard mask layer 202 can also be a multi-layer structure, such as a combination of multi-layer silicon oxide and silicon nitride. In this embodiment, the initial hard mask layer 202 is formed by a chemical vapor deposition process. In other embodiments, the initial hard mask layer 202 can also be formed by a physical vapor deposition process or an atomic layer deposition process, etc. When the initial hard mask layer 202 is formed by an atomic layer deposition process, the precursor gas used in the atomic layer deposition process includes a mixed gas of SiH2Cl2 and NH3, the flow rate of the mixed gas is between 1500 sccm - 4000 sccm, the pressure is between 1 mtorr - 10 mtorr, the deposition temperature is between 200 °C - 600 °C, and the number of deposition times is between 30 times - 100 times.

[0049] Next, a patterned layer 203 is formed on the surface of the initial hard mask layer 202. The material of the patterned layer 203 is photoresist. The patterned layer 203 is exposed and developed to form an etching window. Using the patterned layer 203 as a mask, the initial hard mask layer 202 is etched through the etching window of the patterned layer 203, and a dry etching process is used to form as Figure 3The hard mask layer 204 with an etching window 205 as shown. The etching gas used in dry etching includes: CF4 gas and CHF3 gas. The flow rate of the CF4 gas ranges from 8 sccm to 500 sccm, the flow rate of the CHF3 gas ranges from 30 sccm to 200 sccm, the chamber pressure ranges from 10 mtorr to 2000 mtorr, the source radio frequency power ranges from 100 W to 1300 W, the bias voltage ranges from 80 V to 500 V, and the time ranges from 4 seconds to 500 seconds. Finally, the etch stop layer 201 is etched to expose the substrate 200.

[0050] Then, step S102 is executed: At least one substrate etching is performed on the substrate 200 by using the etching window 205 of the hard mask layer 204 to form a target deep trench; wherein, each substrate etching step includes: Multiple ion implantations are performed on the substrate 200 through the etching window 205 of the hard mask layer 204 to form a modified region; wherein, the size of the modified region is the same as the designed size of the sub-target trench to be formed in this substrate etching; the angle of the next ion implantation is greater than the angle of the previous ion implantation; The modified region is removed by an etching process to form the sub-target trench of this substrate etching; If it is determined that the depth of the sub-target trench formed in this substrate etching is less than the depth of the target deep trench, the next substrate etching is performed; wherein, the etching intensity used to remove the modified region by the etching process during the next substrate etching is greater than the etching intensity used to remove the modified region by the etching process during the previous substrate etching; If it is determined that the depth of the sub-target trench formed in this substrate etching is equal to the depth of the target deep trench, this substrate etching is stopped; The trench formed by the substrate etching is used as the target deep trench.

[0051] Further, before performing at least one substrate etching on the substrate 200 by using the etching window 205 of the hard mask layer 204, the method further includes: The substrate 200 is etched through the etching window 205 of the hard mask layer 204 to obtain an initial trench 206; wherein, the depth of the initial trench 206 is less than the depth of the target deep trench; At least one substrate etching is performed on the substrate 200 at the bottom of the initial trench 206 through the etching window 205 of the hard mask layer 204 to form the target deep trench.

[0052] Further, the depth of the initial trench 206 ranges from 0.3 um to 5 um.

[0053] Further, the multiple ion implantations are performed on the substrate through the etching window of the hard mask layer to form a modified region, including: At least three ion implantations are performed on the substrate through the etching window of the hard mask layer to form a modified region; wherein, the angle of the first ion implantation is 0°, the angle of the second ion implantation is 5°, and the angle of the third ion implantation is 10°.

[0054] Further, the energy of ion implantation ranges from 1 Kev to 5000 Kev, and the ion implantation dose ranges from 10 12 cm -2 -10 15 cm -2 。

[0055] Further, the elements for ion implantation include one or more of germanium element, silicon element and arsenic element.

[0056] Further, the modified region is removed by a dry etching process; the etching gas used in the dry etching process includes CHF3, HBr and Ar; wherein, the flow rate of CHF3 ranges from 10 sccm to 1000 sccm, the flow rate of HBr ranges from 10 sccm to 1000 sccm, and the flow rate of Ar ranges from 10 sccm to 1000 sccm.

[0057] Further, the modified region is removed by a wet etching process; the etching solution used in the wet etching process includes a tetramethylammonium hydroxide solution; wherein, the volume percentage of the tetramethylammonium hydroxide solution ranges from 10% to 80%; the wet etching temperature ranges from 20°C to 80°C.

[0058] Further, the aspect ratio of the target deep trench ranges from 10:1 to 30:1.

[0059] Specifically, in the embodiment of the present invention, the substrate 200 is subjected to multiple ion implantations through the etching window 205 of the hard mask layer 204 to form a target deep trench. If the depth of the target deep trench is small, one substrate etching is performed; if the depth of the target deep trench is large, multiple substrate etchings are performed. The process of substrate etching is as follows: According to the depth and width of the sub-target trench to be formed in this substrate etching, the substrate is subjected to multiple ion implantations to obtain a corresponding modified region, and the size of this modified region is the same as the designed size of the sub-target trench to be formed in this substrate etching. Then, the modified region is removed by etching to obtain a sub-target trench. If the depth of the sub-target trench reaches the depth of the target deep trench, the substrate etching is stopped, and the trench formed by substrate etching is used as the target deep trench. If the depth of the sub-target trench does not reach the depth of the target deep trench, continue with the substrate etching until the depth of the formed sub-target trench reaches the depth of the target deep trench.

[0060] In this embodiment, the substrate 200 is subjected to at least three ion implantations. The angle of the first ion implantation is 0°, the angle of the second ion implantation is 5°, and the angle of the third ion implantation is 10°. Increasing the angle of each ion implantation can ensure the uniformity of ion implantation in the modified region and contribute to the perpendicularity of the sidewalls of the finally formed deep trench.

[0061] Since the modified region is ion-implanted, the substrate structure in the modified region is damaged. Under the same etching conditions, the etching rate of the modified region is greater than that of the nearby substrate 200. When etching the modified region, the nearby substrate 200 will not be etched away. The size of each formed sub-target trench is the same as the designed size, and the morphology will not change. Therefore, the size of the finally formed target deep trench is also the same as the designed size, which can reduce the wall inclination of the deep trench, reduce the gap between the bottom width and the top width of the deep trench, improve the etching uniformity of the deep trench, improve the morphology of the deep trench, and enhance the device performance and reliability.

[0062] Further, if the depth of the etched trench is relatively shallow, the sidewalls of the shallow trench will not be inclined. In this embodiment, before forming the modified region, a shallow trench etching process can be performed first. The substrate 200 is etched through the etching window 205 of the hard mask layer 204 to obtain an Figure 4 initial trench 206 as shown. The depth of the initial trench 206 ranges from 0.3 um to 5 um, and then the substrate etching is performed on the basis of the initial trench 206. This can replace part of the substrate etching with shallow trench etching, reduce the complex process flow of first ion implantation and then etching during the substrate etching process, improve the formation efficiency of the deep trench, and reduce the cost.

[0063] The initial trench 206 can be formed by a dry etching process. The etching gas used in this dry etching process includes CHF3, HBr, and Ar; among them, the flow rate of CHF3 ranges from 10 sccm to 1000 sccm, the flow rate of HBr ranges from 10 sccm to 1000 sccm, and the flow rate of Ar ranges from 10 sccm to 1000 sccm.

[0064] The initial trench 206 can be formed by a wet etching process. The etching solution used in this wet etching process includes a tetramethylammonium hydroxide solution; among them, the volume percentage of the tetramethylammonium hydroxide solution ranges from 10% to 80%; the wet etching temperature ranges from 20°C to 80°C.

[0065] In a possible implementation manner, if the depth of the target deep trench is small, one substrate etching can be performed on the basis of the initial trench 206. According to the designed size of the first sub-target trench 208 to be formed by this substrate etching (i.e., the designed size of the target deep trench), the substrate 200 is ion-implanted to obtain an Figure 5 first modified region 207 as shown. The depth of the first modified region 207 is equal to the depth of the sub-target trench to be formed by this substrate etching, and the width of the first modified region 207 is equal to the width of the sub-target trench to be formed by this substrate etching. The elements for ion implantation include one or more of germanium element, silicon element, and arsenic element. The ion implantation energy ranges from 1 Kev to 5000 Kev, and the ion implantation dose ranges from 10 12 cm-2 -10 15 cm -2 。

[0066] Next, the first modified region 207 is removed by etching to obtain the first sub-target trench 208 as shown in Figure 6 Figure 10, and the first sub-target trench 208 is used as the target deep trench.

[0067] In this embodiment, the modified region is removed by a dry etching process. The etching gas used in the dry etching process includes CHF3, HBr, and Ar. The flow rate of CHF3 ranges from 10 sccm to 1000 sccm, the flow rate of HBr ranges from 10 sccm to 1000 sccm, and the flow rate of Ar ranges from 10 sccm to 1000 sccm. Further, the modified region is removed by a wet etching process. The etching solution used in the wet etching process includes a tetramethylammonium hydroxide solution, and the volume percentage of the tetramethylammonium hydroxide solution ranges from 10% to 80%; the wet etching temperature ranges from 20°C to 80°C.

[0068] In another possible implementation, if the depth of the target deep trench is large, multiple substrate etchings can be performed on the basis of the first sub-target trench 208. According to the depth and width of the second sub-target trench 210 to be formed by the second substrate etching, ion implantation is performed on the substrate 200 at the bottom of the first sub-target trench 208 to obtain the second modified region 209 as shown in Figure 7 Figure 18. The depth of the second modified region 209 is equal to the depth of the second sub-target trench 210 to be formed by the second substrate etching, and the width of the second modified region 209 is equal to the width of the second sub-target trench 210 to be formed by the second substrate etching. Next, the second modified region 209 is removed by etching to obtain the second sub-target trench 210 as shown in Figure 8 Figure 20. If the depth of the second sub-target trench 210 reaches the depth of the target deep trench, the substrate etching is stopped, and the second sub-target trench 210 is used as the target deep trench. If the depth of the second sub-target trench 210 does not reach the depth of the target deep trench, the next substrate etching is continued until the depth of the formed sub-target trench reaches the depth of the target deep trench. The etching intensity used to remove the modified region by the etching process during the next substrate etching is greater than the etching intensity used to remove the modified region by the etching process during the previous substrate etching, which can enhance the bottom etching ability and improve the problem of the inclined trench sidewall.

[0069] The aspect ratio of the target deep trench formed by the method of the present invention ranges from 10:1 to 30:1, the inclination angle of the side wall ranges from 85° to 90°, the difference between the top size (D) and the bottom size (d) of the target deep trench ranges from 0.1 μm to 1 μm, the top size of the target deep trench ranges from 0.3 μm to 5 μm, and the bottom size of the target deep trench ranges from 0.2 μm to 5 μm. It can be seen that the present invention can reduce the inclination of the trench wall of the deep trench, reduce the gap between the bottom width and the top width of the deep trench, improve the etching uniformity of the deep trench, improve the morphology of the deep trench, and enhance the device performance and reliability.

[0070] The second aspect of the present invention provides a semiconductor structure, which includes a target deep trench formed by the deep trench manufacturing method described above.

[0071] The third aspect of the present invention provides a chip, which includes the semiconductor structure described above.

[0072] The fourth aspect of the present invention provides a circuit, which includes the semiconductor structure described above.

[0073] The preferred embodiments of the present invention have been described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solutions of the present invention, and these simple modifications all fall within the protection scope of the present invention.

[0074] In addition, it should be noted that, in the case of no contradiction, the various specific technical features described in the above specific embodiments can be combined in any suitable way. To avoid unnecessary repetition, the present invention will not separately describe various possible combination methods.

[0075] In addition, any combination can be made between various different embodiments of the present invention as long as it does not violate the idea of the present invention, and it should also be regarded as the content disclosed by the present invention.

Claims

1. A deep trench manufacturing method, characterized in that: The deep trench manufacturing method comprises: Providing a substrate, and forming a hard mask layer having an etching window on the upper surface of the substrate; The substrate is etched at least once using the etching window of the hard mask layer to form a target deep trench; wherein each substrate etching step includes: Performing multiple ion implantation on the substrate through the etching window of the hard mask layer to form a modified area; wherein the size of the modified area is the same as the design size of the sub-target groove to be formed by etching the substrate; and the angle of the next ion implantation is greater than the angle of the previous ion implantation; Using an etching process to remove the modified area to form a sub-target groove of the substrate etching; wherein, under the same etching conditions, the etching rate of the modified area is greater than the etching rate of the substrate; If it is determined that the depth of the sub-target groove formed by the substrate etching is less than the depth of the target deep groove, the next substrate etching is performed; wherein the etching intensity used to remove the modified area by the etching process during the next substrate etching is greater than the etching intensity used to remove the modified area by the etching process during the previous substrate etching; If it is determined that the depth of the sub-target groove formed by the secondary substrate etching is equal to the depth of the target deep groove, stopping the secondary substrate etching; A trench formed by etching a substrate is used as the target deep trench.

2. The deep trench manufacturing method according to claim 1, characterized in that: The step of forming a hard mask layer having an etching window on the upper surface of the substrate comprises: forming a liner layer, an initial hard mask layer and a patterning layer in sequence on the upper surface of the substrate; forming an etching window in the patterned layer; The patterned layer is used as a mask, and the initial hard mask layer is etched through the etching window of the patterned layer to form a hard mask layer with an etching window.

3. The deep trench manufacturing method according to claim 1, characterized in that: Before performing at least one substrate etching on the substrate using the etching window of the hard mask layer, the method further includes: Etching the substrate through the etching window of the hard mask layer to obtain an initial groove; wherein the depth of the initial groove is less than the depth of the target deep groove; The substrate at the bottom of the initial trench is etched at least once through the etching window of the hard mask layer to form the target deep trench.

4. The deep trench manufacturing method according to claim 3, characterized in that: The depth of the initial groove is between 0.3 μm and 5 μm.

5. The deep trench manufacturing method according to claim 1, characterized in that: The method of performing multiple ion implantation on the substrate through the etching window of the hard mask layer to form a modified area includes: Ion implantation is performed at least three times on the substrate through the etching window of the hard mask layer to form a modified area; wherein the angle of the first ion implantation is 0°, the angle of the second ion implantation is 5°, and the angle of the third ion implantation is 10°.

6. The deep trench manufacturing method according to claim 1, characterized in that: The energy of ion implantation is between 1keV and 5000keV, and the ion implantation dose is between 10 12 cm -2 -10 15 cm -2 .

7. The deep trench manufacturing method according to claim 1, characterized in that: The elements implanted by ions include one or more of germanium, silicon and arsenic.

8. The deep trench manufacturing method according to claim 1, characterized in that: The modified area is removed by dry etching process; the etching gas used in the dry etching process includes CHF3, HBr and Ar; wherein, the flow rate of CHF3 is between 10sccm-1000sccm, the flow rate of HBr is between 10sccm-1000sccm, and the flow rate of Ar is between 10sccm-1000sccm.

9. The deep trench manufacturing method according to claim 1, characterized in that: The modified area is removed by wet etching process; the etching solution used in the wet etching process includes tetramethylammonium hydroxide solution; wherein the volume percentage of the tetramethylammonium hydroxide solution is between 10% and 80%; and the wet etching temperature is between 20° C. and 80° C.

10. The deep trench manufacturing method according to claim 1, characterized in that: The target deep trench has a depth-to-width ratio between 10:1 and 30:

1.

11. A semiconductor structure, characterized in that: The semiconductor structure includes a target deep trench formed by the deep trench manufacturing method according to any one of claims 1 to 10.

12. A chip, characterized in that: The chip comprises the semiconductor structure according to claim 11.

13. A circuit, characterized in that: The circuit comprises the semiconductor structure of claim 11.

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