A slotting structure, a slotting method and a dicing process for wafer dicing

Abstract

The application discloses a slotting structure, a slotting method and a dicing process for wafer dicing. The slotting structure is formed on a wafer with opposite front and back surfaces, and comprises, along a dicing boundary: a groove A1 and a groove A2 formed on one surface of the wafer, and a convex block formed between the groove A1 and the groove A2; and a groove B formed on the other surface of the wafer and corresponding to the convex block. The width of the convex block is different from the width of the groove B. The application forms non-communicating grooves on the wafer by etching, instead of a dicing channel formed by original hidden cutting, so that the wafer dicing can save cost and improve the expansion rate. Meanwhile, part of the wafer is left in one groove to form a convex block, the stability of adjacent chip connection is increased, irregular fracture of the wafer before expansion is prevented, and the yield is improved.

Description

Technical Field

[0001] This invention relates to the field of wafer dicing technology, and more particularly to a grooving structure, grooving method and dicing process for wafer dicing. Background Technology

[0002] Wafer dicing is the final step in the integrated circuit manufacturing process. It is the process of cutting a finished wafer into individual chips. Whether it is traditional chip packaging or advanced wafer-level packaging technology, wafer dicing is indispensable.

[0003] For traditional chip packaging, wafer dicing is the initial step in the packaging process. However, for wafer-level packaging, dicing is often the final step. Both steps directly affect the final reliability of the packaged product. For example, in MEMS wafer processing, wafer dicing is usually divided into two steps: dicing and wafer expansion. After the wafer is manufactured, dicing tracks are left on the wafer. First, the wafer is attached to a UV film, and then a laser is used to perform invisible dicing. Invisible dicing can break the internal structure of silicon in the dicing track area. Then, a wafer expander is used to expand the wafer into individual chips. Finally, a debonding machine is used to remove the adhesive of the UV film, thereby removing the chips.

[0004] However, the hidden dicing process is not only costly, but also has high requirements for the wafer and dicing process. If the cross-sectional structure of the dicing channel contains multiple layers of different materials, it may lead to a reduction in laser power, which may require multiple hidden dicing processes, resulting in a surge in costs. For example, if there is contamination or residue in a certain area of ​​the dicing channel, it may cause the wafer expansion in that area to fail, and some chips may be connected together and become unusable, resulting in losses.

[0005] Patent document with application number 202011095834.7 discloses a wafer cleaving and expanding device and a wafer cleaving and expanding method. The cleaving method uses a dicing process, which has problems such as complex process, high dicing cost and difficulty in guaranteeing success rate.

[0006] Patent document with application number 202010619237.3 discloses a wafer expansion method including the following steps: the dicing method used in the scheme is also a hidden cutting process with dicing channels, which also has problems such as: complex process, high dicing cost, and difficulty in guaranteeing success rate.

[0007] Therefore, there is a need for a grooving structure, method, and process for wafer dicing that can simplify the dicing production process, reduce dicing costs, and improve the success rate. Summary of the Invention

[0008] To address the aforementioned problems, the present invention aims to provide a grooving structure, grooving method, and dicing process for wafer dicing, thereby simplifying the dicing production process, reducing dicing process costs, and improving the success rate.

[0009] The objective of this invention can be achieved through the following technical solution: a slotting structure for wafer dicing, the slotting structure being formed on a wafer having opposing front and back sides, the slotting structure comprising, along the dicing boundary:

[0010] Grooves A1 and A2 are formed on one side of the wafer, and a protrusion is formed between grooves A1 and A2; groove B is formed on the other side of the wafer at the location corresponding to the protrusion.

[0011] By etching non-connected grooves on both sides of the wafer to replace the original dicing pattern, costs can be saved. At the same time, a portion of the wafer remains in one of the grooves, forming a bump.

[0012] The width of the protrusion is greater than the width of the slot B, which increases the adhesion at the edge of the adjacent chip boundary.

[0013] The width of the bump is greater than the width of slot B, which helps maintain the stability of the connection between adjacent chips before wafer expansion, prevents irregular breakage of the wafer before wafer expansion, and improves yield.

[0014] Furthermore: grooves A1 and A2 are formed on the front side of the wafer, and groove B is formed on the back side of the wafer at the location corresponding to the bump. The depth of groove A1 or groove A2 is less than the depth of groove B.

[0015] Furthermore: grooves A1 and A2 are formed on the back side of the wafer, and groove B is formed on the front side of the wafer at the location corresponding to the bump; the sum of the depth of groove A1 or groove A2 and the depth of groove B is less than the wafer thickness.

[0016] By employing various etching and grooving methods, diverse dicing and grooving schemes can be formed, which can be flexibly selected according to wafer specifications, thus improving wafer dicing quality.

[0017] Furthermore, the wafer is an SOI wafer, which includes a bottom silicon layer, a buried oxide layer, and a top silicon layer stacked together.

[0018] Furthermore: the trench A1 and / or trench A2 penetrate the top silicon to the buried oxide layer, and the trench B penetrates the bottom silicon to the buried oxide layer.

[0019] Furthermore: the trench B penetrates the top silicon to the buried oxide layer, and the trench A1 and / or trench A2 penetrate the bottom silicon to the buried oxide layer.

[0020] Etching SOI wafers creates trenches that extend into the buried oxide layer, which facilitates wafer expansion and separation, resulting in high-quality individual chips.

[0021] A grooving method for forming the aforementioned grooving structure for wafer dicing includes the following steps:

[0022] S11. Coat the surface of the wafer with photoresist;

[0023] S12. Perform photolithography on the photoresist to expose the wafer area that needs to be etched;

[0024] S13. Etch the exposed parts of the wafer to form grooves A1 and A2 at the junction of adjacent chips on the wafer surface, so that a bump is formed between grooves A1 and A2, and remove excess photoresist.

[0025] S14. Coat the other surface of the wafer with photoresist;

[0026] S15. Perform photolithography on the photoresist to expose the wafer area that needs to be etched;

[0027] S16. Etch the exposed parts of the wafer to form groove B at the location corresponding to the bump and remove excess photoresist.

[0028] The width of the bump is greater than the width of the slot B, which increases the adhesion at the edge of the adjacent chip boundary.

[0029] By using the above method, non-connected grooves are formed on the wafer etching, replacing the original dicing channels formed by hidden cutting. This can save costs. At the same time, the remaining part of the wafer in one side of the groove forms a bump, which can increase the stability of the connection between adjacent chips, prevent irregular breakage of the wafer before wafer expansion, and improve the yield.

[0030] Furthermore, the cross-section of a single chip formed by the wafer dicing is square, rhomboid, regular hexagon, or regular dodecagon.

[0031] A dicing process, based on the above-mentioned grooving method, includes the following steps:

[0032] S21. Coat the surface of the wafer with photoresist;

[0033] S22. Perform photolithography on the photoresist to expose the wafer area that needs to be etched;

[0034] S23. Etch the exposed parts of the wafer to form grooves A1 and A2 at the junction of adjacent chips on the wafer surface, so that a bump is formed between grooves A1 and A2, and remove excess photoresist.

[0035] S24. Coat the other surface of the wafer with photoresist;

[0036] S25. Perform photolithography on the photoresist to expose the wafer area that needs to be etched;

[0037] S26. Etch the exposed parts of the wafer to form groove B at the location corresponding to the bump and remove excess photoresist.

[0038] The width of the bump is greater than the width of the slot B, which increases the adhesion at the edge of the adjacent chip boundary.

[0039] The above process forms non-connected grooves on the wafer etching, replacing the original dicing channels formed by hidden cutting, which can save costs. At the same time, the remaining part of the wafer in one side of the groove forms a bump, which can increase the stability of the connection between adjacent chips, prevent irregular breakage of the wafer before wafer expansion, and improve the yield.

[0040] The beneficial effects of this invention are:

[0041] 1. This invention forms non-connected grooves on the wafer by etching, replacing the original dicing channels formed by hidden cutting. This can save costs on wafer dicing and increase the wafer expansion rate. At the same time, a portion of the wafer remains in one of the grooves, forming a bump, which increases the stability of the connection between adjacent chips, prevents irregular breakage of the wafer before wafer expansion, and improves the yield.

[0042] 2. In this invention, while using etched grooves to replace dicing channels, the wafer chips can be equilateral rhombuses, regular hexagons, or regular dodecagons, so that the grooves on a single chip are staggered and will not be connected in a straight line, further increasing the stability of a single chip before wafer expansion.

[0043] 3. The present invention forms the groove through the chip's own process, without the need for additional processes, thus simplifying the process flow. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of a wafer dicing method according to the present invention;

[0045] Figure 2 This is a schematic diagram of another wafer dicing method according to the present invention;

[0046] Figure 3 This is a schematic diagram of another wafer dicing method according to the present invention;

[0047] Figure 4 This is a schematic diagram of another wafer dicing method according to the present invention;

[0048] Figure 5 For the present invention Figure 1-4 A perspective structural diagram of component A in the middle section;

[0049] Figure 6 For the present invention Figure 5 A schematic diagram of the cross-sectional structure;

[0050] Figure 7 For the present invention Figure 1-4Another perspective view of component A;

[0051] Figure 8 For the present invention Figure 7 A schematic diagram of the cross-sectional structure;

[0052] Figure 9 For the present invention Figure 1-4 Another perspective view of component A;

[0053] Figure 10 For the present invention Figure 9 A schematic diagram of the cross-sectional structure;

[0054] Figure 11 For the present invention Figure 1-4 Another perspective view of component A;

[0055] Figure 12 For the present invention Figure 11 A schematic diagram of the cross-sectional structure;

[0056] Figure 13 This is a schematic flowchart of the grooving method of the present invention.

[0057] 100. Wafer; 110. Chip 1; 120. Chip 2; 130. Bump; 140. Slot A1; 150. Slot A2; 160. Slot B;

[0058] 200, silicon wafer; 210, top silicon; 220, buried oxide layer; 230, bottom silicon. Detailed Implementation

[0059] Embodiments of the present invention are described in detail below. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar symbols denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0060] Example 1

[0061] This invention discloses a slotted structure for dicing wafer 100, including wafer 100, which can be a silicon wafer, and the slotted structure is formed at the junction of adjacent chips at the dicing boundary of wafer 100 (i.e., the dotted line in the figure).

[0062] like Figures 1-4 As shown, by dicing a wafer 100, the cross-section of a single chip can be square, rhomboid, regular hexagon, or regular dodecagon. This results in the slots on a single chip being staggered and not forming a straight line, further increasing the stability of the single chip before wafer expansion.

[0063] by Figures 1-4For example, the adjacent chips in part A are shown in the diagram. The structure of part A is as follows: Figure 5 As shown in Figure 6, grooves A1140 and A2150 are etched on the front side of the junction between chip 110 and chip 2120, and groove B160 is formed on the back side. The slotted structure formed by grooves A1140, A2150 and B160 replaces the function of the dicing track, avoids the separate hidden cutting operation, and can ensure the normal progress of subsequent wafer expansion operations.

[0064] Meanwhile, the sum of the depths of groove A1140 or groove A2150 and groove B160 is less than the thickness of wafer 100, making it less likely for chip 110 and chip 2120 to break before wafer expansion.

[0065] Between slot A1140 and slot A2150, the remaining portion of wafer 100 forms a bump 130. The width of the bump 130 is greater than the width of slot B160. This structure can increase the adhesion between the edges of chip 110 and chip 2120, preventing irregular breakage of chip 110 and chip 2120 before wafer expansion.

[0066] Example 2

[0067] like Figure 7 As shown in Figure 8, unlike in Embodiment 1, grooves A1140 and A2150 are etched on the back side of the junction of chip 110 and chip 2120, and groove B160 is formed on the front side. The slotted structure formed by grooves A1140, A2150 and B160 replaces the function of the dicing track, avoids the separate hidden cutting operation, and can ensure the normal progress of subsequent wafer expansion operations.

[0068] Meanwhile, the sum of the depths of groove A1140 or groove A2150 and groove B160 is less than the thickness of wafer 100, making it less likely for chip 110 and chip 2120 to break before wafer expansion.

[0069] Between slot A1140 and slot A2150, the remaining portion of wafer 100 forms a bump 130. The width of the bump 130 is greater than the width of slot B160. This structure can increase the adhesion between the edges of chip 110 and chip 2120, preventing irregular breakage of chip 110 and chip 2120 before wafer expansion.

[0070] Example 3

[0071] Unlike Example 1, the wafer 100 used in this example is an SOI wafer 200. The SOI wafer 200 includes a bottom silicon 230, a buried oxide layer 220 and a top silicon 210 stacked together. The slotted structure is formed at the junction of adjacent chips on the SOI wafer 200.

[0072] like Figure 9As shown in Figure 10, the front side of chip 110 and chip 220 is top silicon 210, and the back side is bottom silicon 230. At the junction of the top silicon 210 of chip 110 and chip 220, trenches A1140 and A2150 are formed. At the junction of the bottom silicon 230 of chip 110 and chip 220, trench B160 is formed. Trench A1140 and / or A2150 penetrate the top silicon 210 to the buried oxide layer 220, and trench B160 penetrates the bottom silicon 230 to the buried oxide layer 220. This structure can effectively utilize the stress differences of each layer of wafer 100, which is beneficial to wafer 100 expansion and separation, and obtaining high-quality chip units.

[0073] Meanwhile, the slotted structure formed by slots A1140 and A2150 with slot B160 replaces the function of the dicing channel, avoiding the hidden cutting operation while ensuring the normal progress of subsequent wafer expansion operations.

[0074] Meanwhile, the remaining portion of wafer 100 between slot A1140 and slot A2150 forms a bump 130. The width of the bump 130 is greater than the width of slot B160. This structure can increase the adhesion between the edges of chip 110 and chip 2120, preventing irregular breakage of chip 110 and chip 2120 before wafer expansion.

[0075] Example 4

[0076] like Figure 11 As shown in Example 12, unlike Example 3, the front side of Chip 110 and Chip 220 is a bottom silicon 230, and the back side is a top silicon 210. At the junction of the bottom silicon 230 of Chip 110 and Chip 220, trenches A1140 and A2150 are formed. At the junction of the top silicon 210 of Chip 110 and Chip 220, trench B160 is formed. Trench A1140 and / or A2150 penetrate the bottom silicon 230 to the buried oxide layer 220, and trench B160 penetrates the top silicon 210 to the buried oxide layer 220. This structure can effectively utilize the stress differences of each layer of wafer 100, which is beneficial for wafer 100 expansion and separation, and obtaining high-quality chip units.

[0077] Meanwhile, the slotted structure formed by slots A1140 and A2150 with slot B160 replaces the function of the dicing channel, avoiding the hidden cutting operation while ensuring the normal progress of subsequent wafer expansion operations.

[0078] Meanwhile, the remaining portion of wafer 100 between slot A1140 and slot A2150 forms a bump 130. The width of the bump 130 is greater than the width of slot B160. This structure can increase the adhesion between the edges of chip 110 and chip 2120, preventing irregular breakage of chip 110 and chip 2120 before wafer expansion.

[0079] Example 5

[0080] This embodiment describes a grooving method used in Embodiments 1 to 4, such as... Figure 13 As shown, it includes the following steps:

[0081] S11. Coat the surface of wafer 100 with photoresist;

[0082] S12. Perform photolithography on the photoresist to expose the wafer 100 area that needs to be etched;

[0083] S13. Etch the exposed parts of the wafer 100 to form grooves A1140 and A2150 at the junction of adjacent chips on the surface of the wafer 100, and form a bump 130 between grooves A1140 and A2150 to remove excess photoresist.

[0084] S14. Coat the other surface of wafer 100 with photoresist;

[0085] S15. Perform photolithography on the photoresist to expose the wafer 100 area that needs to be etched;

[0086] S16. Etch the exposed parts of the wafer 100 to form a groove B160 corresponding to the bump 130 and remove excess photoresist.

[0087] The wafer dicing method described above can produce individual chips with cross-sections that are square, rhomboid, regular hexagonal, or regular dodecagonal. This ensures that the slots on the individual chip are staggered and do not form a straight line, further increasing the stability of the individual chip before wafer expansion.

[0088] Furthermore, the width of the bump 130 is greater than the width of the slot B160, which increases the adhesion at the edge of the adjacent chip boundary; the width of the bump 130 is greater than the width of the slot B160, which helps to maintain the stability of the connection between adjacent chips before wafer expansion, prevents irregular breakage of the wafer 100 before wafer expansion, and improves the yield.

[0089] Furthermore: Grooves A1140 and A2150 are formed on the front side of wafer 100, and groove B160 is formed on the back side of wafer 100 at the location corresponding to bump 130; the sum of the depth of groove A1140 or groove A2150 and the depth of groove B160 is less than the thickness of wafer 100; or, grooves A1140 and A2150 are formed on the back side of wafer 100, and groove B160 is formed on the front side of wafer 100 at the location corresponding to bump 130; the sum of the depth of groove A1140 or groove A2150 and the depth of groove B160 is less than the thickness of wafer 100.

[0090] By employing various etching and grooving methods, diverse dicing and grooving schemes can be formed, which can be flexibly selected according to the wafer 100 specification, thus improving the dicing quality of wafer 100.

[0091] Further, wafer 100 is an SOI wafer 200, which includes a bottom silicon 230, a buried oxide layer 220, and a top silicon 210 stacked together. Trench A1140 and A2150 penetrate the top silicon 210 to the buried oxide layer 220, and trench B160 penetrates the bottom silicon 230 to the buried oxide layer 220; or, trench B160 penetrates the top silicon 210 to the buried oxide layer 220, and trench A1140 and trench A2150 penetrate the bottom silicon 230 to the buried oxide layer 220.

[0092] Etching the SOI wafer 200 creates trenches that extend to the buried oxide layer 220, which facilitates wafer 100 expansion and separation, resulting in high-quality chip units.

[0093] Example 6

[0094] This embodiment describes a grooving process for Embodiment 5, which includes the following steps:

[0095] S21. Coat the surface of wafer 100 with photoresist;

[0096] S22. Perform photolithography on the photoresist to expose the wafer 100 area that needs to be etched;

[0097] S23. Etch the exposed parts of the wafer 100 to form grooves A1140 and A2150 at the junction of adjacent chips on the surface of the wafer 100, and form a bump 130 between grooves A1140 and A2150 to remove excess photoresist.

[0098] S24. Coat the other surface of wafer 100 with photoresist;

[0099] S25. Perform photolithography on the photoresist to expose the wafer 100 area that needs to be etched;

[0100] S26. Etch the exposed parts of the wafer 100 to form a groove B160 corresponding to the bump 130 and remove excess photoresist.

[0101] Among them, the width of the protrusion 130 is greater than the width of the groove B160, which increases the adhesion of the edge at the boundary of adjacent chips.

[0102] Using the above-described grooving process, the present invention can form the groove through the etching process of the chip itself, without the need to add a separate hidden cutting process, thus simplifying the process flow.

[0103] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A grooving method for wafer dicing, characterized in that, Includes the following steps: S11. Coat the surface of the wafer (100) with photoresist; S12. Perform photolithography on the photoresist to expose the wafer (100) area to be etched; S13. Etch the exposed parts of the wafer (100) to form grooves A1 (140) and A2 (150) at the junction of adjacent chips on the surface of the wafer (100), and form a bump (130) between grooves A1 (140) and A2 (150) to remove excess photoresist. S14. Coat the other surface of the wafer (100) with photoresist; S15. Perform photolithography on the photoresist to expose the wafer (100) area to be etched; S16. Etch the exposed parts of the wafer (100) to form a groove B (160) corresponding to the bump (130) and remove excess photoresist. Among them, the width of the protrusion (130) is greater than the width of the groove B (160), which increases the adhesion of the edge at the boundary of the adjacent chip; The slotted structure is formed on a wafer (100) having opposing front and back sides, and the slotted structure includes, along the dicing boundary: A groove A1 (140) and a groove A2 (150) are formed on one side of the wafer (100), and a protrusion (130) is formed between the groove A1 (140) and the groove A2 (150). A groove B (160) is formed on the other side of the wafer (100) at the location corresponding to the bump (130); The width of the protrusion (130) is greater than the width of the groove B (160), which increases the adhesion of the edge at the boundary of the adjacent chip. The wafer (100) has slots A1 (140) and A2 (150) on its front side, and slot B (160) is formed on the back side of the wafer (100) at a position corresponding to the protrusion (130); the width of the protrusion (130) is greater than the width of the slot (B160); The wafer (100) is an SOI wafer (200), which includes a bottom silicon (230), a buried oxide layer (220), and a top silicon (210) stacked together. The trench A1 (140) and / or trench A2 (150) penetrate the top silicon (210) to the buried oxide layer (220), and the trench B (160) penetrates the bottom silicon (230) to the buried oxide layer (220). The trench B (160) penetrates the top silicon (210) to the buried oxide layer (220), and the trench A1 (140) and / or trench A2 (150) penetrate the bottom silicon (230) to the buried oxide layer (220). The wafer (100) has grooves A1 (140) and groove A2 (150) on its back side, and groove B (160) is formed on the front side of the wafer (100) at the position corresponding to the protrusion (130). The sum of the depth of groove A1 (140) or groove A2 (150) and the depth of groove B (160) is less than the thickness of wafer (100); making it less likely for chip one (110) and chip two (120) to break before wafer expansion.

2. The grooving method according to claim 1, characterized in that, The cross-section of a single chip formed by dicing the wafer (100) is square, rhomboid, regular hexagon or regular dodecagon.

3. A dicing process, based on the grooving method according to claim 1 or 2, characterized in that, Includes the following steps: S21. Coat the surface of the wafer (100) with photoresist; S22. Perform photolithography on the photoresist to expose the wafer (100) area to be etched; S23. Etch the exposed parts of the wafer (100) to form grooves A1 (140) and A2 (150) at the junction of adjacent chips on the surface of the wafer (100), so that a bump (130) is formed between grooves A1 (140) and A2 (150), and remove excess photoresist. S24. Coat the other surface of the wafer (100) with photoresist; S25. Perform photolithography on the photoresist to expose the wafer (100) area to be etched; S26. Etch the exposed parts of the wafer (100) to form a groove B (160) corresponding to the bump (130) and remove excess photoresist. Among them, the width of the protrusion (130) is greater than the width of the groove B (160), which increases the adhesion of the edge at the boundary of the adjacent chip.

Images