Semiconductor device

Abstract

The invention relates to a semiconductor device. An example semiconductor device includes a substrate including a first region and a second region; a first bridge pattern extending in a first direction on the first region; a first gate structure extending in a second direction intersecting the first direction; a first epitaxial pattern connected to the first bridge pattern on a side surface of the first gate structure; a first inner spacer interposed between the substrate and the first bridge pattern and between the first gate structure and the first epitaxial pattern; a second bridge pattern extending in the first direction on the second region; a second gate structure extending in a second direction; a second epitaxial pattern connected to the second bridge pattern on a side surface of the second gate structure; and a second inner spacer disposed between the substrate and the second bridge pattern and between the second gate structure and the second epitaxial pattern.

Description

Technical Field

[0001] The disclosure relates to a semiconductor device. Background Art

[0002] As a scaling technology for increasing the density of integrated circuit devices, the concept of multi-gate transistors has been proposed, in which a silicon body is formed on a substrate in the form of fins or nanowires and a gate is formed on the surface of the silicon body. Multi-gate transistors, with their advantage of a three-dimensional (3D) channel, allow easy scaling up and down. In addition, multi-gate transistors provide improved control of current without increasing the gate length. In addition, multi-gate transistors effectively mitigate short channel effect (SCE), which is a phenomenon in which the potential of the channel region is affected by the drain voltage. Summary of the invention

[0003] The present disclosure relates to semiconductor devices having improved performance and methods of manufacturing semiconductor devices having improved performance.

[0004] However, the various aspects of the present disclosure are not limited to those described herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below.

[0005] In some embodiments, a semiconductor device includes: a substrate including a first region and a second region; a first bridge pattern, on the first region, the first bridge pattern extending in a first direction and spaced apart from the substrate, and the first bridge pattern having a first width; a first gate structure extending in a second direction, wherein the second direction intersects the first direction and the first bridge pattern extends through the first gate structure; a first epitaxial pattern connected to the first bridge pattern on a side surface of the first gate structure; a first inner spacer disposed between the substrate and the first bridge pattern and between the first gate structure and the first epitaxial pattern; a second bridge pattern extending in the first direction on the second region, the second bridge pattern spaced apart from the substrate, the second bridge pattern having a second width, and the second width being greater than the first width; a second gate structure extending in the second direction, wherein the second bridge pattern extends through the second gate structure; a second epitaxial pattern connected to the second bridge pattern on a side surface of the second gate structure; and a second inner spacer disposed between the substrate and the second bridge pattern and between the second gate structure and the second epitaxial pattern, wherein a first thickness of the first inner spacer in the first direction is greater than a second thickness of the second inner spacer in the first direction.

[0006] In some embodiments, a semiconductor device includes: a substrate including a first region and a second region; a first bridge pattern and a second bridge pattern, sequentially stacked on the first region, the first bridge pattern and the second bridge pattern extending in a first direction and spaced apart from the substrate; a first gate structure, extending in a second direction, wherein the second direction intersects with the first direction and the first bridge pattern and the second bridge pattern extend through the first gate structure; a first inner spacer, on a side surface of the first gate structure and between the first bridge pattern and the second bridge pattern; a first epitaxial pattern, connected to the first bridge pattern and the second bridge pattern on an outer side surface of the first inner spacer; a third bridge pattern and a fourth bridge pattern, sequentially stacked on the second region, the A third bridging pattern and the fourth bridging pattern extend in the first direction; a second gate structure extends in the second direction, wherein the third bridging pattern and the fourth bridging pattern extend through the second gate structure; a second inner spacer is arranged on a side surface of the second gate structure and between the third bridging pattern and the fourth bridging pattern; and a second epitaxial pattern is connected to the third bridging pattern and the fourth bridging pattern on an outer side surface of the second inner spacer, wherein a first width of the first bridging pattern and the second bridging pattern in the second direction is smaller than a second width of the third bridging pattern and the fourth bridging pattern in the second direction, and a first thickness of the first inner spacer in the first direction is greater than a second thickness of the second inner spacer in the first direction.

[0007] In some embodiments, a semiconductor device includes: a substrate including a first region and a second region arranged along a first direction and a third region between the first region and the second region; a channel structure including a first bridge pattern, a second bridge pattern and a transition pattern, the first bridge pattern extending in the first direction on the first region and having a first width, the second bridge pattern extending in the first direction on the second region and having a second width greater than the first width, and the transition pattern connecting the first bridge pattern and the second bridge pattern on the third region; a first gate structure extending in a second direction intersecting the first direction on the first region, the first gate structure being penetrated by the first bridge pattern; a first epitaxial pattern connected to the first bridge pattern on a side surface of the first gate structure; a second gate structure extending in the second direction on the second region, the second gate structure being penetrated by the second bridge pattern; a second epitaxial pattern connected to the second bridge pattern on a side surface of the second gate structure; and a second inner spacer disposed between the substrate and the second bridge pattern and between the second gate structure and the second epitaxial pattern, wherein a first thickness of the first inner spacer in the first direction is different from a second thickness of the second inner spacer in the first direction.

[0008] It should be noted that the effects of the present disclosure are not limited to those described above, and other effects of the present disclosure will be apparent from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects and features of the present disclosure will become more apparent by describing in detail example embodiments of the present disclosure with reference to the attached drawings.

[0010] Figure 1 is a layout diagram of an example of a semiconductor device.

[0011] Figure 2 Shown along Figure 1 Example cross-sectional views taken along line A1-A1 and line A2-A2.

[0012] Figure 3 Shows Figure 2 An example enlarged cross-sectional view of region R1 and region R2.

[0013] Figure 4 Shown along Figure 1 Example cross-sectional views taken along line B1-B1 and line B2-B2.

[0014] Figure 5 Shown along Figure 1 Example cross-sectional views taken along line C1-C1 and line C2-C2.

[0015] Figures 6 to 8 is an enlarged cross-sectional view of an example of a semiconductor device.

[0016] Fig. 9 A cross-sectional view showing an example of a semiconductor device.

[0017] Fig.10 is a layout diagram of another example of a semiconductor device.

[0018] Fig.11 Shown along Fig.10 Example cross-sectional views taken along line A1-A1 and line A2-A2.

[0019] Fig.12 Shows Fig.11 An example enlarged cross-sectional view of region R3 and region R4.

[0020] Fig.13 An enlarged cross-sectional view showing another example of a semiconductor device.

[0021] Fig.14 A cross-sectional view showing another example of a semiconductor device.

[0022] Fig.15 is a layout diagram of another example of a semiconductor device.

[0023] Fig.16 It is along Fig.15 An example cross-sectional view taken along line A3-A3 of FIG.

[0024] Fig.17A and Fig. 17B is an exemplary cross-sectional view of a semiconductor device.

[0025] Fig.18 is a layout diagram of another example of a semiconductor device.

[0026] Fig.19 It is along Fig.18 An example cross-sectional view taken along line A3-A3 of FIG.

[0027] Fig. 20 is a cross-sectional view of another example of a semiconductor device.

[0028] Fig.21 and Fig. 22 is an example layout diagram of a semiconductor device.

[0029] Figures 23 to 31 are layout diagrams or cross-sectional views illustrating intermediate steps of an example of a method of manufacturing a semiconductor device.

[0030] Figure 32 to Figure 34 are cross-sectional views illustrating intermediate steps of an example of a method of manufacturing a semiconductor device.

[0031] Fig.35 and Fig.36 are cross-sectional views illustrating intermediate steps of an example of a method of manufacturing a semiconductor device.

[0032] Fig.37 and Fig.38 are cross-sectional views illustrating intermediate steps of an example of a method of manufacturing a semiconductor device. DETAILED DESCRIPTION

[0033] It should be understood that the terms "first", "second", "third", etc. used herein to describe various elements, components, regions, layers and / or parts are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the essence and scope of the present disclosure, the first element, component, region, layer or part described below may also be referred to as a second element, component, region, layer or part.

[0034] Furthermore, in the present specification, the term “same” or “identical” includes not only being completely identical but also including slight changes that may occur due to process margin or other factors.

[0035] The following will refer to Figures 1 to 22 Semiconductor devices according to some embodiments of the present disclosure are described.

[0036] Figure 1 is a layout diagram of an example of a semiconductor device. Figure 2 Shown along Figure 1 Example cross-sectional views taken along line A1-A1 and line A2-A2. Figure 3 Shows Figure 2 An example enlarged cross-sectional view of region R1 and region R2. Figure 4 Shown along Figure 1 Example cross-sectional views taken along line B1-B1 and line B2-B2. Figure 5 Shown along Figure 1 Example cross-sectional views taken along line C1-C1 and line C2-C2.

[0037] Reference Figures 1 to 5 The semiconductor device may include: a substrate 100, a field insulating film 105, a first active pattern AP1, a second active pattern AP2, a first gate structure GS1, a second gate structure GS2, a first gate spacer 140, a second gate spacer 240, a first gate capping pattern 150, a second gate capping pattern 250, a first inner spacer 145, a second inner spacer 245, a first epitaxial pattern 160, a second epitaxial pattern 260, an interlayer insulating film 180, a first source / drain contact CA1, and a second source / drain contact CA2.

[0038] The substrate 100 may be a bulk silicon substrate or a silicon on insulator (SOI) substrate. Alternatively, the substrate 100 may be a silicon substrate, or may include silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the substrate 100 may be an epitaxial layer formed on a base substrate. For convenience, the substrate 100 is described as a silicon substrate hereinafter.

[0039] The substrate 100 may include a first region I and a second region II. The first region I and the second region II may be connected regions or separated regions. Transistors having the same conductivity type or having different conductivity types may be formed in both the first region I and the second region II.

[0040] The first active pattern AP1 may be formed on the first region I of the substrate 100. The first active pattern AP1 may extend in a first direction X1 parallel to the upper surface of the substrate 100. The first active pattern AP1 may include a plurality of bridge patterns (e.g., a first bridge pattern 111, a second bridge pattern 112, and a third bridge pattern 113) extending in the first direction X1, the plurality of bridge patterns being sequentially stacked on the upper surface of the substrate 100 and spaced apart from each other. The first active pattern AP1 may be used as a multi-bridge channel field effect transistor (MBCFET). TM The number of bridge patterns included in the first active pattern AP1 is only an example and is not particularly limited.

[0041] In some embodiments, the first active pattern AP1 may further include a first fin pattern 110. The first fin pattern 110 may protrude from the upper surface of the substrate 100 and may extend in the first direction X1. The first fin pattern 110 may be formed by etching a portion of the substrate 100 and may be an epitaxial layer grown from the substrate 100. The first bridge pattern 111, the second bridge pattern 112, and the third bridge pattern 113 may be sequentially stacked on the upper surface of the first fin pattern 110.

[0042] The second active pattern AP2 may be formed on the second region II of the substrate 100. The second active pattern AP2 may extend in a fourth direction X2 parallel to the upper surface of the substrate 100. The fourth direction X2 may be the same as the first direction X1, but the present disclosure is not limited thereto. Alternatively, the fourth direction X2 may be different from the first direction X1. The second active pattern AP2 may include a plurality of bridge patterns (e.g., a fourth bridge pattern 211, a fifth bridge pattern 212, and a sixth bridge pattern 213) extending in the fourth direction X2, the plurality of bridge patterns being sequentially stacked on the upper surface of the substrate 100 and spaced apart from each other. The second active pattern AP2 may be used as an MBCFETTM The number of bridge patterns included in the second active pattern AP2 is only an example and is not particularly limited.

[0043] In some embodiments, the second active pattern AP2 may further include a second fin pattern 210. The second fin pattern 210 may protrude from the upper surface of the substrate 100 and may extend in the fourth direction X2. The second fin pattern 210 may be formed by etching a portion of the substrate 100 and may be an epitaxial layer grown from the substrate 100. A fourth bridge pattern 211, a fifth bridge pattern 212, and a sixth bridge pattern 213 may be sequentially stacked on the upper surface of the second fin pattern 210.

[0044] The first width WA1 of the first active pattern AP1 may be smaller than the second width WA2 of the second active pattern AP2. Here, the first width WA1 refers to a measurement made in the second direction Y1 intersecting the extension direction of the first active pattern AP1 (i.e., the first direction X1), and the second width WA2 refers to a measurement made in the fifth direction Y2 intersecting the extension direction of the second active pattern AP2 (i.e., the fourth direction X2). For example, the first width WA1 may be about 5 nm to about 20 nm, and the second width WA2 may be about 20 nm to about 100 nm. The fifth direction Y2 may be the same as the second direction Y1, but the present disclosure is not limited thereto. The fifth direction Y2 may be different from the second direction Y1.

[0045] Figure 4 and Figure 5 The first width WA1 of the first active pattern AP1 is shown to be uniform along the height direction (i.e., the third direction Z1), but the present disclosure is not limited thereto. Alternatively, depending on the characteristics of the etching (or patterning) process used to form the first active pattern AP1, the first width WA1 of the first active pattern AP1 may decrease in a direction away from the substrate 100. For example, contrary to what is depicted, the width of the first bridge pattern 111 may be smaller than the width of the first fin pattern 110, the width of the second bridge pattern 112 may be smaller than the width of the first bridge pattern 111, and the width of the third bridge pattern 113 may be smaller than the width of the second bridge pattern 112.

[0046] also, Figure 4 and Figure 5The second width WA2 of the second active pattern AP2 is shown to be uniform along the height direction (i.e., the sixth direction Z2), but the present disclosure is not limited thereto. Alternatively, depending on the characteristics of the etching (or patterning) process used to form the second active pattern AP2, the second width WA2 of the second active pattern AP2 may decrease in a direction away from the substrate 100. For example, contrary to what is depicted, the width of the fourth bridge pattern 211 may be smaller than the width of the second fin pattern 210, the width of the fifth bridge pattern 212 may be smaller than the width of the fourth bridge pattern 211, and the width of the sixth bridge pattern 213 may be smaller than the width of the fifth bridge pattern 212. The sixth direction Z2 may be the same as the third direction Z1, but the present disclosure is not limited thereto. Alternatively, the sixth direction Z2 may be different from the third direction Z1.

[0047] The first active pattern AP1 and the second active pattern AP2 may include an elemental semiconductor material, such as silicon (Si) or germanium (Ge). Alternatively, the first active pattern AP1 and the second active pattern AP2 may include a compound semiconductor, such as a group IV-IV compound semiconductor or a group III-V compound semiconductor. The group IV-IV compound semiconductor may be, for example, a binary compound or a ternary compound containing at least two or more of carbon (C), Si, Ge, and tin (Sn), or a compound doped with a group IV element. The group III-V compound semiconductor may be a binary compound, a ternary compound, or a quaternary compound formed by combining at least one group III element, such as aluminum (Al), gallium (Ga), or indium (In), with at least one group V element, such as phosphorus (P), arsenic (As), or antimony (Sb). The first active pattern AP1 and the second active pattern AP2 will be described hereinafter as, for example, a Si pattern.

[0048] In some embodiments, the first active pattern AP1 and the second active pattern AP2 may be arranged at the same level. Here, the phrase "arranged at the same level" means that the corresponding elements are positioned at the same height relative to the surface of the substrate 100. For example, Figure 2 , Figure 4 and Figure 5 As shown, the first bridge pattern 111 , the second bridge pattern 112 , and the third bridge pattern 113 may be arranged at the same height as the fourth bridge pattern 211 , the fifth bridge pattern 212 , and the sixth bridge pattern 213 , respectively.

[0049] In some embodiments, the first active pattern AP1 and the second active pattern AP2 may be formed at the same level. Here, the phrase "formed at the same level" means that the corresponding elements are formed by the same manufacturing process. For example, the first active pattern AP1 and the second active pattern AP2 may be formed of the same material and / or have the same material composition.

[0050] The field insulating film 105 may be formed on the substrate 100. The field insulating film 105 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a combination thereof, but the present disclosure is not limited thereto. For example, the field insulating film 105 may include a silicon oxide film.

[0051] In some embodiments, the field insulating film 105 may cover at least a portion of a side surface of the first fin pattern 110 and at least a portion of a side surface of the second fin pattern 210 . Figure 4 and Figure 5 The upper portions of the first and second fin patterns 110 and 210 are shown to protrude beyond the upper surface of the field insulating film 105 , but the disclosure is not limited thereto. Alternatively, the upper surface of the field insulating film 105 may be coplanar with the upper surfaces of the first and second fin patterns 110 and 210 .

[0052] The first gate structure GS1 may be formed on the first region I of the substrate 100 and the field insulating film 105. The first gate structure GS1 may intersect with the first active pattern AP1. For example, the first gate structure GS1 may extend in the second direction Y1, which is parallel to the upper surface of the substrate 100 and intersects with the first direction X1. The first bridge pattern 111, the second bridge pattern 112, and the third bridge pattern 113 may penetrate the first gate structure GS1 by extending in the first direction X1. That is, the first gate structure GS1 may surround each of the first bridge pattern 111, the second bridge pattern 112, and the third bridge pattern 113.

[0053] The second gate structure GS2 may be formed on the second region II of the substrate 100 and the field insulating film 105. The second gate structure GS2 may intersect with the second active pattern AP2. For example, the second gate structure GS2 may extend in a fifth direction Y2, which is parallel to the upper surface of the substrate 100 and intersects with the fourth direction X2. The fourth bridge pattern 211, the fifth bridge pattern 212, and the sixth bridge pattern 213 may extend through the second gate structure GS2 in the fourth direction X2. That is, the second gate structure GS2 may surround each of the fourth bridge pattern 211, the fifth bridge pattern 212, and the sixth bridge pattern 213.

[0054] In some embodiments, the third width WG1 of the first gate structure GS1 may be the same as the fourth width WG2 of the second gate structure GS2. Here, the third width WG1 refers to a measurement made in the first direction X1 intersecting the extension direction of the first gate structure GS1 (i.e., the second direction Y1), and the fourth width WG2 refers to a measurement made in the fourth direction X2 intersecting the extension direction of the second gate structure GS2 (i.e., the fifth direction Y2).

[0055] The first gate structure GS1 may include a first gate dielectric film 120 and a first gate electrode 130 , and the second gate structure GS2 may include a second gate dielectric film 220 and a second gate electrode 230 .

[0056] The first gate dielectric film 120 may be stacked on the first active pattern AP1. The first gate dielectric film 120 may surround the first active pattern AP1. The first gate dielectric film 120 may extend along an upper surface of the field insulating film 105 and a surface of the first fin pattern 110 protruding from the field insulating film 105.

[0057] The second gate dielectric film 220 may be stacked on the second active pattern AP2 . The second gate dielectric film 220 may surround the second active pattern AP2 . The second gate dielectric film 220 may extend along an upper surface of the field insulating film 105 and a surface of the second fin pattern 210 protruding from the field insulating film 105 .

[0058] The first gate dielectric film 120 and the second gate dielectric film 220 may include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high-k material having a dielectric constant greater than that of silicon oxide. The high-k material may include, for example, hafnium oxide (HfO 2 )、ZrO 2 ), lanthanum oxide (La 2 O 3 ), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), SrTiO 3 ), lanthanum aluminum oxide (LaAlO 3 ), yttrium oxide (Y 2 O 3 ), Hafnium Oxynitride (HfO x N y ), zirconium oxynitride (ZrO x N y ), lanthanum oxynitride (La 2 O x N y ), aluminum oxynitride (Al 2 O x N y ), titanium oxynitride (TiO x N y ), Strontium Titanium Oxynitride (SrTiO x N y ), lanthanum aluminum oxynitride (LaAlO x N y ), yttrium oxynitride (Y 2 O x N y ) and at least one of a combination thereof, but the present disclosure is not limited thereto.

[0059] In some embodiments, the first gate dielectric film 120 may include a first interface film 122 and a first high-k film 124 sequentially stacked on the first active pattern AP1. In some embodiments, the second gate dielectric film 220 may include a second interface film 222 and a second high-k film 224 sequentially stacked on the second active pattern AP2.

[0060] The first interface film 122 may conformally extend along the periphery of the first bridge pattern 111, the second bridge pattern 112, and the third bridge pattern 113. The second interface film 222 may conformally extend along the periphery of the fourth bridge pattern 211, the fifth bridge pattern 212, and the sixth bridge pattern 213. The first interface film 122 and the second interface film 222 may include, for example, at least one of silicon oxide, silicon oxynitride, and silicon nitride. In some embodiments, the first interface film 122 may include an oxide of a material included in the first active pattern AP1, and the second interface film 222 may include an oxide of a material included in the second active pattern AP2. For example, the first interface film 122 and the second interface film 222 may include a silicon oxide film.

[0061] The first high-k film 124 may conformally extend along the outer circumference of the first interface film 122. The second high-k film 224 may conformally extend along the outer circumference of the second interface film 222. The first high-k film 124 and the second high-k film 224 may include, for example, a high-k material.

[0062] The semiconductor device according to some embodiments of the present disclosure may include a negative capacitance (NC) field effect transistor (FET) using a negative capacitor. For example, each of the first interface film 122 and the second interface film 222 may include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0063] The ferroelectric material film may have a negative capacitance, and the paraelectric material film may have a positive capacitance. For example, if two or more capacitors are connected in series and have a positive capacitance, the total capacitance of the two or more capacitors may be lower than the capacitance of each of the two or more capacitors. On the contrary, if at least one of the two or more capacitors has a negative capacitance, the total capacitance of the two or more capacitors may have a positive value and may be greater than the absolute value of the capacitance of each of the two or more capacitors.

[0064] If a ferroelectric material film having negative capacitance is connected in series with a paraelectric material film having positive capacitance, the total capacitance of the ferroelectric material film and the paraelectric material film can be increased. Therefore, a transistor having a ferroelectric material film can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0065] The ferroelectric material film may have ferroelectric properties. The ferroelectric material film may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. For example, hafnium zirconium oxide may be a material obtained by doping hafnium oxide with zirconium (Zr). In another example, hafnium zirconium oxide may be a compound of hafnium (Hf), Zr, and oxygen (O).

[0066] The ferroelectric material film may further include a dopant. For example, the dopant may include at least one of Al, Ti, Nb, lanthanum (La), yttrium (Y), magnesium (Mg), silicon, calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium, scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant may vary depending on the type of material of the ferroelectric material film.

[0067] If the ferroelectric material film includes hafnium oxide, the dopant of the ferroelectric material film may include at least one of Gd, Si, Zr, Al, and Y, for example.

[0068] If the dopant of the ferroelectric material film is Al, the ferroelectric material film may include about 3 atomic % (at%) to about 8 at % Al. Here, the ratio of the dopant in the ferroelectric material film may refer to the ratio of the sum of the amounts of Hf and Al in the ferroelectric material film to the amount of Al.

[0069] If the dopant of the ferroelectric material film is Si, the ferroelectric material film may include about 2 at% to about 10 at% Si. If the dopant of the ferroelectric material film is Y, the ferroelectric material film may include about 2 at% to about 10 at% Y. If the dopant of the ferroelectric material film is Gd, the ferroelectric material film may include about 1 at% to about 7 at% Gd. If the dopant of the ferroelectric material film is Zr, the ferroelectric material film may include about 50 at% to about 80 at% Zr.

[0070] The paraelectric material film may include paraelectric properties. The paraelectric material film may include, for example, at least one of silicon oxide and high-k metal oxide. The high-k metal oxide may include, for example, at least one of hafnium oxide, zirconium oxide, and aluminum oxide, but the present disclosure is not limited thereto.

[0071] The ferroelectric material film and the paraelectric material film may include the same material. The ferroelectric material film may have ferroelectric properties, but the paraelectric material film may not have ferroelectric properties. For example, if the ferroelectric material film and the paraelectric material film include hafnium oxide, the hafnium oxide included in the ferroelectric material film may have a different crystalline structure from the hafnium oxide included in the paraelectric material film.

[0072] The ferroelectric material film may be thick enough to exhibit ferroelectric properties. The ferroelectric material film may have a thickness of, for example, about 0.5 nm to about 10 nm, but the present disclosure is not limited thereto. The critical thickness capable of exhibiting ferroelectric properties may vary depending on the type of ferroelectric material, and therefore, the thickness of the ferroelectric material film may vary depending on the type of ferroelectric material included in the ferroelectric material film.

[0073] For example, the first gate dielectric film 120 and / or the second gate dielectric film 220 may include a ferroelectric material film. In another example, the first gate dielectric film 120 and / or the second gate dielectric film 220 may include a plurality of ferroelectric material films spaced apart from each other. The first gate dielectric film 120 and / or the second gate dielectric film 220 may have a structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0074] The first gate electrode 130 may be formed on the substrate 100 and the field insulating film 105. The first gate electrode 130 may also be stacked on the first gate dielectric film 120. That is, the first gate dielectric film 120 may be interposed between the first active pattern AP1 and the first gate electrode 130. The first gate dielectric film 120 may also be interposed between the first fin pattern 110 and the first gate electrode 130. The first gate electrode 130 may be formed by, for example, a replacement process, but the present disclosure is not limited thereto.

[0075] The second gate electrode 230 may be formed on the substrate 100 and the field insulating film 105. The second gate electrode 230 may also be stacked on the second gate dielectric film 220. That is, the second gate dielectric film 220 may be interposed between the second active pattern AP2 and the second gate electrode 230. The second gate dielectric film 220 may also be interposed between the second fin pattern 210 and the second gate electrode 230. The second gate electrode 230 may be formed by, for example, a replacement process, but the present disclosure is not limited thereto.

[0076] The first gate electrode 130 and the second gate electrode 230 are shown as a single film, but the present disclosure is not limited thereto. Alternatively, the first gate electrode 130 and the second gate electrode 230 may be formed as a stack of multiple conductive layers. For example, each of the first gate electrode 130 and the second gate electrode 230 may include a work function control film for controlling the work function and a filling conductive film filling the space formed by the work function control film. The work function control film may include, for example, at least one of TiN, TaN, TiC, TaC, TiAlC, and a combination thereof. The filling conductive film may include, for example, W or Al.

[0077] In some embodiments, the first gate structure GS1 and the second gate structure GS2 may be formed at the same level.

[0078] The first gate spacer 140 may be formed on the substrate 100 and the field insulating film 105. The first gate spacer 140 may extend along the side surface of the first gate structure GS1. In some embodiments, a portion of the first gate dielectric film 120 may be disposed between the first gate electrode 130 and the first gate spacer 140. For example, the first gate dielectric film 120 may also extend along at least a portion of the inner side surface of the first gate spacer 140. The first gate dielectric film 120 may be formed by a replacement process, but the present disclosure is not limited thereto.

[0079] The second gate spacer 240 may be formed on the substrate 100 and the field insulating film 105. The second gate spacer 240 may extend along the side surface of the second gate structure GS2. In some embodiments, a portion of the second gate dielectric film 220 may be disposed between the second gate electrode 230 and the second gate spacer 240. For example, the second gate dielectric film 220 may also extend along at least a portion of the inner side surface of the second gate spacer 240. The second gate dielectric film 220 may be formed by a replacement process, but the present disclosure is not limited thereto.

[0080] The first gate spacer 140 and the second gate spacer 240 may include, for example, at least one of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbon nitride, and combinations thereof, but the present disclosure is not limited thereto. For example, the first gate spacer 140 and the second gate spacer 240 may include a silicon nitride film. In some embodiments, the first gate spacer 140 and the second gate spacer 240 may be formed at the same level.

[0081] The first gate capping pattern 150 may extend along the upper surface of the first gate structure GS1. In some embodiments, the first gate capping pattern 150 may cover the upper surface of the first gate structure GS1 and the upper surface of the first gate spacer 140. In some embodiments, the upper surface of the first gate structure GS1 and the upper surface of the first gate spacer 140 may include a concave surface. The first gate capping pattern 150 may be formed on the concave surface.

[0082] The second gate capping pattern 250 may extend along the upper surface of the second gate structure GS2. In some embodiments, the second gate capping pattern 250 may cover the upper surface of the second gate structure GS2 and the upper surface of the second gate spacer 240. In some embodiments, the upper surface of the second gate structure GS2 and the upper surface of the second gate spacer 240 may include a concave surface. The second gate capping pattern 250 may be formed on the concave surface.

[0083] The first gate capping pattern 150 and the second gate capping pattern 250 may include, for example, at least one of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbon nitride, and combinations thereof, but the present disclosure is not limited thereto. For example, the first gate capping pattern 150 and the second gate capping pattern 250 may include a silicon nitride film. In some embodiments, the first gate capping pattern 150 and the second gate capping pattern 250 may be formed at the same level.

[0084] The first inner spacer 145 may be formed on a side surface of the first gate electrode 130 between the first to third bridge patterns 111, 112, and 113. The first inner spacer 145 may also be formed on a side surface of the first gate electrode 130 between the first fin pattern 110 and the first bridge pattern 111.

[0085] In some embodiments, the first interface film 122 may be in contact with the first inner spacer 145. For example, Figure 3 As shown, the first interface film 122 may extend along surfaces of the first and second bridge patterns 111 and 112 and may directly contact the first inner side surfaces 145i adjacent to the first and second bridge patterns 111 and 112. The first interface film 122 may not extend along the first inner side surfaces 145i.

[0086] In a cross-sectional view across the first direction X1, the first gate spacer 140 may surround at least a portion of the first active pattern AP1 and at least a portion of the first inner spacer 145. Figure 5 As shown, the first gate spacer 140 may cover side surfaces of the first inner spacer 145 and / or side surfaces and an upper surface of the first active pattern AP1.

[0087] The second inner spacer 245 may be formed on the side surface of the second gate electrode 230 between the fourth bridge pattern 211, the fifth bridge pattern 212, and the sixth bridge pattern 213. The second inner spacer 245 may also be formed on the side surface of the second gate electrode 230 between the second fin pattern 210 and the fourth bridge pattern 211.

[0088] In some embodiments, the second interface film 222 may be in contact with the second inner spacer 245. For example, Figure 3 As shown, the second interface film 222 may extend along surfaces of the fourth and fifth bridge patterns 211 and 212 and may directly contact the second inner side surfaces 245i adjacent to the fourth and fifth bridge patterns 211 and 212. The second interface film 222 may not extend along the second inner side surfaces 245i.

[0089] In a cross-sectional view across the fourth direction X2, the second gate spacer 240 may surround at least a portion of the second active pattern AP2 and at least a portion of the second inner spacer 245. Figure 5 As shown, the second gate spacer 240 may cover side surfaces of the second inner spacer 245 and / or side surfaces and an upper surface of the second active pattern AP2.

[0090] The first inner spacer 145 and the second inner spacer 245 may include, for example, at least one of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbon nitride, and combinations thereof, but the present disclosure is not limited thereto. In some embodiments, the first inner spacer 145 and the second inner spacer 245 may be formed at the same level.

[0091] The first inner spacer 145 and the second inner spacer 245 may include the same material as or a different material from the first gate spacer 140 and the second gate spacer 240. In some embodiments, the first inner spacer 145 and the second inner spacer 245 may have a smaller dielectric constant than the first gate spacer 140 and the second gate spacer 240. For example, the first gate spacer 140 and the second gate spacer 240 may include a silicon nitride film, and the first inner spacer 145 and the second inner spacer 245 may include a silicon oxide film.

[0092] In some embodiments, a first liner film 118 may be formed on the first active pattern AP1 and the first inner spacer 145. The first liner film 118 may be disposed between the first active pattern AP1 and the first gate spacer 140 and between the first inner spacer 145 and the first gate spacer 140. For example, Figure 5 As shown, the first liner film 118 may conformally extend along the upper surface of the substrate 100, the side surface of the first inner spacer 145, and / or the side surface and the upper surface of the first active pattern AP1. The first liner film 118 may not be disposed between the first active pattern AP1 and the first gate structure GS1. The field insulating film 105 may be formed on the first liner film 118.

[0093] In some embodiments, a second liner film 218 may be formed on the second active pattern AP2 and the second inner spacer 245. The second liner film 218 may be disposed between the second active pattern AP2 and the second gate spacer 240 and between the second inner spacer 245 and the second gate spacer 240. For example, Figure 5 As shown, the second liner film 218 may conformally extend along the upper surface of the substrate 100, the side surface of the second inner spacer 245, and / or the side surface and the upper surface of the second active pattern AP2. The second liner film 218 may not be disposed between the second active pattern AP2 and the second gate structure GS2. The field insulating film 105 may be formed on the second liner film 218.

[0094] In some embodiments, the first liner film 118 may be an epitaxial layer grown from the substrate 100 and the first active pattern AP1, and the second liner film 218 may be an epitaxial layer grown from the substrate 100 and the second active pattern AP2. For example, the first liner film 118 and the second liner film 218 may include silicon oxide films.

[0095] In some embodiments, the first liner film 118 and the second liner film 218 may be formed at the same level.

[0096] In some embodiments, at least one of the first liner film 118 and the second liner film 218 may be omitted. Alternatively, contrary to what is depicted, the first gate spacer 140 may contact the first active pattern AP1 and the first inner spacer 145. Alternatively, contrary to what is depicted, the second gate spacer 240 may contact the second active pattern AP2 and the second inner spacer 245.

[0097] The first epitaxial pattern 160 may be formed on the upper surface of the substrate 100 and at least one side (e.g., both sides) of the first gate structure GS1. The first epitaxial pattern 160 may be connected to the first active pattern AP1. For example, the first bridge pattern 111, the second bridge pattern 112, and the third bridge pattern 113 may be connected to the first epitaxial pattern 160 by penetrating the first gate structure GS1 and the first gate spacer 140.

[0098] The first epitaxial pattern 160 may be formed on the outer side surface of the first gate spacer 140 and the first outer side surface 145o of the first inner spacer 145. That is, the first gate spacer 140 and the first inner spacer 145 may be disposed between the first gate structure GS1 and the first epitaxial pattern 160. The first epitaxial pattern 160 may be electrically isolated from the first gate electrode 130 by the first gate spacer 140 and the first inner spacer 145. In some embodiments, the first epitaxial pattern 160 may be in direct contact with the outer side surface of the first gate spacer 140 and / or the first outer side surface 145o of the first inner spacer 145.

[0099] The first epitaxial pattern 160 may include an epitaxial layer. For example, the first epitaxial pattern 160 may be grown from the substrate 100 and / or the first active pattern AP1 by an epitaxial growth method. The first epitaxial pattern 160 may be provided as a source / drain region of a FET formed on the first region I.

[0100] In some embodiments, the uppermost surface of the first epitaxial pattern 160 may be formed at the same height as or higher than the upper surface of the third bridge pattern 113. This is because the first epitaxial pattern 160 is formed from the third bridge pattern 113, which is the uppermost bridge pattern among the first bridge pattern 111, the second bridge pattern 112, and the third bridge pattern 113, using an epitaxial growth method.

[0101] The second epitaxial pattern 260 may be formed on the upper surface of the substrate 100 and at least one side (e.g., both sides) of the second gate structure GS2. The second epitaxial pattern 260 may be connected to the second active pattern AP2. For example, the fourth bridge pattern 211, the fifth bridge pattern 212, and the sixth bridge pattern 213 may be connected to the second epitaxial pattern 260 by penetrating the second gate structure GS2 and the second gate spacer 240.

[0102] The second epitaxial pattern 260 may be formed on the outer side surface of the second gate spacer 240 and the second outer side surface 245o of the second inner spacer 245. That is, the second gate spacer 240 and the second inner spacer 245 may be disposed between the second gate structure GS2 and the second epitaxial pattern 260. The second epitaxial pattern 260 may be electrically isolated from the second gate electrode 230 by the second gate spacer 240 and the second inner spacer 245. In some embodiments, the second epitaxial pattern 260 may be in direct contact with the outer side surface of the second gate spacer 240 and / or the second outer side surface 245o of the second inner spacer 245.

[0103] The second epitaxial pattern 260 may include an epitaxial layer. For example, the second epitaxial pattern 260 may be grown from the substrate 100 and / or the second active pattern AP2 by an epitaxial growth method. The second epitaxial pattern 260 may be provided as a source / drain region of a FET formed on the second region II.

[0104] In some embodiments, the uppermost surface of the second epitaxial pattern 260 may be formed at the same height as or higher than the upper surface of the sixth bridge pattern 213. This is because the second epitaxial pattern 260 is formed from the sixth bridge pattern 213, which is the uppermost bridge pattern among the fourth bridge pattern 211, the fifth bridge pattern 212, and the sixth bridge pattern 213, using an epitaxial growth method.

[0105] In the case where the FET formed on the first region I and / or the FET formed on the second region II is an n-type FET (NFET), the first epitaxial pattern 160 and / or the second epitaxial pattern 260 may include n-type impurities or impurities for preventing diffusion of n-type impurities. For example, the first epitaxial pattern 160 and / or the second epitaxial pattern 260 may include at least one of P, Sb, As, and combinations thereof.

[0106] In some embodiments, the first epitaxial pattern 160 and / or the second epitaxial pattern 260 may further include a tensile stress material. For example, when the first active pattern AP1 and / or the second active pattern AP2 is a Si pattern, the first epitaxial pattern 160 and / or the second epitaxial pattern 260 may include a material having a lattice constant smaller than that of Si, such as silicon carbide (SiC). The tensile stress material can enhance carrier mobility in the channel region by applying tensile stress to the first active pattern AP1 and / or the second active pattern AP2.

[0107] In the case where the FET formed on the first region I and / or the FET formed on the second region II is a p-type FET (PFET), the first epitaxial pattern 160 and / or the second epitaxial pattern 260 may include p-type impurities or impurities for preventing the diffusion of p-type impurities. For example, the first epitaxial pattern 160 and / or the second epitaxial pattern 260 may include at least one of B, In, Ga, Al, and combinations thereof.

[0108] In some embodiments, the first epitaxial pattern 160 and / or the second epitaxial pattern 260 may further include a compressive stress material. For example, when the first active pattern AP1 and / or the second active pattern AP2 is a Si pattern, the first epitaxial pattern 160 and / or the second epitaxial pattern 260 may include a material having a lattice constant greater than that of Si, such as silicon germanium (SiGe). The compressive stress material can improve carrier mobility in the channel region by applying compressive stress to the first active pattern AP1 and / or the second active pattern AP2.

[0109] In some embodiments, the first outer side surface 145o of the first inner spacer 145 opposite to the first epitaxial pattern 160 may include a concave surface. In this case, a side surface of a portion of the first epitaxial pattern 160 contacting the first outer side surface 145o may include a convex surface.

[0110] In some embodiments, the second outer side surface 245o of the second inner spacer 245 opposite to the second epitaxial pattern 260 may include a concave surface. In this case, a side surface of the second epitaxial pattern 260 contacting the second outer side surface 245o may include a convex surface.

[0111] The first inner spacer 145 and the second inner spacer 245 may have different thicknesses. In some embodiments, the first thickness TH1 of the first inner spacer 145 may be greater than the second thickness TH2 of the second inner spacer 245, and this is because the first width WA1 of the first active pattern AP1 forming the first inner spacer 145 is less than the second width WA2 of the second active pattern AP2 forming the second inner spacer 245. Here, the first thickness TH1 refers to a measurement made in the first direction X1, and the second thickness TH2 refers to a measurement made in the fourth direction X2. This will be referred to later. Figures 23 to 31 Give a description.

[0112] The first thickness TH1 and the second thickness TH2 may be defined as measurements taken at the same height from the upper surface of the substrate 100. Alternatively, the first thickness TH1 and the second thickness TH2 may be defined as the minimum thickness of the first inner spacer 145 and the minimum thickness of the second inner spacer 245, respectively. Alternatively, the first thickness TH1 and the second thickness TH2 may be defined as the maximum thickness of the first inner spacer 145 and the maximum thickness of the second inner spacer 245, respectively.

[0113] In some embodiments, the first inner side surface 145i of the first inner spacer 145 opposite to the first gate structure GS1 may include a concave surface. In this case, a side surface of a portion of the first gate structure GS1 contacting the first inner side surface 145i may include a convex surface.

[0114] In some embodiments, the second inner side surface 245i of the second inner spacer 245 opposite to the second gate structure GS2 may include a concave surface. In this case, a side surface of a portion of the second gate structure GS2 contacting the second inner side surface 245i may include a convex surface.

[0115] In some embodiments, the first thickness TH1 of the first inner spacer 145 may decrease and then increase in a direction away from the substrate 100 and the first active pattern AP1. Figure 3 As shown, both the first outer side surface 145o and the first inner side surface 145i of the first inner spacer 145 may include a concave surface. In this case, the first thickness TH1 of the first inner spacer 145 may decrease in a direction away from the first bridge pattern 111 and the second bridge pattern 112. That is, the first thickness TH1 of the first inner spacer 145 may decrease to a certain point and then increase in a direction away from the first bridge pattern 111. The first outer side surface 145o and the first inner side surface 145i may have the same radius of curvature, but the present disclosure is not limited thereto. Alternatively, the first outer side surface 145o and the first inner side surface 145i may have different radii of curvature.

[0116] In some embodiments, the second thickness TH2 of the second inner spacer 245 may decrease and then increase in a direction away from the substrate 100 and the second active pattern AP2. Figure 3 As shown, both the second outer side surface 245o and the second inner side surface 245i of the second inner spacer 245 may include a concave surface. In this case, the second thickness TH2 of the second inner spacer 245 may decrease in a direction away from the fourth bridge pattern 211 and the fifth bridge pattern 212. That is, the second thickness TH2 of the second inner spacer 245 may decrease to a certain point and then increase in a direction away from the fourth bridge pattern 211. The second outer side surface 245o and the second inner side surface 245i may have the same radius of curvature, but the present disclosure is not limited thereto. Alternatively, the second outer side surface 245o and the second inner side surface 245i may have different radii of curvature.

[0117] like Figure 3 As shown, the first inner surface 145i and the second inner surface 245i may have the same radius of curvature, but the present disclosure is not limited thereto. Alternatively, the first inner surface 145i and the second inner surface 245i may have different radii of curvature. For example, the first inner surface 145i may have a larger radius of curvature than the second inner surface 245i. In another example, the first inner surface 145i may have a smaller radius of curvature than the second inner surface 245i.

[0118] In addition, if Figure 3 As shown, the first outer side surface 145o and the second outer side surface 245o may have the same radius of curvature, but the present disclosure is not limited thereto. Optionally, the first outer side surface 145o and the second outer side surface 245o may have different radii of curvature. For example, the first outer side surface 145o may have a larger radius of curvature than the second outer side surface 245o. In another example, the first outer side surface 145o may have a smaller radius of curvature than the second outer side surface 245o.

[0119] The interlayer insulating film 180 may be formed on the substrate 100 and the field insulating film 105. The interlayer insulating film 180 may be formed to fill the space on the outer surface of the first gate spacer 140 and the space on the outer surface of the second gate spacer 240. For example, the interlayer insulating film 180 may cover the field insulating film 105, the first epitaxial pattern 160 and the second epitaxial pattern 260. The interlayer insulating film 180 may expose the upper surface of the first gate capping pattern 150 and the upper surface of the second gate capping pattern 250, but the present disclosure is not limited thereto. Alternatively, the interlayer insulating film 180 may cover the upper surface of the first gate capping pattern 150 and the upper surface of the second gate capping pattern 250.

[0120] The interlayer insulating film 180 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbon, silicon boron nitride, silicon boron carbonitride, silicon oxycarbon nitride, and a low-k material having a dielectric constant less than that of silicon oxide, but the present disclosure is not limited thereto. The low-k material may include, for example, at least one of flowable oxide (FOX), eastern silazane (TOSZ), undoped silicate glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma enhanced tetraethyl orthosilicate (PETEOS), fluorinated silicate glass (FSG), carbon-doped silicon oxide (CDO), dry gel, aerogel, amorphous fluorinated carbon, organic silicate glass (OSG), polyparaxylene, bisbenzocyclobutene (BCB), SiLK, polyimide, porous polymer material, and a combination thereof, but the present disclosure is not limited thereto.

[0121] In some embodiments, an etch stop film 182 covering the first epitaxial pattern 160 and the second epitaxial pattern 260 may be formed. The etch stop film 182 may conformally extend along the contour of the surface of the first epitaxial pattern 160 and the contour of the surface of the second epitaxial pattern 260. The etch stop film 182 may also extend along the upper surface of the field insulating film 105, the side surface of the first gate spacer 140, and the side surface of the second gate spacer 240. The interlayer insulating film 180 may be formed on the etch stop film 182.

[0122] The etching stop film 182 may include a material having an etching selectivity with respect to the interlayer insulating film 180. For example, in the case where the interlayer insulating film 180 includes silicon oxide, the etching stop film 182 may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon oxycarbide (SiOC), and a combination thereof. The etching stop film 182 may be prepared for an etching process for the interlayer insulating film 180.

[0123] The first source / drain contact CA1 may be connected to the first epitaxial pattern 160. For example, the first source / drain contact CA1 may penetrate the interlayer insulating film 180 and the etch stop film 182 by extending in the third direction Z1 and may be connected to the first epitaxial pattern 160.

[0124] The second source / drain contact CA2 may be connected to the second epitaxial pattern 260. For example, the second source / drain contact CA2 may penetrate the interlayer insulating film 180 and the etch stop film 182 by extending in the sixth direction Z2 and may be connected to the second epitaxial pattern 260.

[0125] In some embodiments, a contact spacer 184 may also be formed on the interlayer insulating film 180 and the etching stop film 182. The contact spacer 184 may conformally extend along the profile of the side surface of the first source / drain contact CA1 and the profile of the side surface of the second source / drain contact CA2. The first source / drain contact CA1 and the second source / drain contact CA2 may be connected to the first epitaxial pattern 160 and the second epitaxial pattern 260, respectively, by penetrating the contact spacer 184.

[0126] The contact spacers 184 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbon nitride, and a low-k material having a dielectric constant less than silicon oxide, but the present disclosure is not limited thereto.

[0127] In some embodiments, each of the first source / drain contacts CA1 may include a first silicide film 192, a first barrier metal film 194, and a first metal film 196 sequentially stacked on the corresponding first epitaxial pattern 160. In some embodiments, each of the second source / drain contacts CA2 may include a second silicide film 292, a second barrier metal film 294, and a second metal film 296 sequentially stacked on the corresponding second epitaxial pattern 260.

[0128] The first silicide film 192 may be disposed between the first epitaxial pattern 160 and the first barrier metal film 194, and the second silicide film 292 may be disposed between the second epitaxial pattern 260 and the second barrier metal film 294. The first silicide film 192 and the second silicide film 292 may include a metal silicide such as nickel silicide, cobalt silicide, tungsten silicide, titanium silicide, niobium silicide, or tantalum silicide, but the present disclosure is not limited thereto. For example, the first silicide film 192 and the second silicide film 292 may include titanium silicide.

[0129] A first barrier metal film 194 may be formed on the first silicide film 192. The first barrier metal film 194 may conformally extend along the profile of the upper surface of the first silicide film 192 and the profile of the side surface of the contact spacer 184. A second barrier metal film 294 may be formed on the second silicide film 292. The second barrier metal film 294 may conformally extend along the profile of the upper surface of the second silicide film 292 and the profile of the side surface of the contact spacer 184. The first barrier metal film 194 and the second barrier metal film 294 may include a conductive metal nitride, such as titanium nitride, tantalum nitride, or tungsten nitride, but the present disclosure is not limited thereto. For example, the first barrier metal film 194 and the second barrier metal film 294 may include titanium nitride.

[0130] A first metal film 196 may be formed on the first barrier metal film 194. The first metal film 196 may fill the remaining area on the first silicide film 192 that is not occupied by the first barrier metal film 194. A second metal film 296 may be formed on the second barrier metal film 294. The second metal film 296 may fill the remaining area on the second silicide film 292 that is not occupied by the second barrier metal film 294. The first metal film 196 and the second metal film 296 may include a metal material such as cobalt (Co), titanium (Ti), tantalum (Ta), ruthenium (Ru), tungsten (W) or cobalt tungsten phosphide (CoWP), but the present disclosure is not limited thereto. For example, the first metal film 196 and the second metal film 296 may include Co.

[0131] In some embodiments, the first silicide film 192 may be formed as a result of a reaction of elements included in the first barrier metal film 194 with the corresponding first epitaxial pattern 160 , and the second silicide film 292 may be formed as a result of a reaction of elements included in the second barrier metal film 294 with the corresponding second epitaxial pattern 260 .

[0132] In some embodiments, the first source / drain contact CA1 and the second source / drain contact CA2 may be formed at the same level.

[0133] Figures 6 to 8 is an enlarged cross-sectional view of an example of a semiconductor device. For convenience, the previously referenced Figures 1 to 5 Redundant or repetitive parts of the description that overlap.

[0134] Reference Figure 6 , the first inner side surface 145 i of the first inner spacer 145 and / or the second inner side surface 245 i of the second inner spacer 245 may include a flat surface.

[0135] For example, the first inner spacer 145 may include a first surface S11, a second surface S12, and a third surface S13. The first surface S11 may be a portion of the first inner surface 145i close to the first bridge pattern 111, the third surface S13 may be a portion of the first inner surface 145i close to the second bridge pattern 112, and the second surface S12 may be a portion of the first inner surface 145i connecting the first surface S11 and the third surface S13. In some embodiments, the first surface S11 and the third surface S13 may include concave surfaces, and the second surface S12 may include a flat surface. In this case, the side surface of the first gate structure GS1 in contact with the second surface S12 may include a flat surface.

[0136] For example, the second inner spacer 245 may include a fourth surface S21, a fifth surface S22, and a sixth surface S23. The fourth surface S21 may be a portion of the second inner surface 245i close to the fourth bridge pattern 211, the sixth surface S23 may be a portion of the second inner surface 245i close to the fifth bridge pattern 212, and the fifth surface S22 may be a portion of the second inner surface 245i connecting the fourth surface S21 and the sixth surface S23. In some embodiments, the fourth surface S21 and the sixth surface S23 may include concave surfaces, and the fifth surface S22 may include a flat surface. In this case, the side surface of the second gate structure GS2 in contact with the fifth surface S22 may include a flat surface.

[0137] Figure 6 It is shown that both the first inner side surface 145i and the second inner side surface 245i include a flat surface, but the present disclosure is not limited thereto. Alternatively, one of the first inner side surface 145i and the second inner side surface 245i may not include a flat surface.

[0138] Reference Figure 7 , the first inner side surface 145i and the second inner side surface 245i may include convex surfaces.

[0139] For example, the first surface S11 and the third surface S13 may include concave surfaces, and the second surface S12 may include a convex surface. In this example, a side surface of the first gate structure GS1 contacting the second surface S12 may include a concave surface.

[0140] For example, the fourth surface S21 and the sixth surface S23 may include concave surfaces, and the fifth surface S22 may include a convex surface. In this example, a side surface of the second gate structure GS2 contacting the fifth surface S22 may include a concave surface.

[0141] Figure 7 It is shown that both the first inner side surface 145i and the second inner side surface 245i include a convex surface, but the present disclosure is not limited thereto. Alternatively, one of the first inner side surface 145i and the second inner side surface 245i may not include a convex surface.

[0142] Reference Figure 8 , the first inner spacer 145 may expose a portion of a horizontal plane of the first active pattern AP1, and the second inner spacer 245 may expose a portion of a horizontal plane of the second active pattern AP2.

[0143] For example, the first inner spacer 145 may expose a portion of an upper surface of the first bridge pattern 111 and a portion of a bottom surface of the second bridge pattern 112. A horizontal surface of the first active pattern AP1 exposed by the first inner spacer 145 may directly contact the first epitaxial pattern 160.

[0144] For example, the second inner spacer 245 may expose a portion of an upper surface of the fourth bridge pattern 211 and a portion of a bottom surface of the fifth bridge pattern 212. A horizontal surface of the second active pattern AP2 exposed by the second inner spacer 245 may directly contact the second epitaxial pattern 260.

[0145] Fig. 9 A cross-sectional view of an example of a semiconductor device is shown. For convenience, the descriptions related to the previous reference will be briefly mentioned or omitted. Figures 1 to 8 Redundant or repetitive parts of the description that overlap.

[0146] Reference Fig. 9 , the first inner spacer 145 and the second inner spacer 245 may also be formed on the uppermost bridge pattern (ie, the third bridge pattern 113 and the sixth bridge pattern 213 ).

[0147] For example, the first inner spacer 145 may be formed not only between the first bridge pattern 111, the second bridge pattern 112, and the third bridge pattern 113 and between the first fin pattern 110 and the first bridge pattern 111, but also on the upper surface of the third bridge pattern 113. The first inner spacer 145 located on the upper surface of the third bridge pattern 113 will hereinafter be referred to as the uppermost first inner spacer 145. The uppermost first inner spacer 145 may be disposed between the third bridge pattern 113 and the first gate spacer 140. In some embodiments, the first liner film 118 may be disposed between the uppermost first inner spacer 145 and the first gate spacer 140.

[0148] For example, the second inner spacer 245 may be formed not only between the fourth bridge pattern 211, the fifth bridge pattern 212, and the sixth bridge pattern 213 and between the second fin pattern 210 and the fourth bridge pattern 211, but also on the upper surface of the sixth bridge pattern 213. The second inner spacer 245 located on the upper surface of the sixth bridge pattern 213 will hereinafter be referred to as the uppermost second inner spacer 245. The uppermost second inner spacer 245 may be disposed between the sixth bridge pattern 213 and the second gate spacer 240. In some embodiments, the second liner film 218 may be disposed between the uppermost second inner spacer 245 and the second gate spacer 240.

[0149] In some embodiments, the uppermost surface of the first epitaxial pattern 160 may be formed at the same height as or higher than the upper surface of the uppermost first inner spacer 145, and the uppermost surface of the second epitaxial pattern 260 may be formed at the same height as or higher than the upper surface of the uppermost second inner spacer 245. This will be described later with reference to Figure 32 to Figure 34 Give a description.

[0150] Fig.10 is a layout diagram of another example of a semiconductor device. Fig.11 Shown along Fig.10 Example cross-sectional views taken along lines A1-A1 and A2-A2. Fig.12 Shows Fig.11 For convenience, the previously referenced Figures 1 to 9 Redundant or repetitive parts of the description that overlap.

[0151] Reference Figures 10 to 12 , a first thickness TH1 of the first inner spacer 145 may be smaller than a second thickness TH2 of the second inner spacer 245 .

[0152] This is because the first width WA1 of the first active pattern AP1 forming the first inner spacer 145 is smaller than the second width WA2 of the second active pattern AP2 forming the second inner spacer 245. Fig.35 and Fig.36 A detailed description of this comparison is provided in .

[0153] In some embodiments, the first inner side surface 145i of the first inner spacer 145 opposite to the first gate structure GS1 may include a convex surface. In this case, the side surface of the portion of the first gate structure GS1 in contact with the first inner side surface 145i may include a concave surface. The first outer side surface 145o and the first inner side surface 145i of the first inner spacer 145 may have the same radius of curvature, but the present disclosure is not limited thereto. Alternatively, the first outer side surface 145o and the first inner side surface 145i may have different radii of curvature.

[0154] In some embodiments, the second inner side surface 245i of the second inner spacer 245 opposite to the second gate structure GS2 may include a convex surface. In this case, the side surface of the portion of the second gate structure GS2 in contact with the second inner side surface 245i may include a concave surface. The second outer side surface 245o and the second inner side surface 245i of the second inner spacer 245 may have the same radius of curvature, but the present disclosure is not limited thereto. Alternatively, the second outer side surface 245o and the second inner side surface 245i may have different radii of curvature.

[0155] Fig.13 An enlarged cross-sectional view of another example of a semiconductor device is shown. For convenience, the previously referenced Figures 1 to 12 Redundant or repetitive parts of the description that overlap.

[0156] Reference Fig.13 , the first inner spacer 145 may expose a portion of the horizontal plane of the first active pattern AP1, and the second inner spacer 245 may expose a portion of the horizontal plane of the second active pattern AP2. The first inner spacer 145 and the second inner spacer 245 are Figure 8 Their respective counterparts are the same, so their detailed description will be omitted.

[0157] Fig.14 An enlarged cross-sectional view of another example of a semiconductor device is shown. For convenience, the previously referenced Figures 1 to 13 Redundant or repetitive parts of the description that overlap.

[0158] Reference Fig.14 The first inner spacer 145 and the second inner spacer 245 may also be formed on the uppermost bridge pattern (ie, the third bridge pattern 113 and the sixth bridge pattern 213). Fig. 9 Their respective counterparts are similar, so their detailed description will be omitted.

[0159] In some embodiments, the uppermost surface of the first epitaxial pattern 160 may be formed lower than the upper surface of the uppermost first inner spacer 145, and the uppermost surface of the second epitaxial pattern 260 may be formed lower than the upper surface of the uppermost second inner spacer 245. This will be described later with reference to Fig.37 and Fig.38 Give a description.

[0160] Fig.15 is a layout diagram of another example of a semiconductor device. Fig.16 It is along Fig.15 For convenience, the reference to the previous reference will be briefly mentioned or omitted. Figures 1 to 14Redundant or repetitive parts of the description that overlap.

[0161] Reference Fig.15 and Fig.16 , the semiconductor device may include a channel structure CP.

[0162] The channel structure CP may include a first active pattern AP1, a second active pattern AP2, and a transition pattern TP. The transition pattern TP may connect the first active pattern AP1 and the second active pattern AP2 in the first direction X1 in which the first active pattern AP1 and the second active pattern AP2 extend. For example, the first region I and the second region II may be arranged along the first direction X1, and the substrate 100 may further include a third region III, and the third region III is placed between the first region I and the second region II. That is, the first region I, the third region III, and the second region II may be sequentially arranged along the first direction X1 and connected to each other. The transition pattern TP may be formed on the third region III and may connect the first active pattern AP1 and the second active pattern AP2.

[0163] In some embodiments, the fifth width WA3 of the transition pattern TP may increase in a direction from the first active pattern AP1 to the second active pattern AP2 .

[0164] In some embodiments, the first side surface of the transition pattern TP may be aligned with the first side surface of the first active pattern AP1 and the first side surface of the second active pattern AP2. Fig.15 As shown, the first side surface of the first active pattern AP1, the first side surface of the transition pattern TP, and the first side surface of the second active pattern AP2 may be coplanar with each other. The second surface of the transition pattern TP may extend diagonally relative to the second side surface of the first active pattern AP1 and the second side surface of the second active pattern AP2, and may connect the second side surface of the first active pattern AP1 and the second side surface of the second active pattern AP2.

[0165] The first active pattern AP1, the second active pattern AP2, and the transition pattern TP may be arranged at the same level. For example, the transition pattern TP may be arranged at the same height as the first bridge pattern 111, the second bridge pattern 112, and the third bridge pattern 113 and the fourth bridge pattern 211, the fifth bridge pattern 212, and the sixth bridge pattern 213 relative to the upper surface of the substrate 100.

[0166] In some embodiments, the separation structure DB may be formed on the third region III of the substrate and the field insulating film 105. The separation structure DB may intersect with the transition pattern TP. For example, the separation structure DB may cut the transition pattern TP by extending in the second direction Y1. In some embodiments, the bottom surface of the separation structure DB may be located at the same height as the upper surface of the substrate 100 (or the bottom surface of the first fin pattern 110 and the second fin pattern 210) or lower than the upper surface of the substrate 100 (or the bottom surface of the first fin pattern 110 and the second fin pattern 210).

[0167] The separation structure DB may include an insulating material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a combination thereof, but the present disclosure is not limited thereto. The separation structure DB may physically and electrically separate the first active pattern AP1 and the second active pattern AP2.

[0168] In some embodiments, the sixth width WG3 of the separation structure DB may be the same as the third width WG1 of the first gate structure GS1 and the fourth width WG2 of the second gate structure GS2 .

[0169] In some embodiments, the third gate spacer 340 , the third gate capping pattern 350 , the third inner spacer 345 a , the fourth inner spacer 345 b , and the third liner film 318 may be formed on the side surface of the separation structure DB.

[0170] The third gate spacer 340 may extend along the side surface of the separation structure DB. In some embodiments, the third gate spacer 340 may be formed at the same level as the first gate spacer 140 and the second gate spacer 240. The third gate capping pattern 350 may extend along the upper surface of the third gate spacer 340. In some embodiments, the third gate capping pattern 350 may be formed at the same level as the first gate capping pattern 150 and the second gate capping pattern 250.

[0171] The third inner spacer 345a may be formed on one side surface of the separation structure DB within the transition pattern TP. For example, the third inner spacer 345a may be disposed between the first epitaxial pattern 160 and the separation structure DB. In some embodiments, the third inner spacer 345a may be formed at the same level as the first inner spacer 145 and the second inner spacer 245.

[0172] The fourth inner spacer 345b may be formed on the other side surface of the separation structure DB within the transition pattern TP. For example, the fourth inner spacer 345b may be placed between the second epitaxial pattern 260 and the separation structure DB. In some embodiments, the fourth inner spacer 345b may be formed at the same level as the first inner spacer 145 and the second inner spacer 245.

[0173] The third liner film 318 may be formed on the transition pattern TP, the third inner spacer 345a, and the fourth inner spacer 345b. The third liner film 318 may be disposed between the transition pattern TP and the third gate spacer 340, between the third inner spacer 345a and the third gate spacer 340, and between the fourth inner spacer 345b and the third gate spacer 340. In some embodiments, the third liner film 318 may be formed at the same level as the first liner film 118 and the second liner film 218.

[0174] In some embodiments, the first thickness TH1 of the first inner spacer 145 may be greater than the second thickness TH2 of the second inner spacer 245, and the third thickness TH3 of the third inner spacer 345a may be greater than the fourth thickness TH4 of the fourth inner spacer 345b. This is because the fifth width WA3 of the transition pattern TP is smaller at the position where the third inner spacer 345a is formed than at the position where the fourth inner spacer 345b is formed.

[0175] Fig.15 The third thickness TH3 of the third inner spacer 345a is shown to be the same as the first thickness TH1 of the first inner spacer 145, but the present disclosure is not limited thereto. When the fifth width WA3 of the transition pattern TP is greater than the first width WA1 of the first active pattern AP1, the third thickness TH3 of the third inner spacer 345a may be less than the first thickness TH1 of the first inner spacer 145 at the position where the third inner spacer 345a is formed. In addition, Fig.15 The fourth thickness TH4 of the fourth inner spacer 345b is shown to be the same as the second thickness TH2 of the second inner spacer 245, but the present disclosure is not limited thereto. When the fifth width WA3 of the transition pattern TP is greater than the second width WA2 of the second active pattern AP2, the fourth thickness TH4 of the fourth inner spacer 345b may be greater than the second thickness TH2 of the second inner spacer 245 at a position where the fourth inner spacer 345b is formed.

[0176] Fig.17A and Fig. 17B is an exemplary cross-sectional view of a semiconductor device. For convenience, the previously referenced Figures 1 to 16 Redundant or repetitive parts of the description that overlap.

[0177] Reference Fig.17A , the separation structure DB may partially contact the first epitaxial pattern 160 and the second epitaxial pattern 260 .

[0178] For example, you can remove Fig.16The third inner spacer 345a and the fourth inner spacer 345b are removed, and a portion of the separation structure DB may fill the region where the third inner spacer 345a and the fourth inner spacer 345b have been removed. That is, the separation structure DB may include a protrusion protruding toward the first epitaxial pattern 160 and the second epitaxial pattern 260 in the transition pattern TP.

[0179] Reference Fig. 17B , the separation structure DB may include a third gate dielectric film 520 and a third gate electrode 530 .

[0180] The third gate dielectric film 520 may be stacked on the transition pattern TP. The third gate dielectric film 520 may surround the transition pattern TP. The third gate dielectric film 520 may include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high-k material having a dielectric constant greater than that of silicon oxide.

[0181] In some embodiments, the third gate dielectric film 520 may include a third interface film 522 and a third high-k film 524 sequentially stacked on the transition pattern TP.

[0182] The third gate electrode 530 may be formed on the substrate 100. The third gate electrode 530 may be stacked on the third gate dielectric film 520. That is, the third gate electrode 530 may be placed between the transition pattern TP and the third gate electrode 530. The third gate electrode 530 may be formed by, for example, a replacement process, but the present disclosure is not limited thereto. The third gate electrode 530 is shown as a single film, but the present disclosure is not limited thereto. Alternatively, the third gate electrode 530 may be formed as a stack of multiple conductive layers.

[0183] In some embodiments, the separation structure DB may be formed at the same level as the first gate structure GS1 and the second gate structure GS2 .

[0184] In some embodiments, a voltage may not be applied to the separation structure DB. That is, the separation structure DB may not provide a gate of the FET formed on the third region III. The separation structure DB may electrically separate the first active pattern AP1 and the second active pattern AP2.

[0185] Fig.18 is a layout diagram of another example of a semiconductor device. Fig.19 It is along Fig.18 For convenience, the reference to the previous reference will be briefly mentioned or omitted. Figures 1 to 17B Redundant or repetitive parts of the description that overlap.

[0186] Reference Fig.18 and Fig.19, a first thickness TH1 of the first inner spacer 145 may be smaller than a second thickness TH2 of the second inner spacer 245 , and a third thickness TH3 of the third inner spacer 345 a may be smaller than a fourth thickness TH4 of the fourth inner spacer 345 b .

[0187] This is because the fifth width WA3 of the transition pattern TP is smaller at a position where the third inner spacer 345 a is formed than at a position where the fourth inner spacer 345 b is formed.

[0188] Fig.18 The third thickness TH3 of the third inner spacer 345a is shown to be the same as the first thickness TH1 of the first inner spacer 145, but the present disclosure is not limited thereto. Optionally, when the fifth width WA3 of the transition pattern TP is less than the first width WA1 of the first active pattern AP1 at the position where the third inner spacer 345a is formed, the third thickness TH3 of the third inner spacer 345a may be greater than the first thickness TH1 of the first inner spacer 145. In addition, Fig.18 The fourth thickness TH4 of the fourth inner spacer 345b is shown to be the same as the second thickness TH2 of the second inner spacer 245, but the present disclosure is not limited thereto. Alternatively, when the fifth width WA3 of the transition pattern TP is less than the second width WA2 of the second active pattern AP2 at a position where the fourth inner spacer 345b is formed, the fourth thickness TH4 of the fourth inner spacer 345b may be greater than the second thickness TH2 of the second inner spacer 245.

[0189] Fig. 20 is a cross-sectional view of another example of a semiconductor device. For convenience, the descriptions related to the previous reference will be briefly mentioned or omitted. Figures 1 to 19 Redundant or repetitive parts of the description that overlap.

[0190] Reference Fig. 20 , the separation structure DB may be partially in contact with the first epitaxial pattern 160 and the second epitaxial pattern 260. Fig.17A are similar to their counterparts, so their detailed description will be omitted.

[0191] Fig.21 and Fig. 22 is an example layout diagram of a semiconductor device. For convenience, the previously referenced Figures 1 to 20 Redundant or repetitive parts of the description that overlap.

[0192] Reference Fig.21 and Fig. 22 , both side surfaces of the transition pattern TP may not be aligned with both sides of each of the first active patterns AP1 and both sides of each of the second active patterns AP2 .

[0193] For example, the first side surface of the transition pattern TP may connect the first side surface of each first active pattern AP1 and the first side surface of each second active pattern AP2 by extending diagonally relative to the first side surface of each first active pattern AP1 and the first side surface of each second active pattern AP2. In addition, the second side surface of the transition pattern TP may connect the second side surface of each first active pattern AP1 and the second side surface of each second active pattern AP2 by extending diagonally relative to the second side surface of each first active pattern AP1 and the second side surface of each second active pattern AP2.

[0194] In addition to the shape of the channel structure CP, Fig.21 Semiconductor devices and Fig.15 is similar to its counterpart, and Fig. 22 Semiconductor devices and Fig.18 Its counterpart is almost similar. Therefore, the Fig.21 and Fig. 22 Detailed description of the semiconductor device.

[0195] The following will refer to Figures 1 to 38 Methods of manufacturing semiconductor devices according to some embodiments of the present disclosure are described.

[0196] Figures 23 to 31 is a layout diagram or cross-sectional view showing an intermediate step of an example of a method for manufacturing a semiconductor device. For convenience, the descriptions related to the previous reference will be briefly mentioned or omitted. Figures 1 to 22 Redundant or repetitive parts of the description that overlap.

[0197] Reference Fig.23 and Fig.24 , a first active pattern AP1, a first sacrificial pattern 410, a first dummy gate structure DG1 and a first gate spacer 140 are formed on the first region I of the substrate 100, and a second active pattern AP2, a second sacrificial pattern 510, a second dummy gate structure DG2 and a second gate spacer 240 are formed on the second region II of the substrate 100.

[0198] For example, the first material film and the second material film may be alternately located on the first region I and the second region II of the substrate 100. Thereafter, a patterning process for patterning the first material film and the second material film may be performed. The patterned first material film on the first region I may form a first sacrificial pattern 410, and the patterned second material film on the first region I may form a first bridge pattern 111, a second bridge pattern 112, and a third bridge pattern 113. The patterned first material film on the second region II may form a second sacrificial pattern 510, and the patterned second material film on the second region II may form a fourth bridge pattern 211, a fifth bridge pattern 212, and a sixth bridge pattern 213.

[0199] The first sacrificial pattern 410 may have an etching selectivity with respect to the first bridge pattern 111, the second bridge pattern 112, and the third bridge pattern 113, and the second sacrificial pattern 510 may have an etching selectivity with respect to the fourth bridge pattern 211, the fifth bridge pattern 212, and the sixth bridge pattern 213. For example, the first bridge pattern 111, the second bridge pattern 112, the third bridge pattern 113 and the fourth bridge pattern 211, the fifth bridge pattern 212, and the sixth bridge pattern 213 may include Si, and the first sacrificial pattern 410 and the second sacrificial pattern 510 may include SiGe.

[0200] In some embodiments, during the patterning of the first material film and the second material film, the substrate 100 may be partially etched, and thus, the first fin pattern 110 and the second fin pattern 210 may be formed.

[0201] In some embodiments, a first liner film 118 may be formed on the first active pattern AP1 and the first sacrificial pattern 410 , and a second liner film 218 may be formed on the second active pattern AP2 and the second sacrificial pattern 510 .

[0202] Thereafter, a field insulating film 105 may be formed on the substrate. The field insulating film 105 may cover at least a portion of a side surface of the first fin pattern 110 and at least a portion of a side surface of the second fin pattern 210 .

[0203] Thereafter, a first dummy gate structure DG1 may be formed on the first active pattern AP1 and the first sacrificial pattern 410 , and a second dummy gate structure DG2 may be formed on the second active pattern AP2 and the second sacrificial pattern 510 .

[0204] The first dummy gate structure DG1 and the second dummy gate structure DG2 may extend along the upper surface of the substrate 100 and the upper surface of the field insulating film 105. The first dummy gate structure DG1 may intersect with the first active pattern AP1. For example, the first dummy gate structure DG1 may extend in the second direction Y1. The second dummy gate structure DG2 may intersect with the second active pattern AP2. For example, the second dummy gate structure DG2 may extend in the fifth direction Y2.

[0205] In some embodiments, the first dummy gate structure DG1 may include a first dummy gate dielectric film 320 and a first dummy gate electrode 330, and the second dummy gate structure DG2 may include a second dummy gate dielectric film 420 and a second dummy gate electrode 430. For example, a dielectric film and an electrode film may be sequentially stacked on the substrate 100 and the field insulating film 105. Thereafter, a first mask pattern 450 extending in the second direction Y1 may be formed on the electrode film on the first region I. In addition, a second mask pattern 550 extending in the fifth direction Y2 may be formed on the electrode film on the second region II. Thereafter, a patterning process may be performed to pattern the dielectric film and the electrode film using the first mask pattern 450 and the second mask pattern 550 as etching masks. The patterned dielectric film on the first region I may form the first dummy gate dielectric film 320, and the patterned electrode film on the first region I may form the first dummy gate electrode 330. The patterned dielectric film on the second region II may form a second dummy gate dielectric film 420 , and the patterned electrode film on the second region II may form a second dummy gate electrode 430 .

[0206] The first dummy gate structure DG1 may have an etching selectivity different from the first, second, and third bridge patterns 111, 112, and 113 and the first sacrificial pattern 410, and the second dummy gate structure DG2 may have an etching selectivity different from the fourth, fifth, and sixth bridge patterns 211, 212, and 213 and the second sacrificial pattern 510. For example, the first and second dummy gate electrodes 330 and 430 may include polysilicon (poly-Si).

[0207] Thereafter, a first gate spacer 140 and a second gate spacer 240 may be formed. The first gate spacer 140 may be formed on the substrate 100 and the field insulating film 105. The first gate spacer 140 may extend along a side surface of the first dummy gate structure DG1. The second gate spacer 240 may be formed on the substrate 100 and the field insulating film 105. The second gate spacer 240 may extend along a side surface of the second dummy gate structure DG2.

[0208] Reference Fig.25, a first recess process is performed on the first active pattern AP1 , the first sacrificial pattern 410 , the second active pattern AP2 , and the second sacrificial pattern 510 .

[0209] As a result of the first recess process, portions of the first bridge pattern 111, the second bridge pattern 112, and the third bridge pattern 113 and a portion of the first sacrificial pattern 410 on the outer side of the first dummy gate structure DG1 may be removed to form a first recess 110r. In some embodiments, an upper portion of the first fin pattern 110 may be removed during the formation of the first recess 110r.

[0210] As a result of the first recess process, portions of the fourth bridge pattern 211, the fifth bridge pattern 212, and the sixth bridge pattern 213 and a portion of the second sacrificial pattern 510 on the outer side of the second dummy gate structure DG2 may be removed to form a second recess 210r. In some embodiments, an upper portion of the second fin pattern 210 may be removed during the formation of the second recess 210r.

[0211] Reference Fig.26 , forming a first epitaxial pattern 160 and a second epitaxial pattern 260 .

[0212] The first epitaxial pattern 160 may at least partially fill Fig.25 The first epitaxial pattern 160 may be formed by an epitaxial growth method using the first active pattern AP1 as a seed layer. As a result, the first epitaxial pattern 160 connected to the first active pattern AP1 may be formed.

[0213] The second epitaxial pattern 260 may at least partially fill Fig.25 The second epitaxial pattern 260 may be formed by an epitaxial growth method using the second active pattern AP2 as a seed layer. As a result, the second epitaxial pattern 260 connected to the second active pattern AP2 may be formed.

[0214] In some embodiments, the first epitaxial pattern 160 may be grown using the first active pattern AP1 and the first sacrificial pattern 410 as seed layers, and the second epitaxial pattern 260 may be grown using the second active pattern AP2 and the second sacrificial pattern 510 as seed layers. For example, the first bridge pattern 111, the second bridge pattern 112, and the third bridge pattern 113, and the fourth bridge pattern 211, the fifth bridge pattern 212, and the sixth bridge pattern 213 may include Si, and the first sacrificial pattern 410 and the second sacrificial pattern 510 may include SiGe. In this way, a high-performance semiconductor device can be realized by preventing defects (e.g., stacking defects) in the first epitaxial pattern 160 and the second epitaxial pattern 260.

[0215] After forming the first epitaxial pattern 160 and the second epitaxial pattern 260, an etch stop film 182 and an interlayer insulating film 180 may be formed. The etch stop film 182 may cover the first epitaxial pattern 160 and the second epitaxial pattern 260. The interlayer insulating film 180 may be formed on the etch stop film 182 and may fill a space on an outer side of the first gate spacer 140 and a space on an outer side of the second gate spacer 240.

[0216] Reference Fig. 27 , remove the first dummy gate structure DG1 and the second dummy gate structure DG2.

[0217] As described above, since the first dummy gate structure DG1 has an etching selectivity different from the first bridge pattern 111, the second bridge pattern 112, the third bridge pattern 113, and the first sacrificial pattern 410, and the second dummy gate structure DG2 has an etching selectivity different from the fourth bridge pattern 211, the fifth bridge pattern 212, the sixth bridge pattern 213, and the second sacrificial pattern 510, the first dummy gate structure DG1 and the second dummy gate structure DG2 can be selectively removed. As a result of removing the first dummy gate structure DG1, the first active pattern AP1 and the first sacrificial pattern 410 can be exposed inside the first gate spacer 140. In addition, as a result of removing the second dummy gate structure DG2, the second active pattern AP2 and the second sacrificial pattern 510 can be exposed inside the second gate spacer 240.

[0218] Reference Fig.28 , the first sacrificial pattern 410 and the second sacrificial pattern 510 are removed.

[0219] As described above, since the first dummy gate structure DG1 has an etching selectivity different from that of the first sacrificial pattern 410, and the second dummy gate structure DG2 has an etching selectivity different from that of the second sacrificial pattern 510, the first sacrificial pattern 410 and the second sacrificial pattern 510 can be selectively removed. As a result of removing the first sacrificial pattern 410 and the second sacrificial pattern 510, the first bridge pattern 111, the second bridge pattern 112, and the third bridge pattern 113 spaced apart from each other on the first region I of the substrate 100 may be formed, and the fourth bridge pattern 211, the fifth bridge pattern 212, and the sixth bridge pattern 213 spaced apart from each other on the second region II of the substrate 100 may be formed.

[0220] Reference Fig.29 , a first spacer film 445 and a second spacer film 545 are formed.

[0221] The first spacer film 445 may be stacked on the first active pattern AP1, and the second spacer film 545 may be stacked on the second active pattern AP2. In some embodiments, the first spacer film 445 may not completely fill the space within the first active pattern AP1, and the second spacer film 545 may not completely fill the space within the second active pattern AP2.

[0222] The first spacer film 445 and the second spacer film 545 may include, for example, at least one of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxynitride, and combinations thereof, but the present disclosure is not limited thereto. For example, the first spacer film 445 and the second spacer film 545 may include a silicon oxide film. The first spacer film 445 and the second spacer film 545 may be formed by, for example, a chemical vapor deposition (CVD) method or an atomic layer deposition (ALD) method, but the present disclosure is not limited thereto.

[0223] In some embodiments, the fifth thickness TH5 of the first spacer film 445 on the side surface of the first epitaxial pattern 160 may be greater than the sixth thickness TH6 of the second spacer film 545 on the side surface of the second epitaxial pattern 260. This is because the first width of the first active pattern AP1 (e.g., Fig.23 WA1) is smaller than the second width of the second active pattern AP2 (eg, Fig.23 Specifically, since the space within the first active pattern AP1 is narrower than the space within the second active pattern AP2, the first spacer film 445 may experience folding.

[0224] Reference Fig.30 , forming a first inner spacer 145 and a second inner spacer 245.

[0225] For example, you can Fig.29 The first spacer film 445 and the second spacer film 545 are formed to perform the second recess process. During the second recess process, the first spacer film 445 and the second spacer film 545 may not be completely removed from the side surface of the first epitaxial pattern 160 within the first active pattern AP1 and from the side surface of the second epitaxial pattern 160 within the second active pattern AP2. This is because the space within the first active pattern AP1 and the second active pattern AP2 is narrower than the space on the outer side of the first active pattern AP1 and the outer side of the second active pattern AP2. Therefore, the first inner spacer 145 may be formed in the first active pattern AP1, and the second inner spacer 245 may be formed in the second active pattern AP2.

[0226] Since the first spacer film 445 is folded, the first thickness TH1 of the first inner spacer 145 may be greater than the second thickness TH2 of the second inner spacer 245 after the second recess process.

[0227] Reference Fig.31 , forming a first gate structure GS1 and a second gate structure GS2.

[0228] For example, the first gate dielectric film 120 and the first gate electrode 130 may be sequentially stacked on the first active pattern AP1, and the second gate dielectric film 220 and the second gate electrode 230 may be sequentially stacked on the second active pattern AP2. Thereafter, the first gate capping pattern 150 may be formed on the first gate electrode 130, and the second gate capping pattern 250 may be formed on the second gate electrode 230. In some embodiments, the first gate capping pattern 150 and the second gate capping pattern 250 may be formed after performing an etch-back process on the first gate electrode 130 and the second gate electrode 230.

[0229] Afterwards, refer again to Figure 2 , forming a first source / drain contact CA1 and a second source / drain contact CA2. In this way, it is possible to obtain Figures 1 to 5 semiconductor device.

[0230] An inner spacer between a gate (hereinafter referred to as an "inner gate") and a source / drain in a semiconductor device having a multi-bridge channel is being studied to mitigate leakage current and parasitic capacitance in the multi-bridge channel. However, due to stacking defects and other factors, the growth of the source / drain on the inner spacer poses challenges in applying stress and controlling dispersion through the source / drain, resulting in reduced performance of the semiconductor device.

[0231] However, as mentioned above, the first inner spacer 145 and the second inner spacer 245 may be formed after forming the first epitaxial pattern 160 and the second epitaxial pattern 260 provided as source / drain. In other words, the first epitaxial pattern 160 and the second epitaxial pattern 260 may be formed before forming the first inner spacer 145 and the second inner spacer 245, thereby preventing problems caused by, for example, stacking defects. As a result, a semiconductor device with improved performance can be provided.

[0232] Figure 32 to Figure 34 is a cross-sectional view showing an intermediate step of an example of a method for manufacturing a semiconductor device. For convenience, the descriptions related to the previous reference will be briefly mentioned or omitted. Figures 1 to 31 Redundant or repetitive parts of the description that overlap.

[0233] Reference Fig.23 and Fig.32, the first sacrificial pattern 410 and the second sacrificial pattern 510 may also be formed on the uppermost bridge pattern (eg, the third bridge pattern 113 and the sixth bridge pattern 213 ).

[0234] For example, the first sacrificial pattern 410 may be formed not only between the first bridge pattern 111, the second bridge pattern 112, and the third bridge pattern 113 and between the first fin pattern 110 and the first bridge pattern 111, but also on the upper surface of the third bridge pattern 113. The first sacrificial pattern 410 located on the upper surface of the third bridge pattern 113 will hereinafter be referred to as the uppermost first sacrificial pattern 410. The first sacrificial pattern 410 may be disposed between the third bridge pattern 113 and the first gate spacer 140. In some embodiments, the first liner film 118 may be disposed between the uppermost first sacrificial pattern 410 and the first gate spacer 140.

[0235] For example, the second sacrificial pattern 510 may be formed not only between the fourth bridge pattern 211, the fifth bridge pattern 212, and the sixth bridge pattern 213 and between the second fin pattern 210 and the fourth bridge pattern 211, but also on the upper surface of the sixth bridge pattern 213. The second sacrificial pattern 510 located on the upper surface of the sixth bridge pattern 213 will hereinafter be referred to as the uppermost second sacrificial pattern 510. The second sacrificial pattern 510 may be disposed between the sixth bridge pattern 213 and the second gate spacer 240. In some embodiments, the second liner film 218 may be disposed between the uppermost second sacrificial pattern 510 and the second gate spacer 240.

[0236] Reference Fig.33 , a first recess process is performed on the first active pattern AP1, the first sacrificial pattern 410, the second active pattern AP2, and the second sacrificial pattern 510. Fig.25 The first recess process is described, and thus a detailed description thereof will be omitted.

[0237] Reference Fig.34 , forming the first epitaxial pattern 160 and the second epitaxial pattern 260. Fig.26 The formation of the first epitaxial pattern 160 and the second epitaxial pattern 260 is described, and thus a detailed description thereof will be omitted.

[0238] Since the first epitaxial pattern 160 can be grown using the first active pattern AP1 and the first sacrificial pattern 410 as a seed layer, the uppermost surface of the first epitaxial pattern 160 can be formed at the same height as or higher than the upper surface of the uppermost first sacrificial pattern 410. In addition, since the second epitaxial pattern 260 can be grown using the second active pattern AP2 and the second sacrificial pattern 510 as a seed layer, the uppermost surface of the second epitaxial pattern 260 can be formed at the same height as or higher than the upper surface of the uppermost second sacrificial pattern 510.

[0239] Afterwards, you can execute Figure 2 and Figure 26 to Figure 31 In this way, it is possible to obtain Fig. 9 semiconductor device.

[0240] Fig.35 and Fig.36 is a cross-sectional view showing an intermediate step of another example of a method for manufacturing a semiconductor device. Figures 1 to 34 Redundant or repetitive parts of the description that overlap. Specifically, Fig.35 Shown in Fig.25 Intermediate steps to be performed after the step shown.

[0241] Reference Fig.35 , a third recess process is performed on the first sacrificial pattern 410 and the second sacrificial pattern 510 .

[0242] As a result of the third recess process, a portion of the exposed first sacrificial pattern 410 may be removed to form a third recess 410 r , and a portion of the exposed second sacrificial pattern 510 may be removed to form a fourth recess 510 r .

[0243] In some embodiments, the first depth DT1 of the third recess 410r may be less than the second depth DT2 of the fourth recess 510r. This is because the first width (eg, Fig.23 The width of the second active pattern AP2 is smaller than the second width of the second active pattern AP2 (eg Fig.23 Specifically, since the space within the first active pattern AP1 is narrower than the space within the second active pattern AP2, a loading phenomenon in which an etching rate of the third recess process for the first sacrificial pattern 410 is reduced may occur.

[0244] Reference Fig.36 , forming a first inner spacer 145 and a second inner spacer 245.

[0245] For example, an insulating film may be formed on the outer side surface of the first gate spacer 140 and the outer side surface of the second gate spacer 240, and the fourth recess process may be performed on the insulating film. As a result of the fourth recess process, a filling Fig.35 The first inner spacer 145 of the third recess 410r and the filling Fig.35 The second inner spacer 245 of the fourth recess 510r.

[0246] Due to the loading phenomenon, after the fourth recess process, the first thickness TH1 of the first inner spacer 145 may be smaller than the second thickness TH2 of the second inner spacer 245 .

[0247] Afterwards, you can execute Figure 2 and Figure 26 to Figure 31 In this way, it is possible to obtain Fig.10 and Fig.11 semiconductor device.

[0248] Fig.37 and Fig.38 is a cross-sectional view showing an intermediate step of an example of a method for manufacturing a semiconductor device. For convenience, the descriptions related to the previous reference will be briefly mentioned or omitted. Figures 1 to 36 Redundant or repetitive parts of the description that overlap. Specifically, Fig.37 Shown in Fig.33 Intermediate steps to be performed after the step shown.

[0249] Reference Fig.37 , a third recess process is performed on the first sacrificial pattern 410 and the second sacrificial pattern 510. Fig.35 The third recess process is described, and thus a detailed description thereof will be omitted.

[0250] Reference Fig.38 , forming a first inner spacer 145 and a second inner spacer 245. Fig.36 The formation of the first inner spacer 145 and the second inner spacer 245 is described, and thus a detailed description thereof will be omitted.

[0251] Afterwards, you can execute Figure 2 and Figure 26 to Figure 31 In this way, it is possible to obtain Fig.14 semiconductor device.

[0252] As described above, the first inner spacer 145 and the second inner spacer 245 can be provided to have varying thicknesses depending on regions. Therefore, an inner spacer having a desired thickness can be provided, and as a result, the performance of the semiconductor device can be enhanced.

[0253] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of the claimed protection, but as specific descriptions of specific embodiments that can be specific to specific inventions. Certain features described in the context of separate embodiments in this specification may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations, and even initially claimed to be protected as such, one or more features from the claimed combination may be deleted from the combination in some cases, and the claimed combination may be directed to a sub-combination or a variation of the sub-combination.

[0254] In summarizing the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the preferred embodiments without departing substantially from the principles of the present concept. Therefore, the disclosed preferred embodiments disclosed are used only in a general and descriptive sense and not for a limiting purpose.

Claims

1. A semiconductor device, include: a substrate comprising a first region and a second region; a first bridge pattern, on the first area, the first bridge pattern extending in a first direction and spaced apart from the substrate, and the first bridge pattern having a first width; a first gate structure extending in a second direction, wherein the second direction intersects the first direction, and the first bridge pattern extends through the first gate structure; a first epitaxial pattern connected to the first bridge pattern on a side surface of the first gate structure; a first inner spacer disposed between the substrate and the first bridge pattern and between the first gate structure and the first epitaxial pattern; a second bridge pattern extending in the first direction on the second area, the second bridge pattern being spaced apart from the substrate, the second bridge pattern having a second width, and the second width being greater than the first width; a second gate structure extending in the second direction, wherein the second bridge pattern extends through the second gate structure; a second epitaxial pattern connected to the second bridge pattern on a side surface of the second gate structure; and A second inner spacer is disposed between the substrate and the second bridge pattern and between the second gate structure and the second epitaxial pattern.

2. The semiconductor device according to claim 1, in, A first thickness of the first inner spacer in the first direction is greater than a second thickness of the second inner spacer in the first direction.

3. The semiconductor device according to claim 2, in, An inner side surface of the first inner spacer opposite to the first gate structure includes a concave surface, and An inner side surface of the second inner spacer opposite to the second gate structure includes a concave surface.

4. The semiconductor device according to claim 1, in, A first thickness of the first inner spacer in the first direction is smaller than a second thickness of the second inner spacer in the first direction.

5. The semiconductor device according to claim 4, in, An inner side surface of the first inner spacer opposite to the first gate structure includes a convex surface, and An inner side surface of the second inner spacer opposite to the second gate structure includes a convex surface.

6. The semiconductor device according to claim 1, in, An outer side surface of the first inner spacer opposite to the first epitaxial pattern includes a concave surface, and An outer side surface of the second inner spacer opposite to the second epitaxial pattern includes a concave surface.

7. The semiconductor device according to claim 1, in, The first epitaxial pattern is in contact with the first inner spacer, and The second epitaxial pattern is in contact with the second inner spacer.

8. The semiconductor device according to claim 1, further comprising: include: a transition pattern between the first bridge pattern and the second bridge pattern, the transition pattern connecting the first bridge pattern to the second bridge pattern, The third width of the transition pattern increases in a direction from the first bridge pattern to the second bridge pattern.

9. The semiconductor device according to claim 1, further comprising: include: a third bridge pattern, wherein the third bridge pattern is farther from the substrate than the first bridge pattern on the first region, and the third bridge pattern extends through the first gate structure in the first direction; and A fourth bridge pattern, wherein the fourth bridge pattern is farther from the substrate than the second bridge pattern on the second region, and the fourth bridge pattern extends through the second gate structure in the first direction.

10. The semiconductor device according to claim 9, in, The first inner spacer is disposed between the first bridge pattern and the third bridge pattern, and The second inner spacer is interposed between the second bridge pattern and the fourth bridge pattern.

11. The semiconductor device according to claim 1, in, The first width is 5 nm to 20 nm, and The second width is 20 nm to 100 nm.

12. A semiconductor device, include: a substrate comprising a first region and a second region; a first bridge pattern and a second bridge pattern, sequentially stacked on the first region, the first bridge pattern and the second bridge pattern extending in a first direction and spaced apart from the substrate; a first gate structure extending in a second direction, wherein the second direction intersects the first direction, and the first bridge pattern and the second bridge pattern extend through the first gate structure; a first inner spacer on a side surface of the first gate structure and between the first bridge pattern and the second bridge pattern; a first epitaxial pattern connected to the first bridge pattern and the second bridge pattern on an outer side surface of the first inner spacer; A third bridge pattern and a fourth bridge pattern are sequentially stacked on the second area, and the third bridge pattern and the fourth bridge pattern extend in the first direction; a second gate structure extending in the second direction, wherein the third bridge pattern and the fourth bridge pattern extend through the second gate structure; a second inner spacer disposed on a side surface of the second gate structure and between the third bridge pattern and the fourth bridge pattern; and a second epitaxial pattern connected to the third bridge pattern and the fourth bridge pattern on an outer side surface of the second inner spacer, wherein a first width of the first bridge pattern and the second bridge pattern in the second direction is smaller than a second width of the third bridge pattern and the fourth bridge pattern in the second direction, and Wherein, a first thickness of the first inner spacer in the first direction is greater than a second thickness of the second inner spacer in the first direction.

13. The semiconductor device according to claim 12, in, The first thickness of the first inner spacer decreases to a specific point and increases from the specific point in a direction away from the first bridge pattern.

14. The semiconductor device according to claim 12, in, An inner side surface of the first inner spacer opposite to the first gate structure includes a concave surface.

15. The semiconductor device according to claim 12, in, An outer side surface of the first inner spacer opposite to the first epitaxial pattern includes a concave surface.

16. The semiconductor device according to claim 12, in, The first gate structure includes a first gate dielectric film and a first gate electrode, and the second gate structure includes a second gate dielectric film and a second gate electrode, wherein the first gate dielectric film and the first gate electrode are sequentially stacked on the first bridge pattern and the second bridge pattern, and The second gate dielectric film and the second gate electrode are sequentially stacked on the third bridge pattern and the fourth bridge pattern.

17. The semiconductor device according to claim 16, in, The first gate dielectric film includes a first interface film and a first high-k film, the first interface film extends along a surface of the first bridge pattern and a surface of the second bridge pattern and contacts an inner side surface of the first inner spacer, and the first high-k film is disposed between the first inner spacer and the first gate electrode and between the first interface film and the first gate electrode, and The second gate dielectric film includes a second interface film and a second high-k film, the second interface film extends along the surface of the third bridge pattern and the surface of the fourth bridge pattern and contacts the inner surface of the second inner spacer, and the second high-k film is arranged between the second inner spacer and the second gate electrode and between the second interface film and the second gate electrode.

18. The semiconductor device according to claim 17, in, The first interface film includes an oxide of a material included in the first bridge pattern and the second bridge pattern, and The second interface film includes an oxide of a material included in the third bridge pattern and the fourth bridge pattern.

19. The semiconductor device according to claim 12, in, The first inner spacer and the second inner spacer include oxide.

20. The semiconductor device according to claim 12, further comprising: include: a transition pattern between the first bridge pattern and the second bridge pattern, the transition pattern connecting the first bridge pattern to the second bridge pattern, The third width of the transition pattern increases in a direction from the first bridge pattern to the second bridge pattern.

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