Semiconductor device

Abstract

A semiconductor device includes: a substrate including a standard cell region and a termination cell region at least partially surrounding the standard cell region; a first active pattern in the standard cell region; a first wiring extending in a first direction and on the first active pattern; a first gate electrode extending in the second direction and on the first active pattern; a first gate contact; a second active pattern in the termination cell region; a second wiring extending in the first direction and on the second active pattern; a second gate electrode extending in a second direction and on the second active pattern; and a second gate contact.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0077618 filed in the Korean Intellectual Property Office on June 16, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to semiconductor devices. Background Art

[0004] As semiconductor devices become more highly integrated, it may be desirable to add dummy patterns to solve various problems occurring in a process of manufacturing semiconductor devices, such as pattern uniformity, etching process margin, and degradation of mechanical properties of an interlayer insulating layer. Summary of the invention

[0005] Aspects of the present disclosure provide a semiconductor device including a gate contact disposed in a termination unit region.

[0006] However, aspects of the present disclosure are not limited to the contents set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below.

[0007] According to one aspect of the present disclosure, a semiconductor device includes: a substrate including a standard cell area and a termination cell area at least partially surrounding the standard cell area; a first active pattern in the standard cell area; a first wiring extending in a first direction and on the first active pattern; a first gate electrode extending in a second direction and on the first active pattern; a first gate contact; a second active pattern in the termination cell area; a second wiring extending in the first direction and on the second active pattern; a second gate electrode extending in the second direction and on the second active pattern; and a second gate contact.

[0008] According to another aspect of the present disclosure, a semiconductor device includes: a substrate including a standard cell area and a termination cell area at least partially surrounding the standard cell area; an active pattern in the termination cell area; a power rail extending in a first direction and on the active pattern; a wiring extending in the first direction and on the active pattern; one or more gate electrodes extending in a second direction and on the active pattern; a gate contact located between the gate electrode and the wiring; a source / drain pattern on the active pattern and on one side of the gate electrode; and a well contact located between the source / drain pattern and the power rail.

[0009] According to another aspect of the present disclosure, a semiconductor device includes: a substrate; a first active pattern on the substrate; a second active pattern on the substrate; a first gate electrode on the first active pattern and extending in a second direction; a second gate electrode on the second active pattern and extending in the second direction; a first wiring extending in the first direction and on the first active pattern; a second wiring extending in the first direction and on the second active pattern; a power rail extending in the first direction and on the substrate; a first gate contact located between the first gate electrode and the first wiring; and a second gate contact located between the second gate electrode and the second wiring, wherein the second active pattern is electrically connected to the power rail, and wherein the first wiring and the second wiring are not electrically connected to each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] These and / or other aspects will become clear and more easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a layout diagram of a semiconductor device according to an embodiment of the present disclosure;

[0012] Figure 2 yes Figure 1 An enlarged view of region R;

[0013] Figure 3 is along Figure 2 A cross-sectional view taken along line AA';

[0014] Figure 4 is along Figure 2 A cross-sectional view taken along line BB';

[0015] Figure 5 is along Figure 2 A cross-sectional view taken along line CC';

[0016] Figure 6 is along Figure 2 A cross-sectional view taken along line D-D';

[0017] Figure 7 is along Figure 2 A cross-sectional view taken along line EE';

[0018] Figure 8 is along Figure 2 A cross-sectional view taken along line F-F';

[0019] Fig. 9 is along Figure 2 A cross-sectional view taken along line G-G';

[0020] Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 and Fig.16 is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure; and

[0021] Fig.17 is a layout diagram of a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] In order to clarify the present disclosure, parts not related to the description will be omitted, and the same elements or equivalents are referred to by the same reference numerals throughout the specification. In addition, since the sizes and thicknesses of the constituent members shown in the drawings are arbitrarily given for better understanding and ease of description, the present disclosure is not limited to the sizes and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are excessively displayed for better understanding and ease of description.

[0023] It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" another element, it can be directly on the other element or there can also be an intermediate element. In contrast, when an element is referred to as being "directly above" another element, there is no intermediate element. In addition, spatial relative terms such as "below", "under", "lower", "above", "on", etc. can be used herein to facilitate description of the relationship between an element or feature shown in the accompanying drawings relative to another element or feature. It will be understood that spatial relative terms, in addition to including the orientation shown in the accompanying drawings, are also intended to include different orientations of the device in use or operation. For example, if the device in the accompanying drawings is flipped, the element described as being "below" or "below" other elements or features will be oriented "above" other elements or features. Therefore, the term "below..." can include both the orientation above and below. The device can be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptors used in this article can be interpreted accordingly.

[0024] In addition, unless explicitly described to the contrary, the word "include" and variants such as "contain" or "include" will be understood to mean including the elements described, but not excluding any other elements. As used herein, the phrase "at least one of A, B and C" refers to the logic (A or B or C) using the non-exclusive logic "or", and should not be interpreted as indicating "at least one of A, at least one of B and at least one of C". As used herein, the singular forms "one", "one" and "said" are intended to also include plural forms, unless the context clearly gives the opposite indication. It will also be understood that the terms "include", "have" and / or "include" are used in this article to indicate the presence of stated features, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or combinations thereof. The term "and / or" includes any and all combinations of one or more items listed in association. The term "connection" can be used in this article to refer to physical and / or electrical connections, and can refer to direct or indirect physical and / or electrical connections.

[0025] Figure 1 is a layout diagram of a semiconductor device according to an embodiment.

[0026] Reference Figure 1 , the semiconductor device according to the embodiment may include a standard cell region 12 and a termination cell region 14 .

[0027] One or more standard cells are arranged in the standard cell area 12. Each standard cell may refer to a cell of an integrated circuit whose layout size meets a predetermined rule. The height of the standard cell may be constant, and the width of the standard cell may be different. The standard cell may include a single height cell arranged in a row and a multi-height cell corresponding to multiple rows. Each standard cell may include an input pin and an output pin, and may process an input signal received by the input pin and output an output signal by an output pin. For example, the standard cell may include basic cells such as AND, OR, NOR, and inverters, complex cells such as OR / AND / INVERTER (OAI) and AND / OR / INVERTER (AOI), and storage elements such as master-slave triggers and latches.

[0028] The termination cell region 14 is arranged at the edge of the standard cell region 12, so that the termination cell region 14 at least partially surrounds the standard cell region 12. One or more termination cells are arranged in the termination cell region 14. The termination cell may refer to a cell arranged around a standard cell to reduce the proximity effect from a nearby cell. The termination cell may refer to a termination capping cell, a start cell or a dummy cell.

[0029] For example, the termination unit region 14 may be disposed at the left and right edges of the standard cell region 12 along the first direction D1. The termination unit may be disposed at the left and right edges of the standard cell region 12 along the first direction D1, and may be disposed continuously along the second direction D2. As another example, the termination unit region 14 may also be disposed at the upper and lower edges of the standard cell region 12 along the second direction D2, and may surround the standard cell region 12. The termination unit may also be disposed at the upper and lower edges of the standard cell region 12 along the second direction D2, and may be disposed continuously along the first direction D1.

[0030] Figure 2 yes Figure 1 Magnified view of region R. Figure 3 is along Figure 2 A cross-sectional view taken along line AA'. Figure 4 is along Figure 2 A cross-sectional view taken along line BB'. Figure 5 is along Figure 2 A cross-sectional view taken along line CC'. Figure 6 is along Figure 2 A cross-sectional view taken along line D-D'. Figure 7 is along Figure 2 A cross-sectional view taken along line EE'. Figure 8 is along Figure 2 A cross-sectional view taken along line F-F'. Fig. 9 is along Figure 2 A cross-sectional view taken along line G-G'.

[0031] Reference Figures 1 to 7 According to the embodiment, the semiconductor device includes: a substrate 100; active patterns AP1 and AP2; dummy active patterns AP3 and AP4; a field insulating layer 105; a gate structure GS; source / drain patterns 150, 250, 351, 352, 451 and 452; a source / drain etch stop layer 156; element isolation structures RC and FC; first to third interlayer insulating layers 190, 191 and 192; a first power rail PR1; a second power rail PR2; a first wiring M11; a second wiring M12; source / drain contacts CA1 and CA2; well contacts WC1 and WC2; and gate contacts CB1 and CB2.

[0032] The substrate 100 includes an upper surface and a lower surface opposite to each other in the third direction D3. The substrate 100 may be made of a semiconductor material or may include a semiconductor material. The substrate 100 may be a silicon substrate or a silicon-on-insulator (SOI) substrate. Alternatively, the substrate 100 may include, but is not limited to, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0033] Here, the first direction D1 and the second direction D2 may be directions parallel to the upper surface of the substrate 100. The first direction D1 and the second direction D2 may cross each other. The third direction D3 may be a direction perpendicular to the upper surface of the substrate 100. The third direction D3 may cross the first direction D1 and the second direction D2. The right side and the left side are defined based on the first direction D1, and the upper side and the lower side are defined based on the third direction D3.

[0034] The active patterns AP1 to AP4 are disposed on the substrate 100. For example, the active patterns AP1 to AP4 may be disposed on an upper surface of the substrate 100. Each of the active patterns AP1 to AP4 may extend along the first direction D1. The active patterns AP1 to AP4 may each be arranged along the second direction D2.

[0035] The first active pattern AP1 and the second active pattern AP2 are disposed in the standard cell region 12. The third active pattern AP3 and the fourth active pattern AP4 are disposed in the termination cell region 14.

[0036] The first active pattern AP1 and the third active pattern AP3 may be spaced apart from each other in the first direction D1. The second active pattern AP2 and the fourth active pattern AP4 may be spaced apart from each other in the first direction D1. The first active pattern AP1 and the third active pattern AP3 may be adjacent to each first power rail PR1, and the second active pattern AP2 and the fourth active pattern AP4 may be adjacent to each second power rail PR2. The first active pattern AP1 and the third active pattern AP3 and the second active pattern AP2 and the fourth active pattern AP4 may be disposed between adjacent first power rails PR1 and second power rails PR2.

[0037] The first active pattern AP1 and the third active pattern AP3 are disposed in a region where transistors of the same conductivity type are formed. The second active pattern AP2 and the fourth active pattern AP4 are disposed in a region where transistors of the same conductivity type are formed.

[0038] For example, the first active pattern AP1 and the third active pattern AP3 may be disposed in a region where a P-type transistor is formed. The second active pattern AP2 and the fourth active pattern AP4 may be disposed in a region where an N-type transistor is formed.

[0039] Each third active pattern AP3 includes an active pattern AP31 and an active pattern AP32. Each fourth active pattern AP4 includes an active pattern AP41 and an active pattern AP42. The active patterns AP31, AP32, AP41, AP42 may also be referred to as "active sub-patterns AP31, AP32, AP41, AP42".

[0040] Each of the active patterns AP1 to AP4 may be a multi-channel active pattern. For example, each of the first active patterns AP1 may include a first bottom pattern BP1 and a plurality of first sheet patterns NS1. Each of the second active patterns AP2 may include a second bottom pattern BP2 and a plurality of second sheet patterns NS2. The active pattern AP31 may include a bottom pattern BP31 and a plurality of sheet patterns NS31. The active pattern AP32 may include a bottom pattern BP32 and a plurality of sheet patterns NS32. The active pattern AP41 may include a bottom pattern BP41 and a plurality of sheet patterns NS41. In the semiconductor device according to the embodiment, the first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4 may each be an active pattern including nanosheets or nanowires.

[0041] The bottom patterns BP1, BP2, BP31, BP32, BP41, and BP42 may extend from the substrate 100. For example, the bottom patterns BP1, BP2, BP31, BP32, BP41, and BP42 may extend from the upper surface of the substrate 100. Each of the bottom patterns BP1, BP2, BP31, BP32, BP41, and BP42 may be a fin-shaped pattern.

[0042] The bottom patterns BP1, BP2, BP31, BP32, BP41, and BP42 may extend in the first direction D1. The first bottom pattern BP1 may be spaced apart from the bottom pattern BP31 and the bottom pattern BP32 in the first direction D1. The second bottom pattern BP2 may be spaced apart from the bottom pattern BP41 and the bottom pattern BP42 in the first direction D1. The first bottom pattern BP1 may be spaced apart from the second bottom pattern BP2 in the second direction D2. The bottom patterns BP31 and BP32 may be spaced apart from the bottom pattern BP41 and the bottom pattern BP42 in the second direction D2.

[0043] The bottom patterns BP1, BP2, BP31, BP32, BP41, and BP42 may be separated by the trench T. For example, the upper surface of the substrate 100 may be the bottom surface of the trench T. Each of the bottom patterns BP1, BP2, BP31, BP32, BP41, and BP42 includes a sidewall extending in the first direction D1. The sidewall of each of the bottom patterns BP1, BP2, BP31, BP32, BP41, and BP42 may be defined by the trench T.

[0044] The bottom patterns BP1, BP2, BP31, BP32, BP41, and BP42 may be formed by partially etching the substrate 100, or may include an epitaxial layer grown from the substrate 100. The bottom patterns BP1, BP2, BP31, BP32, BP41, and BP42 may include silicon or germanium as an elemental semiconductor material. In addition, the bottom patterns BP1, BP2, BP31, BP32, BP41, and BP42 may include a compound semiconductor, such as a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0045] The IV-IV compound semiconductor may be, for example, a binary or ternary compound including two or more of carbon (C), silicon (Si), germanium (Ge) and tin (Sn), or may be a compound obtained by doping the binary or ternary compound with a Group IV element.

[0046] The III-V compound semiconductor may be, for example, a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In) as III-group elements with one of phosphorus (P), arsenic (As), and antimony (Sb) as V-group elements.

[0047] The first sheet pattern NS1 may be disposed on the first bottom pattern BP1. The first sheet pattern NS1 may be spaced apart from the first bottom pattern BP1 in the third direction D3. The second sheet pattern NS2 may be disposed on the second bottom pattern BP2. The second sheet pattern NS2 may be spaced apart from the second bottom pattern BP2 in the third direction D3. The sheet pattern NS31 may be disposed on the bottom pattern BP31. The sheet pattern NS31 may be spaced apart from the bottom pattern BP31 in the third direction D3. The sheet pattern NS32 may be disposed on the bottom pattern BP32. The sheet pattern NS32 may be spaced apart from the bottom pattern BP32 in the third direction D3. The sheet pattern NS41 may be disposed on the bottom pattern BP41. The sheet pattern NS41 may be spaced apart from the bottom pattern BP41 in the third direction D3. The sheet pattern NS42 may be disposed on the bottom pattern BP42. The sheet pattern NS42 may be spaced apart from the bottom pattern BP42 in the third direction D3.

[0048] Although each of the sheet patterns NS1 , NS2 , NS31 , NS32 , NS41 , and NS42 is disposed in the third direction D3 in the drawing, this is merely an example used for convenience of description, and the present disclosure is not limited to the example.

[0049] In the case of the first sheet pattern NS1, for example, the width of each first sheet pattern NS1 in the second direction D2 may be increased or decreased in proportion to the width of the first bottom pattern BP1 in the second direction D2. Although the widths of the first sheet pattern NS1 on the first bottom pattern BP1 in the second direction D2 are the same in the drawings, the present disclosure is not limited thereto. The description of the first sheet pattern NS1 may also be applied to the second sheet pattern NS2, sheet pattern NS31, sheet pattern NS32, sheet pattern NS41, and sheet pattern NS42.

[0050] Each of the sheet patterns NS1 , NS2 , NS31 , NS32 , NS41 , and NS42 may include one of an elemental semiconductor material such as silicon or germanium, a group IV-IV compound semiconductor, and a group III-V compound semiconductor.

[0051] The field insulation layer 105 may be disposed on the substrate 100. For example, the field insulation layer 105 may be disposed on an upper surface of the substrate 100. The field insulation layer 105 may fill / be located in a space defined by at least a portion of each trench T.

[0052] The field insulating layer 105 may be disposed on the substrate 100 between the bottom patterns BP1, BP2, BP31, BP32, BP41, and BP42. For example, the field insulating layer 105 may completely cover or overlap the sidewall of each of the bottom patterns BP1, BP2, BP31, BP32, BP41, and BP42. Different from the accompanying drawings, and as another example, the field insulating layer 105 may partially cover or overlap the sidewall of each of the bottom patterns BP1, BP2, BP31, BP32, BP41, and BP42. In this case, a portion of each of the bottom patterns BP1, BP2, BP31, BP32, BP41, and BP42 may extend in the third direction D3 to above the upper surface of the field insulating layer 105.

[0053] The field insulating layer 105 does not cover or overlap an upper surface of each of the bottom patterns BP1 , BP2 , BP31 , BP32 , BP41 , and BP42 .

[0054] The field insulating layer 105 may include, for example, an oxide layer, a nitride layer, an oxynitride layer, or a combination thereof. Although the field insulating layer 105 is illustrated as a single layer, this is merely an example used for convenience of description, and the present disclosure is not limited to this example.

[0055] The gate structure GS is disposed on the upper surface of the substrate 100. The gate structure GS may extend in the second direction D2. The gate structures GS may be spaced apart from each other in the first direction D1.

[0056] The gate structure GS may overlap the bottom patterns BP1, BP2, BP31, BP32, BP41, and BP42. The gate structure GS may overlap the sheet patterns NS1, NS2, NS31, NS32, NS41, and NS42.

[0057] Although the gate structures GS extend in the second direction D2 over different active patterns AP1 to AP4 in the drawings, the present disclosure is not limited thereto. For example, some gate structures GS may be divided into two parts by a gate isolation structure on the field insulating layer 105 and may be disposed on the first active pattern AP1 and the second active pattern AP2.

[0058] Each gate structure GS in the standard cell region 12 may include, for example, a first gate electrode 120, a gate insulating layer 130, a gate spacer 140, and a gate capping pattern 145. Each gate structure GS in the termination cell region 14 may include, for example, a second gate electrode 220, a gate insulating layer 130, a gate spacer 140, and a gate capping pattern 145. The first gate electrode 120 may be disposed in the standard cell region 12, and the second gate electrode 220 may be disposed in the termination cell region 14. The gate structure GS disposed in the termination cell region 14 is a dummy gate structure, and the second gate electrode 220 disposed in the termination cell region 14 is a dummy gate electrode.

[0059] Each gate structure GS may include a plurality of inner gate structures INT_GS formed between sheet patterns NS1, NS2, NS31, NS32, NS41 or NS42 adjacent to each other along the third direction D3 and between the bottom pattern BP1, BP2, BP31, BP32, BP41 or BP42 and the sheet pattern NS1, NS2, NS31, NS32, NS41 or NS42.

[0060] For example, in the case of the first active pattern AP1, the inner gate structure INT_GS can be formed between the upper surface of the first bottom pattern BP1 and the lower surface of the first sheet pattern NS1 and between the upper surface of the first sheet pattern NS1 and the lower surface of the first sheet pattern NS1, and the first sheet patterns NS1 face each other in the third direction D3.

[0061] The number of the inner gate structures INT_GS may be equal to the number of the first sheet pattern NS1 The inner gate structure INT_GS contacts an upper surface of the first bottom pattern BP1 , an upper surface of the first sheet pattern NS1 , and a lower surface of the first sheet pattern NS1 .

[0062] Each inner gate structure INT_GS in the standard cell region 12 includes a first gate electrode 120 and a gate insulating layer 130 . The first gate electrode 120 is disposed between adjacent first sheet patterns NS1 or between the first bottom pattern BP1 and the first sheet pattern NS1 .

[0063] In the case of the active pattern AP31 , for example, each inner gate structure INT_GS in the termination cell region 14 includes a second gate electrode 220 disposed between adjacent sheet patterns NS31 or between the bottom pattern BP31 and the sheet pattern NS31 , and a gate insulating layer 130 .

[0064] The first gate electrode 120 may be disposed on the bottom patterns BP1 and BP2. The first gate electrode 120 may cross the bottom patterns BP1 and BP2. The first gate electrode 120 may cover or overlap the sheet patterns NS1 and NS2. The second gate electrode 220 may be disposed on the bottom patterns BP31, BP32, BP41, and BP42. The second gate electrode 220 may cross the bottom patterns BP31, BP32, BP41, and BP42. The second gate electrode 220 may cover or overlap the sheet patterns NS31, NS32, NS41, and NS42.

[0065] The gate electrodes 120 and 220 may include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride.

[0066] The gate insulating layer 130 may extend along the upper surface of the field insulating layer 105 and the upper surfaces of the bottom patterns BP1, BP2, BP31, BP32, BP41, and BP42. The gate insulating layer 130 may cover or overlap the sheet patterns NS1, NS2, NS31, NS32, NS41, and NS42. The gate insulating layer 130 may be disposed along the periphery of the sheet patterns NS1, NS2, NS31, NS32, NS41, and NS42. The gate electrodes 120 and 220 are disposed on the gate insulating layer 130. The gate insulating layer 130 is disposed between the gate electrodes 120 and 220 and the sheet patterns NS1, NS2, NS31, NS32, NS41, and NS42.

[0067] The gate insulating layer 130 may include silicon oxide, silicon oxynitride, silicon nitride, or a high-k material having a higher dielectric constant than silicon oxide.

[0068] Although the gate insulating layer 130 is shown as a single layer, this is merely an example used for ease of description, and the present disclosure is not limited to this example. The gate insulating layer 130 may also include a plurality of layers. The gate insulating layer 130 may include an interface layer disposed between the active patterns AP1 to AP4 and the gate electrodes 120 and 220, and a high-k insulating layer. For example, the interface layer may not be formed along the contour of the upper surface of the field insulating layer 105.

[0069] The semiconductor device according to the embodiment may include a negative capacitance field effect transistor (FET) using a negative capacitor.For example, the gate insulating layer 130 may include a ferroelectric material layer having ferroelectric characteristics and a paraelectric material layer having paraelectric characteristics.

[0070] The ferroelectric material layer may have a negative capacitance, and the paraelectric material layer may have a positive capacitance. For example, when two or more capacitors are connected in series and the capacitance of each capacitor has a positive value, the total capacitance is reduced compared to the capacitance of each individual capacitor. On the other hand, when at least one of the capacitances of the two or more capacitors connected in series has a negative value, the total capacitance may have a positive value and may be greater than the absolute value of each individual capacitance.

[0071] When a ferroelectric material layer having negative capacitance and a paraelectric material layer having positive capacitance are connected in series, the total capacitance value of the ferroelectric material layer and the paraelectric material layer connected in series can be increased. As a result of the increase in the total capacitance value, a transistor including the ferroelectric material layer can have a subthreshold swing (SS) of less than 60mV / decade at room temperature.

[0072] The ferroelectric material layer may have ferroelectric properties. The ferroelectric material layer may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, for example, hafnium zirconium oxide may be a material obtained by doping hafnium oxide with zirconium (Zr). As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0073] The ferroelectric material layer may further include a dopant of doping. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr) and tin (Sn). The type of dopant included in the ferroelectric material layer may vary depending on the type of ferroelectric material included in the ferroelectric material layer.

[0074] When the ferroelectric material layer includes hafnium oxide, the dopant included in the ferroelectric material layer may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0075] When the dopant is aluminum (Al), the ferroelectric material layer may include 3 atomic % (at %) to 8 at % of aluminum. Here, the ratio of the dopant may be a ratio of aluminum to the sum of hafnium and aluminum.

[0076] When the dopant is silicon (Si), the ferroelectric material layer may include 2at% to 10at% silicon. When the dopant is yttrium (Y), the ferroelectric material layer may include 2at% to 10at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material layer may include 1at% to 7at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material layer may contain 50at% to 80at% zirconium.

[0077] The paraelectric material layer may have paraelectric properties. The paraelectric material layer may include, for example, at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material layer may include, for example, at least one of hafnium oxide, zirconium oxide, and aluminum oxide, but is not limited thereto.

[0078] The ferroelectric material layer and the paraelectric material layer may include the same material. Although the ferroelectric material layer has ferroelectric properties, the paraelectric material layer may not have ferroelectric properties. For example, when the ferroelectric material layer and the paraelectric material layer include hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material layer is different from the crystal structure of the hafnium oxide included in the paraelectric material layer.

[0079] The ferroelectric material layer may have a thickness that has ferroelectric properties. The thickness of the ferroelectric material layer may be, but is not limited to, 0.5 nm to 10 nm. Each ferroelectric material may have a different critical thickness that exhibits ferroelectric properties. Therefore, the thickness of the ferroelectric material layer may vary depending on the ferroelectric material.

[0080] As an example, the gate insulating layer 130 may include a ferroelectric material layer. As another example, the gate insulating layer 130 may include a plurality of ferroelectric material layers spaced apart from each other. The gate insulating layer 130 may have a structure in which a plurality of ferroelectric material layers and a plurality of paraelectric material layers are alternately stacked.

[0081] The gate spacer 140 may be disposed on the sidewalls of the gate electrodes 120 and 220. For example, the gate spacer 140 may be disposed on the long sidewalls of each gate electrode. The gate spacer 140 may not be formed between the bottom patterns BP1, BP2, BP31, BP32, BP41, and BP42 and the sheet patterns NS1, NS2, NS31, NS32, NS41, and NS42 and between the sheet patterns NS1, NS2, NS31, NS32, NS41, and NS42 adjacent in the third direction D3.

[0082] The gate spacer 140 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof. Although each gate spacer 140 is shown as a single layer, this is merely an example used for ease of description, and the present disclosure is not limited to this example.

[0083] The gate capping pattern 145 may be disposed on the gate electrodes 120 and 220 . An upper surface of the gate capping pattern 145 may be an upper surface of each gate structure GS. In a modification, the gate capping pattern 145 may be disposed between the gate spacers 140 .

[0084] The gate capping pattern 145 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and combinations thereof.

[0085] Source / drain patterns 150, 250, 351, 352, 451, and 452 may be disposed on an upper surface of the substrate 100. The source / drain patterns 150 and 250 may be disposed on a side surface of the first gate electrode 120. For example, the source / drain patterns 150 and 250 may contact the inner gate structure INT_GS in the standard cell region 12. The source / drain patterns 351, 352, 451, and 452 may be disposed on a side surface of the second gate electrode 220. For example, the source / drain patterns 351, 352, 451, and 452 may contact the inner gate structure INT_GS in the termination cell region 14.

[0086] The first source / drain pattern 150 may be disposed on the first bottom pattern BP1. The first source / drain pattern 150 may contact each of the first active patterns AP1. The first source / drain pattern 150 may contact the first sheet pattern NS1. The first source / drain pattern 150 is connected to the first sheet pattern NS1 and the first bottom pattern BP1.

[0087] The second source / drain pattern 250 may be disposed on the second bottom pattern BP2. The second source / drain pattern 250 may contact each second active pattern AP2. The second source / drain pattern 250 may contact the second sheet pattern NS2. The second source / drain pattern 250 is connected to the second sheet pattern NS2 and the second bottom pattern BP2.

[0088] The source / drain pattern 351 may be disposed on the bottom pattern BP31. The source / drain pattern 351 may contact the active pattern AP31. The source / drain pattern 351 may contact the sheet pattern NS31. The source / drain pattern 351 is connected to the sheet pattern NS31 and the bottom pattern BP31. The source / drain pattern 352 may be disposed on the bottom pattern BP32. The source / drain pattern 352 may contact the active pattern AP32. The source / drain pattern 352 may contact the sheet pattern NS32. The source / drain pattern 352 is connected to the sheet pattern NS32 and the bottom pattern BP32.

[0089] The source / drain pattern 451 may be disposed on the bottom pattern BP41. The source / drain pattern 451 may contact the active pattern AP41. The source / drain pattern 451 may contact the sheet pattern NS41. The source / drain pattern 451 is connected to the sheet pattern NS41 and the bottom pattern BP41. The source / drain pattern 452 may be disposed on the bottom pattern BP42. The source / drain pattern 452 may contact the active pattern AP42. The source / drain pattern 452 may contact the sheet pattern NS42. The source / drain pattern 452 is connected to the sheet pattern NS42 and the bottom pattern BP42.

[0090] Although not shown, as another example, an internal spacer may also be disposed between the inner gate structure INT_GS and the source / drain patterns 150, 250, 351, 352, 451, and 452. In this case, the source / drain patterns 150, 250, 351, 352, 451, and 452 do not contact the gate insulating layer 130 included in each inner gate structure INT_GS.

[0091] The source / drain patterns 150 , 250 , 351 , 352 , 451 , and 452 may each be included in a source / drain region of a transistor using the sheet pattern NS1 , NS2 , NS31 , NS32 , NS41 , or NS42 as a channel region.

[0092] Each of the source / drain patterns 150, 250, 351, 352, 451, and 452 may include an epitaxial pattern. Each of the source / drain patterns 150, 250, 351, 352, 451, and 452 may include a semiconductor material.

[0093] The first source / drain pattern 150, the source / drain pattern 351, and the source / drain pattern 352 may include a p-type dopant. The p-type dopant may include, but is not limited to, at least one of boron (B) and gallium (Ga). The second source / drain pattern 250, the source / drain pattern 451, and the source / drain pattern 452 may include an n-type dopant. The n-type dopant may include, but is not limited to, at least one of phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi).

[0094] The source / drain etch stop layer 156 may extend along outer walls of the gate spacer 140 and sidewalls of the source / drain patterns 150 , 250 , 351 , 352 , 451 , and 452 . The source / drain etch stop layer 156 may extend along an upper surface of the field insulation layer 105 .

[0095] The source / drain etch stop layer 156 may not extend along the sidewalls of the gate capping pattern 145. In a variation, the source / drain etch stop layer 156 may also extend along the sidewalls of the gate capping pattern 145.

[0096] The source / drain etch stop layer 156 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof.

[0097] The element isolation structures RC and FC are disposed on the substrate 100. The element isolation structures RC and FC may be disposed on the upper surface of the substrate 100. The element isolation structures RC and FC may extend in the second direction D2. The element isolation structures RC and FC may separate adjacent cells.

[0098] The first element isolation structure RC may overlap the gate electrodes 120 and 220. The first element isolation structure RC may be disposed between the source / drain patterns 150, 250, 351, 352, 451, and 452 adjacent to each other in the first direction D1. The second element isolation structure FC may overlap a pair of gate electrodes 120 and 220 adjacent to each other in the second direction D2. The width of the second element isolation structure FC in the first direction D1 may be greater than the width of each of the first element isolation structures RC in the first direction D1.

[0099] The element isolation structures RC and FC may be disposed between the first active pattern AP1 and the third active pattern AP3. The element isolation structures RC and FC may be disposed between the second active pattern AP2 and the fourth active pattern AP4. The element isolation structures RC and FC may be disposed between the active patterns AP1, AP2, AP3, or AP4 adjacent to each other along the first direction D1. For example, the first element isolation structure RC may be disposed between the first active patterns AP1 adjacent to each other along the first direction D1.

[0100] The element isolation structures RC and FC may separate the first bottom pattern BP1 from the third bottom pattern BP3. The element isolation structures RC and FC may separate the second bottom pattern BP2 from the fourth bottom pattern BP4. The element isolation structures RC and FC may be disposed between the bottom patterns BP1, BP2, BP31, BP32, BP41, or BP42 adjacent to each other along the first direction D1. For example, the first element isolation structure RC may be disposed between the first bottom patterns BP1 adjacent to each other along the first direction D1.

[0101] From the upper surface of the substrate 100, the upper surfaces of the element isolation structures RC and FC may be at the same height as the upper surface of the gate capping pattern 145 (i.e., the upper surfaces of the element isolation structures RC and FC and the upper surface of the gate capping pattern 145 extend the same distance from the upper surface of the substrate 100). In a variation, from the upper surface of the substrate 100, the upper surfaces of the element isolation structures RC and FC may also be at a higher height than the upper surface of the gate capping pattern 145 (i.e., the upper surfaces of the element isolation structures RC and FC extend a greater distance from the upper surface of the substrate 100 than the upper surface of the gate capping pattern 145).

[0102] The element isolation structures RC and FC may include an insulating material. Although each of the element isolation structures RC and FC is illustrated as a single layer, the present disclosure is not limited thereto.

[0103] For example, the insulating residual pattern may be disposed between the element isolation structures RC and FC and the source / drain patterns 150, 250, 350, and 450. The insulating residual pattern may include the same material as the gate insulating layer 130.

[0104] The first interlayer insulating layer 190 is disposed on the upper surface of the substrate 100. The first interlayer insulating layer 190 may be disposed on the source / drain patterns 150, 250, 351, 352, 451 and 452. The first interlayer insulating layer 190 may be disposed on the element isolation structures RC and FC. The first interlayer insulating layer 190 may not cover or overlap the upper surface of the gate capping pattern 145. The second interlayer insulating layer 191 is disposed on the first interlayer insulating layer 190. The second interlayer insulating layer 191 may not cover or overlap the upper surfaces of the gate contacts CB1 and CB2. The third interlayer insulating layer 192 is disposed on the second interlayer insulating layer 191.

[0105] Each of the first to third interlayer insulating layers 190 to 192 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material.

[0106] The first power rail PR1, the second power rail PR2, the first wiring M11, and the second wiring M12 may be disposed in the third interlayer insulating layer 192. Each of the first power rail PR1, the second power rail PR2, the first wiring M11, and the second wiring M12 may extend in the first direction D1. The first power rail PR1, the second power rail PR2, the first wiring M11, and the second wiring M12 are disposed at the same metal layer.

[0107] The first power rail PR1 and the second power rail PR2 may be alternately arranged along the second direction D2. The first power rail PR1 may provide a first voltage, and the second power rail PR2 may provide a second voltage different from the first voltage VDD. For example, the first voltage may be a positive (+) voltage, and the second voltage may be a ground (GND) voltage or a negative (-) voltage.

[0108] The first wiring M11 is disposed in the standard cell region 12, and the second wiring M12 is disposed in the termination cell region 14. The first wiring M11 does not extend to the termination cell region 14. The first wiring M11 and the second wiring M12 are separated from each other.

[0109] The first and second wirings M11 and M12 are disposed at the same height from the upper surface of the substrate 100. The first and second wirings M11 and M12 may be, for example, signal lines that transmit signals. The first and second wirings M11 and M12 may be arranged between the first and second power rails PR1 and PR2 along the second direction D2.

[0110] Source / drain contacts CA1 and CA2 and well contacts WC1 and WC2 are disposed on the upper surface of the substrate 100. The first source / drain contact CA1 is disposed in the standard cell region 12. The second source / drain contact CA2 is disposed in the termination cell region 14. The well contacts WC1 and WC2 may be disposed in the termination cell region 14.

[0111] The first source / drain contact CA1 may be disposed on the first source / drain pattern 150 and the second source / drain pattern 250. The first source / drain contact CA1 may be electrically connected to the first source / drain pattern 150 and the second source / drain pattern 250, respectively.

[0112] The second source / drain contact CA2 may be disposed on the source / drain pattern 352 and the source / drain pattern 452. The second source / drain contact CA2 may be electrically connected to the source / drain pattern 352 and the source / drain pattern 452, respectively.

[0113] The first well contact WC1 may be disposed on the source / drain pattern 351. The first well contact WC1 may be electrically connected to the source / drain pattern 351. The first well contact WC1 may be connected to each first power rail PR1 through a first via V01. The source / drain pattern 351 may receive a first voltage through the first well contact WC1 and the first via V01.

[0114] The second well contact WC2 may be disposed on the source / drain pattern 451. The second well contact WC2 may be electrically connected to the source / drain pattern 451. The second well contact WC2 may be connected to each second power rail PR2 through a second via V02. The source / drain pattern 451 may receive a second voltage through the second well contact WC2 and the second via V02.

[0115] Each of the source / drain contacts CA1 and CA2 and the well contacts WC1 and WC2 may include a first barrier layer 171 and a first filling layer 172 .

[0116] The contact silicide layer 155 can be arranged between the first source / drain contact CA1 and the first source / drain pattern 150, between the first source / drain contact CA1 and the second source / drain pattern 250, between the second source / drain contact CA2 and the source / drain pattern 352, between the second source / drain contact CA2 and the source / drain pattern 452, between the first well contact WC1 and the source / drain pattern 351, and between the second well contact WC2 and the source / drain pattern 451.

[0117] The first gate contact CB1 is disposed in the standard cell region 12 , and the second gate contact CB2 is disposed in the termination cell region 14 .

[0118] The first gate contact CB1 is disposed on the first gate electrode 120. Each first gate contact CB1 may extend into the gate capping pattern 145. The first gate contact CB1 is connected to the first gate electrode 120. The first gate contact CB1 may be connected to the first wiring M11. The first gate contact CB1 may contact the first wiring M11 and the first gate electrode 120.

[0119] The second gate contact CB2 is disposed on the second gate electrode 220. Each second gate contact CB2 may extend into the gate capping pattern 145. The second gate contact CB2 is connected to the second gate electrode 220. The second gate contact CB2 may be connected to the second wiring M12. The second gate contact CB2 may contact the second wiring M12 and the second gate electrode 220. The second gate contact CB2 is a dummy gate contact. The second gate contact CB2 is not electrically connected to the first gate contact CB1. The signal provided to the first gate electrode 120 is not provided to the second gate electrode 220. For example, the first wiring M11 connected to the first gate contact CB1 may be separated from the second wiring M12 connected to the second gate contact CB2. The first wiring M11 connected to the standard cell area 12 may not be connected to the second wiring M12 connected to the termination cell area 14.

[0120] The second gate contact CB2 may be disposed on the active pattern AP31 on which the first well contact WC1 is disposed and the active pattern AP41 on which the second well contact WC2 is disposed. The second gate contact CB2 may be disposed between the active pattern AP31 and the second wiring M12 and between the active pattern AP41 and the second wiring M12.

[0121] A plurality of second wirings M12 are provided between the first power rail PR1 and the second power rail PR2 adjacent to each other. The second wirings M12 are arranged along the second direction D2. The second gate contact CB2 is provided on the second wiring M12 adjacent to each first power rail PR1. The second gate contact CB2 is provided on the second wiring M12 adjacent to each second power rail PR2. The second gate contact CB2 is provided on the second wiring M12 closest to each first power rail PR1 and the second wiring M12 closest to each second power rail PR2. That is, the second gate contact CB2 is not provided on the second wiring M12 not closest to each first power rail PR1 and the second wiring M12 not closest to each second power rail PR2. Since the width of the first power rail PR1 and the second power rail PR2 in the second direction D2 is greater than the width of the first wiring M11 and the second wiring M12 in the second direction D2, when the second gate contact CB2 is formed on the second wiring M12 adjacent to each first power rail PR1 or each second power rail PR2, the process margin of the second gate contact CB2 can be increased or improved.

[0122] For example, one second gate electrode 220 may be disposed between second gate contacts CB2 adjacent to each other along the first direction D1. That is, the second gate contact CB2 may be disposed on two second gate electrodes 220 other than the middle second gate electrode 220 among the three second gate electrodes 220 sequentially arranged along the first direction D1. The distance S between the second gate contacts CB2 adjacent to each other in the first direction D1 may be, for example, 72 nm to 198 nm.

[0123] The second gate contact CB2 has the same size as the first gate contact CB1. The depth of each second gate contact CB2 in the third direction D3 is the same as the depth of each first gate contact CB1 in the third direction D3. The length of each second gate contact CB2 in the first direction D1 is the same as the length of each first gate contact CB1 in the first direction D1. The length of each second gate contact CB2 in the second direction D2 is the same as the length of each first gate contact CB1 in the second direction D2. The second gate contact CB2 can be formed by the same process as the first gate contact CB1.

[0124] Each of the gate contacts CB1 and CB2 may include a second barrier layer 181 and a second filling layer 182 .

[0125] Each of the first barrier layer 171 and the second barrier layer 181 may include, for example, at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), and a two-dimensional (2D) material. Each of the first filling layer 172 and the second filling layer 182 may include, for example, at least one of aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), copper (Cu), silver (Ag), gold (Au), manganese (Mn), and molybdenum (Mo).

[0126] The semiconductor device according to the embodiment of the present disclosure includes a second gate contact CB2 located in the termination cell region 14. Therefore, the difference between the density of the second gate contacts CB2 in the termination cell region 14 and the density of the first gate contacts CB1 in the standard cell region 12 can be reduced. This can improve or enhance the planarization effect during a chemical mechanical planarization (CMP) process (e.g., during a CMP process of the first wiring M11 and the second wiring M12).

[0127] Figures 10 to 16is a cross-sectional view of a semiconductor device according to an embodiment. For reference, Fig.10 is along Figure 2 A cross-sectional view taken along line AA'. Fig.11 is along Figure 2 A cross-sectional view taken along line BB'. Fig.12 is along Figure 2 A cross-sectional view taken along line CC'. Fig.13 is along Figure 2 A cross-sectional view taken along line D-D'. Fig.14 is along Figure 2 A cross-sectional view taken along line EE'.

[0128] Fig.15 is along Figure 2 A cross-sectional view taken along line F-F'. Fig.16 is along Figure 2 For ease of description, the following description will focus on the cross-sectional view taken along the line G-G' of FIG. Figures 1 to 9 Describe the differences in semiconductor devices.

[0129] Reference Figures 10 to 16 , in the semiconductor device according to the embodiment, each of the active patterns AP1 to AP4 does not include a sheet pattern.

[0130] The active patterns AP1 to AP4 may be fin-shaped patterns extending over an upper surface of the field insulation layer 105. The field insulation layer 105 may partially cover or overlap sidewalls of the active patterns AP1 to AP4.

[0131] The first to fourth active patterns AP1 to AP4 extending over the upper surface of the field insulating layer 105 may serve as channel regions of transistors.

[0132] exist Figures 10 to 16 In the semiconductor device shown, the gate structure GS does not include the inner gate structure INT_GS.

[0133] Reference Fig.17 , the semiconductor device according to the embodiment includes a cell region 10 , an input / output region 20 , and a block region 30 .

[0134] The unit area 10 includes a reference Figures 1 to 16 A standard cell region 12 and a termination cell region 14 are depicted.

[0135] Input / output pads and input / output buffers or drivers for exchanging data or signals with the outside of the chip may be formed in the input / output region 20 .

[0136] A memory, an analog circuit block, a static random access memory (SRAM), a CPU, etc. may be formed in each block area 30. The analog circuit block may be, for example, a phase locked loop (PLL).

[0137] The cell region 10, the input / output region 20, and the block region 30 may be spaced apart from each other. For example, a dummy pattern may be provided in a field region between the cell region 10 and the input / output region 20 or between the cell region 10 and the block region 30. The semiconductor device according to the embodiment includes a second gate contact CB2 located in the termination cell region 14. Therefore, the difference between the density of the gate contacts in the standard cell region 12, the density of the gate contacts in the termination cell region 14, and the density of the gate contacts in the field region may be reduced, thereby improving or enhancing the planarization effect during the CMP process.

[0138] Although the present disclosure has been specifically shown and described with reference to some exemplary embodiments of the present disclosure, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the present disclosure as defined by the appended claims. The exemplary embodiments should be considered in a descriptive sense only and not for limiting purposes.

Claims

1. A semiconductor device, include: A substrate including a standard cell region and a termination cell region at least partially surrounding the standard cell region; a first active pattern in the standard cell region; a first wiring extending in a first direction and on the first active pattern; a first gate electrode extending in a second direction and on the first active pattern; a first gate contact; a second active pattern in the terminal unit region; a second wiring extending in the first direction and on the second active pattern; a second gate electrode extending in the second direction and on the second active pattern; as well as A second gate contact.

2. The semiconductor device according to claim 1, in, The first gate contact is electrically connected to the first gate electrode and the first wiring, and wherein the second gate contact is electrically connected to the second gate electrode and the second wiring.

3. The semiconductor device according to claim 1, in, The first gate contact and the second gate contact have the same length in at least one of the first direction and the second direction.

4. The semiconductor device according to claim 1, further comprising: include: a first power rail extending in the first direction; a second power rail extending in the first direction and spaced apart from the first power rail in the second direction; as well as a plurality of the second wirings, wherein the plurality of second wirings are located between the first power rail and the second power rail in the second direction, wherein the second gate contact portion is located on a given second wiring among the plurality of second wirings, and The given second wiring is adjacent to the first power rail or the second power rail.

5. The semiconductor device according to claim 1, further comprising: include: a first power rail extending in the first direction; as well as a second power rail extending in the first direction and spaced apart from the first power rail in the second direction, The second active pattern includes a third active sub-pattern electrically connected to the first power rail and a fourth active sub-pattern electrically connected to the second power rail.

6. The semiconductor device according to claim 1, in, The first wiring and the second wiring are not electrically connected.

7. The semiconductor device according to claim 1, in: The first active pattern includes a first fin pattern extending in the first direction and extending from the substrate, The second active pattern includes a second fin pattern extending in the first direction and extending from the substrate, The first gate electrode overlaps the first fin pattern, and The second gate electrode overlaps the second fin pattern.

8. The semiconductor device according to claim 1, in: The first active pattern includes a first fin pattern extending in the first direction and extending from the substrate, The first active pattern includes a first sheet pattern spaced apart from the first fin pattern, The second active pattern includes a second fin pattern extending in the first direction and extending from the substrate, The second active pattern includes a second sheet pattern spaced apart from the second fin pattern, The first gate electrode overlaps with the first sheet pattern, and The second gate electrode overlaps the second sheet pattern.

9. A semiconductor device, include: A substrate including a standard cell region and a termination cell region at least partially surrounding the standard cell region; an active pattern in the termination unit region; a power rail extending in a first direction and on the active pattern; a wiring extending in the first direction and on the active pattern; one or more gate electrodes extending in the second direction and on the active pattern; A gate contact portion, located between the gate electrode and the wiring; a source / drain pattern on the active pattern and on one side of the gate electrode; as well as A well contact is located between the source / drain pattern and the power rail. 10 . The semiconductor device according to claim 9 , wherein the wiring is adjacent to the power rail.

11. The semiconductor device according to claim 9, in: The one or more gate electrodes include a first gate electrode, a second gate electrode, and a third gate electrode spaced apart in the first direction, and The gate contact is on the first gate electrode and the third gate electrode, but not on the second gate electrode.

12. The semiconductor device according to claim 9, in, The wiring does not extend into the standard cell region.

13. The semiconductor device according to claim 9, in, The power rails and the wiring extend the same distance from the substrate.

14. A semiconductor device, include: substrate; a first active pattern on the substrate; a second active pattern on the substrate; a first gate electrode on the first active pattern and extending in a second direction; a second gate electrode on the second active pattern and extending in the second direction; a first wiring extending in a first direction and on the first active pattern; a second wiring extending in the first direction and on the second active pattern; a power rail extending in the first direction and on the substrate; a first gate contact portion, located between the first gate electrode and the first wiring; as well as a second gate contact portion located between the second gate electrode and the second wiring, wherein the second active pattern is electrically connected to the power rail, and The first wiring and the second wiring are not electrically connected to each other.

15. The semiconductor device according to claim 14, in, The second wiring is adjacent to the power rail.

16. The semiconductor device according to claim 14, in: The first active pattern includes a first fin pattern and a first sheet pattern, the first sheet pattern being on the first fin pattern and spaced apart from the first fin pattern, and The second active pattern includes a second fin pattern and a second sheet pattern, the second sheet pattern being on the second fin pattern and spaced apart from the second fin pattern.

17. The semiconductor device according to claim 14, in, The first gate contact and the second gate contact have the same length in at least one of the first direction and the second direction.

18. The semiconductor device according to claim 14, in, The first gate contact and the second gate contact have the same length in a direction perpendicular to an upper surface of the substrate.

19. The semiconductor device according to claim 14, in, The second active pattern is adjacent to the first active pattern in the first direction or in the second direction.

20. The semiconductor device according to claim 14, further comprising: include: a source / drain pattern on the second active pattern and on one side of the second gate electrode; as well as A well contact is located between the source / drain pattern and the power rail.

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