Schottky diode, LDMOSFET integrated with Schottky diode and manufacturing method of LDMOSFET

Abstract

The present invention relates to a Schottky diode, comprising: a well region having a first conductivity type; the body region is arranged at the upper part of the well region and has a second conduction type; the body region is penetrated by a groove, and the bottom of the groove extends into the well region; the first cobalt silicide layer is formed on the bottom surface and the inner wall of the groove, and the first cobalt silicide layer and the well region form Schottky contact; wherein the well region is used as a cathode of the Schottky diode, the first cobalt silicide layer in direct contact with the well region is used as an anode of the Schottky diode, and the first conductive type and the second conductive type are opposite. According to the invention, the first cobalt silicide layer and the well region form Schottky contact with a U-shaped structure by utilizing the bottom surface and the inner wall of the groove, a larger Schottky contact area can be obtained by virtue of a smaller plane area, and the Schottky contact is formed by cobalt silicide, so that the Schottky diode has stronger overcurrent capability.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a Schottky barrier diode, an LDMOSFET (lateral double diffused metal oxide semiconductor field effect transistor) with an integrated Schottky diode, and a method for manufacturing the LDMOSFET with an integrated Schottky diode. Background Art

[0002] Figure 1 is a circuit schematic diagram of an exemplary LDMOSFET, in which a parasitic diode is formed between the source and drain of the LDMOS. The exemplary NLDMOS can form a diode using the drain region, the drift region and the P-body region (P-Body), but the forward conduction voltage drop of the diode is usually about 0.7V, which limits the further reduction of the forward conduction voltage drop and conduction loss.

[0003] See also Figure 2 , a Schottky diode can be integrated inside the LDMOS to obtain lower conduction loss. The exemplary Schottky diode structure uses a planar metal semiconductor interface, which is surrounded by a P-ring. The P-ring is led out at an appropriate distance to form a Schottky diode, so it occupies a larger plane area. Summary of the invention

[0004] Based on this, it is necessary to provide a Schottky diode with a smaller plane area.

[0005] A Schottky diode comprises: a well region having a first conductivity type; a body region arranged on the upper part of the well region and having a second conductivity type; the body region is penetrated by a groove, and the bottom of the groove extends into the well region; a first cobalt silicide layer is formed on the bottom surface and inner wall of the groove, and the first cobalt silicide layer forms a Schottky contact with the well region; wherein the well region serves as the cathode of the Schottky diode, and the first cobalt silicide layer directly in contact with the well region serves as the anode of the Schottky diode, and the first conductivity type and the second conductivity type are opposite conductivity types.

[0006] The above-mentioned Schottky diode utilizes the bottom surface and inner wall of the groove to form a Schottky contact with the first cobalt silicide layer and the well region with a U-shaped cross-section. A larger Schottky contact area can be obtained with a smaller plane area, and because the Schottky contact is formed by cobalt silicide, it has a stronger overcurrent capability.

[0007] In one embodiment, the Schottky diode further includes a first doped region located in the body region, the first doped region has a first conductivity type, and a portion of the first cobalt silicide layer is located on a surface of the first doped region.

[0008] In one of the embodiments, a side surface of the first doped region is disposed close to the top of the trench.

[0009] In one of the embodiments, the Schottky diode further includes: a second doped region, directly in contact with the well region, and having the first conductivity type.

[0010] In one embodiment, the Schottky diode further includes: a field region insulating layer located between the body region and the second doped region.

[0011] In one of the embodiments, the Schottky diode further includes: a substrate, and the well region is located in the substrate.

[0012] In one of the embodiments, the Schottky diode further includes: a second cobalt silicide layer located on a surface of the second doped region, and a cathode of the Schottky diode is led out through the second cobalt silicide layer.

[0013] In one embodiment, the Schottky diode further includes a metal titanium bonding layer located on an upper surface of the first cobalt silicide layer, and a titanium nitride layer located on an upper surface of the metal titanium bonding layer.

[0014] In one embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0015] It is also necessary to provide an LDMOSFET with an integrated Schottky diode.

[0016] A LDMOSFET with an integrated Schottky diode comprises: a substrate; a drift region, which is arranged in the substrate and has a first conductivity type; a body region, which is arranged in the drift region and has a second conductivity type; the body region is penetrated by a groove, and the bottom of the groove extends into the drift region; a first cobalt silicide layer, which is formed on the bottom surface and inner wall of the groove, and the first cobalt silicide layer forms a Schottky contact with the drift region; a source region, which is located in the body region, the source region has the first conductivity type, and a part of the first cobalt silicide layer is located on the surface of the source region; a drain region, which is in direct contact with the drift region and has the first conductivity type; wherein the drift region serves as the cathode of the Schottky diode, and the first cobalt silicide layer in direct contact with the drift region serves as the anode of the Schottky diode, and the first conductivity type and the second conductivity type are opposite conductivity types.

[0017] The LDMOSFET with integrated Schottky diode uses the bottom surface and inner wall of the groove to form a Schottky contact with the drift region with a U-shaped cross-section, so that a larger Schottky contact area can be obtained with a smaller plane area, and because the Schottky contact is formed by cobalt silicide, it has a stronger overcurrent capability. The Schottky diode structure is suitable for LDMOSFETs with low side, high side and full isolation structures, and therefore has a wide range of applicability.

[0018] In one of the embodiments, a side surface of the first doped region is disposed close to the top of the trench.

[0019] In one embodiment, the LDMOSFET further includes: a field region insulating layer located between the body region and the drain region.

[0020] In one of the embodiments, the LDMOSFET further includes: a gate, one side of which is close to the source region and the other side of which is close to the drain region, and a portion of the gate is located on the field region insulating layer.

[0021] In one of the embodiments, the LDMOSFET further includes a second cobalt silicide layer located on the surface of the drain region, and the cathode of the Schottky diode is led out through the second cobalt silicide layer.

[0022] In one embodiment, the LDMOSFET with integrated Schottky diode is a LDMOS with a fully isolated structure, and the LDMOS with a fully isolated structure also includes: a second conductivity type well region, the drift region is located in the second conductivity type well region; a buried region, located below the second conductivity type well region and between the second conductivity type well region and the substrate, the buried region has a first conductivity type; an isolation region, located outside the second conductivity type well region, part of the substrate is located on the side of the isolation region away from the second conductivity type well region, and the bottom of the isolation region is in direct contact with the buried region.

[0023] In one embodiment, the LDMOSFET further includes a metal titanium bonding layer located on an upper surface of the first cobalt silicide layer, and a titanium nitride layer located on an upper surface of the metal titanium bonding layer.

[0024] In one embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0025] It is also necessary to provide a method for manufacturing an LDMOSFET with an integrated Schottky diode.

[0026] A method for manufacturing an LDMOSFET with an integrated Schottky diode, comprising: obtaining a substrate; forming a drift region in the substrate, forming a body region in the drift region, the drift region having a first conductivity type, the body region having a second conductivity type, the first conductivity type and the second conductivity type being opposite conductivity types; forming a source region and a drain region; the source region is formed in the body region, the drain region is in direct contact with the drift region, the source region and the drain region having the first conductivity type; forming a trench penetrating the body region, the bottom of the trench extending into the drift region; forming a metal silicide layer by a self-aligned metal silicide process, the metal silicide layer comprising a first cobalt silicide layer formed on the bottom surface and inner wall of the trench, and a second cobalt silicide layer formed on the surface of the drain region, the first cobalt silicide layer forming a Schottky contact with the drift region; wherein the drift region serves as the cathode of the Schottky diode, and the first cobalt silicide layer in direct contact with the drift region serves as the anode of the Schottky diode.

[0027] The manufacturing method of the LDMOSFET with integrated Schottky diode uses the bottom surface and inner wall of the groove to form a Schottky contact with the drift region with a U-shaped cross-section, which can obtain a larger Schottky contact area with a smaller plane area, and because the Schottky contact is formed by the cobalt silicide layer of the self-aligned metal silicide (salicide) process, it has a stronger overcurrent capability. The Schottky diode structure is suitable for LDMOSFETs with Low Side, High Side and full isolation structures, and therefore has a wide range of applicability.

[0028] In one of the embodiments, before the step of forming the source region and the drain region, the step further includes: forming a field region insulating layer between the body region and the drain region.

[0029] In one of the embodiments, before the step of forming the source region and the drain region, it also includes: forming a gate, one side of the gate is close to the source region and the other side is close to the drain region, and a part of the gate is formed on the field region insulating layer.

[0030] In one embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0031] In one embodiment, after the step of forming the metal silicide layer by the self-aligned metal silicide process, the method further includes the step of forming a metal titanium bonding layer and a titanium nitride layer on the first cobalt silicide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the embodiments and / or examples currently described, and the best modes of these inventions currently understood.

[0033] Figure 1 is a circuit schematic diagram of an exemplary LDMOSFET;

[0034] Figure 2 It is a circuit schematic diagram of an LDMOSFET with an integrated Schottky diode;

[0035] Figure 3 is a schematic cross-sectional structure diagram of an LDMOSFET with an integrated Schottky diode in an embodiment of the present application;

[0036] Figure 4 1 is a schematic diagram of a fully isolated LDMOSFET with an integrated Schottky diode in one embodiment of the present application;

[0037] Figure 5 is a flow chart of a method for manufacturing an LDMOSFET with an integrated Schottky diode in an embodiment of the present application;

[0038] Figures 6a to 6c Is adopted Figure 5 A schematic cross-sectional view of a device during the process of manufacturing LDMOS using the method shown. DETAILED DESCRIPTION

[0039] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0041] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. "Connection" in this specification should be understood as "electrical connection", "communication connection" and the like if the connected circuits, modules, units, etc. have transmission of electrical signals or data to each other. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

[0042] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0043] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present invention. When used herein, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It is understood that "at least one" refers to one or more, and "multiple" refers to two or more. "At least part of an element" refers to part or all of an element. It should also be understood that the terms "compose" and / or "comprise" when used in this specification determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0044] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0045] The semiconductor field vocabulary used in this article is technical vocabulary commonly used by technical personnel in this field. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0046] Figure 3 Schematic diagram of the cross-sectional structure of an LDMOSFET with integrated Schottky diode in one embodiment of the present application. Figure 3 The structure shown is bilaterally symmetrical, so only one of the structures is marked, and the other symmetrical one is not marked. Figure 3 The integrated Schottky diode in the illustrated embodiment includes a well region, a body region 124 and a first cobalt silicide layer 142. The well region is the drift region 122 of the LDMOSFET. The drift region 122 has a first conductivity type. The body region 124 is disposed in the drift region 122 and has a second conductivity type. The body region 124 is penetrated by the groove 131, and the bottom of the groove 131 extends into the drift region 122. The first cobalt silicide layer 142 is formed on the bottom surface and inner wall of the groove 131, and the first cobalt silicide layer 142 forms a Schottky contact with the drift region 122. The drift region 122 serves as the cathode of the Schottky diode, and the first cobalt silicide layer 142 directly in contact with the drift region 122 serves as the anode of the Schottky diode. Figure 3 In the embodiment shown, the LDMOSFET is NLDMOS, the first conductivity type is N-type, and the second conductivity type is P-type. Accordingly, the substrate 110 is a P-type substrate P-Sub, the drift region 122 is an N-type drift region N-Drift, and the body region 124 is a P-type body region P-Body.

[0047] The Schottky diode uses the bottom surface and inner wall of the trench 131 to form a Schottky contact with the first cobalt silicide layer 142 and the drift region 122 with a U-shaped cross-section, and can obtain a larger Schottky contact area with a smaller plane area, so it has a stronger overcurrent capability. On the other hand, since the Schottky contact is formed by cobalt silicide, it is also conducive to obtaining a stronger overcurrent capability.

[0048] exist Figure 3 In the illustrated embodiment, the LDMOSFET further includes a substrate 110, a source region 132 (a first doping region), and a drain region 134 (a second doping region). The drift region 122 is located in the substrate 110. Figure 3 In the illustrated embodiment, the substrate 110 has the second conductivity type. The source region 132 is located in the body region 124, the source region 132 has the first conductivity type, and a portion of the first cobalt silicide layer 142 is located on the surface of the source region 132. Figure 3 In the embodiment shown, one side of the source region 132 is disposed near the top of the trench 131. The drain region 134 is in direct contact with the drift region 122 and has the first conductivity type. The doping concentration of the drain region 134 is greater than the doping concentration of the drift region 122. That is, the source region 132 and the drain region 134 are N+ regions. Figure 3 The structure shown is applicable to the Low Side, High Side and Fully Isolated NLDMOSFET in the half-bridge circuit, and therefore has wide applicability. The source, bulk and substrate of the Low Side NLDMOSFET in the half-bridge circuit have the same potential; the bulk and substrate of the High Side NLDMOSFET in the half-bridge circuit have different potentials; the bulk and substrate of the Fully Isolated NLDMOSFET also have different potentials.

[0049] exist Figure 3 In the embodiment shown, the LDMOSFET further includes a field insulating layer 150 and a gate 136. One side of the gate 136 is close to the source region 132, and the other side is close to the drain region 134. A portion of the gate 136 is located on the field insulating layer 150. In one embodiment of the present application, the field insulating layer 150 is a field oxide layer, and its material is silicon oxide, such as silicon dioxide. In one embodiment of the present application, the gate 136 is a polysilicon material, and in other embodiments, metal, metal nitride, metal silicide or similar compounds can also be used as the material of the gate 136.

[0050] exist Figure 3In the illustrated embodiment, the Schottky diode further includes a second cobalt silicide layer 144 located on the surface of the drain region 134. The cathode of the Schottky diode is led out through the second cobalt silicide layer 144. The second cobalt silicide layer 144 can reduce the contact resistance of the drain region 134.

[0051] In one embodiment of the present application, the Schottky diode further includes a metal titanium bonding layer located on the upper surface of the first cobalt silicide layer 142 , and a titanium nitride layer located on the upper surface of the metal titanium bonding layer.

[0052] Since the U-shaped cross-sectional structure makes the Schottky contact area larger, it has a strong effect of reducing the conduction voltage drop of the Schottky diode. In one embodiment of the present application, the conduction voltage drop of the Schottky diode can be reduced to about 0.3V, reducing the conduction voltage drop and conduction loss of the body diode between the source region 132 and the drain region 134.

[0053] Figure 4 1 is a schematic diagram of a fully isolated LDMOSFET with an integrated Schottky diode in one embodiment of the present application. Figure 3 Based on the embodiment shown, the LDMOSFET further includes a second conductive type well region 126, a buried region 128 and an isolation region 129. The drift region 122 is located in the second conductive type well region 126. The buried region 128 is located below the second conductive type well region 126 and between the second conductive type well region 126 and the substrate 110. Figure 4 In the illustrated embodiment, the buried region 128 is a first conductive type buried layer. The isolation region 129 is located outside the second conductive type well region 126, and a portion of the substrate 110 is located outside the isolation region 129 (i.e., on the side away from the second conductive type well region 126), and the bottom of the isolation region 129 is in direct contact with the buried region 128. In one embodiment of the present application, the isolation region 129 is a first conductive type doped region. The fully isolated structure LDMOSFET isolates the second conductive type well region 126 from the substrate 110, so that the second conductive type well region 126 and the substrate 110 have different potentials.

[0054] The present application accordingly provides a method for manufacturing an LDMOSFET with an integrated Schottky diode, which can be used to manufacture the LDMOSFET with an integrated Schottky diode described in any of the aforementioned embodiments. Figure 5 1 is a flow chart of a method for manufacturing an LDMOSFET with an integrated Schottky diode in an embodiment of the present application, comprising the following steps:

[0055] S210 , obtaining a substrate having a drift region and a body region formed thereon.

[0056] See also Figure 6a, a drift region 122 is formed in the substrate 110, and a body region 124 is formed in the drift region 122. The drift region 122 has a first conductivity type, and the body region 124 has a second conductivity type. Figure 6a In the illustrated embodiment, the manufactured LDMOSFET is NLDMOS, the first conductivity type is N-type, and the second conductivity type is P-type.

[0057] In one embodiment of the present application, the substrate 110 is a semiconductor substrate, and its material may be undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc., and may also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors. Figure 6a In the illustrated embodiment, the material used to form the substrate 110 is single crystal silicon.

[0058] In one embodiment of the present application, the drift region 122 may be formed using a suitable method, such as a doping process. Doping is generally achieved by ion implantation. If an N-type drift region 122 is prepared, N-type ion doping is performed on the region of the substrate 110 where the drift region 122 is to be formed, such as ion implantation after photolithography, to form an N-type drift region 122 in the substrate 110. Similarly, a suitable method may be used to form the body region 124, such as a doping process. If a P-type body region 124 is prepared, P-type ion doping is performed on the region of the drift region 122 where the body region 124 is to be formed, such as ion implantation after photolithography, to form a P-type body region 124 in the substrate 110.

[0059] S220, forming a source region and a drain region.

[0060] The source region 132 is formed in the body region 124, and the drain region 134 is in direct contact with the drift region 122. The source region 132 and the drain region 134 have a first conductivity type.

[0061] In one embodiment of the present application, after step S210 and before step S220, a step of forming a field region insulating layer 150 and a step of forming a gate 136 are also included, see Figure 6b In one embodiment of the present application, the field region insulating layer 150 is a field oxide layer, and its material is silicon oxide, such as silicon dioxide. The field region insulating layer 150 can be formed by a process known to those skilled in the art, such as a thermal oxidation process.

[0062] In one embodiment of the present application, the gate 136 is made of polysilicon; in other embodiments, metal, metal nitride, metal silicide or similar compounds may be used as the gate material. In one embodiment of the present application, the gate 136 may be formed by chemical vapor deposition (CVD), such as low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (LTCVD), plasma chemical vapor deposition (PECVD), and methods such as sputtering and physical vapor deposition (PVD) may also be used. The thickness of the gate 136 may be a suitable thickness according to the size of the device, and no specific limitation is made here.

[0063] In one embodiment of the present application, the method for forming the source region 132 and the drain region 134 includes performing source-drain ion implantation on the region where the source and drain are to be formed in the semiconductor substrate. Specifically, a patterned photoresist layer exposing the region where the source region 132 and the drain region 134 are to be formed can be first formed by a photolithography process, and then the source-drain ion implantation is performed using the patterned photoresist layer as a mask, and finally the patterned photoresist layer is removed by a method such as ashing.

[0064] Subsequently, an annealing process may be performed. For example, the annealing process may be performed using any annealing method known to those skilled in the art, including but not limited to rapid thermal annealing, furnace annealing, peak annealing, laser annealing, etc. For example, a rapid temperature rise annealing process may be performed to activate the dopants in the source region 132 and the drain region 134 using a high temperature of 900 to 1050° C., and simultaneously repair the lattice structure of the semiconductor substrate surface damaged in each ion implantation process. In addition, a lightly doped drain (LDD) may be formed between the source region 132, the drain region 134, and the gate 136, respectively, depending on product requirements and functional considerations.

[0065] S230 , forming a trench penetrating the body region.

[0066] See also Figure 6c , the bottom of the groove 131 extends into the drift region 122. The groove 131 can be formed by photolithography and etching processes. In one embodiment of the present application, in order to maximize the gold semi-interface (the contact surface between the metal or metal silicide and the N-type semiconductor material) of the subsequently formed Schottky diode, the bottom of the groove 131 should be as close to the bottom of the drift region 122 as possible, but must be spaced from the substrate 110 below the drift region 122. The larger the gold semi-interface area of ​​the Schottky diode, the stronger the ability to reduce the conduction voltage drop and conduction loss of the body diode between the source / drain.

[0067] exist Figure 6c In the illustrated embodiment, the top of the trench 131 is located at the edge of the source region 132 .

[0068] S240 , forming a metal silicide layer through a self-aligned metal silicide (salicide) process.

[0069] The device structure after step S240 is completed can refer to Figure 3 The metal silicide layer includes a first cobalt silicide layer 142 formed on the bottom surface and inner wall of the trench 131, and a second cobalt silicide layer 144 formed on the surface of the drain region 134. The first cobalt silicide layer 142 forms a Schottky contact with the well region. The drift region 122 serves as a cathode of the Schottky diode, and the first cobalt silicide layer 142 in contact with the drift region 122 serves as an anode of the Schottky diode.

[0070] Self-aligned silicide (salicide) is a simple and convenient contact metallization process. In the process of manufacturing semiconductor devices, some areas require the salicide process, while some areas require the non-salicide process. For devices that require the non-salicide process, the characteristics of the above-mentioned salicide should be used to cover the areas that require non-salicide with materials that will not react with metals. This material used to cover non-salicide devices is called a self-aligned silicide barrier film (SAB).

[0071] Step S240 can form the first cobalt silicide layer 142 by using the salicide process of the device corresponding to the line width process, such as the salicide process in the 0.18 micron standard BCD (Bipolar-CMOS-DMOS) process. The Schottky contact uses the standard salicide process to chemically react cobalt and silicon to form cobalt silicide, which is simple and easy to operate and has high process compatibility. Figure 3 A portion of the first cobalt silicide layer 142 formed in step S240 is formed on the surface of the source region 132 .

[0072] The manufacturing method of the LDMOSFET with integrated Schottky diode uses the bottom surface and inner wall of the groove 131 to form a Schottky contact with the drift region 122 with a U-shaped cross-section, so that a larger Schottky contact area can be obtained with a smaller plane area, and because the Schottky contact is formed by the cobalt silicide layer of the self-aligned metal silicide (salicide) process, it has a stronger overcurrent capability. The Schottky diode structure is suitable for LDMOSFETs of Low Side, High Side and full isolation structures, and therefore has a wide range of applicability.

[0073] In one embodiment of the present application, after step S240 , a step of forming a metal titanium bonding layer and a titanium nitride layer on the first cobalt silicide layer 142 to form an ohmic contact is further included.

[0074] It should be understood that, although the various steps in the flowchart of the present application are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0075] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0076] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0077] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A Schottky diode, characterized in that: include: a well region having a first conductivity type; a body region, disposed on an upper portion of the well region and having a second conductivity type; The body region is penetrated by a trench, and the bottom of the trench extends into the well region; A first cobalt silicide layer is formed on the bottom surface and inner wall of the trench, and the first cobalt silicide layer forms a Schottky contact with the well region; The well region serves as the cathode of the Schottky diode, the first cobalt silicide layer directly in contact with the well region serves as the anode of the Schottky diode, and the first conductivity type and the second conductivity type are opposite conductivity types.

2. The Schottky diode according to claim 1, characterized in that: It also includes a first doped region located in the body region, the first doped region has a first conductivity type, a side surface of the first doped region is arranged close to the top of the trench, and a portion of the first cobalt silicide layer is located on the surface of the first doped region.

3. The Schottky diode according to claim 1, characterized in that: Also includes: a second doped region, directly contacting the well region and having a first conductivity type; The field region insulating layer is located between the body region and the second doped region.

4. The Schottky diode according to claim 3, characterized in that: Also includes: a substrate, wherein the well region is located in the substrate; and / or A second cobalt silicide layer is located on the surface of the second doped region, and a cathode of the Schottky diode is led out through the second cobalt silicide layer.

5. An LDMOSFET with integrated Schottky diode, characterized in that: include: substrate; A drift region, disposed in the substrate and having a first conductivity type; a body region, disposed in the drift region and having a second conductivity type; The body region is penetrated by a trench, and the bottom of the trench extends into the drift region; A first cobalt silicide layer is formed on the bottom surface and inner wall of the trench, wherein the first cobalt silicide layer forms a Schottky contact with the drift region; A source region, located in the body region, the source region has a first conductivity type, and a portion of the first cobalt silicide layer is located on a surface of the source region; a drain region, directly contacting the drift region and having a first conductivity type; The drift region serves as a cathode of the Schottky diode, the first cobalt silicide layer directly in contact with the drift region serves as an anode of the Schottky diode, and the first conductivity type and the second conductivity type are opposite conductivity types.

6. The LDMOSFET with integrated Schottky diode according to claim 5, characterized in that: Also includes: A field region insulating layer, located between the body region and the drain region; A gate has one side close to the source region and the other side close to the drain region, and a portion of the gate is located on the field region insulating layer.

7. The LDMOSFET with integrated Schottky diode according to claim 5, characterized in that: It also includes a second cobalt silicide layer located on the surface of the drain region, and the cathode of the Schottky diode is led out through the second cobalt silicide layer.

8. The LDMOSFET with integrated Schottky diode according to claim 5, characterized in that: The LDMOSFET with integrated Schottky diode is a LDMOS with full isolation structure, and the LDMOS with full isolation structure further includes: A second conductive type well region, wherein the drift region is located in the second conductive type well region; a buried region, located below the second conductivity type well region and between the second conductivity type well region and the substrate, the buried region having a first conductivity type; The isolation region is located outside the second conductive type well region, part of the substrate is located on a side of the isolation region away from the second conductive type well region, and the bottom of the isolation region is in direct contact with the buried region.

9. A method for manufacturing an LDMOSFET with an integrated Schottky diode, comprising: obtaining a substrate; A drift region is formed in the substrate, a body region is formed in the drift region, the drift region has a first conductivity type, the body region has a second conductivity type, and the first conductivity type and the second conductivity type are opposite conductivity types; forming a source region and a drain region; the source region is formed in the body region, the drain region is in direct contact with the drift region, and the source region and the drain region have a first conductivity type; forming a trench penetrating the body region, wherein the bottom of the trench extends into the drift region; Forming a metal silicide layer by a self-aligned metal silicide process, the metal silicide layer comprising a first cobalt silicide layer formed on the bottom surface and inner wall of the trench, and a second cobalt silicide layer formed on the surface of the drain region, the first cobalt silicide layer forming a Schottky contact with the drift region; The drift region serves as a cathode of the Schottky diode, and the first cobalt silicide layer directly in contact with the drift region serves as an anode of the Schottky diode.

10. The method for manufacturing an LDMOSFET with integrated Schottky diode according to claim 9, characterized in that: Before the step of forming the source region and the drain region, the step further includes: forming a field region insulating layer between the body region and the drain region; A gate is formed, one side of the gate is close to the source region and the other side of the gate is close to the drain region, and a portion of the gate is formed on the field region insulating layer.

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