A p-GaN HEMT device and preparation method

Abstract

The present invention provides a p-GaN HEMT device and a preparation method, a substrate layer; a buffer layer arranged on the substrate layer, a side of the buffer layer away from the substrate layer is provided with a P-type doping region; a channel layer arranged on the buffer layer, the channel layer is in contact with the P-type doping region; a barrier layer, a source electrode and a drain electrode arranged on the channel layer, the source electrode and the drain electrode are arranged on both sides of the barrier layer; a heat dissipation layer arranged on the barrier layer; a cap layer arranged on the barrier layer and on the heat dissipation layer; a passivation layer arranged on the heat dissipation layer, the passivation layer is arranged between the source electrode and the cap layer and between the drain electrode and the cap layer; a gate electrode arranged on the cap layer. The beneficial effects of the present invention are that the number of defects and the interface thermal resistance at the heterojunction interface can be effectively reduced, the heat dissipation capacity of 2DEG at the device channel can be improved, and the mechanical properties of the device can be enhanced, the influence of interface reaction and defects on the working performance of the device can be reduced, the electric field at the 2DEG channel can be effectively modulated, the thermal management capability of the device itself can be improved, and the stability and reliability of the device operation can be improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a p-GaN HEMT device and a preparation method thereof. Background Art

[0002] As a third-generation semiconductor material, GaN has excellent characteristics such as large bandgap, high thermal conductivity, low on-resistance and tolerance to high frequency and high voltage conditions. It is very suitable for the preparation of high-frequency, high-power power electronics and radio frequency devices. Semiconductor devices are the basis of modern electronic information technology, among which gallium nitride high electron mobility transistor (GaN HEMT) is an important semiconductor device, which is widely used in communications, power electronics and other fields.

[0003] Among them, compared with depletion-mode devices, enhancement-mode GaN-based HEMT devices can avoid the risk of false start-up and reduce the complexity of gate drive, and have greater advantages in the field of power electronics applications. Enhancement-mode GaN-based HEMT devices have been industrialized in the fields of mobile phone fast charging and 5G communications, and have shown potential for application in chip power management and extreme scenarios such as high temperature and radiation. At present, the mainstream technologies for realizing enhancement-mode GaN-based HEMT devices are: fluorine (F) ion implantation technology, groove gate structure, common source and common gate cascade structure and p-GaN gate structure. Compared with the first three methods, p-GaN gate technology can obtain enhancement-mode devices with stable threshold voltage, high reliability, strong process controllability and good repeatability, which are suitable for large-scale production and commercial use.

[0004] However, more complex application scenarios and harsh device working environments have placed higher requirements on the gate control capability and device reliability of enhanced p-GaN HEMT devices, which not only affects the performance of the device, but may also lead to device failure. Therefore, how to effectively improve the gate control capability of p-GaN HEMT and improve its reliability and stability is an important challenge facing the current high-power GaN semiconductor device manufacturing technology.

[0005] At present, the existing p-GaN gate technology solutions will face some process difficulties. For example, Mg ions move to the AlGaN barrier layer and GaN channel layer during high-temperature diffusion, resulting in a decrease in electrical properties such as threshold voltage; the existing etching process will damage the AlGaN surface and cannot strictly control the amount of over-etching, which will lead to a decrease in the device's gate control capability; there are many interface defects at the connection between the p-GaN cap layer and the device, the interface adverse reaction is complex, and the improvement in the interface modification direction is small, which will cause gate leakage and reduce the reliability and stability of the device; the location of the 2DEG will cause electric field concentration to cause the self-heating effect of the device. The current direction to solve the heat dissipation problem of GaN-based HEMT devices is mainly to optimize the device epitaxial layer structure and packaging structure to improve the stability and reliability of the device during operation; the electric field control structure of the existing p-GaN-based HEMT device is not conducive to the growth of the device and the reduction of lattice mismatch, resulting in an increase in internal defects in the material, reducing the reliability and service life of the device; there are many interface defects at the connection between the existing p-GaN cap layer and the device, and the gate control capability is weak. Summary of the invention

[0006] In view of the above problems, the present invention provides a p-GaN HEMT device and a preparation method thereof to solve the above or other problems existing in the prior art.

[0007] In order to solve the above technical problems, the technical solution adopted by the present invention is: a p-GaN HEMT device, comprising:

[0008] substrate layer;

[0009] A buffer layer is provided on the substrate layer, wherein a P-type doping region is provided on a side of the buffer layer away from the substrate layer;

[0010] A channel layer is disposed on the buffer layer, and the channel layer is in contact with the P-type doped region;

[0011] A barrier layer, a source electrode and a drain electrode are arranged on the channel layer, and the source electrode and the drain electrode are arranged on both sides of the barrier layer;

[0012] a heat dissipation layer disposed on the barrier layer;

[0013] A cap layer disposed on the barrier layer and the heat dissipation layer;

[0014] A passivation layer is disposed on the heat dissipation layer, wherein the passivation layer is disposed between the source electrode and the cap layer and between the drain electrode and the cap layer;

[0015] A gate is disposed on the cap layer.

[0016] Furthermore, the P-type doped region is arranged in the injection region close to the two side edges along the first direction of the buffer layer. In any injection region, the P-type doped region includes multiple groups of P-type doped region groups, and the multiple groups of P-type doped region groups are arranged in sequence along the first direction of the buffer layer. Each group of P-type doped region groups includes multiple P-type doped sub-regions, and the multiple P-type doped sub-regions are arranged in sequence along the second direction of the buffer layer, and the first direction is arranged perpendicular to the second direction.

[0017] Furthermore, the plurality of P-type doped sub-regions in two adjacent groups of P-type doped regions are arranged in an alternating manner.

[0018] Furthermore, the shape of the P-type doped sub-region is polygonal or circular.

[0019] Furthermore, the cap layer includes a first grooved gate layer and a second grooved gate layer stacked together, the first grooved gate layer is arranged on the barrier layer, and one side of the first grooved gate layer is located in the barrier layer, the other side of the first grooved gate layer contacts the first side of the second grooved gate layer, and the first side of the second grooved gate layer contacts the heat dissipation layer.

[0020] Furthermore, the cap layer is gallium nitride doped with a P-type dopant, the P-type dopant is magnesium, and the doping concentration of the P-type dopant is 1×10 17 -8×10 17 cm -3 .

[0021] Furthermore, the thickness of the first grooved gate layer is 8-13 nm, and the thickness of the second grooved gate layer is 90-130 nm.

[0022] Furthermore, the heat dissipation layer is a single crystal diamond film or a silicon carbide film, and the thickness of the heat dissipation layer is 200nm-700nm.

[0023] Furthermore, the substrate layer is a polycrystalline diamond substrate, and the thickness of the substrate layer is 300-400um.

[0024] Furthermore, the buffer layer and the channel layer are both made of gallium nitride, the thickness of the buffer layer is 200-300 nm, and the thickness of the channel layer is 50-150 nm.

[0025] Furthermore, the barrier layer is gallium aluminum nitride, and the thickness of the barrier layer is 10-20 nm.

[0026] Furthermore, along the channel layer to the outside, the source and the drain both include a Ti layer, an Al layer, a Ni layer and an Au layer arranged in sequence; along the cap layer to the outside, the gate includes a TiN layer, a Ti layer, an Al layer, a Ni layer and an Au layer arranged in sequence.

[0027] Furthermore, the passivation layer is silicon nitride.

[0028] A method for preparing a p-GaN HEMT device comprises the following steps:

[0029] preparing a substrate layer;

[0030] preparing a buffer layer and bonding the buffer layer to the substrate layer;

[0031] Performing P-type ion implantation on the surface of the buffer layer to form a P-type doped region, and performing annealing treatment;

[0032] preparing a channel layer on the buffer layer;

[0033] preparing a barrier layer on the channel layer;

[0034] preparing a heat dissipation layer and bonding the heat dissipation layer to the barrier layer;

[0035] Etching the heat dissipation layer and the barrier layer to form grooves;

[0036] preparing a cap layer on the barrier layer at the trench and on the heat dissipation layer outside the trench;

[0037] preparing a passivation layer;

[0038] A source electrode and a drain electrode are prepared on the channel layer, and a gate electrode is prepared on the cap layer.

[0039] Furthermore, the substrate layer is prepared by chemical vapor deposition, and the substrate layer is a polycrystalline diamond substrate.

[0040] Furthermore, the buffer layer and the channel layer are both gallium nitride, and the buffer layer and the channel layer are prepared by MOCVD method respectively;

[0041] The barrier layer is aluminum gallium nitride, and the barrier layer is prepared by MOCVD;

[0042] The cap layer is gallium nitride doped with a P-type dopant, and is prepared by MOCVD.

[0043] Furthermore, P-type ion implantation is performed on the surface of the buffer layer to form a P-type doped region, and an annealing step is performed in a nitrogen atmosphere at a temperature of 850° C.-1150° C.

[0044] Furthermore, the P-type ions are magnesium ions, the implantation depth is 0.8-1.0um, and the implantation dose is 1×10 15 -1×10 17 cm -2 .

[0045] Furthermore, the heat dissipation layer is a single crystal diamond film or a silicon carbide film, which is grown on a substrate to form the heat dissipation layer, and the substrate is removed after the heat dissipation layer is bonded to the barrier layer.

[0046] Furthermore, a passivation layer is deposited by plasma enhanced chemical vapor deposition, and the passivation layer on the channel layer and the cap layer is removed by etching.

[0047] Due to the adoption of the above technical solution, a heat dissipation layer is provided, and the heat dissipation layer is a single crystal diamond film, and the single crystal diamond film is grown on a polycrystalline diamond substrate. The single crystal diamond film is bonded to the barrier layer by a bonding technology. Since the bonding rate between the single crystal diamond film and the gallium nitride barrier layer reaches more than 92%, the number of defects and interface thermal resistance at the heterojunction interface can be effectively reduced, the heat dissipation capacity of the 2DEG at the device channel can be improved, and the mechanical properties of the device can be enhanced, and the influence of interface reactions and defects on the working performance of the device can be reduced;

[0048] The substrate layer of the device is a polycrystalline diamond substrate, and the device manufacturing process does not need to be changed. The heat dissipation effect of the device is improved by setting the heat dissipation layer and the substrate layer;

[0049] The buffer layer is formed with a P-type doped region by ion implantation. The setting of the P-type doped region can effectively modulate the electric field at the 2DEG channel, alleviate the temperature rise caused by the accumulation of the electric field, further enhance the thermal management capability of the device itself, improve the stability and reliability of the device operation, and extend the service life of the device. At the same time, the setting of the heat dissipation layer can be used as a film layer to effectively prevent magnesium ions from diffusing to the barrier layer and the channel layer at a high temperature of more than 1000°C, and as an etching barrier layer to prevent over-etching of the barrier layer, so as to better control the quality of the device structure.

[0050] The cap layer is a double-layer trench gate structure, which can effectively increase the threshold voltage of the device compared to the traditional structure. The threshold voltage can reach 2.5-3.5V, enriching the high-power application scenarios of the device, and also making the 2DEG discontinuity more obvious, enhancing the gate control capability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 is a schematic structural diagram of a p-GaN HEMT device according to an embodiment of the present invention;

[0052] Figure 2 It is a schematic structural diagram of a buffer layer with a P-type doping region according to an embodiment of the present invention.

[0053] In the figure:

[0054] 1. Substrate layer; 2. Buffer layer; 3. P-type doped region; 4. Channel layer; 5. Barrier layer; 6. Heat dissipation layer; 7. Cap layer; 8. Passivation layer; 9. Gate; 10. Source; 11. Drain; 30. P-type doped sub-region; FA, first direction; FB, second direction. DETAILED DESCRIPTION

[0055] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0056] Figure 1 A schematic structural diagram of an embodiment of the present invention is shown. This embodiment relates to a p-GaN HEMT device and a preparation method. The p-GaN HEMT device has a heat dissipation layer, which is bonded to a barrier layer, reduces the number of defects and interface thermal resistance at a heterojunction interface, improves the heat dissipation capacity of 2DEG at a device channel, and enhances the mechanical properties of the device. The buffer layer is provided with a P-type doping region. The heat dissipation layer can prevent P-type ions from diffusing to the barrier layer and the channel layer, and can also serve as an etching stop layer to prevent the barrier layer from being etched, so that the quality of the device structure is easy to control.

[0057] A p-GaN HEMT device, such as Figure 1 and 2 As shown, it includes a substrate layer 1, a buffer layer 2 arranged on the substrate layer 1, a channel layer 4 arranged on the buffer layer 2, a barrier layer 5 arranged on the channel layer 4, a source 10 and a drain 11, a heat dissipation layer 6 arranged on the barrier layer 5, a cap layer 7 arranged on the barrier layer 5 and the heat dissipation layer 6, a passivation layer 8 arranged on the heat dissipation layer 6 and a gate 9 arranged on the cap layer 7. Along one side of the substrate layer 1 to the outside direction, the buffer layer 2, the channel layer 4, the barrier layer 5, the heat dissipation layer 6, the cap layer 7 and the gate 9 are arranged in sequence, the source 10 and the drain 11 are arranged on both sides of the barrier layer 5, the passivation layer 8 is arranged on both sides of the cap layer 7, and a P-type doping region 3 is arranged in the barrier layer 5.

[0058] Specifically, the substrate layer 1 as the substrate of the device is convenient for the arrangement of subsequent layers, and can dissipate heat to improve the heat dissipation effect of the device. The substrate layer 1 is a polycrystalline diamond substrate, and the substrate layer 1 is prepared by chemical vapor deposition. The thickness of the substrate layer 1 is 300-400um. The thickness of the substrate layer 1 is selected according to actual needs, and no specific requirements are made here.

[0059] The above-mentioned buffer layer 2 is arranged on one side surface of the substrate layer 1, and a P-type doping region 3 is provided on the side of the buffer layer 2 away from the substrate layer 1. The material of the buffer layer 2 is different from the material of the substrate layer 1. In some feasible embodiments, the buffer layer 2 is gallium nitride, which is grown by MOCVD and bonded to the substrate layer 1 by bonding. The thickness of the buffer layer 2 is 200-300nm. The thickness of the buffer layer 2 is selected according to actual needs, and no specific requirements are made here.

[0060] The buffer layer 2 is arranged on one side surface of the substrate layer 1, one side surface of the buffer layer 2 is in contact with the substrate layer 1, and the other side surface of the buffer layer 2 (the side surface is arranged opposite to the side surface in contact with the substrate layer 1) is provided with a P-type doping region 3. The P-type doping region 3 is located in the buffer layer 2 and is formed by ion implantation. The setting of the P-type doping region 3 can modulate the electric field at the 2DEG channel, alleviate the temperature rise caused by the accumulation of the electric field, enhance the thermal management capability of the device itself, improve the stability and reliability of the device operation, and extend the service life of the device.

[0061] In some feasible embodiments, the area of ​​the buffer layer 2 is adapted to the area of ​​the substrate layer 1 , and the buffer layer 2 covers the side surface of the substrate layer 1 .

[0062] The above-mentioned P-type doping region 3 is arranged in the injection area close to the two side edges of the buffer layer 2 along the first direction FA, that is, the P-type doping region 3 is not distributed throughout the entire side surface of the buffer layer 2, but is located in the area of ​​the side surface close to a group of relatively arranged side edges, and the middle area of ​​the side surface of the buffer layer 2 is not provided with the P-type doping region 3; in any injection area, the P-type doping region 3 includes a plurality of groups of P-type doping region groups, and the plurality of groups of P-type doping region groups are arranged in sequence along the first direction FA of the buffer layer 2, and in each injection area, the number of P-type doping region groups is at least two, which can be two, three, or other numbers, and the number of P-type doping region groups in each injection area is selected according to actual needs, and no specific requirements are made here.

[0063] In the two implanted regions, the number of P-type doping region groups may be the same or different, and may be selected and set according to actual needs. In some feasible embodiments, preferably, in one implanted region, the number of P-type doping region groups is two, and in the other implanted region, the number of P-type doping region groups is three.

[0064] Each group of P-type doping area groups includes multiple P-type doping sub-areas 30, and the multiple P-type doping sub-areas 30 are arranged in sequence along the second direction FB of the buffer layer 2. The first direction FA is arranged perpendicular to the second direction FB. The multiple P-type doping sub-areas 30 can be arranged in a straight line, in a curve, or in other arrangements. The selection is made according to actual needs, and no specific requirements are made here.

[0065] In two adjacent groups of P-type doping region groups, multiple P-type doping sub-regions 30 can be arranged one by one, or can be arranged in an interlaced manner, or in other arrangements, and the arrangement is selected according to actual needs. In some feasible embodiments, preferably, multiple P-type doping sub-regions 30 in two adjacent groups of P-type doping region groups are arranged in an interlaced manner, that is, along the second direction FB, the gap between two adjacent P-type doping sub-regions 30 in the first group of P-type doping region groups corresponds to a P-type doping sub-region 30 in the second group of P-type doping sub-regions, so that multiple P-type doping sub-regions 30 can be densely arranged in one injection region, and as many P-type doping sub-regions 30 as possible are arranged in one injection region.

[0066] The shape of the above-mentioned P-type doped sub-region 30 is polygonal or circular. When the P-type doped sub-region 30 is polygonal, the shape of the P-type doped sub-region 30 can be quadrilateral, hexagonal or octagonal, or other shapes, which are selected according to actual needs and are not specifically required here. In some feasible embodiments, the shape of the P-type doped sub-region 30 is preferably hexagonal, so that the distance between each P-type doped sub-region 30 and any P-type doped sub-region 30 on the surrounding side is equal.

[0067] In some feasible embodiments, the P-type doped sub-region 30 is formed by implanting magnesium ions on the surface of the buffer layer 2, the P-type ion implantation junction depth is 0.8-1.0 um, and the implantation dose is 1×10 15 -1×10 17 cm -2 .

[0068] The above-mentioned channel layer 4 is arranged on the buffer layer 2, and the channel layer 4 is arranged on a side surface of the buffer layer 2 where the P-type doping region 3 is arranged. The channel layer 4 is in contact with the P-type doping region 3. At the same time, the channel layer 4 is in contact with the buffer layer 2 where the P-type doping region 3 is not arranged. That is, the channel layer 4 is arranged on the side of the buffer layer 2 away from the contact with the substrate layer 1. The area of ​​the channel layer 4 is adapted to the area of ​​the buffer layer 2, and covers the side of the buffer layer 2. The channel layer 4 is grown on the buffer layer 2 by MOCVD.

[0069] In some feasible embodiments, the channel layer 4 is gallium nitride, and the thickness of the channel layer 4 is 50-150 nm. The thickness of the channel layer 4 is selected according to actual needs and no specific requirements are made here.

[0070] The above-mentioned barrier layer 5, source 10 and drain 11 are all arranged on the channel layer 4, and the source 10 and the drain 11 are arranged on both sides of the barrier layer 5, that is, in the first direction FA, the length of the barrier layer 5 is smaller than the length of the channel layer 4, and along the first direction FA, the source 10, the barrier layer 5 and the drain 11 are arranged in sequence, one side of the barrier layer 5 is in contact with the channel layer 4, and one side of the source 10 and one side of the drain 11 are both in contact with the channel layer 4.

[0071] In some feasible embodiments, the barrier layer 5 is aluminum gallium nitride, which is grown on the channel layer 4 by MOCVD. The thickness of the barrier layer 5 is 10-20 nm. The thickness of the barrier layer 5 is selected according to actual needs and no specific requirements are made here.

[0072] The source electrode 10 and the drain electrode 11 are both prepared by evaporation. Along the direction from the channel layer 4 to the outside, the source electrode 10 and the drain electrode 11 include a Ti layer, an Al layer, a Ni layer and an Au layer arranged in sequence.

[0073] The above-mentioned heat dissipation layer 6 is arranged on the barrier layer 5, and the heat dissipation layer 6 is bonded to the barrier layer 5 by bonding. The setting of the heat dissipation layer 6 can prevent P-type ions from diffusing into the barrier layer 5 and the channel layer 4 during the high-temperature diffusion process, and at the same time can protect the barrier layer 5 to prevent over-etching of the barrier layer 5, and can better control the quality of the device structure.

[0074] The heat dissipation layer 6 is a single crystal diamond film or a silicon carbide film. When the heat dissipation layer 6 is a single crystal diamond film, a single crystal diamond film is grown on other polycrystalline diamond substrates, and the single crystal diamond film is bonded to the barrier layer 5 before the polycrystalline diamond substrate is removed. When the heat dissipation layer 6 is a silicon carbide film, a silicon carbide film is grown on other silicon carbide substrates, and the silicon carbide film is bonded to the barrier layer 5 before the silicon carbide substrate is removed.

[0075] The thickness of the heat dissipation layer 6 is 200 nm-700 nm. The thickness of the heat dissipation layer 6 is selected according to actual needs and no specific requirements are made here.

[0076] The above-mentioned cap layer 7 is arranged on the barrier layer 5 and the heat dissipation layer 6. When preparing the cap layer 7, according to the design requirements, the heat dissipation layer 6 and the barrier layer 5 are etched at a position point to remove the heat dissipation layer 6, and a part of the barrier layer 5 is etched away to form a groove. A part of the cap layer 7 is located in the groove, in contact with the barrier layer 5, and protrudes out of the heat dissipation layer 6 and in contact with the heat dissipation layer 6. Specifically, the cap layer 7 is a double-layer groove gate structure, including a first groove gate layer and a second groove gate layer stacked together, the first groove gate layer is located in the groove, one side of the first groove gate layer is in contact with the barrier layer 5 of the groove, the other side of the first groove gate layer is in contact with the first side of the second groove gate layer, and the first side of the second groove gate layer is in contact with the heat dissipation layer 6, that is, along the heat dissipation layer 6 to the outside direction, the second groove gate layer is arranged on the first groove gate layer and the heat dissipation layer 6, the first groove gate layer is located in the groove on the barrier layer 5 and the heat dissipation layer 6, one side of the first groove gate layer is in contact with the barrier layer 5, and the other side is flush with the upper surface of the heat dissipation layer 6, the number of first groove gate layers is adapted to the number of grooves on the barrier layer 5 and the heat dissipation layer 6, a first groove gate layer is arranged in each groove, the second groove gate layer is arranged on the heat dissipation layer 6, and the second groove gate layer covers each first groove gate layer, the second groove gate layer is in contact with the first groove gate layer in the groove, and the second groove gate layer is in contact with the heat dissipation layer 6 without a groove. The provision of the cap layer 7 of the double-layer trench gate structure can effectively increase the threshold voltage of the device, so that the threshold voltage of the device can reach 2.5-3.5V, enriching the high-power application scenarios of the p-GaN HEMT device.

[0077] The cap layer 7 is GaN doped with a P-type dopant, and the doping concentration of the P-type dopant is 1×10 17 -8×10 17 cm -3 , and are deposited on the barrier layer 5 and the heat dissipation layer 6 by MOCVD, that is, the first groove gate layer and the second groove gate layer are made of the same material, both of which are gallium nitride doped with P-type dopants. The first groove gate layer is formed by depositing in the grooves on the barrier layer 5 and the heat dissipation layer 6 by MOCVD, and the second groove gate layer is formed by depositing on the first groove gate layer and the heat dissipation layer 6 by MOCVD.

[0078] In some feasible embodiments, the P-type dopant is preferably magnesium.

[0079] In some feasible embodiments, the thickness of the first trench gate layer is adapted to the depth of the trench, and the thickness of the first trench gate layer is 8-13 nm. The thickness of the first trench gate layer is selected according to actual needs, and no specific requirements are made here.

[0080] In some feasible embodiments, the thickness of the second trench gate layer is 90-130 nm. The thickness of the second trench gate layer is selected according to actual needs and no specific requirements are made here.

[0081] The above-mentioned passivation layer 8 is arranged on the heat dissipation layer 6, the passivation layer 8 is arranged between the source electrode 10 and the cap layer 7, and the passivation layer 8 is arranged between the drain electrode 11 and the cap layer 7. Since the cap layer 7 protrudes from the heat dissipation layer 6, the passivation layer 8 is arranged on the heat dissipation layer 6 between the source electrode 10 and the cap layer 7, and the passivation layer 8 is arranged on the heat dissipation layer 6 between the drain electrode 11 and the cap layer 7. The passivation layer 8 is formed by deposition by plasma enhanced chemical vapor deposition.

[0082] In some feasible embodiments, the passivation layer 8 is silicon nitride, and the thickness of the passivation layer 8 is selected according to actual needs, but the passivation layer 8 does not protrude from the source 10 and the drain 11, that is, the source 10 and the drain 11 protrude from the passivation layer 8.

[0083] The gate 9 is disposed on the cap layer 7, the gate 9 protrudes from the passivation layer 8, and the gate 9 is prepared by evaporation. Along the cap layer 7 to the outside, the gate 9 includes a TiN layer, a Ti layer, an Al layer, a Ni layer and an Au layer disposed in sequence.

[0084] A method for preparing a p-GaN HEMT device, the method is used to prepare the above-mentioned p-GaN HEMT device, such as Figure 1 and 2 As shown, the following steps are included:

[0085] Preparation of substrate layer 1: The substrate layer 1 is prepared by chemical vapor deposition. The substrate layer 1 is a polycrystalline diamond substrate. The thickness of the substrate layer 1 is 300-400um. The thickness of the substrate layer 1 is selected according to actual needs and no specific requirements are made here.

[0086] Prepare a buffer layer 2 and bond the buffer layer 2 to the substrate layer 1. After the substrate layer 1 is prepared, use MOCVD to prepare the buffer layer 2 and bond the grown buffer layer 2 to the substrate layer 1. The buffer layer 2 is gallium nitride, and the thickness of the buffer layer 2 is 200-300nm. The thickness of the buffer layer 2 is selected according to actual needs, and no specific requirements are made here.

[0087] After the buffer layer 2 is prepared, P-type ion implantation is performed on the surface of the buffer layer 2 to form a P-type doped region 3, and annealing is performed. The P-type ions are magnesium ions, the implantation depth is 0.8-1.0 um, and the implantation dose is 1×10 15 -1×10 17 cm -2When annealing is performed, annealing is performed in a nitrogen atmosphere at a temperature of 850°C-1150°C. The annealing temperature is selected according to actual needs and no specific requirements are given here. P-type ions are injected into the buffer layer 2 to form a P-type doped sub-region 30. Multiple P-type doped sub-regions 30 form a P-type doped region 3, which can effectively modulate the electric field at the 2DEG channel, alleviate the temperature rise caused by electric field accumulation, enhance the thermal management capability of the device itself, improve the stability and reliability of the device, and extend the working life of the device.

[0088] When performing P-type ion implantation, the shape of the P-type doped sub-region 30 is selected as a hexagon, and the number of the P-type doped region 3 groups is selected, and P-type ion implantation is performed in the implantation area close to the two side edges along the first direction FA of the buffer layer 2 to form a P-type doped region 3.

[0089] Prepare the channel layer 4 on the buffer layer 2: grow the channel layer 4 on the buffer layer 2 by MOCVD. The channel layer 4 is gallium nitride. The thickness of the channel layer 4 is 50-150nm. The thickness of the channel layer 4 is selected and set according to actual needs, and no specific requirements are made here.

[0090] Preparing a barrier layer 5 on the channel layer 4: After the channel layer 4 is prepared, a barrier layer 5 is grown on the channel layer 4 by MOCVD. The barrier layer 5 is aluminum gallium nitride, and the thickness of the barrier layer 5 is 10-20 nm. The thickness of the barrier layer 5 is selected according to actual needs, and no specific requirements are made here.

[0091] Prepare a heat dissipation layer 6 and bond the heat dissipation layer 6 to the barrier layer 5. The heat dissipation layer 6 can be a single crystal diamond film or a silicon carbide film. The material of the heat dissipation layer 6 is selected according to actual needs. The heat dissipation layer 6 is grown on a substrate. After the heat dissipation layer 6 is bonded to the barrier layer 5, the substrate is removed. When the heat dissipation layer 6 is a single crystal diamond film, a single crystal diamond film is first prepared, and a single crystal diamond film is grown on other polycrystalline diamond substrates to form a single crystal diamond film, and then the single crystal diamond film is bonded to the barrier layer 5 by bonding, and the polycrystalline diamond substrate is removed, a layer of single crystal diamond film is formed on the barrier layer 5, and the single crystal diamond film is bonded to the gallium nitride aluminum barrier layer 5 by bonding. Since the bonding rate of diamond and gallium nitride reaches more than 92%, the number of defects and interface thermal resistance at the heterojunction interface can be effectively reduced, the heat dissipation capacity of 2DEG at the device channel can be improved, and the mechanical properties of the device can be enhanced. At the same time, the heat dissipation layer 6 can prevent magnesium ions from diffusing to the barrier layer 5 and the channel layer 4 at a high temperature of more than 1000°C. Similarly, when the heat dissipation layer 6 is a silicon carbide film, a layer of silicon carbide film is grown on other silicon carbide substrates, and the silicon carbide film is bonded to the barrier layer 5 and then the silicon carbide substrate is removed.

[0092] The thickness of the heat dissipation layer 6 is 200 nm-700 nm. The thickness of the heat dissipation layer 6 is selected according to actual needs and no specific requirements are made here.

[0093] The heat dissipation layer 6 and the barrier layer 5 are etched to form grooves. The heat dissipation layer 6 and the barrier layer 5 are etched by plasma etching. According to design requirements, the heat dissipation layer 6 and part of the barrier layer 5 are etched away at corresponding positions to form a groove structure. The bottom of the groove is the barrier layer 5, the sidewalls of the groove are the barrier layer 5 and the heat dissipation layer 6, and both sides of the top opening of the groove are the heat dissipation layer 6. The number and setting method of the grooves are selected according to actual needs.

[0094] A cap layer 7 is prepared on the barrier layer 5 at the groove and on the heat dissipation layer 6 outside the groove. The cap layer 7 is located in the groove. At the same time, the cap layer 7 is also located on the heat dissipation layer 6 outside the groove. The cap layer 7 is a double-layer trench gate structure, including a first trench gate layer and a second trench gate layer. The first trench gate layer is deposited by MOCVD, and the first trench gate layer is located in the groove. The second trench gate layer is deposited by MOCVD, and the second trench gate layer is located on the first trench gate layer and the heat dissipation layer 6. The cap layer 7 with a double-layer trench gate structure can increase the threshold voltage of the device, and the threshold voltage can reach 2.5-3.5V, enriching the high-power application scenarios of the device.

[0095] The cap layer 7 is gallium nitride doped with a P-type dopant, wherein the P-type dopant is magnesium with a doping concentration of 1×10 17 -8×10 17 cm -3 .

[0096] The thickness of the first trench gate layer is adapted to the depth of the trench, the thickness of the first trench gate layer is 8-13nm, the thickness of the second trench gate layer is 90-130nm, and the thickness of the first trench gate layer and the thickness of the second trench gate layer are selected according to actual needs, and no specific requirements are made here.

[0097] Preparation of passivation layer 8: After the cap layer 7 is prepared, a passivation layer 8 is deposited on the surface of the device after the cap layer 7 is prepared by plasma enhanced chemical vapor deposition, and the passivation layer 8 is etched to remove the passivation layer 8 on the cap layer 7 and the channel layer 4, leaving only the passivation layer 8 on the heat dissipation layer 6, which is silicon nitride. Due to the provision of the heat dissipation layer 6, the heat dissipation layer 6 can serve as an etching stop layer to prevent the barrier layer 5 from being etched, and can better control the quality of the device structure.

[0098] A source electrode 10 and a drain electrode 11 are prepared on the channel layer 4. After the passivation layer 8 is prepared, the source electrode 10 and the drain electrode 11 are prepared by evaporation on the portion of the channel layer 4 where the barrier layer 5 is not provided. On the channel layer 4, a Ti layer, an Al layer, a Ni layer and an Au layer are sequentially evaporated along the channel layer 4 to the outside to form the source electrode 10 and the drain electrode 11, respectively. The source electrode 10 and the drain electrode 11 are respectively located on both sides of the barrier layer 5.

[0099] A gate 9 is prepared on the cap layer 7. After the source 10 and the drain 11 are prepared, a TiN layer, a Ti layer, an Al layer, a Ni layer and an Au layer are sequentially evaporated on the cap layer 7 along the cap layer 7 to the outside to form a gate 9.

[0100] The device preparation is completed to obtain a p-GaN HEMT device.

[0101] Due to the adoption of the above technical solution, a heat dissipation layer is provided, and the heat dissipation layer is a single crystal diamond film, which is grown on a polycrystalline diamond substrate, and the single crystal diamond film is bonded to the barrier layer by a bonding technology. Since the bonding rate between the single crystal diamond film and the gallium nitride barrier layer reaches more than 92%, the number of defects and the interface thermal resistance at the heterojunction interface can be effectively reduced, the heat dissipation capacity of the 2DEG at the device channel can be improved, and the mechanical properties of the device can be enhanced, and the influence of the interface reaction and defects on the working performance of the device can be reduced; the substrate layer of the device is a polycrystalline diamond substrate, and there is no need to change the device manufacturing process. The heat dissipation effect of the device is improved by setting the heat dissipation layer and the substrate layer; the buffer layer is formed with a P-type doped region by ion implantation, and the P-type doped The setting of the zone can effectively modulate the electric field at the 2DEG channel, alleviate the temperature rise caused by the accumulation of the electric field, further enhance the thermal management capability of the device itself, improve the stability and reliability of the device, and extend the service life of the device. At the same time, the setting of the heat dissipation layer can be used as a film layer to effectively prevent the diffusion of magnesium ions to the barrier layer and the channel layer at a high temperature above 1000°C, and as an etching barrier layer to prevent over-etching of the barrier layer, so as to better control the quality of the device structure; the cap layer is a double-layer trench gate structure, which can effectively increase the threshold voltage of the device compared with the traditional structure. The threshold voltage can reach 2.5-3.5V, enriching the high-power application scenarios of the device, and also making the 2DEG discontinuity more obvious, enhancing the gate control capability of the device.

[0102] The embodiments of the present invention are described in detail above, but the contents described are only preferred embodiments of the present invention and cannot be considered to limit the scope of implementation of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of the patent coverage of the present invention.

Claims

1. A p-GaN HEMT device, characterized in that: include, substrate layer; A buffer layer is provided on the substrate layer, wherein a P-type doping region is provided on a side of the buffer layer away from the substrate layer; A channel layer is disposed on the buffer layer, wherein the channel layer is in contact with the P-type doped region; A barrier layer, a source electrode and a drain electrode are arranged on the channel layer, wherein the source electrode and the drain electrode are arranged on both sides of the barrier layer; A heat dissipation layer provided on the barrier layer: the heat dissipation layer is a single crystal diamond film or a silicon carbide film, and the heat dissipation layer is bonded to the barrier layer by bonding; A cap layer disposed on the barrier layer and the heat dissipation layer; A passivation layer disposed on the heat dissipation layer, wherein the passivation layer is disposed between the source electrode and the cap layer and between the drain electrode and the cap layer; A gate is disposed on the cap layer.

2. The p-GaN HEMT device according to claim 1, characterized in that: The P-type doped region is arranged in the injection region close to the two side edges along the first direction of the buffer layer. In any injection region, the P-type doped region includes multiple groups of P-type doped region groups, and the multiple groups of P-type doped region groups are arranged in sequence along the first direction of the buffer layer. Each group of P-type doped region groups includes multiple P-type doped sub-regions, and the multiple P-type doped sub-regions are arranged in sequence along the second direction of the buffer layer, and the first direction is arranged perpendicular to the second direction.

3. The p-GaN HEMT device according to claim 2, characterized in that: The plurality of P-type doped sub-regions in two adjacent groups of the P-type doped region groups are arranged in an alternating manner.

4. The p-GaN HEMT device according to claim 2 or 3, characterized in that: The shape of the P-type doped sub-region is polygonal or circular.

5. The p-GaN HEMT device according to any one of claims 1 to 3, characterized in that: The cap layer includes a first grooved gate layer and a second grooved gate layer stacked together, wherein the first grooved gate layer is arranged on the barrier layer, and one side of the first grooved gate layer is located in the barrier layer, the other side of the first grooved gate layer contacts the first side of the second grooved gate layer, and the first side of the second grooved gate layer contacts the heat dissipation layer.

6. The p-GaN HEMT device according to claim 5, characterized in that: The cap layer is gallium nitride doped with a P-type dopant, the P-type dopant is magnesium, and the doping concentration of the P-type dopant is 1×10 17 -8×10 17 cm -3 .

7. The p-GaN HEMT device according to claim 6, characterized in that: The thickness of the first groove gate layer is 8-13 nm, and the thickness of the second groove gate layer is 90-130 nm.

8. The p-GaN HEMT device according to any one of claims 1 to 3 and 6 to 7, characterized in that: The thickness of the heat dissipation layer is 200nm-700nm.

9. The p-GaN HEMT device according to claim 8, characterized in that: The substrate layer is a polycrystalline diamond substrate, and the thickness of the substrate layer is 300-400um.

10. The p-GaN HEMT device according to claim 9, characterized in that: The buffer layer and the channel layer are both made of gallium nitride, the buffer layer has a thickness of 200-300 nm, and the channel layer has a thickness of 50-150 nm.

11. The p-GaN HEMT device according to claim 10, characterized in that: The barrier layer is aluminum gallium nitride, and the thickness of the barrier layer is 10-20 nm.

12. The p-GaN HEMT device according to any one of claims 9 to 11, characterized in that: Along the channel layer to the outside, the source and the drain both include a Ti layer, an Al layer, a Ni layer and an Au layer arranged in sequence; along the cap layer to the outside, the gate includes a TiN layer, a Ti layer, an Al layer, a Ni layer and an Au layer arranged in sequence.

13. The p-GaN HEMT device according to claim 12, characterized in that: The passivation layer is silicon nitride.

14. A method for preparing a p-GaN HEMT device, characterized in that: The following steps are included: preparing a substrate layer; preparing a buffer layer, and bonding the buffer layer to the substrate layer; Performing P-type ion implantation on the surface of the buffer layer to form a P-type doped region, and performing annealing treatment; preparing a channel layer on the buffer layer; preparing a barrier layer on the channel layer; Prepare a heat dissipation layer, and bond the heat dissipation layer to the barrier layer, wherein the heat dissipation layer is a single crystal diamond film or a silicon carbide film; Etching the heat dissipation layer and the barrier layer to form grooves; preparing a cap layer on the barrier layer at the groove and on the heat dissipation layer outside the groove; preparing a passivation layer; A source electrode and a drain electrode are prepared on the channel layer, and a gate electrode is prepared on the cap layer.

15. The method for preparing a p-GaN HEMT device according to claim 14, characterized in that: The substrate layer is prepared by chemical vapor deposition, and the substrate layer is a polycrystalline diamond substrate.

16. The method for preparing a p-GaN HEMT device according to claim 14 or 15, characterized in that: The buffer layer and the channel layer are both gallium nitride, and the buffer layer and the channel layer are prepared by MOCVD method respectively; The barrier layer is aluminum gallium nitride, and the barrier layer is prepared by MOCVD; The cap layer is gallium nitride doped with a P-type dopant, and the cap layer is prepared by MOCVD.

17. The method for preparing a p-GaN HEMT device according to claim 16, characterized in that: P-type ion implantation is performed on the surface of the buffer layer to form a P-type doping region, and an annealing treatment step is performed in a nitrogen atmosphere at a temperature of 850° C.-1150° C.

18. The method for preparing a p-GaN HEMT device according to claim 14, 15 or 17, characterized in that: The P-type ions are magnesium ions, the injection junction depth is 0.8-1.0um, and the injection dose is 1×10 15 -1×10 17 cm -2 .

19. The method for preparing a p-GaN HEMT device according to claim 14 or 15, characterized in that: The heat dissipation layer is a single crystal diamond film or a silicon carbide film, which is grown on a substrate and is removed after the heat dissipation layer is bonded to the barrier layer.

20. The method for preparing a p-GaN HEMT device according to claim 14 or 15, characterized in that: The passivation layer is deposited by plasma enhanced chemical vapor deposition, and the passivation layer on the channel layer and the cap layer is removed by etching.

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