High-thermal-conductivity silicon carbide single crystal substrate as well as preparation method and application thereof

Abstract

According to the high-thermal-conductivity silicon carbide single crystal substrate and the preparation method and application thereof provided by the invention, impurity introduction and defect formation are effectively inhibited by optimizing raw material purity, improving thermal field design and regulating and controlling growth kinetic parameters and a post-treatment process, and thermal conductivity close to a theoretical limit is realized. Meanwhile, the invention further provides a controllable preparation method of the high-thermal-conductivity SiC substrate and application of the high-thermal-conductivity SiC substrate in advanced electronic packaging, the substrate serves as a key heat dissipation and bearing material in high-power-density electronic packaging by means of the ultrahigh thermal conductivity of the substrate and the low thermal expansion coefficient matched with a semiconductor chip, and the high-power-density SiC substrate can be applied to high-power-density electronic packaging. The method is suitable for manufacturing an intermediate layer, a thermal diffusion layer, a chip bearing substrate or a packaging integrated substrate and the like, and can effectively solve the problems of heat dissipation and reliability of high-power-density chips (such as high-performance computing chips and power modules).

Description

Technical Field

[0001] This invention belongs to the field of semiconductor materials and advanced packaging technology, specifically relating to a high-purity, low-defect 4H-type silicon carbide (SiC) single crystal substrate with a thermal conductivity greater than 500 W / (m·K), its controllable growth preparation method, and the application of this substrate in high-power, high-density electronic packaging as a key heat dissipation and load-bearing structure (such as an interposer, heat diffusion layer, packaging substrate, or chip carrier substrate). Background Technology

[0002] Silicon carbide (SiC), as a typical wide-bandgap semiconductor material, possesses a high breakdown electric field strength (approximately 3 MV / cm) and a high electron saturation drift velocity (approximately 2 × 10⁻⁶). 7 With its excellent thermal stability and chemical inertness (cm / s), it has been widely used in high-power electronic devices in electric vehicles, 5G communication base stations, rail transit traction systems, and renewable energy conversion systems such as photovoltaic / wind power.

[0003] As chip integration and power density continue to increase, traditional packaging heat dissipation materials face a fundamental dilemma in meeting the dual requirements of "efficient thermal conductivity" and "reliable packaging," specifically manifested as "the difficulty in simultaneously achieving thermal conductivity and CTE matching." Limitations of high thermal conductivity metals: While traditional heat dissipation metals such as copper (Cu) and aluminum (Al) have high thermal conductivity (>300 W / (m·K)), their coefficient of thermal expansion (CTE > 16 ppm / K) is much higher than that of silicon chips (CTE ≈ 2.6-3 ppm / K). Under power cycling and thermal shock, the huge CTE mismatch can cause shear stress at the chip-package interface, leading to reliability issues such as solder joint fatigue cracking and interface delamination. The shortcomings of low CTE materials: Tungsten (W), molybdenum (Mo) and their copper composites (W-Cu, Mo-Cu) have low CTE (4-8 ppm / K) that can be matched with the chip, but their thermal conductivity (130-200 W / (m·K)) is limited, making it difficult to cope with future ultra-high heat flux density scenarios; Performance bottlenecks of ceramic materials: Alumina (Al2O3) is low in cost but has extremely poor thermal conductivity (<30 W / (m·K)); Aluminum nitride (AlN) has good thermal conductivity (170-260 W / (m·K)) and good CTE matching, but it is expensive and its mechanical properties and process maturity need to be improved; Silicon nitride (Si3N4) performs well in terms of strength and thermal shock resistance, but its thermal conductivity (70-90 W / (m·K)) becomes a bottleneck limiting heat dissipation efficiency; Realistic constraints of ideal materials: Although single-crystal diamond has ultra-high thermal conductivity (>2000 W / (m·K)) and extremely low CTE (~1 ppm / K), making it the most ideal heat dissipation material known to date, its manufacturing cost is extremely high, large-area single-crystal preparation is difficult, and integration with semiconductor processes is difficult, which seriously restricts its large-scale application in mainstream electronic packaging.

[0004] Against this backdrop, silicon carbide (SiC) has emerged as a highly promising solution to address the aforementioned challenges due to its balanced and excellent overall performance. SiC achieves an optimal balance between thermal conductivity (270-330 W / (m·K)) and CTE (3.7-4.0 ppm / K).

[0005] Studies have shown that silicon carbide (SiC) has great potential as an electronic packaging material and integrated heat dissipation substrate material due to its excellent thermal conductivity, CTE (which is highly matched to the chip and ensures long-term thermal cycling reliability), mature semiconductor manufacturing process foundation, and significant cost advantage over diamond. It is expected to provide efficient and reliable heat dissipation solutions for high power density chips.

[0006] Currently, the thermal conductivity of SiC single crystal substrates in the industry is generally 250-350 W / (m·K). The low thermal conductivity is mainly due to the following factors: Impurity contamination: Shallow-level doping elements (such as nitrogen (N), boron (B), aluminum (Al), and vanadium (V)) introduced to regulate electrical performance can achieve n-type or p-type conductivity, but they will significantly enhance phonon scattering, thereby suppressing lattice thermal conduction. Crystal defects include micropipes, dislocations (such as base plane dislocations (BPDs), screw dislocations (TEDs), and stacking faults), which disrupt lattice periodicity, intensify phonon-defect interactions, and reduce thermal transport efficiency. Polymorphism: If not properly controlled during crystal growth, non-target polymorphic phases such as 3C-SiC and 6H-SiC may appear, causing local lattice mismatch and increased interfacial thermal resistance, which further degrades the overall thermal conductivity. Growth process limitations: The currently mainstream physical vapor transport (PVT) method with single-zone heating has problems such as large temperature gradient, fast growth rate and uneven thermal field. It is easy to introduce residual stress, dislocation multiplication and impurity segregation into the crystal, which restricts the controllable preparation of high-quality, high thermal conductivity SiC single crystals.

[0007] The aforementioned problems collectively make it difficult for existing SiC substrates to meet the urgent need for efficient thermal management in next-generation high-power-density, high-junction-temperature (>200°C) semiconductor devices. Therefore, there is an urgent need to develop a high-quality SiC single-crystal substrate and its stable fabrication technology that can synergistically suppress impurity incorporation, reduce crystal defects, eliminate multi-type hybridization, and achieve a thermal conductivity exceeding 500 W / (m·K). Summary of the Invention

[0008] The purpose of this invention is to provide a high-purity, low-defect silicon carbide single-crystal substrate with a thermal conductivity greater than 500 W / (m·K). By optimizing raw material purity, improving thermal field design, controlling growth kinetic parameters, and post-processing, the introduction of impurities and the formation of defects are effectively suppressed, achieving thermal conductivity performance close to the theoretical limit. Simultaneously, this invention also provides a controllable preparation method for this high thermal conductivity SiC substrate and its application in advanced electronic packaging. Utilizing its ultra-high thermal conductivity and low coefficient of thermal expansion matching semiconductor chips, this substrate serves as a key heat dissipation and support material in high-power-density electronic packaging. It is suitable for manufacturing interposers, heat diffusion layers, chip support substrates, or integrated packaging substrates, effectively solving the heat dissipation and reliability problems of high-power-density chips (such as high-performance computing chips and power modules).

[0009] Technical solution In a first aspect, the present invention provides a silicon carbide single crystal substrate with a thermal conductivity >500W / (m·K) at room temperature (25°C); The silicon carbide single crystal substrate is of the 4H-SiC crystal form; The silicon carbide single crystal substrate is a single 4H-SiC crystal form, and no 3C-SiC or 6H-SiC impurity phases were detected by X-ray diffraction analysis; The vanadium impurity concentration in the silicon carbide single crystal substrate is ≤1×10⁻⁶. 14 cm⁻³, aluminum impurity concentration ≤5×10⁻⁶ 15 cm⁻³, boron impurity concentration ≤ 1×10⁻⁶ 16 cm⁻³, nitrogen impurity concentration ≤ 5×10 ¹6 cm⁻³ The silicon carbide single crystal substrate has a microtube density ≤ 0.1 cm⁻² and a total dislocation density ≤ 1000 cm⁻². Furthermore, the silicon carbide single-crystal substrate can be processed into different planar geometries according to the needs of the end application scenario, including but not limited to circles, squares, rectangles, or polygons. For example, when used for wafer-level advanced packaging, the standard circular wafer shape (such as 2-18 inch diameter) can be retained; while when used as a customized heat sink or interposer embedded module, it can be cut into rectangles or squares to match the chip layout, improving space utilization and heat conduction path efficiency.

[0010] The silicon carbide single crystal substrate provided by this invention achieves a thermal conductivity exceeding 500 W / (m·K) for the first time by synergistically controlling impurity concentration, defect density, and crystal purity. The high thermal conductivity significantly reduces the operating temperature rise of devices, extends their lifespan, and supports higher power density integration.

[0011] Secondly, the present invention also provides a method for preparing a silicon carbide single crystal substrate, comprising the following steps: Step 1: Deep purification of silicon carbide powder: (1) Place high-purity silicon carbide powder in a reactor, introduce halogen gas, and react at 1800-2200℃ for 1-4 hours; (2) The halogen-purified powder is vacuum distilled for 1-4 hours at 2200-2500℃ and a vacuum degree of <10-3Pa; (3) The distilled powder is subjected to in-situ carbonization treatment and kept at 2000°C or above for 1-4 hours in an Ar atmosphere.

[0012] Preferably, the halogen gas is selected from at least one of Cl2 and HCl, and may optionally be mixed with an inert gas, wherein the inert gas is argon or helium.

[0013] Step 2: Silicon carbide crystal growth:

[0014] The crystal was grown using the physical vapor transport method, with the following specific settings: (1) Crucible and hot zone design: High-purity fine-grained graphite crucibles with tantalum carbide or chromium carbide coating on the inner wall are used. Multi-zone independent temperature control and electromagnetic coupling auxiliary heating technology are adopted. The axial temperature gradient is controlled at 5-15℃ / cm and the radial temperature gradient is controlled at 2-8℃ / cm. (2) Growth parameter settings: At a crystal growth temperature of 2100-2300°C, the growth rate is strictly controlled at 50-150 μm / h; (3) Atmosphere and pressure settings: High-purity argon (Ar) is introduced into the growth chamber as a carrier gas, and hydrogen and / or helium with a volume fraction of 0.1%–1% are added. The system pressure is maintained in the low pressure range of 5–20 Torr. Preferably, the multi-zone independent temperature control technology refers to setting at least three independently temperature-controlled resistance heating zones along the axial direction around the periphery of the growth crucible, and more preferably four independently temperature-controlled resistance heating zones. Preferably, there are four independently temperature-controlled resistive heating zones, namely... Top cover area: Located above the seed crystal end of the crucible, used to control the back temperature of the seed crystal and suppress the condensation of the raw material gas phase at the top; Upper heat preservation zone: Located in the crystal growth zone of the crucible (the area where the seed crystal is located), its temperature directly determines the growth interface temperature; Medium heat preservation zone: Located in the raw material sublimation zone of the crucible (the area where the raw material is located), its temperature is the core that determines the raw material sublimation rate and gas phase supersaturation. Lower insulation zone: Located below the raw material end of the crucible, used to adjust the heat flow at the bottom of the crucible and the longitudinal temperature gradient.

[0015] Preferably, the electromagnetic coupling assisted heating technology involves coaxially mounting a segmented induction coil around the periphery of the resistance heating system; this coil is divided into at least upper and lower sections, each with independently adjustable power. Preferably, the upper coil corresponds to the seed crystal and crystal growth region; the lower coil corresponds to the raw material powder region.

[0016] Resistance heating provides a stable and uniform background thermal field; induction heating provides rapid and local power fine-tuning capabilities, and is particularly good at compensating for dynamic changes in the thermal field caused by raw material consumption and crystal growth.

[0017] Step 3: High-temperature annealing of silicon carbide crystals: After the silicon carbide crystals have been grown, they are placed in a graphite crucible with tantalum carbide coating on the inner wall. Under the protection of high-purity argon (Ar) or helium (He), or under a vacuum of <10-4 Pa, the ingots are rapidly heated to an extremely high temperature of 2150-2300°C and held at that temperature for 30-120 minutes.

[0018] Step 4: Silicon carbide substrate processing:

[0019] (1) Crystal orientation and cutting: X-ray orientation is used to perform diamond multi-wire cutting along the (0001) deflection angle 0-8°; (2) Grinding and polishing: Under low pressure and low speed conditions, diamond abrasive rough grinding and chemical mechanical polishing (CMP) are performed in sequence; the pressure range of rough grinding is 0.5-2.0Kg / cm2, the pressure range of fine grinding is 3-11Kg / cm2, and the rotation speed of the grinding wheel is 30-80rpm; the pressure range of chemical mechanical polishing is 0.05-0.14Kg / cm2, and the polishing wheel is 20-60rpm. Finally, the silicon carbide single crystal substrate is obtained after cleaning.

[0020] In the method for preparing silicon carbide single crystal substrates provided by this invention: (1) Purification is achieved using a halogen mixed gas. The halogen gas reacts with metallic impurities (such as Al, Fe, Ti) and B, N, etc., in the powder to form volatile halides (such as BCl3, AlCl3, FeCl3, TiCl4), which are carried away by the gas flow. The extracted silicon carbide powder is then subjected to in-situ carbonization treatment, which causes excess Si in the powder to volatilize, thus inhibiting the excessive formation of Si or C vacancies from the source.

[0021] (2) During the growth of silicon carbide crystals, the inner wall of the crucible is coated with tantalum carbide or chromium carbide to isolate the diffusion of graphite impurities into the raw materials and crystals. The axial and radial temperature gradients are controlled within an extremely low range to achieve near-isothermal transport and growth conditions. The crystal growth rate is strictly controlled, and the supersaturation of the growth front is greatly reduced through the "subslow growth" mode, which facilitates the orderly arrangement of lattice atoms, the exclusion of impurity incorporation, and the closure and transformation of defects (especially BPDs). During the crystal growth process, trace amounts of hydrogen and / or helium are incorporated into the carrier. Hydrogen helps to reduce oxygen-containing impurities in the gas phase, and the high thermal conductivity of helium can improve the uniformity of the local thermal field. The system pressure is maintained in a low pressure range of 5-20 Torr, which is conducive to impurity volatilization and uniform transport of gas phase components.

[0022] (3) In a graphite crucible with tantalum carbide coating on the inner wall, the crystal is annealed in an inert atmosphere at a high temperature and ultrafast. This process can effectively promote the recombination of point defects (vacancies and interstitial atoms), induce dislocations (especially BPDs) to recombine and annihilate through climb and cross-slip, and at the same time promote the diffusion and volatilization of residual light element impurities (such as N and B) to the grain boundary or surface, thereby significantly reducing the crystal defect density and harmful impurity concentration as a whole.

[0023] (4) This invention aims to provide a high-purity, low-defect 4H-SiC single crystal substrate with a thermal conductivity greater than 500 W / (m·K), as well as its controllable preparation method and applications. Addressing the problem in existing technologies where the actual thermal conductivity of SiC substrates is far below the theoretical limit due to impurity scattering, crystal defects, and multi-type hybridization, this invention proposes a systematic, full-chain synergistic optimization technical solution. This solution is not merely an improvement of a single process, but rather a synergistic approach that overcomes multiple bottlenecks limiting the improvement of thermal conductivity through the deep coupling and mutual reinforcement of four major stages: source purification, precision growth, active repair, and final processing.

[0024] Thirdly, this invention provides the application of the silicon carbide single crystal substrate in electronic packaging, serving as a key heat dissipation and load-bearing structure in high-power, high-density electronic packaging, applicable to various packaging heat dissipation material scenarios, including but not limited to: Intermediate layers or embedded heat dissipation layers in 2.5D / 3D advanced packaging are applied to integrated packaging systems to reduce the cumulative thermal resistance of the internal thermal path of the chip, alleviate the problem of local "hot spots", and improve the thermal management capability and power density of the packaging system. The insulating heat dissipation substrate of the power module replaces the traditional alumina (Al2O3), aluminum nitride (AlN) or metal matrix composite materials, directly supporting wide bandgap power devices such as SiC MOSFET and GaN HEMT, achieving high thermal conductivity and electrical insulation integration. The packaging carrier for high-frequency / millimeter-wave radio frequency devices utilizes the synergistic advantages of low dielectric loss and high thermal conductivity to reduce signal attenuation and stabilize operating temperature. Packaging components for high-reliability electronic systems used in aerospace, electric vehicles, or rail transportation maintain dimensional stability under extreme thermal cycling conditions, avoiding solder joint cracking or delamination failure due to CTE mismatch; As part of a composite material, it can be used in combination with other high thermal conductivity materials (such as diamond / Cu composites) to further optimize the matching degree of thermal conductivity and CTE, and meet the needs of specific application scenarios.

[0025] This application fully leverages the combined advantages of SiC materials in terms of heat, force, and electricity, and is expected to become a key thermal management material for next-generation high-power systems such as high-performance computing, AI chips, and 5G RF modules. Detailed Implementation

[0026] Example 1

[0027] A method for preparing a silicon carbide single crystal substrate, comprising the following steps: Step 1: Deep purification of silicon carbide powder: High-purity silicon carbide powder was loaded into a graphite reaction boat and placed in a high-temperature halogenation furnace. A mixture of Cl2 and argon gas was introduced at a flow rate of 2 L / min, and the reaction was carried out at 2000 °C for 2 h. Subsequently, the vacuum was evacuated to <10-3 Pa, the temperature was raised to 2300 °C, and vacuum distilled for 3 h. After cooling, in-situ carbonization was carried out in an Ar atmosphere at a temperature above 2100 °C for 2 h.

[0028] Step 2: Crystal growth Crystals were grown using the physical vapor transport method, employing a high-purity fine-grained graphite crucible with an inner wall coated with tantalum carbide. A four-zone independent temperature control system with electromagnetic coupling assisted heating was designed. In the four-zone independent temperature control, the upper cover zone temperature was set at 2000-2100℃, the upper insulation zone at 2200-2300℃, the middle insulation zone at 2250-2350℃, and the lower insulation zone at 2230-2330℃. In the electromagnetic coupling assisted heating system, the upper section of the induction coil had a power of 1.8kW, and the lower section had a power of 2.2kW. At the crystal growth temperature of 2100-2300℃, the growth rate was strictly controlled at 100 μm / h. High-purity argon (Ar) is introduced into the growth chamber as a carrier gas, and a mixture of hydrogen (H2) and helium (He) is added (hydrogen accounts for 0.5% by volume and helium accounts for 0.3% by volume). The system pressure is maintained in a low pressure range of 12 Torr. Step 3: High-temperature annealing of silicon carbide crystals: After the silicon carbide crystals have been grown, they are placed in a graphite crucible with tantalum carbide coating on the inner wall. Under the protection of high-purity argon (Ar) gas, the ingots are rapidly heated to an extremely high temperature of 2200°C and held at that temperature for 90 minutes.

[0029] Step 4: Silicon carbide substrate processing: X-ray orientation was used for diamond multi-wire cutting along the (0001) direction at an angle of 4°; rough grinding with diamond abrasive was performed at a pressure of 1.2 kg / cm² and a rotation speed of 50 rpm; fine grinding with diamond abrasive was performed at a pressure of 7 kg / cm² and a rotation speed of 60 rpm; chemical mechanical polishing (CMP) was performed with alkaline colloidal SiO2 polishing solution (pH=10.5) at a pressure of 0.1 kg / cm² and a rotation speed of 40 rpm for 60 min; final cleaning was performed, followed by SC1 → SC2 → supercritical CO2 drying to obtain a silicon carbide single crystal substrate.

[0030] Example 2 A method for preparing a silicon carbide single crystal substrate, comprising the following steps: Step 1: Deep purification of silicon carbide powder: High-purity silicon carbide powder was loaded into a graphite reaction boat and placed in a high-temperature halogenation furnace. A mixture of HCl and helium gas was introduced at a flow rate of 1 L / min, and the reaction was carried out at 1800 °C for 4 h. Subsequently, the vacuum was evacuated to <10-3 Pa, the temperature was raised to 2200 °C, and vacuum distilled for 4 h. After cooling, in-situ carbonization was carried out at 2200 °C for 1 h in an Ar atmosphere.

[0031] Step 2: Crystal growth Crystals were grown using the physical vapor transport method, employing a high-purity fine-grained graphite crucible with an inner chromium carbide coating. A four-zone independent temperature control system with electromagnetic coupling was designed. In the four-zone independent temperature control, the upper cover zone temperature was set at 2000-2100℃, the upper insulation zone at 2200-2300℃, the middle insulation zone at 2250-2350℃, and the lower insulation zone at 2230-2330℃. In the electromagnetic coupling auxiliary heating system, the upper section of the induction coil had a power of 2.0kW, and the lower section had a power of 2.4kW. At the crystal growth temperature of 2100-2300℃, the growth rate was strictly controlled at 50 μm / h. High-purity argon (Ar) is introduced into the growth chamber as a carrier gas, and hydrogen (H2) is added (hydrogen volume percentage is 0.1%), and the system pressure is maintained in a low pressure range of 5 Torr; Step 3: High-temperature annealing of silicon carbide crystals: After the silicon carbide crystals have been grown, they are placed in a graphite crucible with tantalum carbide coating on the inner wall. Under the protection of high-purity argon (Ar) gas, the ingots are rapidly heated to an extremely high temperature of 2150°C and held at that temperature for 120 minutes.

[0032] Step 4: Silicon carbide substrate processing: X-ray orientation was used for diamond multi-wire cutting along the (0001) direction at an 8° angle; rough grinding with diamond abrasive was performed at a pressure of 0.5 kg / cm² and a rotation speed of 80 rpm; fine grinding with diamond abrasive was performed at a pressure of 3 kg / cm² and a rotation speed of 80 rpm; chemical mechanical polishing (CMP) was performed with alkaline colloidal SiO2 polishing solution (pH=10.5) at a pressure of 0.05 kg / cm², a rotation speed of 60 rpm, and a time of 70 min; final cleaning was performed, followed by SC1 → SC2 → supercritical CO2 drying to obtain a silicon carbide single crystal substrate.

[0033] Example 3 A method for preparing a silicon carbide single crystal substrate, comprising the following steps: Step 1: Deep purification of silicon carbide powder: High-purity silicon carbide powder was loaded into a graphite reaction boat and placed in a high-temperature halogenation furnace. A mixed gas of Cl2, HCl and argon was introduced at a flow rate of 3 L / min, and the reaction was carried out at 2200 °C for 1 h. Subsequently, the vacuum was evacuated to <10-3 Pa, the temperature was raised to 2500 °C, and vacuum distilled for 1 h. After cooling, in-situ carbonization was carried out at 2050 °C for 4 h in an Ar atmosphere.

[0034] Step 2: Crystal growth Crystals were grown using the physical vapor transport method, employing a high-purity fine-grained graphite crucible with an inner wall coated with tantalum carbide. A four-zone independent temperature control and electromagnetic coupling auxiliary heating technology were designed. In the four-zone independent temperature control, the thermal field temperature was set at 2000-2100℃ for the upper cover zone, 2200-2300℃ for the upper insulation zone, 2250-2350℃ for the middle insulation zone, and 2230-2330℃ for the lower insulation zone. In the electromagnetic coupling auxiliary heating technology, the upper section of the induction coil had a power of 1.5kW, and the lower section had a power of 2.0kW. At the crystal growth temperature of 2100-2300℃, the growth rate was strictly controlled at 150 μm / h. High-purity argon (Ar) gas is introduced into the growth chamber as a carrier gas, and a mixed gas of helium (He) gas (helium volume percentage of 1%) is added. The system pressure is maintained in a low pressure range of 20 Torr. Step 3: High-temperature annealing of silicon carbide crystals: After the silicon carbide crystals have been grown, they are placed in a graphite crucible with tantalum carbide coating on the inner wall. Under the protection of high-purity argon (Ar) gas, the ingots are rapidly heated to an extremely high temperature of 2150°C and held at that temperature for 120 minutes.

[0035] Step 4: Silicon carbide substrate processing: X-ray orientation was used for diamond multi-wire cutting along the (0001) direction at an angle of 2°; rough grinding with diamond abrasive was performed at a pressure of 2.0 kg / cm² and a rotation speed of 30 rpm; fine grinding with diamond abrasive was performed at a pressure of 11 kg / cm² and a rotation speed of 30 rpm; chemical mechanical polishing (CMP) was performed with alkaline colloidal SiO2 polishing solution (pH=10.5) at a pressure of 0.14 kg / cm² and a rotation speed of 20 rpm for 80 min; final cleaning was performed, followed by SC1 → SC2 → supercritical CO2 drying to obtain a silicon carbide single crystal substrate.

[0036] It is worth noting that the silicon carbide single crystal ingots prepared in Examples 1–3 above, after being cut, ground, and polished, can be further cut into different shapes according to the specific needs of downstream applications. For example: When used to be compatible with standard semiconductor process lines, maintain the circular wafer form; When used as an interposer for high-power modules or 2.5D / 3D packaging, it can be laser-cut or diamond-diced into square or rectangular sheets. In special application scenarios, it can also be processed into polygons or other customized outlines.

[0037] Regardless of shape, as long as it meets the core indicators such as thermal conductivity, crystal purity, impurity concentration, and defect density described in this invention, it falls within the protection scope of this invention.

[0038] Comparative Example 1 A method for preparing a silicon carbide single crystal substrate, which differs from Example 1 in that the halogen gas removal purification step is performed in the deep purification of silicon carbide powder in step 1. Comparative Example 2

[0039] A method for preparing a silicon carbide single crystal substrate, which differs from Example 1 in that the vacuum distillation purification step is removed in the deep purification of silicon carbide powder in step 1. Comparative Example 3

[0040] A method for preparing a silicon carbide single crystal substrate, which differs from Example 1 in that the in-situ carbonization treatment step is removed in the deep purification of silicon carbide powder in step 1. Comparative Example 4

[0041] A method for preparing a silicon carbide single crystal substrate, which differs from Example 1 in that, in step 2, the four-zone independent temperature control technology is removed during the silicon carbide crystal growth process, and a resistance heating method with no zone independent temperature control is adopted. Comparative Example 5

[0042] A method for preparing a silicon carbide single crystal substrate, which differs from Example 1 in that electromagnetic coupling auxiliary heating is removed during the silicon carbide crystal growth process in step 2. Comparative Example 6

[0043] A method for preparing a silicon carbide single crystal substrate, which differs from Example 1 in that, in step 2, a carrier gas is introduced into the growth chamber to completely remove the incorporated hydrogen and helium. Comparative Example 7

[0044] A method for preparing a silicon carbide single crystal substrate, which differs from Example 1 in that the high-temperature annealing step in step 3 is omitted.

[0045] Results analysis: The silicon carbide single crystal substrates obtained in Examples 1-3 and Comparative Examples 1-7 were subjected to performance tests. The test indicators included thermal conductivity, nitrogen concentration, boron concentration, microtube density, total dislocation density, and surface roughness.

[0046] Serial Number 4H-SiC crystal area Thermal conductivity W / (mK) <![CDATA[Nitrogen concentration cm -3 > <![CDATA[Boron concentration cm -3 > <![CDATA[Vanadium concentration cm -3 > <![CDATA[Aluminum concentration cm -3 > <![CDATA[Microtubule density / cm 2 > <![CDATA[Total dislocation density cm 2 > Example 1 100% 560 <![CDATA[4×10¹ 6 cm⁻³]]> <![CDATA[1×10 15 cm⁻³]]> <![CDATA[1×10 14 cm⁻³]]> <![CDATA[4×10 15 cm⁻³]]> 0 cm⁻² 522 cm⁻² Example 2 100% 556 <![CDATA[5×10¹ 6 cm⁻³]]> <![CDATA[1×10 16 cm⁻³]]> <![CDATA[1×10 15 cm⁻³]]> <![CDATA[5×10 15 cm⁻³]]> 0cm⁻² 530 cm⁻² Example 3 100% 550 <![CDATA[5×10¹ 6 cm⁻³]]> <![CDATA[1×10 16 cm⁻³]]> <![CDATA[1×10 15 cm⁻³]]> <![CDATA[5×10 15 cm⁻³]]> 0 cm⁻² 620 cm⁻² Comparative Example 1 90% 440 <![CDATA[5×10 18 cm⁻³]]> <![CDATA[1×10 19 cm⁻³]]> <![CDATA[1×10 19 cm⁻³]]> <![CDATA[5×10 17 cm⁻³]]> 0.38cm⁻² 4510cm⁻² Comparative Example 2 90% 442 <![CDATA[5×10 18 cm⁻³]]> <![CDATA[1×10 19 cm⁻³]]> <![CDATA[1×10 19 cm⁻³]]> <![CDATA[5×10 17 cm⁻³]]> 0.40cm⁻² 4515cm⁻² Comparative Example 3 90% 438 <![CDATA[5×10 18 cm⁻³]]> <![CDATA[1×10 19 cm⁻³]]> <![CDATA[1×10 19 cm⁻³]]> <![CDATA[5×10 17 cm⁻³]]> 0.43cm⁻² 4356 cm⁻² Comparative Example 4 90% 445 <![CDATA[5×10 18 cm⁻³]]> <![CDATA[1×10 19 cm⁻³]]> <![CDATA[1×10 19 cm⁻³]]> <![CDATA[5×10 17 cm⁻³]]> 0.32cm⁻² 3518 cm⁻² Comparative Example 5 90% 452 <![CDATA[5×10 18 cm⁻³]]> <![CDATA[1×10 19 cm⁻³]]> <![CDATA[1×10 19 cm⁻³]]> <![CDATA[5×10 17 cm⁻³]]> 0.30cm⁻² 3745 cm⁻² Comparative Example 6 90% 468 <![CDATA[5×10 17 cm⁻³]]> <![CDATA[1×10 18 cm⁻³]]> <![CDATA[1×10 17 cm⁻³]]> <![CDATA[5×10 16 cm⁻³]]> 0.29cm⁻² 3280 cm⁻² Comparative Example 7 95% 470 <![CDATA[5×10 17 cm⁻³]]> <![CDATA[1×10 18 cm⁻³]]> <![CDATA[1×10 17 cm⁻³]]> <![CDATA[5×10 16 cm⁻³]]> 0.28cm⁻² 2985cm⁻² Examples 1-3, through deep purification, strict control of production conditions, and high-temperature annealing, synergistically reduce impurities, defects, and lattice mismatch in silicon carbide single crystal substrates, thereby improving the thermal conductivity of the single crystal substrates.

[0047] Compared with Example 1, the step of removing halogen gas in Comparative Example 1 resulted in an increase in impurity content, a significant decrease in thermal conductivity, and the induction of defect proliferation.

[0048] Compared with Example 1, Comparative Example 2 removes vacuum distillation purification. Vacuum distillation can further volatilize high-boiling-point impurities. Without distillation, residual impurities enter the crystal lattice during growth, disrupting periodicity, increasing defects, and reducing thermal conductivity.

[0049] Compared with Example 1, Comparative Example 3 removed the in-situ carbonization treatment. In-situ carbonization promotes the volatilization of excess Si and inhibits the formation of Si vacancies. Without the in-situ carbonization treatment, the Si / C stoichiometric ratio is unbalanced, resulting in vacancy defects, increased dislocations, and decreased thermal conductivity.

[0050] Compared with Example 1, Comparative Example 4 removed the four-zone independent temperature control and replaced it with ordinary resistance heating. The lack of zoned temperature control resulted in an excessively large and uneven axial / radial temperature gradient, unstable growth interface, and easy induction of polymorphic transformation (3C / 6H incorporation), microtubule nucleation and dislocation proliferation, which reduced thermal conductivity.

[0051] Compared to Example 1, Comparative Example 5 eliminates electromagnetic coupling-assisted heating, allowing electromagnetic induction heating to dynamically compensate for changes in the thermal field caused by raw material consumption and crystal growth. After this removal, fluctuations in the supersaturation at the growth front lead to an increase in defect density and a decrease in thermal conductivity.

[0052] Compared to Example 1, Comparative Example 6 removes the dopant gas from the growth atmosphere. Helium has high thermal conductivity, which can improve the uniformity of the local thermal field in the crucible. Removing helium causes temperature fluctuations in micro-regions and increases defects. Hydrogen can reduce impurities in the gas phase and prevent them from decomposing and introducing contamination. Removing hydrogen reduces the impurity removal ability and increases the impurity concentration. If both hydrogen and helium are removed simultaneously, both impurities and defects increase, and the thermal conductivity of the substrate decreases.

[0053] Compared with Example 1, Comparative Example 7 omits the high-temperature annealing step. High-temperature annealing can promote the recombination of point defects, the annihilation of dislocation climb, and the diffusion of impurities to the surface. Without annealing, defects are "frozen" in the crystal, resulting in a decrease in thermal conductivity.

Claims

1. A silicon carbide single crystal substrate, characterized in that, The substrate has a thermal conductivity greater than 500 W / (m·K) at room temperature (25°C).

2. The silicon carbide single crystal substrate according to claim 1, characterized in that, The substrate is of the 4H-SiC crystal form.

3. The silicon carbide single crystal substrate according to claim 2, characterized in that, The substrate is a single 4H-SiC crystal form, and no 3C-SiC or 6H-SiC impurity phases were detected by X-ray diffraction analysis.

4. The silicon carbide single crystal substrate according to claim 3, characterized in that, The vanadium impurity concentration in the substrate is ≤1×10⁻⁶. 14 cm⁻³, aluminum impurity concentration ≤5×10⁻⁶ 15 cm⁻³, boron impurity concentration ≤ 1×10⁻⁶ 16 cm⁻³ Nitrogen impurity concentration ≤ 5×10¹ 6 cm⁻³.

5. The silicon carbide single crystal substrate according to claim 4, characterized in that, The substrate Microtubule density ≤ 0.1 cm⁻², total dislocation density ≤ 1000 cm⁻².

6. A method for preparing a silicon carbide single-crystal substrate as described in any one of claims 1-5, characterized in that, The substrate obtained by the method has a thermal conductivity >500 W / (m·K) at room temperature (25°C) and includes the following steps: (1) Deep purification of silicon carbide powder: Silicon carbide powder is placed in a graphite reaction boat and reacted with halogen gas at 1800–2200°C for 1–4 h; then vacuum distilled at 2200–2500°C and vacuum degree < 10⁻³ Pa for 1–4 h; and then in-situ carbonization is carried out in Ar atmosphere at above 2000°C for 1–4 h. (2) Silicon carbide crystal growth: Physical vapor transport (PVT) was used with a high-purity fine-grained graphite crucible coated with tantalum carbide or chromium carbide on the inner wall. The axial temperature gradient was controlled at 5–15°C / cm and the radial temperature gradient at 2–8°C / cm through multi-zone independent temperature control and electromagnetic coupling auxiliary heating technology. The crystal was grown at 50–150 μm / h at 2100–2300°C. The growth atmosphere was argon carrier gas, with 0.1%–1% hydrogen and / or helium by volume. The system pressure was maintained at 5–20 Torr. (3) High-temperature annealing: The grown crystal is placed in a graphite crucible with the inner wall coated with tantalum carbide or chromium carbide, and annealed under a vacuum of < 10⁻ 4 Under the protection of Pa or high-purity Ar / He, the temperature is rapidly increased to 2150–2300°C and held for 30–120 min. (4) Substrate processing: After X-ray orientation, the substrate is cut along the (0001) surface at an angle of 0-8°, and then subjected to rough grinding, fine grinding and chemical mechanical polishing (CMP) in sequence. Finally, the substrate is cleaned and dried to obtain the substrate.

7. The preparation method according to claim 6, characterized in that, The halogen gas is selected from at least one of Cl2 and HCl, and may optionally be mixed with an inert gas, wherein the inert gas is argon or helium.

8. The preparation method according to claim 6, characterized in that, The multi-zone independent temperature control includes four independently controlled temperature resistance heating zones arranged along the axial direction of the crucible, namely: Top cover area: Located above the seed crystal end, used to suppress gas phase condensation; Upper heat preservation zone: Located in the crystal growth zone, it controls the interface temperature; Medium insulation zone: Located in the raw material sublimation zone, it controls the supersaturation of the gas phase; Lower insulation zone: Located below the raw material end, it regulates the longitudinal heat flow.

9. The preparation method according to claim 6, characterized in that, The electromagnetic coupling-assisted heating uses segmented induction coils, including at least an upper coil and a lower coil, which correspond to the crystal growth region and the raw material region, respectively, and the power can be adjusted independently.

10. The application of a silicon carbide single-crystal substrate as described in any one of claims 1-5 in electronic packaging, characterized in that: The substrate has a thermal conductivity >500 W / (m·K) and serves as a key heat dissipation and load-bearing structure in high-power, high-density electronic packaging. It is suitable for various packaging heat dissipation material scenarios, including but not limited to: Intermediate layers or embedded heat dissipation layers in 2.5D / 3D advanced packaging are used in integrated packaging systems to reduce the cumulative thermal resistance of the internal thermal path of the chip, alleviate the problem of local "hot spots", and improve the thermal management capability and power density of the packaging system. The insulating heat dissipation substrate of the power module replaces the traditional alumina (Al2O3), aluminum nitride (AlN) or metal matrix composite materials, directly supporting wide bandgap power devices such as SiC MOSFET and GaN HEMT, achieving high thermal conductivity and electrical insulation integration. The packaging carrier for high-frequency / millimeter-wave radio frequency devices utilizes the synergistic advantages of low dielectric loss and high thermal conductivity to reduce signal attenuation and stabilize operating temperature. Packaging components for high-reliability electronic systems used in aerospace, electric vehicles, or rail transportation maintain dimensional stability under extreme thermal cycling conditions, avoiding solder joint cracking or delamination failure due to CTE mismatch; As part of a composite material, it can be used in combination with other high thermal conductivity materials (such as diamond / Cu composites) to further optimize the matching degree of thermal conductivity and CTE, and meet the needs of specific application scenarios.

11. The silicon carbide single-crystal substrate according to any one of claims 1–5, characterized in that, The planar shape of the substrate is selected from any one of circular, square, rectangular or polygonal shapes, and the specific shape is determined according to its application requirements in advanced packaging or heat dissipation structures.