Semiconductor device, manufacturing method thereof and electronic equipment
By setting the etching selection ratio of the barrier layer and the conductive layer in the semiconductor memory device, the problem of inconsistent gate extension positions of different transistors is solved, the memory density and performance uniformity are improved, and a more efficient memory array is achieved performance.
Patent Information
- Application Number
- CN202310721065.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-16
- Publication Date
- 2024-12-17
AI Technical Summary
In semiconductor memory devices, in traditional vertical transistor designs, the gate extension positions of different transistors are inconsistent, resulting in poor storage density and performance uniformity, making it difficult to achieve efficient storage cell density on a limited substrate.
By setting a barrier layer and a conductive layer on the substrate, the etching selection ratio between the conductive layer and the barrier layer when forming vias is greater than 1, ensuring that the barrier layer is less likely to etch, thereby alleviating the over-etching problem and improving the process uniformity of the transistor and Storage array performance.
It effectively alleviates the over-etching problem when etching vias, improves the process uniformity of different transistors and the performance of memory arrays, especially the morphological uniformity of the gate near the substrate.
Smart Images
Figure CN119153511A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present disclosure relate to but are not limited to semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art
[0002] Semiconductor storage can be divided into volatile memory (RAM, including DRAM and SRAM, etc.) and non-volatile memory (ROM and non-ROM) based on application.
[0003] Taking DRAM as an example, the traditional known DRAM has multiple repeated "storage cells", each of which has a capacitor and a transistor. The capacitor can store 1 bit of data, and after charging and discharging, the amount of charge stored in the capacitor can correspond to the binary data "1" and "0" respectively. The transistor is the switch that controls the charging and discharging of the capacitor.
[0004] In order to reduce the cost of products as much as possible, people hope to make as many storage units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products.
[0005] The design of transistor devices is particularly important. Vertical transistors can improve storage density compared to planar transistors. Vertical transistors, especially transistors with gates extending vertically to the substrate, have attracted much attention. The gates of such transistors are made in through-holes, and the depth of the through-holes determines the extension position of the gates close to the substrate. In the entire memory, designers hope that the gates of different transistors extend to the same horizontal plane as much as possible at the end close to the substrate, or the gap is as small as possible. It can also be understood that the repeatability of the morphology of each transistor is as consistent as possible to improve the performance of the entire device. Summary of the invention
[0006] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
[0007] The embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof, and an electronic device, which improve the uniformity of different transistors.
[0008] The present disclosure provides a semiconductor device, including:
[0009] A substrate, a first electrode disposed on the substrate, the first electrode comprising a barrier layer and a conductive layer at least partially disposed on a side of the barrier layer away from the substrate;
[0010] A second electrode disposed on a side of the first electrode away from the substrate;
[0011] A via hole penetrating the second electrode, partially penetrating the conductive layer, and at least partially penetrating the barrier layer;
[0012] A semiconductor layer at least disposed in the via hole and connected to the conductive layer of the first electrode and the second electrode;
[0013] A gate electrode disposed on a side of the semiconductor layer away from the substrate and filling the via hole;
[0014] The barrier layer and the conductive layer satisfy the following requirement: when etching to form the via hole, an etching selectivity ratio between the conductive layer and the barrier layer is greater than 1.
[0015] In some embodiments, the etching selectivity ratio is greater than or equal to 5.
[0016] In some embodiments, a bottom wall of the via hole exposes the barrier layer.
[0017] In some embodiments, the conductive layer includes a first sublayer disposed on a side of the barrier layer facing the substrate and a second sublayer disposed on a side of the barrier layer facing away from the substrate.
[0018] In some embodiments, on a plane parallel to the substrate, orthographic projections of the first sub-layer, the second sub-layer, and the barrier layer overlap.
[0019] In some embodiments, a bottom wall of the via hole exposes the first sub-layer.
[0020] In some embodiments, the barrier layer matches the work function of the semiconductor layer to reduce contact resistance.
[0021] In some embodiments, a ratio of a thickness of the barrier layer penetrated by the via hole to a thickness of the barrier layer is less than or equal to 0.1.
[0022] In some embodiments, the barrier layer includes a conductive material or an insulating material.
[0023] An embodiment of the present disclosure provides an electronic device, comprising the semiconductor device described in any of the above embodiments.
[0024] The present disclosure provides a method for manufacturing a semiconductor device, comprising:
[0025] forming a first electrode on a substrate, wherein the first electrode comprises a barrier layer and a conductive layer at least partially disposed on a side of the barrier layer away from the substrate;
[0026] forming a second electrode on a side of the first electrode away from the substrate;
[0027] forming a via hole penetrating the second electrode, a portion of the conductive layer and at least a portion of the barrier layer, wherein when etching the via hole, an etching selectivity ratio between the conductive layer and the barrier layer is greater than 1;
[0028] A semiconductor film, a gate insulating film and a gate electrode are deposited in sequence to form a semiconductor layer covering the sidewall and bottom wall of the via hole, a gate insulating layer covering the semiconductor layer and a gate electrode filling the via hole.
[0029] In some embodiments, forming the first electrode on the substrate includes: depositing a first conductive film, a barrier layer film, and a second conductive film in sequence on the substrate to form a first sublayer, a barrier layer, and a second sublayer as the first electrode.
[0030] The disclosed embodiments include a semiconductor device and a manufacturing method thereof, and an electronic device, wherein the semiconductor device includes: a substrate, a first electrode disposed on the substrate, the first electrode including a barrier layer and a conductive layer at least partially disposed on the barrier layer away from the substrate; a second electrode disposed on the first electrode away from the substrate; a via hole penetrating the second electrode, penetrating part of the conductive layer, and at least partially penetrating the barrier layer; a semiconductor layer disposed in the via hole and connected to the conductive layer of the first electrode and the second electrode; a gate electrode disposed on the semiconductor layer away from the substrate and filling the via hole; wherein the barrier layer and the conductive layer satisfy: when etching to form the via hole, the etching selectivity ratio of the conductive layer to the barrier layer is greater than 1. The solution provided in this embodiment can alleviate over-etching when etching the via hole by providing a barrier layer that is less easily etched than the conductive layer, improve the process uniformity of different transistors, and improve the performance of the storage array using the device.
[0031] Other features and advantages of the present disclosure will be described in the following description, and partly become apparent from the description, or be understood by implementing the present disclosure. The objects and advantages of the present disclosure can be realized and obtained by the structures particularly pointed out in the description and the drawings.
[0032] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution and do not constitute a limitation on the technical solution.
[0034] Figure 1A A schematic cross-sectional view of a semiconductor device along a direction perpendicular to a substrate provided by an exemplary embodiment;
[0035] Figure 1B A schematic cross-sectional view of a semiconductor device along a direction perpendicular to a substrate provided for another exemplary embodiment;
[0036] Figure 1CA schematic cross-sectional view of a semiconductor device along a direction perpendicular to a substrate provided for yet another exemplary embodiment;
[0037] Figure 1D A schematic cross-sectional view of a semiconductor device along a direction perpendicular to a substrate provided by an exemplary embodiment;
[0038] Figure 1E A schematic cross-sectional view of a semiconductor device along a direction perpendicular to a substrate provided for another exemplary embodiment;
[0039] Figure 2 A schematic cross-sectional view of an exemplary embodiment provided after forming a first electrode along a direction perpendicular to the substrate;
[0040] Figure 3 A schematic cross-sectional view of an exemplary embodiment provided after forming a second electrode along a direction perpendicular to the substrate;
[0041] Figure 4 A schematic cross-sectional view along a direction perpendicular to the substrate after forming a second insulating layer provided by an exemplary embodiment;
[0042] Figure 5 A schematic cross-sectional view along a direction perpendicular to the substrate after forming a via hole provided by an exemplary embodiment;
[0043] Figure 6 A schematic cross-sectional view along a direction perpendicular to the substrate after forming a semiconductor layer, a gate insulating layer and a gate electrode provided by an exemplary embodiment;
[0044] Figure 7 A flow chart of a method for manufacturing a semiconductor device is provided for an exemplary embodiment. DETAILED DESCRIPTION
[0045] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other arbitrarily.
[0046] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the common meanings understood by a person having ordinary skills in the field to which the present disclosure belongs.
[0047] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values shown in the drawings.
[0048] The ordinal numbers such as “first”, “second” and “third” in the present disclosure are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.
[0049] In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the disclosure and can be appropriately replaced according to the circumstances.
[0050] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a physical connection or a signal connection, a contact connection or an integral connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.
[0051] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be interchanged.
[0052] In the present disclosure, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.
[0053] The phrase “the orthographic projection of B is within the range of the orthographic projection of A” in the present disclosure means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A.
[0054] The present disclosure provides a semiconductor device, which may include:
[0055] A substrate, a first electrode disposed on the substrate, the first electrode comprising a barrier layer and a conductive layer at least partially disposed on a side of the barrier layer away from the substrate;
[0056] A second electrode disposed on a side of the first electrode away from the substrate;
[0057] A via hole penetrating the second electrode, partially penetrating the conductive layer, and at least partially penetrating the barrier layer;
[0058] A semiconductor layer at least disposed in the via hole and connected to the conductive layer of the first electrode and the second electrode;
[0059] A gate electrode is disposed on the semiconductor layer at a side away from the substrate and fills the via hole, wherein the barrier layer and the conductive layer satisfy: when etching to form the via hole, an etching selectivity ratio of the conductive layer to the barrier layer is greater than 1.
[0060] The solution provided in this embodiment can alleviate over-etching during via etching by providing a barrier layer that is less prone to etching than the conductive layer, thereby improving the process uniformity of different transistors, especially improving the morphology uniformity of the gate on the side close to the substrate, and improving the performance of the storage array.
[0061] In an exemplary embodiment, partially penetrating the conductive layer may include: penetrating a region of the conductive layer that is disposed on a side of the barrier layer away from the substrate.
[0062] Figure 1A A schematic cross-sectional view of a semiconductor device provided by an embodiment of the present disclosure along a direction perpendicular to the substrate. Figure 1A As shown, the semiconductor device may include:
[0063] Substrate ( Figure 1A not shown);
[0064] A first electrode 10 is disposed on the substrate, the first electrode 10 may include a barrier layer 12 and a conductive layer at least partially disposed on a side of the barrier layer 12 away from the substrate. In this embodiment, the conductive layer may include a first sublayer 11 disposed on a side of the barrier layer 12 facing the substrate and a second sublayer 13 disposed on a side of the barrier layer 12 away from the substrate, that is, the first electrode 10 may include a first sublayer 11, a barrier layer 12, and a second sublayer 13 disposed sequentially on the substrate;
[0065] A first insulating layer 14 disposed on a side of the first electrode 10 away from the substrate;
[0066] A second electrode 20 disposed on a side of the first insulating layer 14 away from the substrate;
[0067] A second insulating layer 15 disposed on a side of the second electrode 20 away from the substrate;
[0068] A via K1 penetrating the second insulating layer 15, the second electrode 20, the first insulating layer 14, the second sub-layer 13 and partially penetrating the barrier layer 12;
[0069] A semiconductor layer 23 disposed on a side of the second insulating layer 15 away from the substrate;
[0070] A gate insulating layer 24 disposed on a side of the semiconductor layer 23 away from the substrate;
[0071] and, a gate electrode 26 disposed on a side of the gate insulating layer 24 away from the substrate;
[0072] The semiconductor layer 23 may cover the sidewalls and bottom wall of the via hole K1, the semiconductor layer 23 is insulated from the gate electrode 26 by the gate insulating layer 24, and the gate electrode 26 fills the via hole K1. The sidewalls of the via hole K1 expose the second electrode 20 and the second sublayer 13, and the semiconductor layer 23 is connected to the second electrode 20 and the second sublayer 13. The barrier layer 12 and the conductive layer satisfy: when etching to form the via hole K1, the etching selectivity ratio of the conductive layer to the barrier layer is greater than 1. The etching selectivity ratio of the conductive layer to the barrier layer 12 may be the ratio of the etching rate of the conductive layer to the etching rate of the barrier layer 12.
[0073] The solution provided in this embodiment can reduce the probability of over-etching and improve the process uniformity of different transistors by providing a barrier layer that is less susceptible to etching than the conductive layer.
[0074] In an exemplary embodiment, the etching selectivity ratio of the conductive layer to the barrier layer 12 may be greater than or equal to 5. The barrier layer 12 has a slower etching rate than the conductive layer, and the etching selectivity ratio between the conductive layer and the barrier layer 12 is relatively large, which can effectively prevent over-etching and improve the process uniformity of different transistors.
[0075] In an exemplary embodiment, the barrier layer 12 may match the work function of the semiconductor layer 23 to reduce contact resistance. However, the disclosed embodiment is not limited thereto, and the barrier layer 12 may not match the work function of the semiconductor 13, and the conductive layer may match the work function of the semiconductor layer 23.
[0076] In an exemplary embodiment, the materials of the first sub-layer 11 and the second sub-layer 13 may be the same or different.
[0077] In an exemplary embodiment, if Figure 1A As shown, the bottom wall of the via hole K1 may expose the barrier layer 12 .
[0078] In an exemplary embodiment, if Figure 1B As shown, the bottom wall of the via hole K1 can expose the first sub-layer 11. That is, the barrier layer 12 can be completely penetrated, and the over-etching condition can still be improved compared with the solution without the barrier layer 12. At this time, the semiconductor layer 23 is connected to the first sub-layer 11.
[0079] In an exemplary embodiment, the ratio of the film thickness h of the barrier layer 12 penetrated by the via hole K1 to the thickness H of the barrier layer 12 may be less than or equal to 10%. The thickness H of the barrier layer 12 is the maximum distance between the upper surface and the small surface of the barrier layer 12 in a direction perpendicular to the substrate, and the film thickness h of the barrier layer 2 penetrated by the via hole K1 is the distance between the bottom wall of the via hole K1 and the upper surface of the barrier layer 12.
[0080] In an exemplary embodiment, on a plane parallel to the substrate, the orthographic projections of the first sublayer 11, the second sublayer 13, and the barrier layer 12 may overlap, that is, the first sublayer 11, the barrier layer 12, and the second sublayer 13 may be formed by one patterning, simplifying the process.
[0081] In an exemplary embodiment, on a plane parallel to the substrate, the orthographic projection of the barrier layer 12 may be located within the orthographic projections of the first sub-layer 11 and the second sub-layer 13, and the orthographic projection of the via K1 on the substrate is located within the orthographic projection of the barrier layer 12 on the substrate (i.e., within the outer contour of the orthographic projection of the barrier layer 12 on the substrate). Figure 1C In this embodiment, the barrier layer 12 may have a different size from the first sub-layer 11 and the third sub-layer 13, and the barrier layer 12 only needs to cover the area where the via K1 is located, thereby preventing over-etching and improving the process uniformity of different transistors.
[0082] In an exemplary embodiment, the barrier layer 12 may include a conductive material or an insulating material.
[0083] In an exemplary embodiment, the barrier layer 12 includes but is not limited to at least one of the following: aluminum oxide (Al2O3), indium tin oxide (ITO), indium zinc oxide (IGZO), IZO, and the like.
[0084] In an exemplary embodiment, the conductive layer may be one or more of the following different types of materials.
[0085] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;
[0086] Alternatively, it can be a metal oxide, metal nitride, metal silicide, metal carbide, etc., such as tin-doped indium oxide ITO, indium-doped zinc oxide IZO, indium oxide InO, aluminum-doped zinc oxide (Al-doped ZnO, AZO), iridium oxide (IrOx), ruthenium oxide (RuOx) and other metal oxide conductive materials; for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN) and other metal nitride materials.
[0087] Figures 1A to 1C In the embodiment, the first electrode 10 includes three stacked film layers, but the embodiments of the present disclosure are not limited thereto, and more or fewer film layers may be provided.
[0088] In an exemplary embodiment, if Figure 1D As shown, the first electrode 10 may include only a barrier layer 12 and a second sublayer 13 disposed on the side of the barrier layer 12 facing away from the substrate. The bottom wall of the via exposes the barrier layer 12. Compared with the solution in which the first electrode 10 includes three film layers stacked in sequence, the solution provided in this embodiment can simplify the process. When the first electrode 10 includes three film layers stacked, the three film layers can be used to match the work function with the semiconductor layer 23, which is more conducive to reducing the contact resistance than matching the work function of two film layers.
[0089] In an exemplary embodiment, if Figure 1E As shown, the first electrode 10 may include a first sublayer 11, a first blocking sublayer 121, a second sublayer 13, a second blocking sublayer 122, and a third sublayer 16 sequentially arranged on the substrate, that is, in this embodiment, the blocking layer 12 includes the first blocking sublayer 121 and the second blocking sublayer 122, and the conductive layer includes the first sublayer 11, the second sublayer 13, and the third sublayer 16. The bottom wall of the via hole may expose the second blocking sublayer 122 or the first sublayer 11.
[0090] The first electrode 10, the second electrode 20, the semiconductor layer 23, the gate insulating layer 24 and the gate electrode 26 constitute a transistor, and the transistor can form a 2T0C storage unit with other transistors, or form a 1T1C storage unit with a capacitor, or form a 2T1C storage unit with other transistors and capacitors, etc., but is not limited thereto, and the transistor can be applied to other electronic devices. The transistor or storage unit can store a transistor array or a storage array, etc.
[0091] The technical solution of this embodiment is further explained below through the manufacturing process of the semiconductor device of this embodiment. The "patterning process" mentioned in this embodiment includes deposition of film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes coating of film layer, mask exposure and development, which are mature manufacturing processes in related technologies. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here. In the description of this embodiment, it should be understood that "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or a photolithography process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" still requires a patterning process or a photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".
[0092] In an exemplary embodiment, the manufacturing process of the semiconductor device may include:
[0093] 1) forming a first electrode 10;
[0094] The forming of the first electrode 10 may include:
[0095] A first conductive film, a barrier layer film and a second conductive film are sequentially deposited on a substrate to form a first sublayer 11, a barrier layer 12 and a second sublayer 13. The first electrode includes the first sublayer 11, the barrier layer 12 and the second sublayer 13. Figure 2 As shown, Figure 2 A schematic cross-sectional view along a direction perpendicular to the substrate after forming the first electrode 10 is provided as an exemplary embodiment.
[0096] In an exemplary embodiment, an etching selectivity ratio among the first conductive film, the second conductive film and the barrier film is greater than 1.
[0097] In an exemplary embodiment, the etching selectivity is greater than or equal to 5. In the process of manufacturing the semiconductor device, the etching rate of the barrier film is lower than the etching rate of the first conductive film and the second conductive film, and the etching rate difference is large, which can effectively prevent over-etching.
[0098] In an exemplary embodiment, the barrier film may include metal or insulating material.
[0099] In an exemplary embodiment, the first conductive film and the second conductive film may be the following conductive materials:
[0100] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;
[0101] Alternatively, it may be a metal oxide, a metal nitride, a metal silicide, a metal carbide, etc., such as metal oxide materials with high conductivity such as indium tin oxide ITO, indium zinc oxide IZO, indium oxide InO, etc.; for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), etc.;
[0102] Alternatively, it may be polysilicon material, conductive doped semiconductor material, such as conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc., or other materials that exhibit conductivity.
[0103] In an exemplary embodiment, the barrier layer film includes but is not limited to at least one of the following: aluminum oxide (Al2O3) and indium tin oxide (ITO).
[0104] In an exemplary embodiment, on a plane parallel to the substrate, the orthographic projection of the barrier layer 12 may overlap with the orthographic projections of the first sub-layer 11 and the second sub-layer 13 .
[0105] In an exemplary embodiment, on a plane parallel to the substrate, the orthographic projection of the barrier layer 12 may overlap with the orthographic projections of the first sub-layer 11 and the second sub-layer 13. However, the embodiments of the present disclosure are not limited thereto, and the orthographic projection of the barrier layer 12 may overlap with the orthographic projections of the first sub-layer 11 and the second sub-layer 13.
[0106] In this embodiment, the first sublayer 11 and the second sublayer 13 are both made of a first conductive film, but the embodiments of the present disclosure are not limited thereto, and the first sublayer 11 and the second sublayer 13 may be made of different conductive films.
[0107] 2) forming a second electrode 20;
[0108] The forming of the second electrode 20 may include:
[0109] Depositing a first insulating film on the substrate forming the above structure to form a first insulating layer 14, wherein the first insulating layer 14 covers the second sub-layer 13;
[0110] Deposit a third conductive film and pattern to form a second electrode 20, such as Figure 3 As shown, Figure 3 A schematic cross-sectional view along a direction perpendicular to the substrate after forming the second electrode 20 is provided as an exemplary embodiment.
[0111] In an exemplary embodiment, the orthographic projection of the second electrode 20 on the substrate may overlap with the orthographic projection of the first electrode 10 on the substrate, and overlap with the orthographic projection of the barrier layer 12 on the substrate.
[0112] In an exemplary embodiment, the third conductive film may be the following conductive material:
[0113] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;
[0114] Alternatively, it may be a metal oxide, a metal nitride, a metal silicide, a metal carbide, etc., such as metal oxide materials with high conductivity such as indium tin oxide ITO, indium zinc oxide IZO, indium oxide InO, etc.; for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), etc.;
[0115] Alternatively, it may be polysilicon material, conductive doped semiconductor material, etc., for example, conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials that embody conductivity, etc.
[0116] In an exemplary embodiment, the third conductive film may be the same as or different from the first conductive film and the second conductive film.
[0117] In an exemplary embodiment, the first insulating film may include, but is not limited to, at least one of the following: silicon oxide, silicon nitride, and silicon oxynitride.
[0118] 3) forming a second insulating layer 15;
[0119] The forming of the second insulating layer 15 may include: depositing a second insulating film on the substrate forming the above structure to form the second insulating layer 15, wherein the second insulating layer 15 completely covers the second electrode 20, such as Figure 4 shown. Figure 4 A schematic cross-sectional view taken along a direction perpendicular to the substrate after forming a second insulating layer is provided for an exemplary embodiment.
[0120] In an exemplary embodiment, the second insulating film may include, but is not limited to, at least one of the following: silicon oxide, silicon nitride, and silicon oxynitride.
[0121] 4) forming a via K1;
[0122] The forming of the via hole K1 may include: etching the via hole K1 penetrating the second insulating layer 15, the second electrode 20, the first insulating layer 14, the second sub-layer 13 and partially penetrating the barrier layer 12, such as Figure 5 As shown, Figure 5 A schematic cross-sectional view along a direction perpendicular to the substrate after forming a via hole is provided for an exemplary embodiment.
[0123] In an exemplary embodiment, the bottom wall of the via hole K1 may expose the barrier layer 12, the side wall of the via hole K1 may expose the second electrode 20, and the side wall of the via hole K1 may expose the second sub-layer 13 and the barrier layer 12. Alternatively, the bottom wall of the via hole K1 may expose the first sub-layer 11, the side wall of the via hole K1 exposes the second electrode 20, and the second sub-layer 13, the barrier layer 12, and the first sub-layer 11 may be exposed. Alternatively, the bottom wall of the via hole K1 may expose the first sub-layer 11, the side wall of the via hole K1 exposes the second electrode 20, and the second sub-layer 13 and the barrier layer 12 may be exposed, and the side wall of the via hole K1 does not expose the first sub-layer 11.
[0124] In the solution provided by this embodiment, the barrier layer 12 is less likely to be overetched than the second sub-layer 13 , and compared with the solution without a barrier layer, it is beneficial to improve the process uniformity of different semiconductor devices.
[0125] In an exemplary embodiment, the ratio of the etched thickness of the barrier layer 12 (ie, the etched thickness when forming the via K1) to the thickness of the barrier layer 12 may be less than or equal to a preset value x. The thickness of the barrier layer 12 is the thickness along a direction perpendicular to the substrate.
[0126] In an exemplary embodiment, the preset value x may be 0.1.
[0127] 5) forming a semiconductor layer 23, a gate insulating layer 24 and a gate electrode 26;
[0128] The forming of the semiconductor layer 23, the gate insulating layer 24 and the gate electrode 26 may include: depositing a semiconductor film, a gate insulating film and a gate electrode film in sequence on the substrate forming the aforementioned structure to form the semiconductor layer 23, the gate insulating layer 24 and the gate electrode 26, wherein the gate electrode 26 fills the via hole K1, such as Figure 6 As shown, Figure 6A schematic cross-sectional view of an exemplary embodiment after forming a semiconductor layer 23, a gate insulating layer 24 and a gate electrode 26 along a direction perpendicular to the substrate. The semiconductor layer 23 is connected to the second electrode 21, and is connected to the second sub-layer 13. The gate electrode 26 is insulated from the semiconductor layer 23 by the gate insulating layer 24. The gate electrode 26 may include a vertical portion disposed in the via K1 and a horizontal electrode portion connected to the vertical portion and extending in a direction parallel to the substrate. The semiconductor layer 23 may include a horizontal semiconductor portion extending in a direction parallel to the substrate and a recessed portion disposed on the sidewall and bottom wall of the via, and the recessed portion is connected to the first electrode 10 and the second electrode 20.
[0129] In an exemplary embodiment, the semiconductor film may be a material such as silicon or polysilicon with a band gap smaller than 1.65 eV, or may be a wide band gap material such as a metal oxide material with a band gap larger than 1.65 eV.
[0130] For example, the material of the metal oxide semiconductor layer or channel may include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may contain compounds of other elements, such as N, Si, etc., and may contain other small amounts of doping elements.
[0131] In some embodiments, the material of the metal oxide semiconductor layer or the channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO , IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) and other materials. As long as the leakage current of the transistor can meet the requirements, the specific details can be adjusted according to the actual situation.
[0132] These materials have a wide band gap and a low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15A, thereby improving the working performance of dynamic memory.
[0133] The material of the metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic proportion in the material and the film quality of the material.
[0134] In an exemplary embodiment, the gate insulating film may include one or more layers of Low-K and / or High-K dielectric materials, or include two or more regions with different dielectric constants K.
[0135] Low-K materials, such as silicon oxide.
[0136] High-K materials, such as dielectric materials with a dielectric constant K>3.9. In some embodiments, oxides of one or more of hafnium, aluminum, lanthanum, zirconium, etc. may be included. Exemplary, for example, may include but are not limited to at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2) and other high-K materials.
[0137] In an exemplary embodiment, the gate electrode film may be one or more of the following different types of materials.
[0138] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;
[0139] Alternatively, it may be a metal oxide, a metal nitride, a metal silicide, a metal carbide, etc., such as metal oxide materials with high conductivity such as indium tin oxide ITO, indium zinc oxide IZO, indium oxide InO, etc.; for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), etc.;
[0140] Alternatively, it may be a polysilicon material. Alternatively, it may be a conductive doped semiconductor material, such as conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; or other materials that embody conductivity.
[0141] The present disclosure also provides an electronic device, including the semiconductor device of the above embodiment. The electronic device may be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply. The storage device may include a memory in a computer, etc., which is not limited here.
[0142] like Figure 7 As shown, the present disclosure provides a method for manufacturing a semiconductor device, which may include:
[0143] Step 701, forming a first electrode on a substrate, wherein the first electrode comprises a barrier layer and a conductive layer at least partially disposed on a side of the barrier layer away from the substrate;
[0144] Step 702, forming a second electrode on a side of the first electrode away from the substrate;
[0145] Step 703, forming a via hole penetrating the second electrode, a portion of the conductive layer and at least a portion of the barrier layer, wherein when etching the via hole, an etching selectivity ratio between the conductive layer and the barrier layer is greater than 1;
[0146] Step 704 , sequentially depositing a semiconductor film, a gate insulating film and a gate electrode to form a semiconductor layer covering the sidewalls and bottom wall of the via hole, a gate insulating layer covering the semiconductor layer and a gate electrode filling the via hole.
[0147] The semiconductor device manufacturing method provided in this embodiment can prevent over-etching by forming a barrier layer, thereby improving the process uniformity of different transistors and improving the performance of a memory array including the transistors.
[0148] In this embodiment, the structure, materials, related parameters and detailed manufacturing process of each film layer have been described in detail in the previous embodiments and will not be repeated here.
[0149] In an exemplary embodiment, forming the first electrode on the substrate may include: sequentially depositing a first conductive film, a barrier layer film, and a second conductive film on the substrate to form a first sublayer, a barrier layer, and a second sublayer as the first electrode.
[0150] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted to facilitate understanding of the present invention and are not intended to limit the present invention. Any technician in the field to which the present invention belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined in the attached claims.
Claims
1. A semiconductor device, characterized in that: include: A substrate, a first electrode disposed on the substrate, the first electrode comprising a barrier layer and a conductive layer at least partially disposed on a side of the barrier layer away from the substrate; A second electrode disposed on a side of the first electrode away from the substrate; A via hole penetrating the second electrode, partially penetrating the conductive layer, and at least partially penetrating the barrier layer; A semiconductor layer at least disposed in the via hole and connected to the conductive layer of the first electrode and the second electrode; A gate electrode disposed on a side of the semiconductor layer away from the substrate and filling the via hole; The barrier layer and the conductive layer satisfy the following requirement: when etching to form the via hole, an etching selectivity ratio between the conductive layer and the barrier layer is greater than 1.
2. The semiconductor device according to claim 1, wherein: The etching selectivity ratio is greater than or equal to 5.
3. The semiconductor device according to claim 1, wherein: A bottom wall of the via hole exposes the barrier layer.
4. The semiconductor device according to claim 1, wherein: The conductive layer includes a first sublayer disposed on a side of the barrier layer facing the substrate and a second sublayer disposed on a side of the barrier layer facing away from the substrate.
5. The semiconductor device according to claim 4, characterized in that On a plane parallel to the substrate, the orthographic projections of the first sub-layer, the second sub-layer, and the barrier layer overlap.
6. The semiconductor device according to claim 4, characterized in that A bottom wall of the via hole exposes the first sub-layer.
7. The semiconductor device according to any one of claims 1 to 6, characterized in that: The barrier layer matches the work function of the semiconductor layer to reduce contact resistance.
8. The semiconductor device according to any one of claims 1 to 6, characterized in that: A ratio of a thickness of the barrier layer penetrated by the via hole to a thickness of the barrier layer is less than or equal to 0.
1.
9. The semiconductor device according to any one of claims 1 to 6, characterized in that: The barrier layer includes a conductive material or an insulating material.
10. An electronic device, characterized in that: Comprising the semiconductor device as claimed in any one of claims 1 to 9.
11. A method for manufacturing a semiconductor device, characterized in that: include: forming a first electrode on a substrate, wherein the first electrode comprises a barrier layer and a conductive layer at least partially disposed on a side of the barrier layer away from the substrate; forming a second electrode on a side of the first electrode away from the substrate; forming a via hole penetrating the second electrode, a portion of the conductive layer and at least a portion of the barrier layer, wherein an etching selectivity ratio of the conductive layer to the barrier layer is greater than 1 when etching the via hole; A semiconductor film, a gate insulating film and a gate electrode are deposited in sequence to form a semiconductor layer covering the sidewall and bottom wall of the via hole, a gate insulating layer covering the semiconductor layer and a gate electrode filling the via hole.
12. The method for manufacturing a semiconductor device according to claim 11, wherein: The forming of the first electrode on the substrate comprises: depositing a first conductive film, a barrier layer film and a second conductive film in sequence on the substrate to form a first sublayer, a barrier layer and a second sublayer as the first electrode.