Driving circuit and half-bridge driving circuit

Abstract

The invention discloses a driving circuit and a half-bridge driving circuit which are used for driving a target power tube, and the circuit comprises a floating rail circuit which is connected between a first node and a second node and is used for generating a floating voltage and a clamping voltage; the control signal generating circuit is connected between the first node and the floating voltage and generates a control signal based on the PWM signal. The gate driving circuit is connected between the first node and the second node, is connected with the clamping voltage, and is used for generating a target driving signal based on the plurality of control signals so as to drive the target power tube. Floating voltage is generated through the floating rail circuit, so that the control signal generation circuit works in a floating voltage domain, and the risk that a high-voltage tube is broken down is avoided; a clamping voltage is generated through the floating rail circuit, so that an output tube of the gate drive circuit can adopt a low-voltage tube, and the reaction speed of the gate drive circuit is increased; half-bridge driving can be realized based on two groups of floating rail circuits, and the circuit area is saved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a drive circuit and a half-bridge drive circuit. Background Art

[0002] Ginseng Figure 1 The figure shows a half-bridge driving circuit in the prior art. The driving voltage PVCC is a high voltage (e.g., 7.5V), but the high voltage process does not support thick gate oxide, i.e., the V GS When the voltage is less than 5V, a low voltage (e.g. 5V) internal floating drive is required to ensure the V GS Will not be penetrated.

[0003] Ginseng Figure 2 The floating rail circuit in the prior art is shown, which generates a floating voltage through a driving tube and a voltage stabilizing capacitor. For example, on the PMOS driving side, a floating voltage of PVCC-5V (or BST-5V) is generated; on the NMOS driving side, a floating voltage of PGND+5V (or SW+5V) is generated.

[0004] The disadvantage of the prior art is that the driving tube and the stabilizing capacitor of the floating rail circuit occupy a large circuit area. Figure 3 As shown, for a half-bridge driving circuit, in order to obtain sufficient driving capability and a stable driving voltage, four floating voltages (PVCC-5V, BST-5V, PGND+5V and SW+5V) need to be generated through four sets of floating rail circuits, thus requiring a larger circuit area.

[0005] Therefore, in view of the above technical problems, it is necessary to provide a driving circuit and a half-bridge driving circuit. Summary of the invention

[0006] The object of the present invention is to provide a driving circuit and a half-bridge driving circuit, which can generate a floating voltage domain with a smaller circuit area to adapt to the thin gate process of high-voltage driving.

[0007] In order to achieve the above object, a technical solution provided by a specific embodiment of the present invention is as follows:

[0008] A driving circuit is used to drive a target power tube, the driving circuit comprising:

[0009] A floating rail circuit connected between a first node and a second node, used to generate a floating voltage based on a voltage on the first node and a clamping voltage based on a voltage on the second node, wherein the floating voltage is lower than the voltage on the first node and the clamping voltage is higher than the voltage on the second node;

[0010] A control signal generating circuit, connected between the first node and the floating voltage, for generating a plurality of control signals based on the PWM signal;

[0011] A gate drive circuit is connected between the first node and the second node and is connected to the clamping voltage. The gate drive circuit is a multi-level structure. Each level of the gate drive circuit corresponds to at least one control signal. The gate drive circuit is used to generate a target drive signal based on a plurality of control signals to drive a target power tube.

[0012] In one or more embodiments of the present invention, the floating rail circuit includes a first Zener tube, a first resistor, a second resistor, a first MOS tube, a third resistor and a second Zener tube; wherein,

[0013] The first end of the first Zener tube is connected to the first end of the first resistor, the second end of the first Zener tube is connected to the first node, and the second end of the first resistor is connected to the second node;

[0014] The first end of the second resistor is connected to the first node, the second end of the second resistor is connected to the floating voltage, the first end of the first MOS transistor is connected to the floating voltage, the second end of the first MOS transistor is connected to the second node, and the control end of the first MOS transistor is connected to the first end of the first Zener transistor;

[0015] The first end of the third resistor is connected to the first node, the second end of the third resistor is connected to the clamping voltage, the first end of the second Zener diode is connected to the second node, and the second end of the second Zener diode is connected to the clamping voltage.

[0016] In one or more embodiments of the present invention, the floating rail circuit further includes:

[0017] A first capacitor, wherein a first end of the first capacitor is connected to the first node, and a second end of the first capacitor is connected to a floating voltage;

[0018] A second capacitor, wherein a first end of the second capacitor is connected to the clamping voltage, and a second end of the second capacitor is connected to the second node.

[0019] In one or more embodiments of the present invention, the gate driving circuit includes a latch unit, a first driving unit, a second driving unit, a first power tube and a second power tube; wherein,

[0020] The latch unit is connected to the control signal generating circuit, and the latch unit generates a latch signal based on a first control signal and a second control signal, wherein the first control signal and the second control signal have opposite phases;

[0021] The first driving unit is connected to the control signal generating circuit and the latch unit, and the first driving unit is used to generate a first driving signal based on the latch signal and the second control signal;

[0022] The second driving unit is connected to the first driving unit, and the second driving unit is used to generate a power tube driving signal based on the first driving signal and the third control signal;

[0023] The first end of the first power tube is connected to the first node, the control end of the first power tube receives a fourth control signal, and the second end of the first power tube is connected to the control end of the target power tube;

[0024] The first end of the second power tube is connected to the second node, the control end of the second power tube is connected to the second driving unit and receives the power tube driving signal, and the second end of the second power tube is connected to the control end of the target power tube.

[0025] In one or more embodiments of the present invention, the first driving unit includes a third input tube, a third clamping tube and a third output tube; wherein,

[0026] The first end of the third input tube is connected to the first node, the second end of the third input tube is connected to the second end of the third clamp tube, and the control end of the third input tube receives a second control signal;

[0027] The control end of the third clamping tube is connected to the clamping voltage, and the first end of the third clamping tube is connected to the second end of the third output tube;

[0028] The control end of the third output tube is connected to the latch unit and receives the latch signal, the first end of the third output tube is connected to the second node, and the second end of the third output tube is connected to the second driving unit and generates a first driving signal.

[0029] In one or more embodiments of the present invention, the second driving unit includes a fourth input tube, a fourth clamping tube and a fourth output tube; wherein,

[0030] The first end of the fourth input tube is connected to the first node, the second end of the fourth input tube is connected to the second end of the fourth clamp tube, and the control end of the fourth input tube receives a third control signal;

[0031] The control end of the fourth clamping tube is connected to the clamping voltage, and the first end of the fourth clamping tube is connected to the second end of the fourth output tube;

[0032] The control end of the fourth output tube is connected to the first driving unit and receives the first driving signal, the first end of the fourth output tube is connected to the second node, and the second end of the fourth output tube is connected to the control end of the second power tube and generates a power tube driving signal.

[0033] In one or more embodiments of the present invention, the control signal generating circuit includes a plurality of connected inverters, and the plurality of inverters are used to invert and delay the PWM signal to generate a first control signal, a second control signal, a third control signal and a fourth control signal; wherein,

[0034] The first control signal is in phase with the PWM signal;

[0035] The second control signal is inversely proportional to the PWM signal, and the second control signal is delayed relative to the first control signal;

[0036] The third control signal is in phase with the PWM signal, and the third control signal is delayed from the second control signal;

[0037] The fourth control signal is inversely proportional to the PWM signal, and the fourth control signal is delayed relative to the third control signal.

[0038] In one or more embodiments of the present invention, the latch unit includes a first input tube, a second input tube, a first clamping tube, a second clamping tube, a first output tube and a second output tube; wherein,

[0039] The first end of the first input tube is connected to the first node, the second end of the first input tube is directly or indirectly connected to the second end of the first clamp tube, and the control end of the first input tube receives a second control signal;

[0040] The first end of the second input tube is connected to the first node, the second end of the second input tube is directly or indirectly connected to the second end of the second clamp tube, and the control end of the second input tube receives a first control signal;

[0041] The control ends of the first clamping tube and the second clamping tube are connected to the clamping voltage, the first end of the first clamping tube is directly or indirectly connected to the second end of the first output tube, and the first end of the second clamping tube is directly or indirectly connected to the second end of the second output tube;

[0042] The first end of the first output tube is connected to the second node, and the control end of the first output tube is connected to the first end of the second clamping tube;

[0043] The first end of the second output tube is connected to the second node, and the control end of the second output tube is connected to the first end of the first clamping tube.

[0044] In one or more embodiments of the present invention, the latch unit further includes a fourth resistor, a fifth resistor, a sixth resistor and a seventh resistor; wherein,

[0045] The first end of the fourth resistor is connected to the second end of the first input tube, and the second end of the fourth resistor is connected to the second end of the first clamp tube;

[0046] The first end of the fifth resistor is connected to the second end of the second input tube, and the second end of the fifth resistor is connected to the second end of the second clamp tube;

[0047] The first end of the sixth resistor is connected to the first end of the first clamping tube, and the second end of the sixth resistor is connected to the second end of the first output tube;

[0048] The first end of the seventh resistor is connected to the first end of the second clamping tube, and the second end of the seventh resistor is connected to the second end of the second output tube.

[0049] In one or more embodiments of the present invention, the first node is connected to a BST pin in a driving circuit, the second node is connected to a SW pin in the driving circuit, and the target power tube is a high-voltage side power tube.

[0050] In one or more embodiments of the present invention, the first node is connected to a power supply voltage, the second node is connected to a ground potential, and the target power tube is a low-voltage side power tube.

[0051] Another specific embodiment of the present invention provides a technical solution as follows:

[0052] A half-bridge driving circuit, comprising a first driving circuit and a second driving circuit; wherein:

[0053] The first driving circuit is the above-mentioned driving circuit; and / or,

[0054] The second driving circuit is the driving circuit mentioned above.

[0055] Compared with the prior art, the driving circuit and the half-bridge driving circuit of the present invention generate a floating voltage through a floating rail circuit, so that the control signal generating circuit operates in a floating voltage domain, thereby making the control signals all signals in the floating voltage domain, and the input tube in the gate driving circuit operates in a floating voltage domain of about 5V, thereby preventing the input tube in the gate driving circuit from being broken down;

[0056] The clamping voltage generated by the floating rail circuit allows the output tube in the gate drive circuit to use a low-voltage tube, and prevents the output tube in the gate drive circuit from being broken down, thereby improving the response speed of the gate drive circuit and reducing power consumption;

[0057] The gate drive circuit adopts a push-pull structure, and generates a stable target drive signal that meets the target drive capability through step-by-step driving.

[0058] For a half-bridge driving circuit, only two sets of floating rail circuits are needed to obtain sufficient driving capability and stable driving voltage, thus saving circuit area. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0060] Figure 1 is a schematic diagram of a half-bridge driving circuit in the prior art;

[0061] Figure 2 is a schematic diagram of another floating rail circuit in the prior art;

[0062] Figure 3 is a schematic diagram of another half-bridge driving circuit in the prior art;

[0063] Figure 4 is a schematic diagram of a driving circuit in Embodiment 1 of the present invention;

[0064] Figure 5 Schematic diagram of a floating rail circuit of a driving circuit in Embodiment 1 of the present invention;

[0065] Figure 6 Schematic diagram of a control signal generating circuit of a driving circuit in Embodiment 1 of the present invention;

[0066] Figure 7 Schematic diagram of a gate driving circuit of a driving circuit in Embodiment 1 of the present invention;

[0067] Figure 8 is a schematic diagram of a driving circuit in Embodiment 2 of the present invention;

[0068] Fig. 9 Schematic diagram of a half-bridge driving circuit in Embodiment 3 of the present invention. DETAILED DESCRIPTION

[0069] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0070] The term "coupled" or "connected" or "connected" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include connection through other active or passive devices on the basis of achieving the same or similar functional purpose, such as connection through circuits or components such as switches and follower circuits. In addition, in the present invention, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity or order between these technical features.

[0071] Embodiment 1:

[0072] like Figure 4 As shown, a driving circuit in an embodiment is used to drive a target power tube, and the driving circuit includes a floating rail circuit 10 , a control signal generating circuit 20 and a gate driving circuit 30 .

[0073] The floating rail circuit 10 is connected between a first node and a second node, and is used to generate a floating voltage VFLOAT based on a voltage on the first node, and to generate a clamping voltage VCLAMP based on a voltage on the second node. The floating voltage VFLOAT is lower than the voltage on the first node, and the clamping voltage VCLAMP is higher than the voltage on the second node.

[0074] In one embodiment, the target power tube is a high-voltage side power tube, so the first node is connected to the BST pin of the driving circuit, and the second node is connected to the SW pin of the driving circuit. The difference between the voltage on the BST pin and the voltage on the SW pin is about 7.5 V. For easy distinction, in one embodiment, BST refers to the first node and SW refers to the second node.

[0075] The control signal generating circuit 20 is connected between the first node BST and the floating voltage VFLOAT, and is used for generating a plurality of control signals based on the PWM signal.

[0076] The gate drive circuit 30 is connected between the first node BST and the second node SW, and is connected to the clamping voltage VCLAMP. The gate drive circuit 30 is a multi-level structure. Each level of the gate drive circuit 30 corresponds to at least one control signal. The gate drive circuit 30 is used to generate a target drive signal HO based on a plurality of control signals to drive the target power tube.

[0077] like Figure 5 As shown, the floating rail circuit 10 in one embodiment includes a first Zener transistor D1, a first resistor R1, a second resistor R2, a first MOS transistor M1, a third resistor R3, a second Zener transistor D2, a first capacitor C1 and a second capacitor C2.

[0078] Specifically, a first end of the first Zener diode D1 is connected to a first end of the first resistor R1 , a second end of the first Zener diode D1 is connected to a first node BST, and a second end of the first resistor R1 is connected to a second node SW.

[0079] The first end of the second resistor R2 is connected to the first node BST, the second end of the second resistor R2 is connected to the floating voltage VFLOAT, the first end of the first MOS transistor M1 is connected to the floating voltage VFLOAT, the second end of the first MOS transistor M1 is connected to the second node SW, and the control end of the first MOS transistor M1 is connected to the first end of the first Zener transistor D1. In this embodiment, the first MOS transistor M1 is a high-voltage PMOS, the first end of the first MOS transistor M1 is a source, the second end is a drain, and the control end is a gate.

[0080] A first end of the third resistor R3 is connected to the first node BST, a second end of the third resistor R3 is connected to the clamping voltage VCLAMP, a first end of the second Zener diode D2 is connected to the second node SW, and a second end of the second Zener diode D2 is connected to the clamping voltage VCLAMP.

[0081] A first end of the first capacitor C1 is connected to the first node BST, and a second end of the first capacitor C1 is connected to the floating voltage VFLOAT. A first end of the second capacitor C2 is connected to the clamping voltage VCLAMP, and a second end of the second capacitor C2 is connected to the second node SW.

[0082] like Figure 5 As shown, the floating rail circuit 10 uses the reverse breakdown voltage Vzener (about 6V) of the first Zener transistor D1 and the second Zener transistor D2 to generate a floating voltage VFLOAT and a clamping voltage VCLAMP to achieve voltage stabilization. The floating voltage VFLOAT is equal to BST-Vzener+VGS M1 , clamping voltage VCLAMP=SW+Vzener.

[0083] Specifically, the potential of the control terminal of the first MOS tube M1 is clamped to BST-Vzener by the first Zener tube D1, and the floating voltage VFLOAT is equal to BST-Vzener+VGS. M1 Therefore, the floating voltage domain BST-VFLOAT between the first node BST and the floating voltage VFLOAT is Vzener-VGS M1 The floating voltage domain BST-VFLOAT ranges about 5V, which can prevent the high-voltage tube from being broken down under the thin-gate process.

[0084] like Figure 6 As shown, the control signal generating circuit 20 includes a plurality of stages of inverters connected in series, and each stage of the inverters operates in a floating voltage domain BST-VFLOAT.

[0085] like Figure 7 As shown, the gate drive circuit 30 of this embodiment includes a latch unit 31, a first drive unit 32, a second drive unit 33, a first power tube HV_PMOS and a second power tube HV_NMOS. It can be understood that the gate drive circuit 30 is a multi-stage structure, wherein the latch unit 31 can be regarded as a first-stage structure, the first drive unit 32 can be regarded as a second-stage structure, the second drive unit 33 can be regarded as a third-stage structure, and the first power tube HV_PMOS and the second power tube HV_NMOS can be regarded as an output stage structure.

[0086] The latch unit 31 is connected to the control signal generating circuit 20. The latch unit 31 generates a latch signal based on the first control signal A1 and the second control signal A2. The first control signal A1 and the second control signal A2 have opposite phases. It can be understood that the latch signal is Figure 7 The potential at point B2 is shown.

[0087] The first driving unit 32 is connected to the control signal generating circuit 20 and the latch unit 31 , and is used for generating a first driving signal B3 based on the latch signal and the second control signal A2 .

[0088] The second driving unit 33 is connected to the first driving unit 32, and the second driving unit 33 is used to generate a power tube driving signal NGATE based on the first driving signal B3 and the third control signal A3. It can be understood that the power tube driving signal is Figure 7 The NGATE point potential is shown.

[0089] The first power tube HV_PMOS and the second power tube HV_NMOS form an output stage, the second end of the first power tube HV_PMOS and the second end of the second power tube HV_NMOS are connected to the control end of the target power tube, and generate a target drive signal HO to the control end of the target power tube. In one embodiment, the first power tube HV_PMOS and the second power tube HV_NMOS are both high-voltage tubes.

[0090] Specifically, a first end of the first power tube HV_PMOS is connected to the first node BST, a control end of the first power tube HV_PMOS receives the fourth control signal A4, and a second end of the first power tube HV_PMOS is connected to the control end of the target power tube. A first end of the second power tube HV_NMOS is connected to the second node SW, a control end of the second power tube HV_NMOS is connected to the second driving unit 33 and receives the power tube driving signal NGATE, and a second end of the second power tube HV_NMOS is connected to the control end of the target power tube.

[0091] It can be understood that the latch unit 31, the first driving unit 32 and the second driving unit 33 all include corresponding input tubes, clamping tubes and output tubes. The input tube is connected to the first node BST, the second end of the input tube is directly or indirectly connected to the second end of the clamping tube, and the control end of the input tube receives the corresponding control signal. The control end of the clamping tube is connected to the clamping voltage VCLAMP, and the first end of the clamping tube is directly or indirectly connected to the second end of the output tube. The first end of the output tube is connected to the second node SW.

[0092] Furthermore, the input tubes of the latch unit 31, the first driving unit 32 and the second driving unit 33 are all high-voltage tubes. From the above analysis, it can be seen that the control signal generating circuit 20 is connected between the first node BST and the floating voltage VFLOAT, and the control signals generated by it are all signals within the floating voltage domain BST-VFLOAT. Therefore, the VGS of the input tubes of the latch unit 31, the first driving unit 32 and the second driving unit 33 all operate within the range of Vzener-VGS (about 5V) and will not be broken down by high voltage.

[0093] The clamping tubes of the latch unit 31, the first driving unit 32, and the second driving unit 33 are all high-voltage tubes, and the clamping tubes can be considered to be always in the on state. The output tubes of the latch unit 31, the first driving unit 32, and the second driving unit 33 are all low-voltage tubes, and the first terminal voltage of the clamping tube, that is, the source voltage of the clamping tube is clamped to VCLAMP-VGS, so the output tube works in the voltage range of about 5V. Specifically, the B1 node is clamped to VCLAMP-VGS Q3 , node B2 is clamped to VCLAMP-VGS Q4 , node B3 is clamped to VCLAMP-VGS Q8 , NGATE node is clamped to VCLAMP-VGS Q11 .

[0094] It can be understood that the control terminal voltage of the second power tube HV_NMOS is approximately SW+5V, and the control terminal voltage of the first power tube HV_PMOS is approximately BST-5V, that is, the driving circuit in one embodiment generates two floating voltages (SW+5V and BST-5V) through a floating rail circuit.

[0095] Specifically, the latch unit 31 includes a first input tube Q1, a second input tube Q2, a first clamping tube Q3, a second clamping tube Q4, a first output tube Q5, and a second output tube Q6. The first input tube Q1 and the second input tube Q2 are high-voltage PMOS, the first clamping tube Q3 and the second clamping tube Q4 are high-voltage NMOS, and the first output tube Q5 and the second output tube Q6 are low-voltage NMOS.

[0096] A first end of the first input tube Q1 is connected to the first node BST, a second end of the first input tube Q1 is directly or indirectly connected to a second end of the first clamp tube Q3, and a control end of the first input tube Q1 receives a second control signal A2.

[0097] A first end of the second input tube Q2 is connected to the first node BST, a second end of the second input tube Q2 is directly or indirectly connected to a second end of the second clamp tube Q4, and a control end of the second input tube Q2 receives a first control signal A1.

[0098] The control ends of the first clamping tube Q3 and the second clamping tube Q4 are connected to the clamping voltage VCLAMP, the first end of the first clamping tube Q3 is directly or indirectly connected to the second end of the first output tube Q5, and the first end of the second clamping tube Q4 is directly or indirectly connected to the second end of the second output tube Q6.

[0099] The first end of the first output tube Q5 is connected to the second node SW, and the control end of the first output tube Q5 is connected to the first end of the second clamping tube Q4. The first end of the second output tube Q6 is connected to the second node SW, and the control end of the second output tube Q6 is connected to the first end of the first clamping tube Q3.

[0100] Furthermore, the latch unit 31 in one embodiment further includes a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a seventh resistor R7. Among them, the first end of the fourth resistor R4 is connected to the second end of the first input tube Q1, and the second end of the fourth resistor R4 is connected to the second end of the first clamp tube Q3. The first end of the fifth resistor R5 is connected to the second end of the second input tube Q2, and the second end of the fifth resistor R5 is connected to the second end of the second clamp tube Q4. The first end of the sixth resistor R6 is connected to the first end of the first clamp tube Q3, and the second end of the sixth resistor R6 is connected to the second end of the first output tube Q5. The first end of the seventh resistor R7 is connected to the first end of the second clamp tube Q4, and the second end of the seventh resistor R7 is connected to the second end of the second output tube Q6.

[0101] like Figure 7 As shown, the first driving unit 32 in one embodiment includes a third input tube Q7, a third clamping tube Q8 and a third output tube Q9. The third input tube Q7 is a high-voltage PMOS tube, the third clamping tube Q8 is a high-voltage NMOS tube, and the third output tube Q9 is a low-voltage NMOS tube.

[0102] A first end of the third input tube Q7 is connected to the first node BST, a second end of the third input tube Q7 is connected to the second end of the third clamping tube Q8, and a control end of the third input tube Q7 receives a second control signal A2.

[0103] A control end of the third clamping tube Q8 is connected to the clamping voltage VCLAMP, and a first end of the third clamping tube Q8 is connected to a second end of the third output tube Q9.

[0104] The control end of the third output tube Q9 is connected to the latch unit 31 and receives the latch signal, the first end of the third output tube Q9 is connected to the second node SW, and the second end of the third output tube Q9 generates the first driving signal B3.

[0105] like Figure 7 As shown, the second driving unit 33 in one embodiment includes a fourth input tube Q10, a fourth clamping tube Q11 and a fourth output tube Q12. The fourth input tube Q10 is a high-voltage PMOS tube, the fourth clamping tube Q11 is a high-voltage NMOS tube, and the fourth output tube Q12 is a low-voltage NMOS tube.

[0106] A first end of the fourth input tube Q10 is connected to the first node BST, a second end of the fourth input tube Q10 is connected to the second end of the fourth clamping tube Q11 , and a control end of the fourth input tube Q10 receives the third control signal A3 .

[0107] A control end of the fourth clamping tube Q11 is connected to the clamping voltage VCLAMP, and a first end of the fourth clamping tube Q11 is connected to a second end of the fourth output tube Q12.

[0108] The control end of the fourth output tube Q12 is connected to the second end of the third output tube Q9 of the first driving unit 32 and receives the first driving signal B3, the first end of the fourth output tube Q12 is connected to the second node SW, and the second end of the fourth output tube Q12 is connected to the control end of the second power tube HV_NMOS and generates a power tube driving signal NGATE.

[0109] Combination Figure 6 and Figure 7 It can be seen that the control signal generating circuit 20 is used to cooperate with the gate driving circuit 30 to enable the gate driving circuit 30 to achieve step-by-step driving. Figure 7 In the gate driving circuit 30 shown, the control signal generating circuit 20 needs to generate four control signals, namely a first control signal A1 , a second control signal A2 , a third control signal A3 and a fourth control signal A4 .

[0110] Furthermore, the driving capabilities of the first control signal A1, the second control signal A2, the third control signal A3 to the first control signal A4 are gradually enhanced, and the phases are gradually delayed, so that the input tube of the latch unit 31 of the gate drive circuit 30, the input tube of the first drive unit 32, the input tube of the second drive unit 33 and the first power tube HV_PMOS begin to turn on step by step.

[0111] Specifically, the first control signal A1 is in phase with the PWM signal; the second control signal A2 is in phase with the PWM signal, and the second control signal A2 is delayed from the first control signal A1; the third control signal A3 is in phase with the PWM signal, and the third control signal A3 is delayed from the second control signal A2; the fourth control signal A4 is in phase with the PWM signal, and the fourth control signal A4 is delayed from the third control signal A3.

[0112] like Figure 6 As shown, the control signal generating circuit 20 in one embodiment includes a multi-stage connected inverter, each inverter includes an NMOS tube and a PMOS tube. Among them, the first end of the PMOS tube is connected to the first node BST, the second end of the PMOS tube is connected to the second end of the NMOS tube, the control end of the PMOS tube is connected to the control end of the NMOS tube and serves as the input end of the inverter, the first end of the NMOS tube is connected to the floating voltage VFLOAT, and the second end of the NMOS tube is connected to the second end of the PMOS tube and serves as the output end of the inverter. The input end of the first inverter receives the PWM signal, and the output end of the first inverter is connected to the input end of the next inverter, and so on, and the corresponding control signal is obtained through the output ends of different inverters.

[0113] Specifically, the PWM signal in one embodiment generates a first control signal A1 after passing through two inverters, and the first control signal A1 is in phase with the PWM signal. The first control signal A1 generates a second control signal A2 after passing through an inverter, and the second control signal A2 is in phase opposite to the first control signal A1. The second control signal A2 generates a third control signal A3 after passing through three inverters, and the third control signal A3 is in phase opposite to the second control signal A2. The first control signal A1 generates a fourth control signal A4 after passing through five inverters, and the fourth control signal A4 is in phase opposite to the first control signal A1.

[0114] When the PWM signal is at a high level, the first control signal A1 is at a high level, the second control signal A2 is at a low level, the third control signal A3 is at a high level, the fourth control signal A4 is at a low level, the first input tube Q1 is turned on, the second input tube Q2 is turned off, the B1 node is pulled up, so the second output tube Q6 is turned on, the B2 node is pulled down, and the third output tube Q9 is turned off. Since the third input tube Q7 is turned on, the B3 node is pulled high, the fourth output tube Q12 is turned on, the fourth input tube Q10 is turned off, the power tube drive signal (i.e., the NGATE node voltage) is pulled low, the second power tube HV_NMOS is turned off, the first power tube HV_PMOS is turned on, and the target drive signal HO is pulled high.

[0115] When the PWM signal is at a low level, the first control signal A1 is at a low level, the second control signal A2 is at a high level, the third control signal A3 is at a low level, the fourth control signal A4 is at a high level, the first input tube Q1 is turned off, the second input tube Q2 is turned on, the B2 node is pulled up, so the first output tube Q5 is turned on, the B1 node is pulled down, and the third output tube Q9 is turned on. Since the third input tube Q7 is turned off, the B3 node is pulled down, the fourth output tube Q12 is turned off, the fourth input tube Q10 is turned on, the power tube drive signal (i.e., the NGATE node voltage) is pulled high, the second power tube HV_NMOS is turned on, the first power tube HV_PMOS is turned off, and the target drive signal HO is pulled low.

[0116] The voltage range of the target driving signal HO is between the voltage on the first node BST and the voltage on the second node SW, but other MOS transistors in the driving unit 32 operate in a voltage domain of about 5V under the action of the clamping voltage VCLAMP to avoid breakdown.

[0117] Furthermore, by gradually delaying the phases of the first control signal A1, the second control signal A2, the third control signal A3 to the first control signal A4, the gate drive circuit 30 is started step by step. It is also achieved that the first power tube HV_PMOS and the second power tube HV_NMOS will not be turned on or off at the same time. After the on or off state of the second power tube HV_NMOS is determined, the first power tube HV_PMOS is controlled to be turned on or off, thereby avoiding the possible damage to the circuit by a large current.

[0118] Embodiment 2:

[0119] like Figure 8 As shown, a driving circuit in an embodiment is used to drive a target power tube, and the driving circuit includes a floating rail circuit 10 , a control signal generating circuit 20 and a gate driving circuit 30 .

[0120] It can be understood that the specific circuit structure of the driving circuit in one embodiment is consistent with that in embodiment 1, and the difference is that the target power tube in one embodiment is a low-voltage side power tube, and the gate driving circuit 30 generates a target driving signal LO to control the low-voltage side power tube. Therefore, the first node in this embodiment is connected to the power supply voltage PVCC, and the second node is connected to the ground potential PGND. The difference between the power supply voltage PVCC and the ground potential PGND is about 7.5V.

[0121] The floating rail circuit 10 uses the reverse breakdown voltage Vzener (about 6V) of the first Zener diode D1 and the second Zener diode D2 to generate a floating voltage VFLOAT and a clamping voltage VCLAMP to achieve voltage stabilization. The floating voltage VFLOAT=PVCC-Vzener+VGS, and the clamping voltage VCLAMP=PGND+Vzener.

[0122] Specifically, the control end node of the first MOS tube M1 is clamped to PVCC-Vzener by the first Zener tube D1, so the floating voltage domain PVCC-VFLOAT between the first node and the floating voltage VFLOAT is Vzener-VGS. The value of the floating voltage domain PVCC-VFLOAT is about 5V, which can ensure that the high-voltage tube under the thin gate process will not be broken down.

[0123] The working principle of this embodiment is similar to that of Embodiment 1 and will not be described again here.

[0124] Embodiment 3:

[0125] like Fig. 9 As shown, a half-bridge driving circuit in an embodiment includes a first driving circuit 41 and a second driving circuit 42. The first driving circuit 41 is the driving circuit in Example 1, the first node is connected to the BST pin in the half-bridge driving circuit, and the second node is connected to the SW pin in the half-bridge driving circuit, for driving the high-voltage side power tube.

[0126] The second driving circuit 42 is the driving circuit in Embodiment 2, the first node is connected to the power supply voltage PVCC, the second node is connected to the ground potential PVCC, and is used to drive the low-voltage side power tube.

[0127] The output end of the first driving circuit 41 (i.e., the second end of the first power tube HV_PMOS and the second end of the second power tube HV_NMOS) is connected to the logic combination unit logiccombination of the second driving circuit 42 through a level conversion unit LVL_H2L. The logic combination unit logiccombination of the second driving circuit 42 is used to receive the corresponding PWM signal, and its output end is connected to the corresponding control signal generating circuit.

[0128] The output end of the second driving circuit 42 (i.e., the second end of the first power tube HV_PMOS and the second end of the second power tube HV_NMOS) is connected to the logic combination unit logiccombination of the first driving circuit 41 through a level conversion unit LVL_H2L. The logic combination unit logiccombination of the first driving circuit 41 is used to receive the corresponding PWM signal, and its output end is connected to the corresponding control signal generating circuit.

[0129] It can be seen from the above technical solutions that the present invention has the following beneficial effects:

[0130] The present invention can be applied to a high-voltage driving circuit, but the high-voltage process does not have thick gate oxide and does not support high-voltage VGS. The present invention generates a floating voltage through a floating rail circuit, so that the control signal generating circuit works in a floating voltage domain, that is, the control signals are all signals generated in the floating voltage domain BST-VFLOAT, so the VGS of the input tube in the gate driving circuit all works in the range of Vzener-VGS (about 5V), preventing the input tube from being broken down;

[0131] The present invention generates a clamping voltage through a floating rail circuit so that an output tube in a gate drive circuit can use a low-voltage tube and will not be broken down by a high voltage, thereby improving the response speed of the gate drive circuit and reducing power consumption.

[0132] The gate drive circuit of the present invention adopts a push-pull structure, and generates a target drive signal that meets a certain driving capability and is stable through step-by-step driving. For a drive circuit, only one set of floating rail circuits is needed to make the voltage variation range of the target drive signal between the voltage at the first node and the voltage at the second node. And for a half-bridge drive circuit, only two sets of floating rail circuits are needed to obtain sufficient driving capability and stable driving voltage. Figure 2 The prior art shown saves about 40% of area;

[0133] The half-bridge driving circuit of the present invention adopts a symmetrical structure. When the target driving signal generated in the low-voltage domain PVCC-PGND is quickly switched to the high-voltage domain BST-SW, the instantaneous change speed of the DC current is prevented from affecting the generation of the floating domain.

[0134] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0135] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A driving circuit for driving a target power tube, characterized in that: The driving circuit comprises: A floating rail circuit connected between a first node and a second node, used to generate a floating voltage based on a voltage on the first node and a clamping voltage based on a voltage on the second node, wherein the floating voltage is lower than the voltage on the first node and the clamping voltage is higher than the voltage on the second node; A control signal generating circuit, connected between the first node and the floating voltage, for generating a plurality of control signals based on the PWM signal; A gate drive circuit is connected between the first node and the second node and is connected to the clamping voltage. The gate drive circuit is a multi-level structure. Each level of the gate drive circuit corresponds to at least one control signal. The gate drive circuit is used to generate a target drive signal based on a plurality of control signals to drive a target power tube.

2. The driving circuit according to claim 1, characterized in that: The floating rail circuit includes a first Zener tube, a first resistor, a second resistor, a first MOS tube, a third resistor and a second Zener tube; wherein, The first end of the first Zener tube is connected to the first end of the first resistor, the second end of the first Zener tube is connected to the first node, and the second end of the first resistor is connected to the second node; The first end of the second resistor is connected to the first node, the second end of the second resistor is connected to the floating voltage, the first end of the first MOS transistor is connected to the floating voltage, the second end of the first MOS transistor is connected to the second node, and the control end of the first MOS transistor is connected to the first end of the first Zener transistor; The first end of the third resistor is connected to the first node, the second end of the third resistor is connected to the clamping voltage, the first end of the second Zener diode is connected to the second node, and the second end of the second Zener diode is connected to the clamping voltage.

3. The driving circuit according to claim 2, characterized in that: The floating rail circuit also includes: A first capacitor, wherein a first end of the first capacitor is connected to the first node, and a second end of the first capacitor is connected to a floating voltage; A second capacitor, wherein a first end of the second capacitor is connected to the clamping voltage, and a second end of the second capacitor is connected to the second node.

4. The driving circuit according to claim 1, characterized in that: The gate driving circuit includes a latch unit, a first driving unit, a second driving unit, a first power tube and a second power tube; wherein, The latch unit is connected to the control signal generating circuit, and the latch unit generates a latch signal based on a first control signal and a second control signal, wherein the first control signal and the second control signal have opposite phases; The first driving unit is connected to the control signal generating circuit and the latch unit, and the first driving unit is used to generate a first driving signal based on the latch signal and the second control signal; The second driving unit is connected to the first driving unit, and the second driving unit is used to generate a power tube driving signal based on the first driving signal and the third control signal; The first end of the first power tube is connected to the first node, the control end of the first power tube receives a fourth control signal, and the second end of the first power tube is connected to the control end of the target power tube; The first end of the second power tube is connected to the second node, the control end of the second power tube is connected to the second driving unit and receives the power tube driving signal, and the second end of the second power tube is connected to the control end of the target power tube.

5. The driving circuit according to claim 4, characterized in that: The first driving unit includes a third input tube, a third clamping tube and a third output tube; wherein, The first end of the third input tube is connected to the first node, the second end of the third input tube is connected to the second end of the third clamp tube, and the control end of the third input tube receives a second control signal; The control end of the third clamping tube is connected to the clamping voltage, and the first end of the third clamping tube is connected to the second end of the third output tube; The control end of the third output tube is connected to the latch unit and receives the latch signal, the first end of the third output tube is connected to the second node, and the second end of the third output tube is connected to the second driving unit and generates a first driving signal.

6. The driving circuit according to claim 4, characterized in that: The second driving unit includes a fourth input tube, a fourth clamping tube and a fourth output tube; wherein, The first end of the fourth input tube is connected to the first node, the second end of the fourth input tube is connected to the second end of the fourth clamp tube, and the control end of the fourth input tube receives a third control signal; The control end of the fourth clamping tube is connected to the clamping voltage, and the first end of the fourth clamping tube is connected to the second end of the fourth output tube; The control end of the fourth output tube is connected to the first driving unit and receives the first driving signal, the first end of the fourth output tube is connected to the second node, and the second end of the fourth output tube is connected to the control end of the second power tube and generates a power tube driving signal.

7. The driving circuit according to claim 4, characterized in that: The control signal generating circuit includes a plurality of connected inverters, and the plurality of inverters are used to invert and delay the PWM signal to generate a first control signal, a second control signal, a third control signal and a fourth control signal; wherein, The first control signal is in phase with the PWM signal; The second control signal is inversely proportional to the PWM signal, and the second control signal is delayed relative to the first control signal; The third control signal is in phase with the PWM signal, and the third control signal is delayed from the second control signal; The fourth control signal is inversely proportional to the PWM signal, and the fourth control signal is delayed relative to the third control signal.

8. The driving circuit according to claim 4, characterized in that: The latch unit includes a first input tube, a second input tube, a first clamping tube, a second clamping tube, a first output tube and a second output tube; wherein, The first end of the first input tube is connected to the first node, the second end of the first input tube is directly or indirectly connected to the second end of the first clamp tube, and the control end of the first input tube receives a second control signal; The first end of the second input tube is connected to the first node, the second end of the second input tube is directly or indirectly connected to the second end of the second clamp tube, and the control end of the second input tube receives a first control signal; The control ends of the first clamping tube and the second clamping tube are connected to the clamping voltage, the first end of the first clamping tube is directly or indirectly connected to the second end of the first output tube, and the first end of the second clamping tube is directly or indirectly connected to the second end of the second output tube; The first end of the first output tube is connected to the second node, and the control end of the first output tube is connected to the first end of the second clamping tube; The first end of the second output tube is connected to the second node, and the control end of the second output tube is connected to the first end of the first clamping tube.

9. The driving circuit according to claim 8, characterized in that: The latch unit further includes a fourth resistor, a fifth resistor, a sixth resistor and a seventh resistor; wherein, The first end of the fourth resistor is connected to the second end of the first input tube, and the second end of the fourth resistor is connected to the second end of the first clamp tube; The first end of the fifth resistor is connected to the second end of the second input tube, and the second end of the fifth resistor is connected to the second end of the second clamp tube; The first end of the sixth resistor is connected to the first end of the first clamping tube, and the second end of the sixth resistor is connected to the second end of the first output tube; The first end of the seventh resistor is connected to the first end of the second clamping tube, and the second end of the seventh resistor is connected to the second end of the second output tube.

10. The driving circuit according to claim 1, characterized in that: The first node is connected to a BST pin in the driving circuit, the second node is connected to a SW pin in the driving circuit, and the target power tube is a high-voltage side power tube.

11. The driving circuit according to claim 1, characterized in that: The first node is connected to a power supply voltage, the second node is connected to a ground potential, and the target power tube is a low-voltage side power tube.

12. A half-bridge driving circuit, characterized in that: The half-bridge driving circuit includes a first driving circuit and a second driving circuit; wherein, The first driving circuit is the driving circuit according to any one of claims 1 to 10; and / or, The second driving circuit is the driving circuit according to any one of claims 1 to 9 or 11.

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