Analog-to-digital conversion control device and control method

Abstract

The present invention belongs to the field of analog-to-digital conversion controller design, and discloses an analog-to-digital conversion control device and control method. The device receives the CPU's scheduling through a system bus, and generates a control signal to control the analog-to-digital converter. The device is characterized in that it includes an interface conversion unit, a decoding unit, a sampling clock generator, a channel calibration unit, a reference processing unit, a zero-crossing detection unit, and a threshold detection unit. The present invention directly uses the channel calibration unit in hardware to compensate for channel differences and uses the reference processing unit to process reference errors. At the same time, hardware can be used for zero-crossing detection and threshold detection without additional software overhead, thereby reducing resource consumption and improving system efficiency. It is convenient for users to select a processing method according to the application scenario, supporting both the operation method of the prior art and the processing method without additional software overhead.

Description

Technical Field

[0001] The invention belongs to the field of analog-to-digital conversion controller design, and in particular relates to an analog-to-digital conversion control device and a control method. Background Art

[0002] MCUs usually integrate analog-to-digital converters, which can be used to convert analog values ​​that represent changes in light, sound, pressure, and temperature into digital values. To ensure the efficient operation of the analog-to-digital converter, accurate control of the analog-to-digital conversion controller is required. The analog-to-digital conversion controller is interconnected with the system bus, and the CPU is used to schedule the operation of the analog-to-digital conversion controller. After receiving the CPU's scheduling, the analog-to-digital conversion controller generates a control signal to directly control the analog-to-digital converter to convert analog quantities into digital quantities.

[0003] Existing analog-to-digital conversion controllers usually do not include a post-processing structure. After the analog-to-digital converter completes the conversion, a conversion completion interrupt is generated. After the interrupt controller receives the interrupt, it triggers the CPU to run the corresponding interrupt service program in the storage. In the interrupt service program, the CPU can read the corresponding register to obtain the conversion value. The obtained conversion value is only globally calibrated and cannot compensate for the differences in the various channels of the analog-to-digital converter. At the same time, the source of the analog signal carries a certain reference error, which is converted together with the signal, and the final error is also reflected in the conversion value.

[0004] In view of the above situation, the prior art needs to consume additional software overhead for data processing to obtain accurate conversion values. In some scenarios, it is necessary to perform zero crossing detection and threshold detection on the conversion value. The prior art cannot directly obtain the zero crossing detection state and threshold detection state from the hardware, and it needs to consume additional software overhead for data processing. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides an analog-to-digital conversion control device and a control method, so as to achieve the purpose of eliminating the need for additional software overhead, thereby reducing resource consumption and improving system efficiency.

[0006] To achieve the above object, the technical solution of the present invention is as follows:

[0007] An analog-to-digital conversion control device, the device receives the CPU's scheduling through a system bus and generates a control signal to control the analog-to-digital converter, including an interface conversion unit, a decoding unit, a sampling clock generator, a channel calibration unit, a reference processing unit, a zero-crossing detection unit and a threshold detection unit;

[0008] CPU: Central Processing Unit, accesses the analog-to-digital conversion controller through the system bus;

[0009] The interface conversion unit is connected to the system bus and converts the bus protocol into read and write operations;

[0010] The decoding unit: decodes the read and write operations generated by the interface conversion unit, generates an enable signal 1, a global calibration value and a channel selection signal to send to the analog-to-digital converter, and the channel selection signal is sent to the channel calibration unit at the same time; generates a clock division value to send to the sampling clock generator; generates different channel calibration values ​​to send to the channel calibration unit; generates a reference value to send to the reference value processing unit; generates an enable signal 2 to the zero-crossing detection unit; generates an enable signal 3 to the threshold detection unit; receives the sampling conversion value sent by the analog-to-digital converter and the post-processing value sent by the reference value processing unit, and sends them to the interface conversion unit;

[0011] The sampling clock generator generates sampling clocks of different frequencies according to the clock frequency division value and sends them to the analog-to-digital converter;

[0012] The channel calibration unit processes the sampled conversion values ​​sent by the analog-to-digital converter according to the channel selection signal and the calibration values ​​of different channels, and sends the results to the reference processing unit;

[0013] The reference processing unit processes the result output by the channel calibration unit according to the reference value, sends the post-processing value to the decoding unit, the zero-crossing detection unit and the threshold detection unit, and generates a post-processing completion interrupt to send to the interrupt controller;

[0014] The zero-crossing detection unit: when the second enable signal is at a high level, a sign bit determination is performed on the post-processing value, and once the sign bit is flipped, a zero-crossing detection interrupt is immediately generated and sent to the interrupt controller;

[0015] The threshold detection unit: when the enable signal 3 is at a high level, the post-processing value is determined according to the threshold value, and once the post-processing value is higher than the maximum threshold value or lower than the minimum threshold value, a threshold detection interrupt is immediately generated and sent to the interrupt controller;

[0016] The analog-to-digital converter: under the control of the enable signal 1, the global calibration value, the channel selection signal and the sampling clock, samples and converts the input analog signal, sends the sampled conversion value to the decoding unit and the channel calibration unit, and generates a conversion completion interrupt to send to the interrupt controller;

[0017] The interrupt controller triggers the CPU to run the corresponding interrupt service program in the storage after receiving the zero-crossing detection interrupt, the threshold detection interrupt, the conversion completion interrupt and the post-processing completion interrupt.

[0018] An analog-to-digital conversion control method, using the analog-to-digital conversion control device as described above, comprises the following steps:

[0019] (1) The CPU issues a series of write bus operations to the analog-to-digital converter controller;

[0020] (2) The interface conversion unit that reaches the analog-to-digital conversion controller via the system bus;

[0021] (3) The interface conversion unit converts the bus operation into a write operation and sends it to the decoding unit;

[0022] (4) The decoding unit decodes the write operation, generates an enable signal, a channel selection signal, and a global calibration value, which are sent to the analog-to-digital converter, and generates a clock division value which is sent to the sampling clock generator;

[0023] (5) The sampling clock generator generates sampling clocks of different frequencies according to the clock division value and sends them to the analog-to-digital converter;

[0024] (6) The analog-to-digital converter samples and converts the input analog signal according to the enable signal 1, the channel selection signal, the global calibration value, and the sampling clock, sends the sampled conversion value to the decoding unit and the channel calibration unit, and generates a conversion completion interrupt to the interrupt controller; at this time, the decoding unit does not send different channel calibration values ​​to the channel calibration unit, so the channel calibration unit does not work;

[0025] (7) After the interrupt controller receives the conversion completion interrupt, it triggers the CPU to run the corresponding interrupt service program in the storage, obtains the sampled conversion value sent by the decoding unit through the conversion interface unit, and uses software to compensate.

[0026] An analog-to-digital conversion control method, using the analog-to-digital conversion control device as described above, comprises the following steps:

[0027] (1) The CPU issues a series of write bus operations to the analog-to-digital converter controller;

[0028] (2) The interface conversion unit that reaches the analog-to-digital conversion controller via the system bus;

[0029] (3) The interface conversion unit converts the bus operation into a write operation and sends it to the decoding unit;

[0030] (4) The decoding unit decodes the write operation, generates an enable signal 1, a channel selection signal, and a global calibration value, and sends them to the analog-to-digital converter. The channel selection signal is also sent to the channel calibration unit, generates a clock division value and sends it to the sampling clock generator, generates different channel calibration values ​​and sends them to the channel calibration unit, and generates a reference value and sends it to the reference value processing unit;

[0031] (5) The sampling clock generator generates sampling clocks of different frequencies according to the clock division value and sends them to the analog-to-digital converter;

[0032] (6) The analog-to-digital converter samples and converts the input analog signal according to the enable signal 1, the channel selection signal, the global calibration value, and the sampling clock, and sends the sampled conversion value to the decoding unit and the channel calibration unit;

[0033] (7) The channel calibration unit processes the sampled conversion values ​​sent by the analog-to-digital converter according to the channel selection signal and the calibration values ​​of different channels, and sends the results to the reference processing unit;

[0034] (8) The reference processing unit processes the result output by the channel calibration unit according to the reference value, sends the post-processing value to the decoding unit, the zero-crossing detection unit and the threshold detection unit, and generates a post-processing completion interrupt to the interrupt controller; at this time, the enable signal 2 and the enable signal 3 are low level, and the zero-crossing detection unit and the threshold detection unit do not work;

[0035] (9) After the interrupt controller receives the post-processing completion interrupt, it triggers the CPU to run the corresponding interrupt service program in the storage, and obtains the post-processing value sent by the decoding unit through the conversion interface unit, which can be used directly without software compensation.

[0036] An analog-to-digital conversion control method, using the analog-to-digital conversion control device as described above, comprises the following steps:

[0037] (1) The CPU issues a series of write bus operations to the analog-to-digital converter controller;

[0038] (2) The interface conversion unit that reaches the analog-to-digital conversion controller via the system bus;

[0039] (3) The interface conversion unit converts the bus operation into a write operation and sends it to the decoding unit;

[0040] (4) The decoding unit decodes the write operation, generates an enable signal 1, a channel selection signal, and a global calibration value, and sends them to the analog-to-digital converter. The channel selection signal is also sent to the channel calibration unit, generates a clock division value and sends it to the sampling clock generator, generates different channel calibration values ​​and sends them to the channel calibration unit, generates a reference value and sends it to the reference value processing unit, generates an enable signal 2 and sends it to the zero-crossing detection unit, and generates an enable signal 3 and sends it to the threshold detection unit;

[0041] (5) The sampling clock generator generates sampling clocks of different frequencies according to the clock division value and sends them to the analog-to-digital converter;

[0042] (6) The analog-to-digital converter samples and converts the input analog signal according to the enable signal 1, the channel selection signal, the global calibration value, and the sampling clock, and sends the sampled conversion value to the decoding unit and the channel calibration unit;

[0043] (7) The channel calibration unit processes the sampled conversion values ​​sent by the analog-to-digital converter according to the channel selection signal and the calibration values ​​of different channels, and sends the results to the reference processing unit;

[0044] (8) The reference processing unit processes the result output by the channel calibration unit according to the reference value, and sends the post-processing value to the decoding unit, the zero-crossing detection unit, and the threshold detection unit;

[0045] (9) When the enable signal 2 is at a high level, the zero-crossing detection unit performs a sign bit determination on the post-processing value. Once the sign bit flips, a zero-crossing detection interrupt is immediately generated and sent to the interrupt controller;

[0046] When the enable signal 3 is at a high level, the threshold detection unit determines the post-processing value according to the threshold value, and once the post-processing value is higher than the maximum threshold value or lower than the minimum threshold value, a threshold detection interrupt is immediately generated and sent to the interrupt controller;

[0047] (10) After the interrupt controller receives the zero-crossing detection interrupt or the threshold detection interrupt, it triggers the CPU to run the corresponding interrupt service program in the storage, and obtains the post-processing value generated by the reference value processing unit through the conversion interface unit and the decoding unit, which can be used directly without software compensation.

[0048] Through the above technical solution, the analog-to-digital conversion control device and control method provided by the present invention have the following beneficial effects:

[0049] The analog-to-digital conversion control device disclosed in the present invention directly uses a channel calibration unit in hardware to compensate for channel differences and uses a reference processing unit to process reference errors. At the same time, hardware can be used for zero-crossing detection and threshold detection without additional software overhead, thereby reducing resource consumption and improving system efficiency. It is convenient for users to select a processing method according to the application scenario, supporting both the operation method of the existing technology and the processing method without additional software overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below.

[0051] Figure 1 A schematic diagram of an analog-to-digital conversion control device disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0052] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0053] The present invention provides an analog-to-digital conversion control device, such as Figure 1As shown, the device receives the CPU's scheduling through the system bus and generates a control signal to control the analog-to-digital converter, including an interface conversion unit, a decoding unit, a sampling clock generator, a channel calibration unit, a reference processing unit, a zero-crossing detection unit and a threshold detection unit.

[0054] CPU: Central Processing Unit, accesses the analog-to-digital converter controller through the system bus.

[0055] Interface conversion unit: connected to the system bus and converts the bus protocol into read and write operations.

[0056] Decoding unit: decodes the read and write operations generated by the interface conversion unit, generates enable signal 1, global calibration value and channel selection signal and sends them to the analog-to-digital converter, and the channel selection signal is sent to the channel calibration unit at the same time; generates clock division value and sends it to the sampling clock generator; generates calibration values ​​of different channels and sends them to the channel calibration unit; generates reference value and sends it to the reference value processing unit; generates enable signal 2 to the zero-crossing detection unit; generates enable signal 3 to the threshold detection unit; receives the sampling conversion value sent by the analog-to-digital converter and the post-processing value sent by the reference value processing unit, and sends them to the interface conversion unit.

[0057] Sampling clock generator: Generates sampling clocks of different frequencies according to the clock division value and sends them to the analog-to-digital converter.

[0058] Channel calibration unit: processes the sampled conversion values ​​sent by the analog-to-digital converter according to the channel selection signal and different channel calibration values, and sends the results to the reference processing unit.

[0059] Reference processing unit: processes the result output by the channel calibration unit according to the reference value, sends the post-processing value to the decoding unit, the zero-crossing detection unit and the threshold detection unit, and generates a post-processing completion interrupt to the interrupt controller.

[0060] Zero-crossing detection unit: When the enable signal 2 is at a high level, the sign bit of the post-processing value is determined. Once the sign bit is flipped, a zero-crossing detection interrupt is immediately generated and sent to the interrupt controller.

[0061] Threshold detection unit: When the enable signal three is at a high level, the post-processing value is determined according to the threshold. Once the post-processing value is higher than the maximum threshold or lower than the minimum threshold, a threshold detection interrupt is immediately generated and sent to the interrupt controller.

[0062] Analog-to-digital converter: Under the control of enable signal 1, global calibration value, channel selection signal and sampling clock, it samples and converts the input analog signal, sends the sampled conversion value to the decoding unit and channel calibration unit, and generates a conversion completion interrupt to the interrupt controller.

[0063] Interrupt controller: After receiving the zero-crossing detection interrupt, threshold detection interrupt, conversion completion interrupt and post-processing completion interrupt, it triggers the CPU to run the corresponding interrupt service program in the storage.

[0064] The analog signal channels supported by the analog-to-digital converter are set to 16 according to actual conditions, and one of the 16 channels can be sampled and converted at the same time.

[0065] The basic mode 1 supported by the present invention has the same effect as the prior art, directly outputting the sample conversion value without post-processing, as follows:

[0066] An analog-to-digital conversion control method, using the above analog-to-digital conversion control device, comprises the following steps:

[0067] (1) The CPU issues a series of write bus operations to the analog-to-digital converter controller;

[0068] (2) The interface conversion unit that reaches the analog-to-digital conversion controller via the system bus;

[0069] (3) The interface conversion unit converts the bus operation into a write operation and sends it to the decoding unit;

[0070] (4) The decoding unit decodes the write operation, generates an enable signal, a channel selection signal, and a global calibration value, which are sent to the analog-to-digital converter, and generates a clock division value which is sent to the sampling clock generator;

[0071] (5) The sampling clock generator generates sampling clocks of different frequencies according to the clock division value and sends them to the analog-to-digital converter;

[0072] (6) The analog-to-digital converter samples and converts the input analog signal according to the enable signal 1, the channel selection signal, the global calibration value, and the sampling clock, sends the sampled conversion value to the decoding unit and the channel calibration unit, and generates a conversion completion interrupt to the interrupt controller; at this time, the decoding unit does not send different channel calibration values ​​to the channel calibration unit, so the channel calibration unit does not work;

[0073] (7) After the interrupt controller receives the conversion completion interrupt, it triggers the CPU to run the corresponding interrupt service program in the storage, obtains the sampled conversion value sent by the decoding unit through the conversion interface unit, and uses software to compensate.

[0074] The present invention supports mode 2, using the post-processing part to perform channel calibration and reference value processing, as follows:

[0075] An analog-to-digital conversion control method, using the above analog-to-digital conversion control device, comprises the following steps:

[0076] (1) The CPU issues a series of write bus operations to the analog-to-digital converter controller;

[0077] (2) The interface conversion unit that reaches the analog-to-digital conversion controller via the system bus;

[0078] (3) The interface conversion unit converts the bus operation into a write operation and sends it to the decoding unit;

[0079] (4) The decoding unit decodes the write operation, generates an enable signal 1, a channel selection signal, and a global calibration value, and sends them to the analog-to-digital converter. The channel selection signal is also sent to the channel calibration unit, generates a clock division value and sends it to the sampling clock generator, generates different channel calibration values ​​and sends them to the channel calibration unit, and generates a reference value and sends it to the reference value processing unit;

[0080] (5) The sampling clock generator generates sampling clocks of different frequencies according to the clock division value and sends them to the analog-to-digital converter;

[0081] (6) The analog-to-digital converter samples and converts the input analog signal according to the enable signal 1, the channel selection signal, the global calibration value, and the sampling clock, and sends the sampled conversion value to the decoding unit and the channel calibration unit;

[0082] (7) The channel calibration unit processes the sampled conversion values ​​sent by the analog-to-digital converter according to the channel selection signal and the calibration values ​​of different channels, and sends the results to the reference processing unit;

[0083] (8) The reference processing unit processes the result output by the channel calibration unit according to the reference value, sends the post-processing value to the decoding unit, the zero-crossing detection unit and the threshold detection unit, and generates a post-processing completion interrupt to the interrupt controller; at this time, the enable signal 2 and the enable signal 3 are low level, and the zero-crossing detection unit and the threshold detection unit do not work;

[0084] (9) After the interrupt controller receives the post-processing completion interrupt, it triggers the CPU to run the corresponding interrupt service program in the storage, and obtains the post-processing value sent by the decoding unit through the conversion interface unit, which can be used directly without software compensation.

[0085] The present invention supports mode 3, using the post-processing part to perform zero-crossing detection and threshold detection on the post-processing value, as follows:

[0086] An analog-to-digital conversion control method, using the above analog-to-digital conversion control device, comprises the following steps:

[0087] (1) The CPU issues a series of write bus operations to the analog-to-digital converter controller;

[0088] (2) The interface conversion unit that reaches the analog-to-digital conversion controller via the system bus;

[0089] (3) The interface conversion unit converts the bus operation into a write operation and sends it to the decoding unit;

[0090] (4) The decoding unit decodes the write operation, generates an enable signal 1, a channel selection signal, and a global calibration value, and sends them to the analog-to-digital converter. The channel selection signal is also sent to the channel calibration unit, generates a clock division value and sends it to the sampling clock generator, generates different channel calibration values ​​and sends them to the channel calibration unit, generates a reference value and sends it to the reference value processing unit, generates an enable signal 2 and sends it to the zero-crossing detection unit, and generates an enable signal 3 and sends it to the threshold detection unit;

[0091] (5) The sampling clock generator generates sampling clocks of different frequencies according to the clock division value and sends them to the analog-to-digital converter;

[0092] (6) The analog-to-digital converter samples and converts the input analog signal according to the enable signal 1, the channel selection signal, the global calibration value, and the sampling clock, and sends the sampled conversion value to the decoding unit and the channel calibration unit;

[0093] (7) The channel calibration unit processes the sampled conversion values ​​sent by the analog-to-digital converter according to the channel selection signal and the calibration values ​​of different channels, and sends the results to the reference processing unit;

[0094] (8) The reference processing unit processes the result output by the channel calibration unit according to the reference value, and sends the post-processing value to the decoding unit, the zero-crossing detection unit, and the threshold detection unit;

[0095] (9) When the enable signal 2 is at a high level, the zero-crossing detection unit performs a sign bit determination on the post-processing value. Once the sign bit flips, a zero-crossing detection interrupt is immediately generated and sent to the interrupt controller;

[0096] When the enable signal 3 is at a high level, the threshold detection unit determines the post-processing value according to the threshold value, and once the post-processing value is higher than the maximum threshold value or lower than the minimum threshold value, a threshold detection interrupt is immediately generated and sent to the interrupt controller;

[0097] (10) After the interrupt controller receives the zero-crossing detection interrupt or the threshold detection interrupt, it triggers the CPU to run the corresponding interrupt service program in the storage, and obtains the post-processing value generated by the reference value processing unit through the conversion interface unit and the decoding unit, which can be used directly without software compensation.

[0098] In addition, the user configures the channel calibration value and the reference value to 0, and the post-processing value is equal to the sample conversion value. At this time, the sample conversion value can be subjected to zero-crossing detection and threshold detection.

[0099] In summary, the analog-to-digital conversion control device of the present invention facilitates users to select a processing method according to application scenarios, supports both the operation methods of the prior art and the processing methods without additional software overhead, reduces resource consumption, and improves system efficiency.

[0100] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An analog-to-digital conversion control device, which receives the CPU's scheduling through a system bus and generates a control signal to control an analog-to-digital converter, characterized in that: It includes an interface conversion unit, a decoding unit, a sampling clock generator, a channel calibration unit, a reference processing unit, a zero-crossing detection unit and a threshold detection unit; CPU: Central Processing Unit, accesses the analog-to-digital conversion controller through the system bus; The interface conversion unit is connected to the system bus and converts the bus protocol into read and write operations; The decoding unit: decodes the read and write operations generated by the interface conversion unit, generates an enable signal 1, a global calibration value and a channel selection signal to send to the analog-to-digital converter, and the channel selection signal is sent to the channel calibration unit at the same time; generates a clock division value to send to the sampling clock generator; generates different channel calibration values ​​to send to the channel calibration unit; generates a reference value to send to the reference value processing unit; generates an enable signal 2 to the zero-crossing detection unit; generates an enable signal 3 to the threshold detection unit; receives the sampling conversion value sent by the analog-to-digital converter and the post-processing value sent by the reference value processing unit, and sends them to the interface conversion unit; The sampling clock generator generates sampling clocks of different frequencies according to the clock frequency division value and sends them to the analog-to-digital converter; The channel calibration unit processes the sampled conversion values ​​sent by the analog-to-digital converter according to the channel selection signal and the calibration values ​​of different channels, and sends the results to the reference processing unit; The reference processing unit processes the result output by the channel calibration unit according to the reference value, sends the post-processing value to the decoding unit, the zero-crossing detection unit and the threshold detection unit, and generates a post-processing completion interrupt to send to the interrupt controller; The zero-crossing detection unit: when the second enable signal is at a high level, a sign bit determination is performed on the post-processing value, and once the sign bit is flipped, a zero-crossing detection interrupt is immediately generated and sent to the interrupt controller; The threshold detection unit: when the enable signal 3 is at a high level, the post-processing value is determined according to the threshold value, and once the post-processing value is higher than the maximum threshold value or lower than the minimum threshold value, a threshold detection interrupt is immediately generated and sent to the interrupt controller; The analog-to-digital converter: under the control of the enable signal 1, the global calibration value, the channel selection signal and the sampling clock, samples and converts the input analog signal, sends the sampled conversion value to the decoding unit and the channel calibration unit, and generates a conversion completion interrupt to send to the interrupt controller; The interrupt controller triggers the CPU to run the corresponding interrupt service program in the storage after receiving the zero-crossing detection interrupt, the threshold detection interrupt, the conversion completion interrupt and the post-processing completion interrupt.

2. An analog-to-digital conversion control method, using an analog-to-digital conversion control device as claimed in claim 1, characterized in that: The steps include: (1) The CPU issues a series of write bus operations to the analog-to-digital converter controller; (2) The interface conversion unit that reaches the analog-to-digital conversion controller via the system bus; (3) The interface conversion unit converts the bus operation into a write operation and sends it to the decoding unit; (4) The decoding unit decodes the write operation, generates an enable signal, a channel selection signal, and a global calibration value, which are sent to the analog-to-digital converter, and generates a clock division value which is sent to the sampling clock generator; (5) The sampling clock generator generates sampling clocks of different frequencies according to the clock division value and sends them to the analog-to-digital converter; (6) The analog-to-digital converter samples and converts the input analog signal according to the enable signal 1, the channel selection signal, the global calibration value, and the sampling clock, sends the sampled conversion value to the decoding unit and the channel calibration unit, and generates a conversion completion interrupt to the interrupt controller; at this time, the decoding unit does not send different channel calibration values ​​to the channel calibration unit, so the channel calibration unit does not work; (7) After the interrupt controller receives the conversion completion interrupt, it triggers the CPU to run the corresponding interrupt service program in the storage, obtains the sampled conversion value sent by the decoding unit through the conversion interface unit, and uses software to compensate.

3. An analog-to-digital conversion control method, using an analog-to-digital conversion control device as claimed in claim 1, characterized in that: The steps include: (1) The CPU issues a series of write bus operations to the analog-to-digital converter controller; (2) The interface conversion unit that reaches the analog-to-digital conversion controller via the system bus; (3) The interface conversion unit converts the bus operation into a write operation and sends it to the decoding unit; (4) The decoding unit decodes the write operation, generates an enable signal 1, a channel selection signal, and a global calibration value, and sends them to the analog-to-digital converter. The channel selection signal is also sent to the channel calibration unit, generates a clock division value and sends it to the sampling clock generator, generates different channel calibration values ​​and sends them to the channel calibration unit, and generates a reference value and sends it to the reference value processing unit; (5) The sampling clock generator generates sampling clocks of different frequencies according to the clock division value and sends them to the analog-to-digital converter; (6) The analog-to-digital converter samples and converts the input analog signal according to the enable signal 1, the channel selection signal, the global calibration value, and the sampling clock, and sends the sampled conversion value to the decoding unit and the channel calibration unit; (7) The channel calibration unit processes the sampled conversion values ​​sent by the analog-to-digital converter according to the channel selection signal and the calibration values ​​of different channels, and sends the results to the reference processing unit; (8) The reference processing unit processes the result output by the channel calibration unit according to the reference value, sends the post-processing value to the decoding unit, the zero-crossing detection unit and the threshold detection unit, and generates a post-processing completion interrupt to the interrupt controller; at this time, the enable signal 2 and the enable signal 3 are low level, and the zero-crossing detection unit and the threshold detection unit do not work; (9) After the interrupt controller receives the post-processing completion interrupt, it triggers the CPU to run the corresponding interrupt service program in the storage, and obtains the post-processing value sent by the decoding unit through the conversion interface unit, which can be used directly without software compensation.

4. An analog-to-digital conversion control method, using an analog-to-digital conversion control device as claimed in claim 1, characterized in that: The steps include: (1) The CPU issues a series of write bus operations to the analog-to-digital converter controller; (2) The interface conversion unit that reaches the analog-to-digital conversion controller via the system bus; (3) The interface conversion unit converts the bus operation into a write operation and sends it to the decoding unit; (4) The decoding unit decodes the write operation, generates an enable signal 1, a channel selection signal, and a global calibration value, and sends them to the analog-to-digital converter. The channel selection signal is also sent to the channel calibration unit, generates a clock division value and sends it to the sampling clock generator, generates different channel calibration values ​​and sends them to the channel calibration unit, generates a reference value and sends it to the reference value processing unit, generates an enable signal 2 and sends it to the zero-crossing detection unit, and generates an enable signal 3 and sends it to the threshold detection unit; (5) The sampling clock generator generates sampling clocks of different frequencies according to the clock division value and sends them to the analog-to-digital converter; (6) The analog-to-digital converter samples and converts the input analog signal according to the enable signal 1, the channel selection signal, the global calibration value, and the sampling clock, and sends the sampled conversion value to the decoding unit and the channel calibration unit; (7) The channel calibration unit processes the sampled conversion values ​​sent by the analog-to-digital converter according to the channel selection signal and the calibration values ​​of different channels, and sends the results to the reference processing unit; (8) The reference processing unit processes the result output by the channel calibration unit according to the reference value, and sends the post-processing value to the decoding unit, the zero-crossing detection unit, and the threshold detection unit; (9) When the enable signal 2 is at a high level, the zero-crossing detection unit performs a sign bit determination on the post-processing value. Once the sign bit flips, a zero-crossing detection interrupt is immediately generated and sent to the interrupt controller; When the enable signal 3 is at a high level, the threshold detection unit determines the post-processing value according to the threshold value, and once the post-processing value is higher than the maximum threshold value or lower than the minimum threshold value, a threshold detection interrupt is immediately generated and sent to the interrupt controller; (10) After the interrupt controller receives the zero-crossing detection interrupt or the threshold detection interrupt, it triggers the CPU to run the corresponding interrupt service program in the storage, and obtains the post-processing value generated by the reference value processing unit through the conversion interface unit and the decoding unit, which can be used directly without software compensation.

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