Digital-to-analog converter

Abstract

A digital-to-analog converter (DAC) is a digital-to-analog converter (A to 2DAC) realized based on a digital-to-analog converter (B to 2DAC), and comprises a 0-th circuit unit to an n-th circuit unit, and the 0-th circuit unit is a digital-to-analog converter (B to 2DAC). The i-th circuit unit among the first to (n-1)-th circuit units includes: a B to 2DAC having two output voltages as two input voltages of the B to 2DAC of the (i-1)-th circuit unit; and (B-2) 2C (i) to 1DAC having (B-2) output voltages as (B-2) input voltages of the B to 2DAC of the (i-1) th circuit unit, where C (i) is the ith parameter. The nth circuit unit includes: an X to 2DAC having two output voltages as two input voltages of the B to 2DAC of the (n-1) th circuit unit; and (B-2) 2C (n) to 1DAC having (B-2) output voltages as (B-2) input voltages of the B to 2DAC of the (n-1) th circuit unit, where C (n) is the nth parameter.

Description

Technical Field

[0001] The present invention relates to a digital-to-analog converter, and more particularly to an area-saving digital-to-analog converter. Background Art

[0002] In the driving circuit of a liquid crystal display (LCD), an operational amplifier (OPA) is generally used to drive the liquid crystal on the panel. By driving different output voltages, the operational amplifier can change the transmittance of the liquid crystal to display different grayscales. Please refer to Figure 1 The operational amplifier circuit can be divided into a voltage selection digital-to-analog converter (DAC) 11 and a current interpolation operational amplifier circuit 13. The digital-to-analog converter 11 outputs two voltage values ​​(VH, VL), which are then passed through the operational amplifier circuit 13 to generate a voltage value between VH and VL, such as Figure 1 The figure shows that a 10-bit digital-to-analog conversion can be completed by using a 7-bit digital-to-analog converter 11 and a 3-bit operational amplifier circuit 13 for current interpolation. 7 +1) input voltages (VR0~VR128) and 2 output voltages (VH, VL), so the 7-bit digital-to-analog converter 11 is also called 129 to 2DAC.

[0003] Figure 1 The 7-bit digital-to-analog converter 11 shown is conventionally implemented using a tree type architecture. This architecture has the problem of redundant switches. For the sake of convenience, Figure 2 The structure of a 3-bit tree-like digital-to-analog converter (also called a 9-to-2 DAC) and its corresponding truth table are shown, where the 9-to-2 DAC includes 28 switches and 9 (=2 3 +1) reference voltages (VR0~VR8), the values ​​of variables b0, b1, b2 in the truth table represent the state of the switch in the 9 to 2 DAC, and the switch can be switched by a set of values ​​(b0, b1, b2) to generate a set of voltage values ​​(VH, VL). For example, when a set of (b0, b1, b2) is (1, 0, 1), the voltage value (VH, VL) is (VR6, VR5), and the Figure 2 It can be observed that the VH of the previous group of outputs is the VL of the next group of outputs. Therefore, the same voltage node in the 9-to-2 DAC circuit will be repeatedly selected by two switching switches, so the same voltage node will be connected to two switches, resulting in the use of redundant transistor switches and increasing the area of ​​the circuit layout.

[0004] As the number of bits of the digital-to-analog converter increases, the number of switches required also increases dramatically. For example, when the number of bits is extended to 7 bits, taking 129 to 2DAC as an example, Figure 3As shown, it can be considered as consisting of two 128 to 1 DACs, where the number of switches of one 128 to 1 DAC is 128+64+32+16+8+4+2=254. Therefore, a 7-bit tree-like digital-to-analog converter requires a total of 508 switches to complete the voltage selection of the 128-file.

[0005] Therefore, there are still many deficiencies in the circuit design of the conventional digital-to-analog converter and there is a need to improve them. Summary of the invention

[0006] The main purpose of the present invention is to provide an area-saving digital-to-analog converter, by implementing an A-to-2 digital-to-analog converter based on a B-to-2 digital-to-analog converter, so as to effectively reduce the required circuit area.

[0007] To achieve the aforementioned objectives, the present invention provides a digital-to-analog converter, which is an A-to-2 digital-to-analog converter implemented based on a B-to-2 digital-to-analog converter, wherein A and B are integers greater than 2 and A is greater than B, and the digital-to-analog converter includes 0th to nth circuit units, n is an integer greater than 0, and the 1st to nth circuit units have 1st to nth parameters respectively, wherein the 0th circuit unit is a B-to-2 digital-to-analog converter; there is an i-th circuit unit in the 1st to (n-1)th circuit units, wherein i=1 to (n-1), and the i-th circuit unit includes: a B-to-2 digital-to-analog converter having 2 output voltages as 2 of the B input voltages of the B-to-2 digital-to-analog conversion circuit of the (i-1)th circuit unit; and (B-2) 2 C (i) a digital-to-analog converter having (B-2) output voltages as the remaining (B-2) input voltages of the B-to-2 digital-to-analog converter of the (i-1)th circuit unit, wherein C(i) represents the i-th parameter; the n-th circuit unit comprising: an X-to-2 digital-to-analog converter having 2 output voltages as 2 of the B input voltages of the B-to-2 digital-to-analog converter of the (n-1)th circuit unit, wherein X is an integer between 3 and B; and (B-2) 2 C(n) to 1 digital-to-analog converter, having (B-2) output voltages as the remaining (B-2) input voltages of the B to 2 digital-to-analog converter of the (n-1)th circuit unit, wherein C(n) represents the nth parameter.

[0008] The above summary and the following detailed description are exemplary in nature and are intended to further illustrate the claims of the present invention. Other objects and advantages of the present invention will be described in the subsequent description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Schematic diagram of an operational amplifier.

[0010] Figure 2 Shows the structure of a 3-bit tree-like digital-to-analog converter and its corresponding truth table.

[0011] Figure 3 Shows a 129 to 2 digital to analog converter composed of two 128 to 1 digital to analog converters.

[0012] Figure 4 A system architecture diagram showing the area-saving digital-to-analog converter of the present invention.

[0013] Figure 5A Display each 2 of the i-th circuit unit C(i) 2 to 1 Digital to Analog Converter C(i) An input voltage.

[0014] Figure 5B Display each 2 of the nth circuit unit C(n) 2 to 1 Digital to Analog Converter C(n) An input voltage.

[0015] Figure 6 The digital-to-analog converter of the present invention is shown to be a 129-to-2 digital-to-analog converter implemented based on a 3-to-2 digital-to-analog converter.

[0016] Figure 7 The digital-to-analog converter of the present invention is shown to be a 129-to-2 digital-to-analog converter implemented based on a 5-to-2 digital-to-analog converter.

[0017] Explanation of symbols:

[0018] Digital to Analog Converter 11

[0019] Operational amplifier circuit 13

[0020] Circuit unit CKT DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the implementation of the present invention and are not intended to limit the present invention.

[0022] Figure 4The system architecture diagram of the area-saving digital-to-analog converter (DAC) of the present invention is shown, wherein the area-saving digital-to-analog converter (DAC) is an A-to-2 digital-to-analog converter (A-to-2DAC), and the A-to-2DAC is implemented based on a B-to-2 digital-to-analog converter (B-to-2DAC), wherein A and B are integers greater than 2 and A is greater than B, such as Figure 4 As shown, the area-saving digital-to-analog converter includes (n+1) circuit units CKT, namely the 0th circuit unit CKT(0) to the nth circuit unit CKT(n), wherein n is an integer greater than 0, and the 1st circuit unit CKT(1) to the nth circuit unit CKT(n) respectively have the 1st parameter to the nth parameter.

[0023] like Figure 4 As shown, the circuit structure of the 0th circuit unit CKT(0) includes a B to 2DAC; and each circuit unit of the 1st circuit unit CKT(1) to the (n-1)th circuit unit CKT(n-1) has a similar circuit structure. For the sake of generality, the circuit structure of the 1st circuit unit CKT(1) to the (n-1)th circuit unit CKT(n-1) is explained by taking the i-th circuit unit CKT(i) (i=1~(n-1)) as an example, wherein the i-th circuit unit CKT(i) has the i-th parameter, and the i-th circuit unit CKT(i) includes a B to 2DAC, and (B-2) 2 C(i) to 1 digital to analog converter (2 C(i) to 1DAC), where C(i) represents the i-th parameter.

[0024] The B to 2DAC of the aforementioned i-th circuit unit CKT(i) has 2 output voltages as 2 of the B input voltages of the B to 2DAC of the (i-1)-th circuit unit CKT(i-1), and the B to 2DAC of the i-th circuit unit CKT(i) has B input voltages.

[0025] The (B-2) 2 of the i-th circuit unit CKT(i) C(i) The B to 1 DAC has a total of (B-2) output voltages as the remaining (B-2) input voltages of the B to 2 DAC of the (i-1)th circuit unit CKT(i-1), and each 2 C (i) to 1DAC with 2 C(i) An input voltage.

[0026] According to the circuit structure of the i-th circuit unit CKT(i) described above, it can be known that the two output voltages of the B to 2DAC of the (i+1)-th circuit unit CKT(i+1) and the (B-2) 2 of the (i+1)-th circuit unit CKT(i+1) C(i+1) to 1 digital to analog converter (2C(i+1) The (B-2) output voltage of the B to 1 DAC) is used as the B input voltage of the B to 2 DAC of the i-th circuit unit CKT(i). Based on this, the circuit structure and circuit connection relationship of the 0th circuit unit CKT(0) to the (n-1)th circuit unit CKT(n-1) can be understood.

[0027] Furthermore, the nth circuit unit CKT(n) includes an X to 2 digital analog converter (X to 2 DAC), and (B-2) 2 C (n) to 1 digital to analog converter (2 C(n) To 1DAC), wherein X is an integer between 3 and B (3<=X<=B), C(n) represents the nth parameter, the X to 2 digital analog converter (X to 2DAC) of the aforementioned nth circuit unit CKT(n) has 2 output voltages as 2 of the B input voltages of the B to 2DAC of the (n-1)th circuit unit CKT(n-1), and the X to 2DAC of the nth circuit unit CKT(n) has X input voltages. The (B-2) 2 C(n) The B to 1 DAC has a total of (B-2) output voltages as the remaining (B-2) input voltages of the B to 2 DAC of the (n-1)th circuit unit CKT(n-1), and each 2 C(n) to 1DAC with 2 C(n) An input voltage is obtained, based on which the circuit structure and circuit connection relationship of the nth circuit unit CKT(n) can be understood.

[0028] To further optimize the circuit, in the area-saving digital-to-analog converter of the present invention, the A value and the B value can be selected to be divisible by (A-1) / (B-1); and the value n representing the number of circuit units CKT can be obtained by the following relationship: When there is a value q such that log2((A-1) / (B-1) q )=1, then n=q, otherwise n is in accordance with log2((A-1) / (B-1) n )=2; Furthermore, the value of X in the nth circuit unit CKT(n) is A / (2 C(1) +2 C(2) +2 C(3) +…+2 C(n) )×(B-2)), where C(1) to C(n) represent the first to nth parameters, respectively, and the first to nth parameters are log2((A-1) / (B-1) Y ), Y is an integer between 1 and n (1≤Y≤n).

[0029] Please refer to Figure 4, each of the i-th circuit unit CKT(i) (i=1 to (n-1)) 2 C(i) 2 to 1DAC C(i) input voltage, and each of the nth circuit unit CKT(n) C(n) 2 to 1DAC C(n) The input voltages are selected from A reference voltages (VR[0] to VR[A-1]), and the X to 2DAC input voltages of the n-th circuit unit CKT(n) are each 2 of the A reference voltages not selected as the input voltages of the i-th circuit unit CKT(i) (i=1 to (n-1)). C(i) 2 to 1DAC C(i) input voltage, and 2 of the nth circuit unit CKT(n) C(n) 2 to 1DAC C(n) The aforementioned A reference voltages include the 0th reference voltage VR[0] to the (A-1)th reference voltage VR[A-1], and the 0th reference voltage VR[0] to the (A-1)th reference voltage VR[A-1] are increasing or decreasing voltages.

[0030] Figure 5A Show how to select each of the i-th circuit unit CKT(i) (i=1 to (n-1)) from A reference voltages 2 C(i) 2 to 1DAC C(i) input voltages, which lists each 2 C(i) 2 to 1DAC C(i) The calculation method of the input voltage is to calculate the kth 2 of the i-th circuit unit. C(i) 2 to 1DAC C(i) The input voltage is expressed as: VR[2 C (n-i+1)-1 ×k]、VR[2 C(n-i+1)-1 ×k+(B-1) i ×1]、VR[2 C(n-i+1)-1 ×k+(B-1) i ×2], …VR[2 C(n-i+1)-1 ×k+(B-1) i ×(2 C(i) -1)], where k is an integer between 1 and (B-2) (1≤k≤(B-2)), VR[m] represents the mth reference voltage, and m is an integer between 0 and (A-1) (0≤m≤(A-1)).

[0031] Figure 5B Show how to select each of the aforementioned n-th circuit unit CKT(n) from A reference voltages 2 C(n) 2 to 1DAC C(n)input voltages, which lists each 2 C(n) 2 to 1DAC C(n) The calculation method of the input voltage is to obtain a general method by taking the kth 2 of the nth circuit unit CKT(n) as C(n) 2 to 1DAC C(n) The input voltage is expressed as: VR[2 C(n-i+1)-1 ×k]、VR[2 C(n-i+1)-1 ×k+(B-1) n ×1]、VR[2 C(n-i+1)-1 ×k+(B-1) n ×2], …VR[2 C(n-i+1)-1 ×k+(B-1) n ×(2 C(n) -1)], where k is an integer between 1 and (B-2) (1≤k≤(B-2)), VR[m] represents the mth reference voltage, and m is an integer between 0 and (A-1) (0≤m≤(A-1)).

[0032] Figure 6 The area-saving digital-to-analog converter of the present invention is a 129-to-2 digital-to-analog converter (129-to-2DAC) (i.e., A=129, B=3) implemented based on a 3-to-2 digital-to-analog converter (3-to-2DAC), which has 129 reference voltages VR[0]-VR

[128] . Since there is a value of 6 such that log2((129-1) / (3-1) 6 )=1, so n=6. As shown in the figure, the 129 to 2DAC includes the 0th circuit unit CKT(0) to the 6th circuit unit CKT(6), and the 1st to 6th parameters of the 1st circuit unit CKT(1) to the 6th circuit unit CKT(6) are 6, 5, 4, 3, 2, and 1 respectively (that is, C(1)=6, C(2)=5, C(3)=4, C(4)=3, C(5)=2, and C(6)=1). Among them, the 1st circuit unit CKT(1) has a 2 C(1) 2 to 1DAC C (1) The input voltages are (VR[1], VR[3], ... VR

[125] , VR

[127] ); the second circuit unit CKT (2) has a 2 C(2) 2 to 1DAC C(2) The input voltages are (VR[2], VR[6], ... VR

[122] , VR

[126] ); 1 of the third circuit unit CKT (3) is 2 C (3) 2 to 1DAC C(3)The input voltages are (VR[4], VR

[12] , ... VR

[116] , VR

[124] ); 1 of the 4th circuit unit CKT (4) is 2 C(4) 2 to 1DAC C(4) The input voltages are (VR[8], VR

[24] , ... VR

[104] , VR

[120] ); 1 of the 5th circuit unit CKT (5) is 2 C(5) 2 to 1DAC C(5) The input voltages are VR

[16] , VR

[48] , VR

[80] , VR

[112] ; 1 of the 2 circuit units in the 6th circuit C(6) 2 to 1DAC C(6) The input voltage is (VR

[32] , VR

[96] ), and because 129 / (2 6 +2 5 +2 4 +2 3 +2 2 +2 1 )×(3-2)) is 3, so the three input voltages of the X(=3)-to-2 digital-to-analog converter (3-to-2DAC) of the sixth circuit unit CKT(6) are (VR[0], VR

[64] , VR

[128] ), that is, they are each 2 of the aforementioned 129 reference voltages VR[0]-VR

[128] that are not selected as the i-th circuit unit CKT(i) (i=1-5)). C(i) 2 to 1DAC C(i) The input voltage and the 2 C(n) 2 to 1DAC C(n) The residual reference voltage for each input voltage.

[0033] Figure 7 The area-saving digital-to-analog converter of the present invention is a 129-to-2 digital-to-analog converter (129-to-2DAC) (i.e., A=129, B=5) implemented based on a 5-to-2 digital-to-analog converter (5-to-2DAC), which has 129 reference voltages VR[0]-VR

[128] . Since there is a value of 3 such that log2((129-1) / (5-1) 3 )=1, so n=3. As shown in the figure, the 129 to 2DAC includes the 0th circuit unit CKT(0) to the 3rd circuit unit CK(3), and the 1st to 3rd parameters of the 1st circuit unit CKT(1) to the 3rd circuit unit CKT(3) are 5, 3, and 1 respectively (that is, C(1)=5, C(2)=3, C(3)=1). Among them, the 3 2 C(1) 2 to 1DAC C(1)The input voltages are (VR[1], VR[5], … VR

[121] , VR

[125] ), (VR[2], VR[6], … VR

[122] , VR

[126] ), and (VR[3], VR[7], … VR

[123] , VR

[127] ); the three 2 C(2) 2 to 1DAC C(2) The input voltages are (VR[4], VR

[20] , … VR

[100] , VR

[116] ), (VR[8], VR

[24] , … VR

[104] , VR

[120] ), and (VR

[12] , VR

[28] , … VR

[108] , VR

[128] ); the three 2 C(3) 2 to 1DAC C(3) The input voltages are (VR

[16] , VR

[80] ), (VR

[32] , VR

[96] ), (VR

[48] , VR

[112] ), and because 129 / (2 (3) +2 (2) +2 (1) )×(5-2)) is 3, so the three input voltages of the X(=3)-to-2 digital-to-analog converter (3-to-2DAC) of the third circuit unit are (VR[0], VR

[64] , VR

[128] ). That is, they are each 2 of the aforementioned 129 reference voltages VR[0]-VR

[128] that are not selected as the i-th circuit unit CKT(i) (i=1-2)). C(i) 2 to 1DAC C(i) input voltage, and 2 of the third circuit unit CKT(3) C(n) 2 to 1DAC C(n) The residual reference voltage for each input voltage.

[0034] From the above description, it can be seen that the present invention realizes the A to 2 digital-to-analog converter by using the B to 2 digital-to-analog converter. Since most of the input reference voltages used will only be selected by one switch, the number of switches used can be greatly reduced. In contrast, in the existing digital-to-analog converter, the same voltage node will be repeatedly selected by two switches, resulting in the use of redundant switches and increased circuit layout area. In response to this problem, the present invention proposes a circuit design that effectively reduces the number of switches used, which can effectively realize an area-saving digital-to-analog converter.

[0035] The above embodiments are merely examples for the convenience of description. The scope of rights claimed by the present invention should be based on the claims, but not limited to the above embodiments.

Claims

1. A digital-to-analog converter, which is an A-to-2 digital-to-analog converter implemented based on a B-to-2 digital-to-analog converter, wherein A and B are integers greater than 2 and A is greater than B, the digital-to-analog converter comprises 0th to nth circuit units, n is an integer greater than 0, and the 1st to nth circuit units have 1st to nth parameters respectively, characterized in that: The 0th circuit unit is a B to 2 digital to analog converter; There is an i-th circuit unit among the 1st to (n-1)th circuit units, wherein i=1-(n-1), and the i-th circuit unit includes: a B-to-2 digital-to-analog converter having two output voltages as two of the B input voltages of the B-to-2 digital-to-analog conversion circuit of the (i-1)th circuit unit; and (B-2)2 C(i) A B to 1 digital-to-analog converter having a (B-2) output voltage as the remaining (B-2) input voltages of the B to 2 digital-to-analog converter of the (i-1)th circuit unit, wherein C(i) represents the i-th parameter; The nth circuit unit comprises: an X-to-2 digital-to-analog converter having two output voltages as two of the B input voltages of the B-to-2 digital-to-analog converter of the (n-1)th circuit unit, wherein X is an integer between 3 and B; and (B-2)2 C(n) to 1 digital-to-analog converter, having (B-2) output voltages as the remaining (B-2) input voltages of the B to 2 digital-to-analog converter of the (n-1)th circuit unit, wherein C(n) represents the nth parameter.

2. The digital-to-analog converter according to claim 1, wherein: X is A / (2 C(1) +2 C(2) +2 C(3) +…+2 C(n) )×(B-2)), where C(1)~C(n) represent the 1st parameter to the nth parameter respectively.

3. The digital-to-analog converter according to claim 1, wherein: (A-1) / (B-1) is divisible.

4. The digital-to-analog converter according to claim 3, wherein: When there exists a value q such that log2((A-1) / (B-1) q )=1, then n=q, otherwise n is in accordance with log2((A-1) / (B-1) n )=2.

5. The digital-to-analog converter according to claim 4, wherein: The first to nth parameters are log2((A-1) / (B-1) Y ), Y is an integer between 1 and n.

6. The digital-to-analog converter according to claim 1, wherein: Each 2 of the i-th circuit unit C(i) to 1 digital-to-analog converter with 2 C(i) input voltage; each 2 of the nth circuit unit C(n) to 1 digital-to-analog converter with 2 C(n) An input voltage.

7. The digital-to-analog converter according to claim 6, wherein: Each of the 2 C(i) 2 to 1 Digital to Analog Converter C(i) An input voltage, and the 2 C(n) 2 to 1 Digital to Analog Converter C(n) The input voltage is selected from A reference voltages, where the A reference voltages include a 0th reference voltage to an (A-1)th reference voltage.

8. The digital-to-analog converter according to claim 7, wherein: The 0th reference voltage to the (A-1)th reference voltage are increasing or decreasing voltages.

9. The digital-to-analog converter according to claim 7, wherein: The kth 2 C(i) 2 to 1 Digital to Analog Converter C(i) The input voltage is VR[2 C(n-i+1)-1 ×k]、VR[2 C(n-i+1)-1 ×k+(B-1) i ×1]、VR[2 C(n -i+1)-1 ×k+(B-1) i ×2], …VR[2 C(n-i+1)-1 ×k+(B-1) i ×(2 C(i) -1)], where k is an integer between 1 and (B-2), VR[m] represents the mth reference voltage, and m is an integer between 0 and (A-1).

10. The digital-to-analog converter according to claim 7, wherein: The kth 2 of the nth circuit unit C(n) 2 to 1 Digital to Analog Converter C(n) The input voltage is VR[2 C(n-i+1)-1 ×k]、VR[2 C(n-i+1)-1 ×k+(B-1) n ×1]、VR[2 C (n-i+1)-1 ×k+(B-1) n ×2], …VR[2 C(n-i+1)-1 ×k+(B-1) n ×(2 C(n) -1)], where k is an integer between 1 and (B-2), VR[m] represents the mth reference voltage, and m is an integer between 0 and (A-1).

11. The digital-to-analog converter according to claim 7, wherein: The X-to-2 digital-to-analog converter has X input voltages, and the X input voltages are each 2 of the A reference voltages that are not selected as the i-th circuit unit. C(i) 2 to 1 Digital to Analog Converter C(i) input voltage, and 2 of the nth circuit unit C(n) 2 to 1 Digital to Analog Converter C(n) The residual reference voltage for each input voltage.

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