CRC verification method and device, communication equipment and storage medium

Abstract

The invention provides a CRC checking method and device, communication equipment and a storage medium, and relates to the technical field of communication, data to be checked can be divided into multiple pieces of parallel block data, and the data to be checked are interleaved coded data; data rearrangement processing is carried out on column elements in each piece of parallel block data, so that the multiple pieces of parallel block data correspond to the multiple column elements in the same row and are arranged according to the sequence from small to large, and the increasing step length of the multiple column elements is equal to the number of the column elements in each piece of parallel block data; determining a first CRC result of each piece of parallel block data in parallel by utilizing a CRC check unit, wherein the first CRC result is a CRC result obtained after the CRC check unit checks each piece of parallel block data by adopting a preset initial value; and merging the first CRC results of the parallel block data through a time division multiplexing CRC check unit to obtain a CRC result of the to-be-checked data. According to the invention, the CRC check cost and the check complexity can be reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technology, and in particular to a CRC verification method, device, communication equipment and storage medium. Background Art

[0002] Mobile communication is the communication between mobile objects, or between mobile objects and fixed objects. Mobile objects can be people, cars, trains, ships, radios and other objects in a moving state. In the actual existing network environment, due to the presence of various obstacles, the signals received by the terminal are more complicated, and there are multipath fading caused by multipath propagation, shadow fading caused by obstacles blocking or shielding the radio waves, and free space path loss. In this case, the use of interleaving coding can discretize signal errors and improve the fading of mobile communication signals. However, interleaving will cause the order of data transmission to change, which is not convenient for the receiving end to perform cyclic redundancy check (CRC) code verification. Summary of the invention

[0003] The present disclosure provides a CRC check method, apparatus, communication equipment and storage medium, which can solve the technical problems of high check cost and check complexity when performing CRC check on interleaved encoded data.

[0004] A first aspect of the present disclosure provides a CRC verification method, including:

[0005] Dividing the data to be verified into a plurality of parallel block data, wherein the data to be verified is interleaved coded data;

[0006] Rearranging the column elements in each parallel block data so that the column elements in the same row corresponding to the plurality of parallel block data are arranged in ascending order, and the incrementing step length of the plurality of column elements is equal to the number of column elements in the plurality of parallel block data;

[0007] Determine in parallel a first CRC result of each parallel block data by using a CRC check unit, wherein the first CRC result is a CRC result obtained after the CRC check unit checks each parallel block data using a preset initial value;

[0008] The CRC check unit is multiplexed in time division to combine the first CRC results of the parallel block data to obtain the CRC result of the data to be checked.

[0009] A second aspect of the present disclosure provides a CRC check device, including:

[0010] A division module, used for dividing the data to be checked into a plurality of parallel block data, wherein the data to be checked is interleaved coded data;

[0011] A first processing module is used to perform data rearrangement processing on the column elements in each parallel block data, so that the plurality of column elements corresponding to the plurality of parallel block data in the same row are arranged in ascending order, and the increment step length of the plurality of column elements is equal to the number of column elements in the plurality of parallel block data;

[0012] A determination module, configured to determine in parallel a first CRC result of each parallel block data by using a CRC check unit, wherein the first CRC result is a CRC result obtained after the CRC check unit checks each parallel block data using a preset initial value;

[0013] The second processing module is used to combine the first CRC results of the parallel block data by time-division multiplexing the CRC check unit to obtain the CRC result of the data to be checked.

[0014] The third aspect embodiment of the present disclosure provides a communication device, which includes: a transceiver; a memory; a processor, which is connected to the transceiver and the memory respectively, and is configured to control the wireless signal reception and transmission of the transceiver by executing computer-executable instructions on the memory, and can implement the method of the first aspect embodiment of the present disclosure.

[0015] The fourth aspect embodiment of the present disclosure provides a computer storage medium, wherein the computer storage medium stores computer executable instructions; after the computer executable instructions are executed by a processor, the method of the first aspect embodiment of the present disclosure can be implemented.

[0016] The CRC verification method, device, communication equipment and storage medium provided by the embodiments of the present disclosure can divide the data to be verified into multiple parallel block data, and then rearrange the column elements in each parallel block data, so that the multiple parallel block data correspond to multiple column elements in the same row and are arranged in order from small to large, and the incremental step of the multiple column elements is equal to the number of column elements in each parallel block data; then use the CRC verification unit to determine the first CRC result of each parallel block data in parallel, and the first CRC result is the CRC result obtained after the CRC verification unit uses a preset initial value to verify each parallel block data; by time-division multiplexing the CRC verification unit, the first CRC result of each parallel block data is merged to obtain the CRC result of the data to be verified. The technical solution in the present disclosure can reduce the complexity of CRC verification and improve the verification efficiency by rearranging multiple parallel block data and using a CRC verification unit to perform CRC verification on the parallel block data after rearrangement in parallel; in addition, by time-division multiplexing of the CRC verification unit, the number of CRC verification units can be reduced, which can reduce the cost of CRC verification.

[0017] Additional aspects and advantages of the present disclosure will be given in part in the following description and in part will be obvious from the following description or learned through practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present disclosure will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0019] Figure 1 A schematic diagram of a CRC verification method according to an embodiment of the present disclosure;

[0020] Figure 2 It is a schematic diagram of an example of a plurality of parallel block data before interleaving encoding according to an embodiment of the present disclosure;

[0021] Figure 3 It is a schematic diagram of an example of multiple parallel block data after interleaving encoding according to an embodiment of the present disclosure;

[0022] Figure 4 It is a schematic diagram of an example of multiple parallel block data after data rearrangement processing according to an embodiment of the present disclosure;

[0023] Figure 5 A schematic diagram of a CRC verification method according to an embodiment of the present disclosure;

[0024] Figure 6 A schematic diagram of a CRC check principle flow according to an embodiment of the present disclosure;

[0025] Figure 7 is a block diagram of a CRC checking device according to an embodiment of the present disclosure;

[0026] Figure 8 is a structural schematic diagram of a communication device according to an embodiment of the present disclosure;

[0027] Fig. 9 A schematic diagram of the structure of a chip provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] Embodiments of the present disclosure are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present disclosure, and should not be construed as limiting the present disclosure.

[0029] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limitations on the present application. It should be noted that, in the absence of conflict, the embodiments of the present application and the features in the embodiments may be combined with each other.

[0030] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the embodiments of the present application. The singular forms of "a" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0031] It should be understood that, although the terms first, second, third, etc. may be used to describe various information in the embodiments of the present application, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the embodiments of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at..." or "when..." or "in response to determination".

[0032] Related technologies require the use of multiple CRC calculation units to perform collaborative verification on the interleaved encoded data, which results in high verification cost and complexity of the CRC verification.

[0033] To solve the above technical problems, the present embodiment proposes a CRC check method, apparatus, communication device and storage medium, which can reduce the CRC check cost and check complexity for the interleaved coded data.

[0034] The CRC verification method, device, communication equipment and storage medium provided in the present application are described in detail below in conjunction with the accompanying drawings.

[0035] Figure 1 FIG. 2 shows a flow chart of a CRC check method according to an embodiment of the present disclosure. Figure 1 As shown, the embodiment may include the following steps.

[0036] Step 101: Divide the data to be verified into a plurality of parallel block data, where the data to be verified is interleaved coded data.

[0037] In the embodiments of the present disclosure, interleaving coding can be used to disperse signal errors and improve the fading of mobile communication signals. Figure 2 The communication data before interleaving coding shown in FIG. 1 can be obtained after interleaving coding as shown in FIG. Figure 3 For the embodiment of the present disclosure, after obtaining the data to be checked, the data to be checked can be divided into a plurality of parallel block data according to the parallelism and code length of the data to be checked. For example, assuming that the code length K = 40 and the parallelism N = 8, Figure 3 As shown, each column (ie, parallel block data) has a total of S=K / N=5 data (column elements), and each column represents data processed by a parallel block.

[0038] In one embodiment of the present disclosure, the decoding results corresponding to the 8 data in each row in parallel are generated at the same time.

[0039] Step 102: Rearrange the column elements in each parallel block data so that multiple column elements in the same row corresponding to multiple parallel block data are arranged in ascending order, and the increment step of the multiple column elements is equal to the number of column elements in each parallel block data.

[0040] For the embodiments of the present disclosure, the column elements in each parallel block data can be rearranged with reference to the particularity of interleaved coding, so that each data path belongs to a continuous data block, the data in the block are in disorder, and the disorder pattern between the sequence blocks of each path is consistent. Figure 4 As shown, multiple parallel block data correspond to multiple column elements in the same row and are arranged in order from small to large, and the increment step of the multiple column elements is equal to the number of column elements in each parallel block data.

[0041] Among them, when the parallelism N can divide the code length K, the interleaving code has the following characteristics:

[0042] Contention-free and maximally-vectorizable: elements in different columns remain in different columns after interleaving; elements in the same row remain in the same row after interleaving.

[0043] Parity remains unchanged: elements with odd numbers remain odd after interleaving; elements with even numbers remain even after interleaving.

[0044] For example, Figure 4 As shown, after Figure 3 After the column elements in each parallel block data shown are rearranged, 8 parallel block data can be obtained: crc_in7, crc_in6, crc_in5, crc_in4, crc_in3, crc_in2, crc_in1, crc_in0. Compared with Figure 2The communication data before interleaving coding shown in the figure is arranged in a disordered order. The 8 parallel block data correspond to multiple column elements in the same row. Figure 3 The interleaved coded communication data shown is arranged in ascending order and has a certain arrangement pattern. For example, the 8 column elements in the first row corresponding to the 8 parallel block data are arranged in ascending order as follows: 0, 5, 10, 15, 20, 25, 30, 35, and the increment step of the 8 column elements is equal to the number of column elements in each parallel block data, 5.

[0045] Step 103: Use a CRC check unit to determine a first CRC result of each parallel block data in parallel. The first CRC result is a CRC result obtained after the CRC check unit checks each parallel block data using a preset initial value.

[0046] In one embodiment of the present disclosure, since the random CRC is used for calculation, the first CRC result of each parallel block data is its contribution to the final CRC. When the CRC check unit input is 0, it does not contribute to the final CRC result. Therefore, the CRC check unit input can be fixed to 1, and the parallel input of each parallel block data is judged to determine whether to accumulate its contribution to the CRC result. For the embodiment of the present disclosure, after the column elements in each parallel block data are rearranged, a CRC check unit can be used to use a preset initial value to parallel check the first CRC result of each parallel block data.

[0047] Step 104: By using the time-division multiplexing CRC check unit, the first CRC results of each parallel block data are combined and processed to obtain the CRC result of the data to be checked.

[0048] For the embodiments of the present disclosure, the first CRC results of each parallel block data can be merged by time-division multiplexing the CRC check unit. Compared with the existing CRC check method, the number of CRC check units used can be reduced. Only one CRC check unit is used to perform CRC check on the rearranged parallel block data in parallel, which can reduce the cost of CRC check.

[0049] For example, Figure 4As shown, for 8 parallel block data, after the parallel processing of the first CRC results of each parallel block data in step 103 of the embodiment, 8 independent first CRC results corresponding to the 8 parallel block data can be obtained. For the embodiment of the present disclosure, the CRC check unit can be time-division multiplexed according to the division order of the 8 parallel block data from front to back: crc_in7, crc_in6, crc_in5, crc_in4, crc_in3, crc_in2, crc_in1, crc_in0, and the first CRC results of the 8 parallel block data are merged. When merging the first CRC results, since the first CRC results of the 8 parallel block data are the check values ​​of different segmented data, it is necessary to perform CRC matrix compensation on the 8 parallel block data in turn, compensate the corresponding parallel matrix according to its bit position in the parallel block data, and perform bit XOR on the compensated second CRC result and the first CRC result of the next parallel block data until the bit XOR is performed with the first CRC result of the last parallel block data, and the final CRC result corresponding to the data to be checked can be obtained.

[0050] In summary, according to the CRC verification method provided in the embodiment of the present disclosure, by rearranging multiple parallel block data and using a CRC verification unit to perform CRC verification on the rearranged parallel block data in parallel, the complexity of CRC verification can be reduced and the verification efficiency can be improved; in addition, by time-division multiplexing of the CRC verification unit, the number of CRC verification units can be reduced, which can reduce the cost of CRC verification.

[0051] Figure 5 FIG. 2 shows a flow chart of a CRC check method according to an embodiment of the present disclosure. Figure 5 As shown, the embodiment may include the following steps.

[0052] Step 201: Divide the data to be verified into a plurality of parallel block data, where the data to be verified is interleaved coded data.

[0053] For the embodiments of the present disclosure, after the data to be verified is obtained, the data to be verified can be divided into multiple parallel block data according to the parallelism and code length of the data to be verified. Accordingly, the steps of the embodiment may include: determining the code length and parallelism of the data to be verified; dividing the data to be verified into multiple parallel block data based on the code length and parallelism, wherein each parallel block data in the multiple parallel block data corresponds to the same number of column elements, and the number of column elements in each parallel block data is the ratio of the code length to the parallelism. Exemplarily, assuming that the code length K = 40 and the parallelism N = 8, as Figure 3 As shown, each column (ie, parallel block data) has a total of S=K / N=5 data (column elements), and each column represents data processed by a parallel block.

[0054] Step 202: Rearrange the column elements in each parallel block data so that multiple column elements in the same row corresponding to multiple parallel block data are arranged in ascending order, and the increment step of the multiple column elements is equal to the number of column elements in each parallel block data.

[0055] For the embodiment of the present disclosure, the specific implementation process can refer to the relevant description in step 102 of the embodiment, which will not be repeated here.

[0056] Step 203: configure a preset initial value for the CRC check unit, where the preset initial value is that the input bit is 1 and the input data is the first parallel block data in the continuous data block.

[0057] In the disclosed embodiment, since the random CRC is used for calculation, the first CRC result of each parallel block data is its contribution to the final CRC. When the CRC check unit input is 0, it does not contribute to the final CRC result. Therefore, the CRC check unit input bit can be fixed to 1, and the parallel input of each parallel block data is judged to determine whether to accumulate its contribution to the CRC result. Figure 4 As shown, since different 8 parallel block data correspond to multiple column elements in the same row and correspond to the same incremental step, the first parallel block data among the 8 parallel block data can reflect the disordered mode of other parallel block data.

[0058] For the disclosed embodiment, in order to reduce the number of CRC check units configured and reduce the CRC check cost, a CRC check unit can be uniformly configured for multiple parallel block data based on the common disorder characteristics of multiple parallel block data, and a preset initial value is configured for the CRC check unit: the input bit is 1, the input data is the first parallel block data in the continuous data block, and the multiple parallel block data are checked simultaneously using the CRC check unit configured with the preset initial value, so as to obtain the first CRC result of each parallel block data. Under the same preset initial value, multiple parallel block data are checked in parallel, which can improve the check efficiency.

[0059] Step 204: Perform parallel verification on each parallel block data using a CRC verification unit configured with a preset initial value to obtain a first CRC result for each parallel block data.

[0060] For the embodiment of the present disclosure, a corresponding check circuit can be configured for each parallel block data, such as Figure 6 As shown, the check circuit may include a multiplexer (MUX), an exclusive OR gate (XOR) and a trigger (D), and the input end of the multiplexer is connected to the output end of the CRC check unit (serial random CRC768). In addition to the output value of the CRC check unit, the multiplexer also inputs the column elements corresponding to different bit positions of the parallel block data. Figure 6As shown, each parallel block data contains 768 column elements. Taking the first parallel block data among the multiple parallel block data as an example, the multiplexer corresponding to the first parallel block data, in addition to the output value of the CRC check unit under the preset initial value, will also input the column elements of the parallel block data at different bit positions: b0-b767. The multiplexer will input the output value and each column element in each parallel data block into the XOR gate in the order of bit position from small to large, and perform bit XOR superposition operation until the bit XOR superposition operation of the last column element is completed, and the trigger outputs the first CRC result crc_out0 corresponding to the parallel block data. Accordingly, the embodiment steps may include: determining the output value of the CRC check unit under the preset initial value; performing bit XOR superposition operation on the output value and each column element in each parallel data block, and obtaining the first CRC result of each parallel block data.

[0061] Step 205: By time-division multiplexing the CRC check unit, the first CRC results of each parallel block data are combined and processed to obtain the CRC result of the data to be checked.

[0062] For the embodiments of the present disclosure, Figure 6 As shown, for 8 parallel block data, after the parallel processing of the first CRC results of each parallel block data in step 204 of the embodiment, 8 independent first CRC results corresponding to the 8 parallel block data can be obtained. Figure 6 In Stage 2, the CRC check unit can be time-division multiplexed in the order of the 8 parallel block data from front to back, and the first CRC results of the 8 parallel block data: crc_out0, crc_out1, crc_out2, crc_out3, crc_out4, crc_out5, crc_out6, crc_out7 are merged. When merging the first CRC result, since the first CRC results of the 8 parallel block data are the check values ​​of different segmented data, the 8 parallel block data need to be compensated by the CRC matrix in sequence, and the corresponding parallel matrix is ​​compensated according to its bit position in the parallel block data, and the compensated second CRC result is bit-exclusive-ORed with the first CRC result of the next parallel block data, until it is bit-exclusive-ORed with the first CRC result of the last parallel block data, and the final CRC result corresponding to the data to be checked can be obtained.

[0063] The steps of the embodiment may include: repeatedly executing the following process until it is determined that the next parallel block data is the last parallel block data among the multiple parallel block data, and determining the initial value of the first CRC result of the next parallel block data as the CRC result of the data to be checked: determining each parallel block data as the current parallel block data in turn according to the data block order of the multiple parallel block data from front to back, and time-division multiplexing the CRC check unit, performing CRC matrix compensation on the initial value of the first CRC result of the current parallel block data, and obtaining the second CRC result of the current parallel block data, wherein the first parallel block data among the multiple parallel block data directly determines the corresponding first CRC result as the initial value of the first CRC result; performing bitwise XOR on the second CRC result of the current parallel block data and the first CRC result of the next parallel block data, and obtaining the initial value of the first CRC result of the next parallel block data.

[0064] For example, Figure 6 As shown, for 8 parallel block data, when the first CRC results of each parallel block data are combined and processed to obtain the CRC result of the data to be checked, the first parallel block data can be first determined as the current parallel block data, the CRC check unit is reused, and the first CRC result corresponding to the first parallel block data is directly used as the initial value a of the first CRC result for CRC matrix compensation to obtain the second CRC result A of the first parallel block data; then the second CRC result A can be bit-exclusive-ORed with the first CRC result corresponding to the second parallel block data to obtain the initial value b of the first CRC result of the second parallel block data, the second parallel block data is determined as the current parallel block data, the CRC check unit is reused, and the initial value b of the first CRC result of the second parallel block data is compensated by CRC matrix to obtain the second parallel block data. The second CRC result B of the block data; then the second CRC result B can be bit-XORed with the first CRC result corresponding to the third parallel block data to obtain the initial value C of the first CRC result of the third parallel block data, the third parallel block data is determined as the current parallel block data, the CRC check unit is reused, and the initial value c of the first CRC result of the third parallel block data is compensated by CRC matrix to obtain the second CRC result C of the third parallel block data; ...; repeat the above process until it is determined that the current parallel block data is the second to last parallel block data among the 8 parallel block data, that is, the next parallel block data corresponding to the current parallel block data is the last parallel block data among the multiple parallel block data, at this time, the initial value h of the first CRC result of the last parallel block data can be determined as the final CRC result of the data to be checked.

[0065] In an embodiment of the present disclosure, when a time-division multiplexing CRC check unit performs CRC matrix compensation on an initial value of a first CRC result of current parallel block data to obtain a second CRC result of the current parallel block data, the embodiment steps may include: determining a parallel matrix corresponding to the current parallel block data; and using the time-division multiplexing CRC check unit to perform compensation processing on an initial value of a first CRC result of the current parallel block data using a parallel matrix to obtain a second CRC result of the current parallel block data.

[0066] Correspondingly, when using a parallel matrix to perform compensation processing on the initial value of the first CRC result of the current parallel block data to obtain the second CRC result of the current parallel block data, the implementation steps may include: inputting the initial value of the first CRC result of the current parallel block data into the corresponding parallel matrix to calculate the influence value of the current parallel block data; performing bitwise XOR on the influence value of the current parallel block data and the initial value of the first CRC result of the current parallel block data to obtain the second CRC result of the current parallel block data.

[0067] In summary, according to the CRC verification method provided in the embodiment of the present disclosure, by rearranging multiple parallel block data and using a CRC verification unit to perform CRC verification on the rearranged parallel block data in parallel, the complexity of CRC verification can be reduced and the verification efficiency can be improved; in addition, by time-division multiplexing of the CRC verification unit, the number of CRC verification units can be reduced, which can reduce the cost of CRC verification.

[0068] Corresponding to the CRC verification methods provided in the above-mentioned embodiments, the present disclosure also provides a CRC verification device. Since the CRC verification device provided in the embodiment of the present disclosure corresponds to the CRC verification methods provided in the above-mentioned embodiments, the implementation method of the CRC verification method is also applicable to the CRC verification device provided in this embodiment and will not be described in detail in this embodiment.

[0069] Figure 7 A schematic diagram of the structure of a CRC check device 300 provided in an embodiment of the present disclosure.

[0070] like Figure 7 , the device 300 comprises:

[0071] A division module 310, which can be used to divide the data to be checked into a plurality of parallel block data, where the data to be checked is interleaved coded data;

[0072] The first processing module 320 may be used to perform data rearrangement processing on the column elements in each parallel block data, so that the multiple column elements corresponding to the multiple parallel block data in the same row are arranged in ascending order, and the increment step length of the multiple column elements is equal to the number of column elements in each parallel block data;

[0073] A determination module 330, which may be used to determine a first CRC result of each parallel block data in parallel by using a CRC check unit, wherein the first CRC result is a CRC result obtained after the CRC check unit checks each parallel block data by using a preset initial value;

[0074] The second processing module 340 may be used to combine the first CRC results of each parallel block data through time-division multiplexing of the CRC check unit to obtain the CRC result of the data to be checked.

[0075] In some embodiments of the present disclosure, the division module 310 can be used to determine the code length and parallelism of the data to be verified; based on the code length and parallelism, the data to be verified is divided into multiple parallel block data, wherein each parallel block data in the multiple parallel block data corresponds to the same number of column elements, and the number of column elements in each parallel block data is the ratio of the code length to the parallelism.

[0076] In some embodiments of the present disclosure, the determination module 330 can be used to configure a preset initial value for the CRC check unit, where the preset initial value is that the input bit is 1, and the input data is the first parallel block data in the continuous data block; and each parallel block data is checked in parallel using the CRC check unit configured with the preset initial value to obtain the first CRC result of each parallel block data.

[0077] In some embodiments of the present disclosure, the determination module 330 can be used to determine the output value of the CRC check unit under a preset initial value; the output value is subjected to a bitwise XOR superposition operation with each column element in each parallel data block to obtain a first CRC result of each parallel block data.

[0078] In some embodiments of the present disclosure, the second processing module 340 can be used to repeatedly execute the following process until it is determined that the next parallel block data is the last parallel block data among the multiple parallel block data, and the initial value of the first CRC result of the next parallel block data is determined as the CRC result of the data to be checked: according to the data block order of the multiple parallel block data from front to back, each parallel block data is determined as the current parallel block data in turn, and the CRC check unit is time-division multiplexed to perform CRC matrix compensation on the initial value of the first CRC result of the current parallel block data to obtain the second CRC result of the current parallel block data, wherein the first parallel block data among the multiple parallel block data directly determines the corresponding first CRC result as the initial value of the first CRC result; the second CRC result of the current parallel block data is bit-XORed with the first CRC result of the next parallel block data to obtain the initial value of the first CRC result of the next parallel block data.

[0079] In some embodiments of the present disclosure, the second processing module 340 can be used to determine the parallel matrix corresponding to the current parallel block data; the time-division multiplexing CRC check unit uses the parallel matrix to compensate the initial value of the first CRC result of the current parallel block data to obtain the second CRC result of the current parallel block data.

[0080] In some embodiments of the present disclosure, the second processing module 340 can be used to input the initial value of the first CRC result of the current parallel block data into the corresponding parallel matrix to calculate the influence value of the current parallel block data; and perform bitwise XOR on the influence value of the current parallel block data and the initial value of the first CRC result of the current parallel block data to obtain the second CRC result of the current parallel block data.

[0081] See also Figure 8 , Figure 8 1 is a schematic diagram of the structure of a communication device 1400 provided in an embodiment of the present application. The communication device 1400 may be a network device, or a user device, or a chip, a chip system, or a processor that supports the network device to implement the above method, or a chip, a chip system, or a processor that supports the user device to implement the above method. The device may be used to implement the method described in the above method embodiment, and the details may refer to the description in the above method embodiment.

[0082] The communication device 1400 may include one or more processors 1401. The processor 1401 may be a general-purpose processor or a dedicated processor, etc. For example, it may be a baseband processor or a central processing unit. The baseband processor may be used to process the communication protocol and communication data, and the central processing unit may be used to control the communication device (such as a base station, a baseband chip, a terminal device, a terminal device chip, a DU or a CU, etc.), execute a computer program, and process the data of the computer program.

[0083] Optionally, the communication device 1400 may further include one or more memories 1402, on which a computer program 1404 may be stored, and the processor 1401 executes the computer program 1404 so that the communication device 1400 performs the method described in the above method embodiment. Optionally, data may also be stored in the memory 1402. The communication device 1400 and the memory 1402 may be provided separately or integrated together.

[0084] Optionally, the communication device 1400 may further include a transceiver 1405 and an antenna 1406. The transceiver 1405 may be referred to as a transceiver unit, a transceiver, or a transceiver circuit, etc., for implementing a transceiver function. The transceiver 1405 may include a receiver and a transmitter, the receiver may be referred to as a receiver or a receiving circuit, etc., for implementing a receiving function; the transmitter may be referred to as a transmitter or a transmitting circuit, etc., for implementing a transmitting function.

[0085] Optionally, the communication device 1400 may further include one or more interface circuits 1407. The interface circuit 1407 is used to receive code instructions and transmit them to the processor 1401. The processor 1401 executes the code instructions to enable the communication device 1400 to execute the method described in the above method embodiment.

[0086] In one implementation, the processor 1401 may include a transceiver for implementing receiving and sending functions. For example, the transceiver may be a transceiver circuit, an interface, or an interface circuit. The transceiver circuit, interface, or interface circuit for implementing the receiving and sending functions may be separate or integrated. The above-mentioned transceiver circuit, interface, or interface circuit may be used for reading and writing code / data, or the above-mentioned transceiver circuit, interface, or interface circuit may be used for transmitting or delivering signals.

[0087] In one implementation, the processor 1401 may store a computer program 1403, which runs on the processor 1401 and enables the communication device 1400 to perform the method described in the above method embodiment. The computer program 1403 may be fixed in the processor 1401, in which case the processor 1401 may be implemented by hardware.

[0088] In one implementation, the communication device 1400 may include a circuit that can implement the functions of sending or receiving or communicating in the aforementioned method embodiment. The processor and transceiver described in the present application can be implemented in an integrated circuit (IC), an analog IC, a radio frequency integrated circuit RFIC, a mixed signal IC, an application specific integrated circuit (ASIC), a printed circuit board (PCB), an electronic device, etc. The processor and transceiver can also be manufactured using various IC process technologies, such as complementary metal oxide semiconductor (CMOS), N-type metal oxide semiconductor (nMetal-oxide-semiconductor, NMOS), P-type metal oxide semiconductor (positive channelmetal oxide semiconductor, PMOS), bipolar junction transistor (bipolar junction transistor, BJT), bipolar CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), etc.

[0089] The communication device described in the above embodiments may be a network device or a user device, but the scope of the communication device described in the present application is not limited thereto, and the structure of the communication device may not be limited thereto. Figure 8 The communication device may be an independent device or may be part of a larger device. For example, the communication device may be:

[0090] (1) Independent integrated circuit IC, or chip, or chip system or subsystem;

[0091] (2) having a set of one or more ICs, and optionally, the IC set may also include a storage component for storing data and computer programs;

[0092] (3) ASIC, such as modem;

[0093] (4) Modules that can be embedded in other devices;

[0094] (5) Receivers, terminal devices, intelligent terminal devices, cellular phones, wireless devices, handheld devices, mobile units, vehicle-mounted devices, network devices, cloud devices, artificial intelligence devices, etc.;

[0095] (6)Others

[0096] For the case where the communication device may be a chip or a chip system, see Fig. 9 Schematic diagram of the chip structure shown. Fig. 9 The chip shown includes a processor 1501 and an interface 1502. The number of the processor 1501 can be one or more, and the number of the interface 1502 can be multiple.

[0097] Optionally, the chip further includes a memory 1503, and the memory 1503 is used to store necessary computer programs and data.

[0098] Those skilled in the art may also understand that the various illustrative logical blocks and steps listed in the embodiments of the present application may be implemented by electronic hardware, computer software, or a combination of the two. Whether such functions are implemented by hardware or software depends on the specific application and the design requirements of the entire system. Those skilled in the art may use various methods to implement the functions for each specific application, but such implementation should not be understood as exceeding the scope of protection of the embodiments of the present application.

[0099] The present application also provides a readable storage medium having instructions stored thereon, which implement the functions of any of the above method embodiments when executed by a computer.

[0100] The present application also provides a computer program product, which implements the functions of any of the above method embodiments when executed by a computer.

[0101] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs. When the computer program is loaded and executed on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer program can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer program can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server, data center, etc. that contains one or more available media integrated. Available media may be magnetic media (eg, floppy disks, hard disks, tapes), optical media (eg, high-density digital video discs (DVD)), or semiconductor media (eg, solid state disks (SSD)).

[0102] The embodiments or examples of the present disclosure are not exhaustive, but are only illustrative of some embodiments or examples, and are not intended to be specific limitations on the scope of protection of the present disclosure. In the absence of contradiction, each step in a certain embodiment or example can be implemented as an independent example, and the steps can be combined arbitrarily. For example, the scheme after removing some steps in a certain embodiment or example can also be implemented as an independent example, and the order of the steps in a certain embodiment or example can be arbitrarily exchanged. In addition, the optional methods or optional examples in a certain embodiment or example can be combined arbitrarily; in addition, the various embodiments or examples can be combined arbitrarily, for example, some or all steps of different embodiments or examples can be combined arbitrarily, and a certain embodiment or example can be combined arbitrarily with the optional methods or optional examples of other embodiments or examples.

[0103] In some implementation schemes or examples, "in response to ...", "in the case of ...", "at the time of ...", "when ...", "if ...", "if ...", etc. in the present disclosure may be replaced with each other.

[0104] In some embodiments or examples, the description methods of the present disclosure, such as "A or B", "A and / or B", "at least one of A and B", "A in one case, B in another case", "in response to one case A, in response to another case B", etc., may include at least one of the following technical solutions according to the situation: executing A independently of B, that is, A in some embodiments or examples; executing B independently of A, that is, B in some embodiments or examples; selectively executing A and B, that is, selecting to execute from A and B in some embodiments or examples; executing both A and B, that is, A and B in some embodiments or examples.

[0105] In some embodiments or examples, “including A”, “comprising A”, “used to indicate A” and “carrying A” in the present disclosure may be interpreted as directly carrying A or indirectly indicating A.

[0106] In addition, each element, each row, or each column in the table involved in the present disclosure can be implemented as an independent embodiment, and the combination of any elements, any rows, and any columns can also be implemented as an independent embodiment.

[0107] A person skilled in the art may understand that the various numerical numbers such as first and second involved in the present application are only used for the convenience of description and are not used to limit the scope of the embodiments of the present application, and also indicate the order of precedence.

[0108] At least one in the present application can also be described as one or more, and a plurality can be two, three, four or more, which is not limited in the present application. In the embodiments of the present application, for a technical feature, the technical features in the technical feature are distinguished by "first", "second", "third", "A", "B", "C" and "D", etc., and there is no order of precedence or size between the technical features described by the "first", "second", "third", "A", "B", "C" and "D".

[0109] As used herein, the terms "machine-readable medium" and "computer-readable medium" refer to any computer program product, apparatus, and / or device (e.g., disk, optical disk, memory, programmable logic device (PLD)) for providing machine instructions and / or data to a programmable processor, including a machine-readable medium that receives machine instructions as a machine-readable signal. The term "machine-readable signal" refers to any signal for providing machine instructions and / or data to a programmable processor.

[0110] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0111] A computer system may include clients and servers. Clients and servers are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship to each other.

[0112] In some embodiments, devices, etc. can be interpreted as physical or virtual, and their names are not limited to the names recorded in the embodiments. Terms such as "device", "equipment", "device", "circuit", "network element", "node", "function", "unit", "section", "system", "network", "chip", "chip system", "entity", and "subject" can be used interchangeably.

[0113] In some embodiments, the terms "terminal", "terminal device", "user equipment (UE)", "user terminal" "mobile station (MS)", "mobile terminal (MT)", subscriber station, mobile unit, subscriber unit, wireless unit, remote unit, mobile device, wireless device, wireless communication device, remote device, mobile subscriber station, access terminal, mobile terminal, wireless terminal, remote terminal, handset, user agent, mobile client, client and the like can be used interchangeably.

[0114] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0115] In addition, it should be understood that the various embodiments of the present application may be implemented individually or in combination with other embodiments when the solution permits.

[0116] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0117] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0118] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A CRC verification method, characterized in that: include: Dividing the data to be verified into a plurality of parallel block data, wherein the data to be verified is interleaved coded data; Rearranging the column elements in each parallel block data so that the column elements in the same row corresponding to the plurality of parallel block data are arranged in ascending order, and the incrementing step length of the plurality of column elements is equal to the number of column elements in the plurality of parallel block data; Determine in parallel a first CRC result of each parallel block data by using a CRC check unit, wherein the first CRC result is a CRC result obtained after the CRC check unit checks each parallel block data using a preset initial value; The CRC check unit is multiplexed in time division to combine the first CRC results of the parallel block data to obtain the CRC result of the data to be checked.

2. The method according to claim 1, characterized in that The step of dividing the data to be verified into a plurality of parallel blocks of data includes: Determine the code length and parallelism of the data to be verified; The data to be checked is divided into a plurality of parallel block data based on the code length and the degree of parallelism, wherein each parallel block data in the plurality of parallel block data corresponds to the same number of column elements, and the number of column elements in each parallel block data is a ratio of the code length to the degree of parallelism.

3. The method according to claim 1, characterized in that The method of using the CRC check unit to determine the first CRC result of each parallel block data in parallel includes: A preset initial value is configured for the CRC check unit, wherein the preset initial value is that the input bit is 1, and the input data is the first parallel block data in the continuous data block; The parallel block data are checked in parallel by using a CRC check unit configured with the preset initial value to obtain a first CRC result of the parallel block data.

4. The method according to claim 3, characterized in that The method of performing parallel verification on each parallel block data by using the CRC verification unit configured with the preset initial value to obtain a first CRC result of each parallel block data includes: Determine the output value of the CRC check unit under the preset initial value; The output value is respectively subjected to a bitwise exclusive-OR superposition operation with each column element in each parallel data block to obtain a first CRC result of each parallel block data.

5. The method according to claim 1, characterized in that The CRC checking unit is multiplexed by time division to combine the first CRC results of each parallel block data to obtain the CRC result of the data to be checked, including: Repeat the following process until it is determined that the next parallel block data is the last parallel block data among the multiple parallel block data, and the initial value of the first CRC result of the next parallel block data is determined as the CRC result of the data to be checked: According to the data block order of the plurality of parallel block data from front to back, each parallel block data is sequentially determined as the current parallel block data, and the CRC check unit is time-division multiplexed to perform CRC matrix compensation on the initial value of the first CRC result of the current parallel block data to obtain the second CRC result of the current parallel block data, wherein the first parallel block data among the plurality of parallel block data directly determines the corresponding first CRC result as the initial value of the first CRC result; The second CRC result of the current parallel block data is bit-exclusive ORed with the first CRC result of the next parallel block data to obtain an initial value of the first CRC result of the next parallel block data.

6. The method according to claim 5, characterized in that The time-division multiplexing CRC check unit performs CRC matrix compensation on the initial value of the first CRC result of the current parallel block data to obtain a second CRC result of the current parallel block data, including: Determine the parallel matrix corresponding to the current parallel block data; The CRC check unit is time-division multiplexed, and the parallel matrix is ​​used to perform compensation processing on the initial value of the first CRC result of the current parallel block data to obtain the second CRC result of the current parallel block data.

7. The method according to claim 6, characterized in that The method of using the parallel matrix to perform compensation processing on an initial value of a first CRC result of the current parallel block data to obtain a second CRC result of the current parallel block data includes: Inputting the initial value of the first CRC result of the current parallel block data into the corresponding parallel matrix, and calculating the influence value of the current parallel block data; Perform bitwise exclusive OR of the impact value of the current parallel block data and the initial value of the first CRC result of the current parallel block data to obtain a second CRC result of the current parallel block data.

8. A CRC check device, characterized in that: include: A division module, used for dividing the data to be checked into a plurality of parallel block data, wherein the data to be checked is interleaved coded data; A first processing module is used to perform data rearrangement processing on the column elements in each parallel block data, so that the plurality of column elements corresponding to the plurality of parallel block data in the same row are arranged in ascending order, and the increment step length of the plurality of column elements is equal to the number of column elements in the plurality of parallel block data; A determination module, configured to determine in parallel a first CRC result of each parallel block data by using a CRC check unit, wherein the first CRC result is a CRC result obtained after the CRC check unit checks each parallel block data using a preset initial value; The second processing module is used to combine the first CRC results of the parallel block data by time-division multiplexing the CRC check unit to obtain the CRC result of the data to be checked.

9. A communication device, wherein: include: Transceiver; Memory; A processor is connected to the transceiver and the memory, respectively, and is configured to control the wireless signal reception and transmission of the transceiver by executing computer executable instructions on the memory, and can implement any one of the methods of claims 1-7.

10. A computer storage medium, wherein: The computer storage medium stores computer executable instructions; after the computer executable instructions are executed by the processor, the method described in any one of claims 1 to 7 can be implemented.

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