Optical fiber communication system and method based on FPGA technology

Abstract

The invention provides an optical fiber communication system and method based on an FPGA technology. The optical fiber communication system comprises an energy storage converter PCS, a digital energy adapter, a digital energy switch and a digital energy concentrator. One end of the PCS is connected with a power grid, and the other end of the PCS is connected with the digital energy network card through the digital energy adapter. The digital energy adapter is in optical fiber communication connection with the digital energy switch, and the digital energy switch is in communication connection with the digital energy network card through the digital energy concentrator; fPGA chips are arranged in the digital energy adapter and the digital energy switch; according to the optical fiber communication system and method based on the FPGA technology, the structure of a DESS system can be optimized, the data transmission efficiency of the DESS system is improved, the data transmission accuracy of the system is improved, the operation safety of the DESS system is enhanced, the influence of electromagnetic interference in the environment where the system is located on data transmission of the system is reduced, and the reliability of the system is improved; and the system operation cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of encoding, decoding or code conversion in energy storage systems, and in particular to an optical fiber communication system and method based on FPGA technology. Background Art

[0002] At present, the digital energy exchange system DESS, as the core device for realizing energy digitization and efficient management, is increasingly widely used in the energy field. However, the existing DESS system has significant deficiencies in communication.

[0003] Specifically, the RS485 half-duplex communication method is usually used between the digital energy switch and the digital energy adapter in the DESS system. This communication method has many limitations, such as low data transmission rate, which makes it difficult to cope with the growing demand for large-scale data transmission. It also performs poorly in terms of real-time performance. Due to the half-duplex characteristics and limited communication rate, there is a significant delay in data update and transmission, which cannot meet the energy management system's requirements for rapid response and precise control of energy storage modules.

[0004] 2) In the actual application environment of DESS battery dynamic reconstruction, electromagnetic interference is particularly serious, and the electrical signal of RS485 communication is easily interfered, resulting in data transmission errors, which in turn affects the normal operation and decision-making of the system. This not only reduces the performance and efficiency of the DESS system, but also increases the maintenance cost and operation risk of the system, limiting its application and development in more key areas.

[0005] In particular, a. Communication base stations and data centers need to ensure uninterrupted and stable power supply, and have extremely high requirements for the reliability of the power supply system and the real-time performance of data transmission. The existing DESS system communication method cannot meet the needs of these key facilities for high-speed, stable and anti-interference communication.

[0006] b. In power plants and centralized / distributed renewable energy power generation sites, efficient energy management and deployment are required to achieve maximum utilization and stable supply of energy. The shortcomings of the original communication methods in data transmission rate and real-time performance limit the optimal scheduling of energy.

[0007] c. Energy storage systems such as buildings, communities, and homes require smarter, more convenient, and more reliable energy management to reduce energy costs and improve efficiency. Current communication methods cannot provide timely and accurate energy data, which affects user experience and the optimal operation of the system.

[0008] d. Wind-solar-storage-charging microgrids and DC distribution network systems need to achieve the coordination and optimal configuration of multiple energy sources, and have strict requirements on the real-time, stability and anti-interference capabilities of communications. Existing communication methods are difficult to meet the needs of these complex systems.

[0009] e. The battery network experimental platform requires accurate and high-speed data transmission to support scientific research and experimental work. Traditional communication methods have shortcomings in data accuracy and transmission speed, which affects experimental results and research progress.

[0010] In addition, in the prior art, energy storage management and control is performed through digital energy switches and digital energy adapters. However, since the existing digital energy switches and digital energy adapters only rely on the CPU to directly process communications, this results in a large amount of CPU resources being occupied, greatly limiting its ability to handle other key system tasks, thereby affecting the overall operating efficiency of the system. Therefore, it is of great significance to study how to improve the data transmission rate and accuracy of data transmission in the DESS communication system while reducing the impact of electromagnetic interference on the system and improving the system operating efficiency.

[0011] In patent CN115001139A, a control system of a cascade energy storage system is mentioned. The control system is used for controlling an energy storage system of a cascade topology structure. Each cascade energy storage subsystem of the energy storage system of the cascade topology structure is configured with a battery cluster unit and a PCS unit. Each battery cluster unit includes a plurality of battery PACK devices. A plurality of cascade energy storage subsystems are cascaded to form a cascade energy storage system. The control system includes a plurality of sub-control systems. The plurality of sub-control systems are hierarchically controlled. Each level of sub-control system independently controls the equipment of the same level and is connected to the upper and lower level control systems through communication. The expanded sub-control system does not affect the configuration of the original control system and does not affect the operating stability of the original control system. If a certain level of sub-control system fails, it can automatically bypass and exit without affecting the operation of other sub-control systems. Until the bypassed sub-control system reaches a preset threshold, the entire energy storage system exits operation, and can realize the failure exit of different sub-control systems, but does not improve the data transmission rate and transmission accuracy in the system. In addition, the system adopts a rigid connection method, which makes the scheduling flexibility of energy in the system poor, and cannot effectively solve the problem of differences between batteries in the sub-systems. Summary of the invention

[0012] In view of this, the present invention aims to propose an optical fiber communication system and method based on FPGA technology to solve the problems existing in the prior art, such as low data transmission rate and poor transmission accuracy in the DESS system; serious electromagnetic interference in the application environment of dynamic reconstruction of DESS batteries; and excessive CPU burden and low system operation efficiency in the existing energy storage system; thereby optimizing the structure of the DESS system, improving the data transmission efficiency of the DESS system, improving the data transmission accuracy of the system, enhancing the operational safety of the DESS system, reducing the impact of electromagnetic interference in the environment where the system is located on the system data transmission, improving the reliability of the system, and reducing the cost of system operation. Reduce the burden on the CPU in the system and greatly improve the operating efficiency of the system.

[0013] To achieve the above object, the technical solution of the present invention is achieved as follows:

[0014] The present invention relates to an optical fiber communication system and method based on FPGA technology. The optical fiber communication system based on FPGA technology comprises an energy storage converter PCS, a digital energy adapter, a digital energy switch and a digital energy hub; one end of the energy storage converter PCS is connected to a power grid, and the other end is connected to a digital energy network card through a digital energy adapter; the digital energy network card is connected to energy components in a one-to-one correspondence, the digital energy adapter is connected to the digital energy switch through optical fiber communication, and the digital energy switch is connected to the digital energy network card through a digital energy hub; the digital energy network card is electrically connected to the digital energy adapter, and an FPGA chip is arranged in the digital energy adapter and the digital energy switch, so as to realize rapid response processing of data and accurately control access or isolation of energy components under the action of the FPGA chip.

[0015] Furthermore, the FPGA chip includes a sending processing logic module and a receiving processing logic module; the sending processing logic module is connected to the optical fiber sending device, and the receiving processing logic module is connected to the optical fiber receiving device.

[0016] Furthermore, the FPGA chip also includes a switch FPGA and an adapter FPGA; the switch FPGA is set in the digital energy switch, the adapter FPGA is set in the digital energy adapter, the optical fiber transmitting device of the switch FPGA is connected to the optical fiber receiving device of the adapter FPGA through optical fiber communication, and the optical fiber receiving device of the switch FPGA is connected to the optical fiber transmitting device of the adapter FPGA through optical fiber communication.

[0017] Furthermore, the FPGA chip is connected to components in the digital energy switch or digital energy adapter via a data address bus.

[0018] Furthermore, the digital energy switch includes a switch CPU, and the switch FPGA is connected to the switch CPU via a data address bus; the digital energy adapter includes an adapter CPU, and the adapter FPGA is connected to the adapter CPU via a data address bus.

[0019] Furthermore, the FPGA chip also includes a data buffer area, which is respectively connected to the sending processing logic module and the receiving processing logic module, and the data buffer area is connected to the switch CPU or the adapter CPU through a data address bus.

[0020] Furthermore, the sending processing logic module includes a sending framing processing module, an encoding module, and a parallel-to-serial conversion module; the sending framing processing module is connected to the data buffer area, and the sending framing processing module is connected to the optical fiber sending device through the encoding module and the parallel-to-serial conversion module in turn.

[0021] Furthermore, the receiving processing logic module includes a receiving analysis processing module, a decoding module, and a serial-to-parallel conversion module; one end of the optical fiber receiving device is connected to the optical fiber, and the other end of the optical fiber receiving device is connected to the data buffer area through the serial-to-parallel conversion module, the decoding module, and the receiving analysis processing module in sequence.

[0022] Furthermore, both the encoding module and the decoding module adopt 8B / 10B data encoding method.

[0023] A method for optical fiber communication based on FPGA technology, the method is applied to an optical fiber communication system based on FPGA technology, characterized in that the method comprises the following steps:

[0024] Step 1: Build a communication hardware platform: Set the FPGA chip in the digital energy switch and the digital energy adapter respectively;

[0025] Step 2: Software setup: Develop a communication control program based on FPGA chip;

[0026] Step 3: Protocol setting: Use the DESS system-based proprietary communication protocol and set the data frame format corresponding to the protocol;

[0027] Step 4: Run the system to send and receive data.

[0028] Compared with the prior art, the optical fiber communication system and method based on FPGA technology described in the present invention has the following beneficial effects:

[0029] Through the setting of the system, the structure of the DESS system can be optimized, the data transmission efficiency of the DESS system can be improved, the data transmission accuracy of the system can be improved, the operational safety of the DESS system can be enhanced, the impact of electromagnetic interference in the environment where the system is located on the system data transmission can be reduced, the reliability of the system can be improved, and the cost of system operation can be reduced. Through the setting of the method, it is beneficial to improve the data transmission rate between the components in the system and avoid the occurrence of delays in the transmission process. Improve the anti-interference ability of the system and enhance the reliability of the system. In addition, in the present application, the optical fiber communication based on FPGA technology is successfully applied to the DESS system. Through the overall system integration of data transmission between the digital energy switch and the digital energy adapter, the CPU burden can be greatly reduced and the system efficiency can be improved. In addition, the system of the present application introduces FPGA to specifically handle communication. Through the setting of the data buffer area in the FPGA, the burden of the CPU can be greatly liberated, so that the CPU does not need to spend a lot of time and energy to process complex communication protocols. So that the CPU can focus more computing resources on other important tasks of the system, such as more complex energy scheduling algorithm optimization, in-depth monitoring and analysis of system status, rapid fault diagnosis and emergency response, etc. Through this reallocation and optimization of resources, the operating efficiency of the entire system has been significantly improved, and it can respond to various energy management and system control needs more quickly and accurately, providing strong support for achieving efficient and stable energy supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings, which constitute part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations of the present invention.

[0031] In the figure:

[0032] Figure 1 It is the overall structure diagram of DESS system;

[0033] Figure 2 A schematic diagram of the connection structure between a digital energy switch and a digital energy adapter;

[0034] Figure 3 It is a schematic diagram of the data transmission flow chart;

[0035] Figure 4 The figure is a schematic diagram of the data receiving flow chart. DETAILED DESCRIPTION

[0036] The inventive concepts of the present disclosure will be described below using terms commonly used by those skilled in the art to convey the essence of their work to other persons skilled in the art. However, these inventive concepts can be embodied in many different forms and should not be considered limited to the embodiments described herein.

[0037] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0038] The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0039] In the prior art, the digital energy switch and the digital energy adapter in the DESS system usually use RS485 half-duplex communication mode, which has many limitations, resulting in low data transmission efficiency and poor transmission accuracy of the system.

[0040] In order to solve the problems of low data transmission rate and poor transmission accuracy in the DESS system in the prior art, and serious electromagnetic interference in the application environment of dynamic reconstruction of DESS batteries; this embodiment proposes an optical fiber communication system and method based on FPGA technology, wherein the optical fiber communication system based on FPGA technology is a digital energy exchange system DESS, which is a soft-defined dynamic topology energy exchange system, and the DESS system is a core device for realizing energy digitization. The system includes an energy storage converter PCS, a digital energy adapter, a digital energy switch, and a digital energy hub; one end of the energy storage converter PCS is connected to the power grid, and the other end is connected to the digital energy network card through the digital energy adapter. The digital energy network card is connected to the energy components one by one. The digital energy adapter is connected to the digital energy switch through optical fiber communication, and the digital energy switch is connected to the digital energy network card through the digital energy hub. The digital energy network card is electrically connected to the digital energy adapter. Among them, FPGA chips are set in the digital energy adapter and the digital energy switch, which are used to realize rapid response processing of data under the action of the FPGA chip, and accurately control the access or isolation of energy components. In this embodiment, the energy storage converter PCS can be used to convert the DC power output by the digital energy adapter into AC power and transmit it to the power grid, and can also convert the AC power of the power grid into DC power and transmit it to the energy component, which is a battery cell or a photovoltaic panel. The digital energy network card is a high-speed control and data acquisition device for the energy component. A customized copper bus is directly fixed on the battery module or battery rack, and has a charge and discharge drive switch for the battery module, which responds to the command configuration of the digital energy hub. The FPGA chip is a field programmable gate array, which appears as a semi-custom circuit in the field of application-specific integrated circuits (ASICs). It not only solves the shortcomings of customized circuits, but also overcomes the shortcomings of the limited number of gate circuits of the original programmable device. The digital energy switch, the digital energy hub, and the digital energy network card are connected via Ethernet communication.

[0041] Through the DESS system, combined with power electronics technology and information technology, and a variety of isolation sampling technologies, the energy informationization setting is realized to realize the digital processing of energy systems such as electrochemical energy storage systems, photovoltaic systems, and photovoltaic storage complementary systems, and realize the software-defined dynamic topology structure. After the energy components are connected through the DESS system, the system will perform online dynamic digital integration based on the energy status information of each sub-unit to form an intrinsically safe, highly available, and efficient energy system. Among them, the digital energy hub is responsible for the equipment control, data collection, judgment, and forwarding of the energy units at the device layer; performs online dynamic reconstruction of the series-parallel topology of the energy units; and performs detection and protection actions for overvoltage, overtemperature, overcharge, overdischarge, and other abnormal conditions of the energy units.

[0042] like Figure 1 As shown, N digital energy hubs are provided, where N is a positive integer. Each digital energy hub is communicatively connected to a corresponding digital energy network card. Each digital energy hub is connected to m energy components and digital energy network cards, where m is a positive integer and m≤16.

[0043] like Figure 1 As shown, when m=9, each digital energy hub is connected to 9 energy components and digital energy network cards, and the 9 energy components are connected to the 9 digital energy network cards one by one. The 9 digital energy network cards are respectively recorded as NIC0-NIC8. After NIC0, NIC1, and NIC2 are connected in parallel, one end is connected to the digital energy adapter or the digital energy network card connected to the adjacent digital energy hub. After NIC0, NIC1, and NIC2 are connected in parallel, the other end is connected to the end of NIC3, NIC4, and NIC5 connected in parallel. After NIC3, NIC4, and NIC5 are connected in parallel, the other end is connected to the end of NIC6, NIC7, and NIC8 connected in parallel. After NIC6, NIC7, and NIC8 are connected in parallel, the other end is connected to the digital energy network card or digital energy adapter connected to the adjacent digital energy hub.

[0044] Through the cascade setting of digital energy network cards, dynamic topology switching of energy components can be realized. It is also beneficial to timely isolate or handle the energy components through digital energy network cards in the event of failure or abnormality of energy components, so as to realize dynamic energy scheduling of energy components in the system.

[0045] The FPGA chip includes a sending processing logic module and a receiving processing logic module. The sending processing logic module is connected to the optical fiber sending device, and the receiving processing logic module is connected to the optical fiber receiving device. The FPGA chip also includes a switch FPGA and an adapter FPGA. The switch FPGA is set in the digital energy switch, and the adapter FPGA is set in the digital energy adapter. Figure 2As shown, the optical fiber transmitting device (TX) of the switch FPGA is connected to the optical fiber receiving device (RX) of the adapter FPGA through optical fiber communication; the optical fiber receiving device (RX) of the switch FPGA is connected to the optical fiber transmitting device (TX) of the adapter FPGA through optical fiber communication. The FPGA chip is connected to the components in the digital energy switch or digital energy adapter through the data address bus. In this embodiment, the FPGA chip uses the domestic Anlu EG4D20EG176 FPGA.

[0046] Through the setting of FPGA chip, the full-duplex communication mode is adopted, which is conducive to improving the real-time performance of data transmission in the system and enhancing the efficiency of data sending and receiving in the system. Different from the half-duplex communication mode of RS485, the data transmission rate is low. The setting of FPGA chip is also conducive to achieving the data transmission rate between the digital energy switch and the digital energy adapter, and enhancing the security of data transmission. In addition, FPGA has powerful parallel processing capabilities and flexible programmability, and can quickly process large amounts of data and implement complex communication protocols and algorithms. By implementing data encoding, decoding, frame format processing and error checking functions in FPGA, the speed and efficiency of data processing can be significantly improved, thereby solving the problems of slow communication rate and poor real-time performance. Optical fiber communication uses optical signals to transmit data in optical fibers. Compared with traditional electrical signal communication methods, it has extremely high bandwidth and anti-electromagnetic interference capabilities. By adopting optical fiber communication technology, data can be transmitted quickly and accurately without electromagnetic interference, thereby solving the problem that the existing RS485 communication method is susceptible to interference in complex electromagnetic environments. It is conducive to enhancing the stability of system operation and reducing system costs.

[0047] The digital energy switch includes a switch CPU, and the switch FPGA is connected to the switch CPU through a data address bus; the digital energy adapter includes an adapter CPU, and the adapter FPGA is connected to the adapter CPU through a data address bus. Among them, the digital energy switch is a comprehensive control unit for the overall energy scheduling, high-level strategy execution and communication management of the DESS system. It is used to collect the working status of each circuit, analyze, judge and execute the corresponding system management strategy; upload the necessary data information of each part of the system; coordinate the scheduling of related systems (such as PCS); and can perform corresponding actions according to the system status and superior scheduling instructions. The digital energy adapter is a system-level acquisition, control and management device of the DESS, and is the interface for the system's DC input and output. Responsible for data acquisition, fault protection and system management of the system input and output, the digital energy adapter also receives the scheduling instructions of the digital energy switch to ensure the safe and stable operation of the system under various working conditions.

[0048] Different from the conventional digital energy switches and digital energy adapters that use RS485 half-duplex communication, which results in slow data communication rate within the system, insufficient real-time performance of data communication, complex on-site electromagnetic environment, and signals that are easily interfered with, leading to transmission errors, the digital energy switches and digital energy adapters of the present application use FPGA and CPU in conjunction with each other, and through full-duplex communication, the paths for receiving and sending data do not affect each other, greatly improving the communication rate and helping to improve the real-time performance of system data transmission. In addition, the use of fiber-optic communication uses light waves to transmit information, which is naturally immune to electromagnetic interference, ensuring high reliability of data transmission in the complex electromagnetic environment of the DESS system. Solve the product technology research and development problems that have long been plagued by poor system stability, and better meet customers' actual needs for efficient and reliable energy management systems.

[0049] The FPGA chip also includes a data buffer area, which is connected to the sending processing logic module and the receiving processing logic module respectively, and the data buffer area is connected to the switch CPU or the adapter CPU through the data address bus. The sending processing logic module includes a sending framing processing module, an encoding module, and a parallel-to-serial conversion module. The sending framing processing module is connected to the data buffer area and is used to fetch data through the data buffer area. The sending framing processing module is connected to the optical fiber sending device through the encoding module and the parallel-to-serial conversion module in turn, and the data is sent out through the optical fiber sending device; the receiving processing logic module includes a receiving analysis processing module, a decoding module, and a serial-to-parallel conversion module. One end of the optical fiber receiving device is connected to the optical fiber and is used to receive the optical fiber transmission signal. The other end of the optical fiber receiving device is connected to the data buffer area through the serial-to-parallel conversion module, the decoding module, and the receiving analysis processing module in turn, and is used to store the data in the data buffer area, and send the data to the adapter CPU or the switch CPU through the data buffer area. Among them, the encoding module and the decoding module both adopt the 8B / 10B data encoding method. The optical fiber sending device and the optical fiber receiving device adopt the domestic devices FT-1629Z and FT-2529Z respectively.

[0050] By selecting the domestic FPGA chip, optical fiber transmitting device and optical fiber receiving device in this embodiment, the system risk caused by the limited supply of foreign chips can be avoided, the chip cost can be reduced, and the market competitiveness of the product can be improved. And by adopting the setting of the FPGA chip, the transmission of data in the system can be made more efficient, and the delay time in the data transmission process can be reduced. In addition, the data buffer area set by the FPGA can play a key role during the operation of the system. The existence of the data buffer area greatly liberates the burden of the CPU, so that the CPU no longer needs to consume resources to process complex communication protocols. It is beneficial for the CPU to devote more energy and computing power to other important tasks of the system, such as the execution of more complex energy management algorithms, in-depth analysis of system status, and rapid decision-making. This optimized resource allocation method significantly improves the operating efficiency and response speed of the entire system.

[0051] An optical fiber communication method based on FPGA technology, the method is applied to an optical fiber communication system based on FPGA technology, the method comprises the following steps:

[0052] Step 1: Build a communication hardware platform: Set the FPGA chip in the digital energy switch and the digital energy adapter respectively; wherein the FPGA chip is connected to the switch CPU or the adapter CPU through a data address bus, and the data width of the data address bus is 16 bits.

[0053] Step 2: Software setup: Develop a communication control program based on FPGA chip; used to implement data encoding, decoding, frame format processing and error checking. The CPU software adapts to the new DESS system protocol only needs to read and write data, which greatly improves the processing efficiency and real-time performance of the product, can respond to problems more quickly, and accurately control the system; in this embodiment, the new DESS system protocol refers to the optimized proprietary communication protocol in step 3.

[0054] Step 3: Protocol setting: Use the DESS system-based proprietary communication protocol and set the data frame format corresponding to the protocol.

[0055] Step 4: Run the system to send and receive data.

[0056] The setting of the method is conducive to improving the data transmission rate between the components in the system and avoiding the occurrence of delays during the transmission process. Improve the anti-interference ability of the system and enhance the reliability of the system. Through the data address bus with a 16-bit data width, seamless connection and efficient data transmission between FPGA and digital energy switch or digital energy adapter are realized. The present invention can be easily integrated into the existing DESS system architecture, reducing the cost and difficulty of system upgrade, transformation and maintenance. At the same time, the architecture has good scalability, setting flexibility and good compatibility, and can support the upgrading of system functions and the access of new equipment without large-scale changes to the existing architecture, meet the needs of the continuous development and evolution of the future DESS system, provide convenience for the future development and upgrading of the system, enable it to better adapt to the changing market demand and technological development trends, and provide strong technical guarantees for technological innovation and application expansion in the field of energy management. In addition, through the setting of each step in the method, in the system initialization stage, it can ensure the accurate setting and coordination of each component, laying a solid foundation for subsequent stable and efficient data transmission. Through the fine operation of the configuration link, the system can be optimized and adjusted according to actual needs and specific scenarios, giving full play to its performance advantages. In terms of system maintenance, the fiber-optic communication system based on FPGA technology has demonstrated a high degree of stability and reliability. It can shorten the time required for maintenance and ensure that the system can continue to operate stably. For example, when processing large-scale energy data, the CPU can focus on data analysis and prediction without worrying about the details of the underlying communication, thereby more accurately scheduling and optimizing energy. When responding to sudden changes in energy demand, the system can rely on efficient communication and the rapid response of the CPU to timely adjust the energy distribution in different energy components and ensure the stability of energy supply in the system. In general, the application of fiber-optic communication based on FPGA technology in the DESS system has achieved efficient integration of data transmission, brought innovative breakthroughs to the field of energy management, and provided strong technical support for building a smarter and more efficient energy system.

[0057] Among them, the data length of each data frame corresponding to the protocol is 64 bits, and the structure of each data frame includes address command information, data segment, frame sequence number and CRC check data. The data in the address command information, data segment, frame sequence number and CRC check data are arranged in sequence to form the data of each data frame, wherein the data length of the address command information is 16 bits, the data length of the data segment is 32 bits, the data length of the frame sequence number is 8 bits, and the data length of the CRC check data is 8 bits. By setting the above data frame format, the accuracy, integrity and orderliness of data transmission can be effectively ensured. Reduce data transmission conflicts and confusion. Ensure that each data frame can be accurately sent, received and processed, and provide solid technical support for the refined energy management and intelligent control of the DESS system.

[0058] Step 4 includes: running the system, and processing data reception and data transmission in the digital energy switch or the digital energy adapter in parallel in a full-duplex manner without interfering with each other.

[0059] Among them, the data transmission process in step 4 is as follows: the data generated by the switch CPU of the digital energy switch or the adapter CPU of the digital energy adapter is transmitted to the corresponding FPGA chip through the data address bus, and the data is stored in the data cache area of ​​the FPGA chip. The FPGA chip is encapsulated according to the protocol, and the address command information, data segment information, frame sequence number and CRC check data are added to form a 64-bit data frame, and the data in the data frame is encoded to form the original data. After the original data enters the parallel-to-serial conversion module, the data is transmitted serially to the optical fiber sending device. After the optical fiber sending device converts the electrical signal into an optical signal, it is sent to the digital energy adapter or digital energy switch through the optical fiber. Among them, the encoding adopts 8B / 10B encoding, and the number of bits of the original data is 80 bits. The model of the optical fiber sending device is FT-1629Z. Among them, the frame sequence number data is generated by the counter in the digital energy switch or digital energy adapter.

[0060] The data receiving process in step 4 is as follows: after the optical fiber receiving device of the digital energy adapter or digital energy switch receives the optical signal, it converts the received optical signal into an electrical signal and transmits it to the serial-to-parallel conversion module of the FPGA chip. The FPGA chip first decodes the received data, then performs protocol analysis, extracts the address command information, data segment information, frame sequence number and CRC check data. Perform CRC check, if the check passes, the valid data is stored in the data buffer area of ​​the FPGA chip, and transmitted to the digital energy adapter or digital energy switch through the data address bus.

[0061] Specifically, the working principle of data transmission is as follows:

[0062] like Figure 3 As shown in the figure, when the digital energy switch or digital energy adapter generates data, the data will be quickly and stably transmitted to the FPGA in parallel via the data address bus with a 16-bit data width. The data first enters the specially set data buffer area inside the FPGA for temporary storage to prepare for subsequent processing steps.

[0063] This data cache uses advanced storage management technology and high-speed cache architecture to quickly receive and temporarily store data, providing efficient buffering for subsequent processing steps. In the data cache, data is arranged and stored in an orderly manner, waiting for the FPGA processing logic to perform packaging operations.

[0064] FPGA begins to carefully encapsulate the data according to its own communication protocol that is carefully pre-set and strictly follows the DESS system specifications. The first 16-bit address command information added is generated through precise encoding and mapping. These encodings and mappings are based on the system's pre-defined rules and instruction sets, and can clearly and accurately indicate the type of data transmission. The transmission type not only includes conventional energy status data and equipment configuration data, but also covers any one or more of emergency control instructions and system diagnostic information. At the same time, the address command information also accurately identifies the target address of the data to ensure that the data can be accurately transmitted to the designated digital energy switch or digital energy adapter. In addition, the relevant operation instructions are also encoded in detail in the data frame, providing clear guidance for the subsequent processing and execution of the data.

[0065] Next, the 32-bit specific data content, i.e., the data in the data segment, is closely connected after the address command information. These specific data contents come from a wide range of sources, including energy status data collected by sensors in real time, data of internal parameters of the device, and any one or more of the control instruction data generated by the system. The energy status data collected by the sensor in real time includes any one or more of voltage fluctuation data accurate to the microsecond level, current change data at the millisecond level, power output data accurate to the watt level, and energy storage data in joules; the data of internal parameters of the device includes any one or more of the unique identifier of the device, detailed settings of the working mode, and specific values ​​of various configuration parameters; the control instruction data generated by the system includes any one or more of the instructions for starting, stopping, power adjustment, and working mode switching of the device. These data are rich and detailed, providing key information support for the precise control and efficient management of the system.

[0066] Subsequently, the added 8-bit frame number is generated by a high-precision counter. This counter works in a strictly incremental manner, starting from 0 and increasing by 1 in steps. When it reaches 255, it starts counting again from 0. The frame number of each data frame is different, so that during the data transmission process, no matter what the situation, the order and integrity of the data can be accurately maintained, effectively avoiding data loss, duplication, misordering and other problems, and greatly improving the reliability and accuracy of data transmission.

[0067] Finally, an advanced cyclic redundancy check (CRC) algorithm is used to generate 8 bits of CRC check data for the previous 56 bits of data. The CRC algorithm is based on complex polynomial operations and XOR operations of data bits to perform in-depth analysis of the data content and generate check codes. At the receiving end, the receiver can use the same CRC algorithm to check the received data. By comparing the calculated check value with the check value generated by the sender and sent along with the data, it can quickly and accurately determine whether data errors or losses have occurred during the data transmission process. This verification method has extremely high accuracy and sensitivity, and can detect most data transmission errors, providing a solid guarantee for the integrity and accuracy of the data.

[0068] After the above series of fine and rigorous encapsulation operations, a complete 64-bit data frame is formed. This data frame has a compact structure and complete information, and has the basic conditions for accurate transmission in a complex communication environment.

[0069] After the encapsulation, the 64-bit data frame is quickly and accurately sent to the specially designed 8B / 10B encoding module for encoding. The 8B / 10B encoding module uses high-performance hardware logic and optimized encoding algorithms to quickly convert the input 64-bit data into 80-bit encoded data. The core principle of this encoding method is to effectively enhance the DC balance of the data by increasing the number of conversions between "0" and "1" in the data, and significantly reduce the probability of long-term "0" or "1". This feature makes the data more resistant to electromagnetic interference, signal attenuation, inter-code crosstalk, etc. during transmission, thereby greatly improving the transmission reliability and stability of data in complex electromagnetic environments and noise interference.

[0070] The encoded 80-bit data then enters the advanced parallel-to-serial conversion module. The parallel-to-serial conversion module uses high-speed digital circuits and precise clock synchronization technology to quickly and accurately convert the parallel input 80-bit data into serial data. This serial data format is more suitable for transmission in optical fiber communication links, which can effectively reduce the number of lines, reduce transmission costs, and increase transmission speed and distance.

[0071] The serialized 80-bit data is then accurately transmitted to the FT-1629Z fiber optic transmitter. The FT-1629Z fiber optic transmitter integrates a high-performance electro-optical conversion circuit, which uses advanced semiconductor laser technology and high-speed modulation technology to convert the received electrical signals into optical signals with extremely high efficiency and speed. These optical signals are transmitted through the high-quality, low-loss optical fiber medium connected to it. The optical fiber medium has extremely high bandwidth, extremely low transmission loss and extremely strong anti-interference ability, and can transmit optical signals to the target device at a speed close to the speed of light, with extremely low signal attenuation and extremely low bit error rate, thereby realizing the fast, stable and accurate transmission of data from the data source (digital energy switch or digital energy adapter) to the target device.

[0072] During the entire data transmission process, a comprehensive, intelligent, and real-time monitoring logic is integrated inside the FPGA. This monitoring logic uses advanced sensor technology, high-speed data acquisition technology, and complex data analysis algorithms to continuously monitor and manage each link in the data transmission process in real time, dynamically, and comprehensively.

[0073] On the one hand, for data storage and reading operations in the data cache area, the monitoring logic ensures that data storage and reading operations are carried out efficiently and accurately by real-time monitoring of key parameters such as cache area occupancy, data writing and reading speed, and data queue length, combined with advanced cache management strategies and data scheduling algorithms. Through intelligent flow control and congestion avoidance mechanisms, data accumulation, loss, or erroneous reading and writing are effectively prevented, ensuring the safe and fast flow of data in the cache area.

[0074] On the other hand, the monitoring logic conducts strict and detailed monitoring and control of the encoding, parallel-to-serial conversion, and data transmission process between the FT-1629Z optical fiber transmission device. By real-time acquisition and analysis of key parameters in the data transmission process, the key parameters include the accuracy and efficiency of encoding, the accuracy and speed of parallel-to-serial conversion, the data transmission rate in the optical fiber link, signal strength, bit error rate, and any one or more parameters, and compare and analyze these real-time monitoring data with the thresholds and performance indicators pre-set by the system. According to the comparison and analysis results, combined with the preset adaptive adjustment strategy and control algorithm, the data transmission rate, signal strength, encoding parameters and other key factors are dynamically adjusted to ensure that data transmission is always in the best state, adapt to different network conditions and transmission environment changes, and maximize the performance and reliability of data transmission.

[0075] Once the monitoring logic detects any abnormal situation, including any one or more of coding errors, conversion errors, transmission interruptions, rate anomalies, excessive signal attenuation, and bit error rates exceeding the allowed threshold, the FPGA will quickly trigger the corresponding error handling mechanism. These error handling mechanisms include automatically starting re-encoding operations, re-encoding erroneous data frames, ensuring coding accuracy, starting data retransmission mechanisms, retransmitting lost or erroneous data frames, ensuring data integrity, dynamically adjusting transmission parameters (dynamically adjusting transmission parameters includes flexibly adjusting encoding methods, changing transmission rates, and enhancing signal strength according to current transmission quality and environmental conditions), optimizing data transmission performance, issuing system alarm signals, and promptly feeding back error information to the system's monitoring and management center, and notifying relevant personnel to perform any one or more of the following operations: fault diagnosis and repair. Through these fast and effective error handling measures, errors can be corrected in a timely and accurate manner, normal data transmission can be quickly restored, the impact of errors on system performance and stability can be minimized, data can be sent to the target device accurately, completely, and in a timely manner, and the entire communication system can always maintain a stable and reliable operating state.

[0076] Specifically, the working principle of the data receiving process is as follows:

[0077] like Figure 4 As shown, the FT-2529Z optical fiber receiving device is always in a highly sensitive standby state, and its internal photoelectric conversion elements and signal receiving circuits are always ready to receive optical signals transmitted through optical fibers.

[0078] Once the optical signal reaches the FT-2529Z optical fiber receiving device, the high-performance photoelectric conversion circuit inside the module will quickly convert the optical signal into an electrical signal at a nanosecond response speed. After preliminary amplification, filtering and shaping, these electrical signals are accurately and quickly transmitted to the serial-to-parallel conversion module of the FPGA.

[0079] In the serial-to-parallel conversion module, the received serial electrical signal undergoes a high-speed and accurate conversion process. The serial-to-parallel conversion module can accurately convert the serial electrical signal into parallel 80-bit data based on the serial electrical signal. These parallel data are then stably and quickly transmitted to the processing logic inside the FPGA.

[0080] After receiving the parallel 80-bit data, the FPGA first starts the 8B / 10B decoding module to decode the data. The 8B / 10B decoding module uses the decoding algorithm and logic circuit corresponding to the encoding process to accurately decode the received 80-bit data and restore it to the original 64-bit data frame.

[0081] The decoded 64-bit data frame is analyzed in depth according to the DESS system's own communication protocol. First, the FPGA extracts 16 bits of address command information from the beginning of the data frame. By analyzing and interpreting these address command information, according to the system's pre-set rules and instruction sets, the data type (data type includes any one or more of control instructions, state feedback, and measurement data), source (data source includes the identifier of the digital energy switch or digital energy adapter that sends data), target (target device identifier for data reception) and operation instructions (operation instructions include any one of read requests, write instructions, and control actions) are accurately determined, thereby providing a clear basis and direction for subsequent data distribution and processing.

[0082] Next, the FPGA will read the subsequent 32-bit specific data content. These data contents include the current energy state of the device, the operating parameters of the device, and any one or more key information in the control feedback information. Among them, the current energy state of the device includes any one or more information in real-time voltage, current, power, and energy storage level, the operating parameters of the device include any one or more information in operating temperature, operating time, and fault code, and the control feedback information includes any one or more information in instruction execution results and device response status. By acquiring and analyzing these specific data contents, the system can understand the operating status of the equipment and the actual effect of energy management in real time, providing data support for further decision-making and control.

[0083] Then, the FPGA will parse the 8-bit frame number in the data frame. By analyzing and processing the frame number, the data frame is accurately sorted and grouped according to the increasing order and cycle rules of the frame number, ensuring that the order of data reception is completely consistent with the order of data transmission, effectively preventing data disorder or loss, and ensuring data integrity and continuity.

[0084] Finally, the FPGA reads the 8-bit CRC check data at the end of the data frame and uses the same CRC check algorithm as the sender to check the integrity and accuracy of the previous 56-bit data content. The calculated check value is compared and analyzed with the received check value.

[0085] Determine whether the calculated checksum is consistent with the received checksum?

[0086] If the two are completely consistent, it means that there is no error or loss in the data transmission process, the data is complete and accurate, and can be processed and applied later; the CRC check result shows that there is no error or loss in the data transmission process, and the FPGA will first temporarily store the parsed valid data in the internal data cache for temporary storage and management. The data cache uses high-speed, low-latency storage technology and data management strategies, which can quickly and securely store and manage the received data, waiting for subsequent processing and distribution.

[0087] No, if the two are inconsistent, it indicates that an error occurred during data transmission. The FPGA will take appropriate error handling measures based on the type and severity of the error. The handling measures include requesting data retransmission, discarding erroneous data, triggering an error alarm, or starting the system error correction mechanism.

[0088] Subsequently, these valid data will be accurately and quickly transmitted to the designated digital energy switch or digital energy adapter through the data address bus with a 16-bit data width in a parallel, high-speed and stable transmission mode. During the data transmission process, the FPGA chip will monitor and manage the data transmission process in real time to ensure that the data transmission is accurate, complete and timely for subsequent processing, analysis and decision-making. The subsequent processing, analysis and decision-making include any processing method in the control adjustment of the equipment, the distribution management of energy, and the status update of the system.

[0089] During the entire data reception process, the internal monitoring logic of the FPGA always remains highly active and vigilant, performing real-time, comprehensive and detailed monitoring and management of each link of data reception.

[0090] On the one hand, FPGA pays close attention to the data receiving status of the serial-to-parallel conversion module. By real-time monitoring of the input signal strength, conversion rate, data accuracy and any one or more key parameters of the serial-to-parallel conversion module, combined with advanced signal quality evaluation algorithms and fault diagnosis logic, it ensures continuous, stable and accurate data reception. Once any one or more problems such as interruption of data reception, abnormal signal strength and conversion error are found, FPGA will immediately take corresponding emergency measures, including adjusting receiving parameters, starting backup receiving channels, and issuing fault alarms, to ensure stable data reception.

[0091] On the other hand, FPGA strictly and meticulously monitors the 8B / 10B decoding, protocol analysis, and data transmission process with the digital energy switch or digital energy adapter. By real-time acquisition and analysis of key data and parameters in these processes, such as decoding accuracy, protocol analysis results, data transmission rate, error rate, etc., and comparing and evaluating these data with the system's preset performance indicators and quality standards. Based on the comparison and evaluation results, FPGA adjusts the data processing parameters and transmission mode in real time. The data processing parameters and transmission mode include optimizing the decoding algorithm, adjusting the protocol analysis strategy, and changing the data transmission rate and mode, to ensure the accuracy of data processing and the efficiency of transmission.

[0092] Once an error is detected during the data reception process, the error type includes any one or more of decoding error, CRC check failure, data transmission interruption, and data disorder, and the FPGA will immediately take corresponding error handling measures. These error handling measures include but are not limited to requesting data retransmission from the sender to obtain correct data; discarding erroneous data frames to avoid the adverse effects of erroneous data on the system; triggering error alarms and promptly notifying the system's monitoring and management center of the error information so that relevant personnel can troubleshoot and repair the problem; starting the system error correction mechanism to correct and recover erroneous data through error correction coding and redundant data. Through these timely and effective error handling measures, it can ensure that the system can stably and reliably receive and process data, ensure the normal operation of the DESS system and the accuracy of energy management, and provide solid technical support and guarantee for the efficient, stable and safe operation of the entire system.

[0093] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An optical fiber communication system based on FPGA technology, characterized in that: It includes an energy storage inverter PCS, a digital energy adapter, a digital energy switch, and a digital energy hub; one end of the energy storage inverter PCS is connected to the power grid, and the other end is connected to the digital energy network card through the digital energy adapter; the digital energy network card is connected to the energy components one by one, the digital energy adapter and the digital energy switch are connected through optical fiber communication, and the digital energy switch is connected to the digital energy network card through the digital energy hub; the digital energy network card is electrically connected to the digital energy adapter, and FPGA chips are provided in the digital energy adapter and the digital energy switch, which are used to realize rapid response processing of data under the action of the FPGA chip, and accurately control the access or isolation of energy components.

2. The optical fiber communication system based on FPGA technology according to claim 1, characterized in that: The FPGA chip includes a sending processing logic module and a receiving processing logic module; the sending processing logic module is connected to the optical fiber sending device, and the receiving processing logic module is connected to the optical fiber receiving device.

3. The optical fiber communication system based on FPGA technology according to claim 2, characterized in that: The FPGA chip also includes a switch FPGA and an adapter FPGA; the switch FPGA is arranged in the digital energy switch, the adapter FPGA is arranged in the digital energy adapter, the optical fiber transmitting device of the switch FPGA is connected to the optical fiber receiving device of the adapter FPGA through optical fiber communication, and the optical fiber receiving device of the switch FPGA is connected to the optical fiber transmitting device of the adapter FPGA through optical fiber communication.

4. The optical fiber communication system based on FPGA technology according to claim 2, characterized in that: The FPGA chip is connected to components in a digital energy switch or a digital energy adapter via a data address bus.

5. The optical fiber communication system based on FPGA technology according to claim 4, characterized in that: The digital energy switch comprises a switch CPU, and the switch FPGA is connected to the switch CPU via a data address bus; the digital energy adapter comprises an adapter CPU, and the adapter FPGA is connected to the adapter CPU via a data address bus.

6. The optical fiber communication system based on FPGA technology according to claim 5, characterized in that: The FPGA chip also includes a data buffer area; the data buffer area is connected to the sending processing logic module and the receiving processing logic module respectively, and the data buffer area is connected to the switch CPU or the adapter CPU through a data address bus.

7. The optical fiber communication system based on FPGA technology according to claim 6, characterized in that: The sending processing logic module includes a sending framing processing module, an encoding module, and a parallel-to-serial conversion module; the sending framing processing module is connected to the data buffer area, and the sending framing processing module is connected to the optical fiber sending device through the encoding module and the parallel-to-serial conversion module in turn.

8. The optical fiber communication system based on FPGA technology according to claim 7, characterized in that: The receiving processing logic module includes a receiving analysis processing module, a decoding module, and a serial-to-parallel conversion module; one end of the optical fiber receiving device is connected to the optical fiber, and the other end of the optical fiber receiving device is connected to the data buffer area through the serial-to-parallel conversion module, the decoding module, and the receiving analysis processing module in sequence.

9. The optical fiber communication system based on FPGA technology according to claim 8, characterized in that: The encoding module and the decoding module both adopt 8B / 10B data encoding method.

10. A method for optical fiber communication based on FPGA technology, the method being applied to an optical fiber communication system based on FPGA technology according to any one of claims 1 to 9, characterized in that: The method comprises the following steps: Step 1: Build a communication hardware platform: Set the FPGA chip in the digital energy switch and the digital energy adapter respectively; Step 2: Software setup: Develop a communication control program based on FPGA chip; Step 3: Protocol setting: Use the DESS system-based proprietary communication protocol and set the data frame format corresponding to the protocol; Step 4: Run the system to send and receive data.

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