Semiconductor structure and preparation method thereof

Abstract

The preparation method of the semiconductor structure comprises the steps that a substrate is provided, bit line structures and first isolation structures are arranged on the substrate, the first isolation structures and the bit line structures are arranged in a crossed mode, the top surfaces of the first isolation structures are higher than the top surfaces of the bit line structures, and a first contact hole is defined by every two adjacent bit line structures and every two adjacent first isolation structures; initial conductive layers are formed in the first contact holes, mask patterns are formed on the initial conductive layers, the top surfaces of the initial conductive layers are lower than the top surfaces of the first isolation structures, the mask patterns are located on the side walls of the first isolation structures, and first grooves are formed between the mask patterns on the opposite side walls of the adjacent first isolation structures; removing part of the initial conductive layer along the first groove to form a first isolation groove; and filling the first isolation groove with an isolation material to form a second isolation structure. According to the preparation method, the conductive structure without an air gap can be formed in the first contact hole, and the performance of the semiconductor structure is greatly improved.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuits, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] As the feature size of integrated circuit devices continues to shrink, the requirements for dynamic random access memory (DRAM) process technology are becoming increasingly higher, and the design of storage node contact holes (NC contact holes) in the array area is also very important. Currently, there is an air gap in the conductive layer formed in the NC contact hole, which will affect the performance of the semiconductor device.

[0003] Therefore, how to remove the air gaps in the conductive layer has become the focus of current research. Summary of the invention

[0004] The technical problem to be solved by the embodiments of the present disclosure is to provide a semiconductor structure and a method for preparing the same, which can form a conductive structure without air gaps and improve the performance of the semiconductor structure.

[0005] In order to solve the above problems, an embodiment of the present disclosure provides a method for preparing a semiconductor structure, which comprises: providing a substrate, on which a bit line structure and a first isolation structure are arranged, the first isolation structure and the bit line structure are arranged crosswise, and the top surface of the first isolation structure is higher than the top surface of the bit line structure, and two adjacent bit line structures and two adjacent first isolation structures form a first contact hole; forming an initial conductive layer in the first contact hole, and forming a mask pattern on the initial conductive layer, the top surface of the initial conductive layer is lower than the top surface of the first isolation structure, the mask pattern is located on the side wall of the first isolation structure, and a first groove is provided between the mask patterns on the opposite side walls of adjacent first isolation structures; removing part of the initial conductive layer along the first groove to form a first isolation groove; filling the first isolation groove with isolation material to form a second isolation structure.

[0006] The disclosed embodiment also provides a semiconductor structure, which includes: a substrate; a bit line structure, arranged on the substrate; a first isolation structure, arranged on the substrate, the first isolation structure and the bit line structure are arranged crosswise, and two adjacent bit line structures and two adjacent first isolation structures form a first contact hole; a second isolation structure, arranged in the first contact hole and separating the first contact hole into a target contact hole; a conductive structure, arranged in the target contact hole, the top surface of the conductive structure being lower than the top surfaces of the first isolation structure, the second isolation structure and the bit line structure.

[0007] The semiconductor structure and preparation method provided by the embodiment of the present disclosure first fill an initial conductive layer in the first contact holes defined by two adjacent first isolation structures, and then form a second isolation structure in the initial conductive layer. The second isolation structure can penetrate the initial conductive layer, so that the air gap in the initial conductive layer can be removed. The first isolation structure, the second isolation structure and the bit line structure define a target contact hole. The initial conductive layer in the target contact hole serves as the final conductive structure. There is no air gap in the conductive structure, which greatly improves the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a schematic diagram of a semiconductor structure;

[0009] Figure 2 is a schematic diagram of the steps of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0010] Figure 3A to Figure 3K It is a schematic diagram of a semiconductor structure formed by the main steps of the preparation method provided in one embodiment of the present disclosure;

[0011] Figure 4A to Figure 4I It is a schematic diagram of a semiconductor structure formed by the main steps of a preparation method provided in another embodiment of the present disclosure. DETAILED DESCRIPTION

[0012] The specific implementation methods of the semiconductor structure and the preparation method thereof provided by the present disclosure are described in detail below with reference to the accompanying drawings.

[0013] Figure 1 is a schematic diagram of a semiconductor structure, see Figure 1 In the semiconductor structure, the isolation structure 100 defines a conductive contact hole 110, the conductive contact hole 110 is filled with a conductive structure 120, and the conductive contact material 130 covers the conductive structure 120. Affected by the deposition process, the conductive structure 120 filled in the conductive contact hole 110 has an air gap 121, which may affect the performance of the semiconductor structure.

[0014] In view of this, some embodiments of the present disclosure provide a method for preparing a semiconductor structure, which can form a conductive structure without an air gap, thereby improving the performance of the semiconductor structure.

[0015] Figure 2 Schematic diagram of the steps of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure. Figure 2The preparation method includes: step S20, providing a substrate, on which a bit line structure and a first isolation structure are arranged, the first isolation structure and the bit line structure are arranged crosswise, and the top surface of the first isolation structure is higher than the top surface of the bit line structure, and two adjacent bit line structures and two adjacent first isolation structures form a first contact hole; step S21, forming an initial conductive layer in the first contact hole, and forming a mask pattern on the initial conductive layer, the top surface of the initial conductive layer is lower than the top surface of the first isolation structure, the mask pattern is located on the side wall of the first isolation structure, and a first groove is provided between the mask patterns on the opposite side walls of adjacent first isolation structures; step S22, removing part of the initial conductive layer along the first groove to form a first isolation groove; step S23, filling the first isolation groove with an isolation material to form a second isolation structure.

[0016] Some embodiments of the present disclosure provide a method for preparing a semiconductor structure, which first fills an initial conductive layer in a first contact hole defined by two adjacent first isolation structures, and then forms a second isolation structure in the initial conductive layer. The second isolation structure can penetrate the initial conductive layer, thereby removing the air gap in the initial conductive layer. The first isolation structure, the second isolation structure and the bit line structure define a target contact hole. The initial conductive layer in the target contact hole serves as the final conductive structure, and there is no air gap in the conductive structure, thereby greatly improving the performance of the semiconductor structure.

[0017] Figure 3A to Figure 3K It is a schematic diagram of a semiconductor structure formed by the main steps of the preparation method provided in one embodiment of the present disclosure.

[0018] See also Figure 2 and Figure 3A , among which Figure 3A In the figure, (a) is a top view, (b) is a cross-sectional view along line A-A1 in (a), and (c) is a cross-sectional view along line B-B1 in (a). In step S20, a substrate 200 is provided, on which a bit line structure 210 and a first isolation structure 220 are arranged. The first isolation structure 220 is cross-arranged with the bit line structure 210 and a top surface of the first isolation structure 220 is higher than a top surface of the bit line structure 210. Two adjacent bit line structures 210 and two adjacent first isolation structures 220 form a first contact hole 230.

[0019] The substrate 200 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, an SOI substrate or a GOI (Germanium-on-Insulator) substrate, etc.; the substrate 200 may also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide or silicon carbide, etc. The substrate 200 may also be a stacked structure, such as a silicon / silicon germanium stack, etc. In addition, the substrate 200 may be an ion-doped substrate, which may be P-type doped or N-type doped; a plurality of peripheral devices may also be formed in the substrate 200, such as field effect transistors, capacitors, inductors and / or diodes, etc. In this embodiment, the substrate 200 is a silicon substrate, which may also include other device structures, such as transistor structures, metal wiring structures, etc.

[0020] The first isolation structure 220 and the bit line structure 210 are arranged crosswise, including the first isolation structure 220 straddling the bit line structure 210, or the first isolation structure 220 is arranged in sections between the bit line structures 210. In this embodiment, the first isolation structure 220 straddling the bit line structure 210 is used as an example for description. In some embodiments, the first isolation structure 220 is arranged vertically or at an acute angle to the bit line structure 210. In this embodiment, the first isolation structure 220 and the bit line structure 210 are arranged vertically as an example for description.

[0021] A plurality of bit line structures 210 are disposed on the substrate 200. In some embodiments, the plurality of bit line structures 210 are arranged at intervals along a first direction D1 and each bit line structure 210 extends along a second direction D2. The first direction D1 and the second direction D2 are directions parallel to the plane where the substrate 200 is located, and the first direction D1 is perpendicular to the second direction D2. In this embodiment, the first direction D1 is an X direction in a Cartesian coordinate system, and the second direction D2 is a Y direction in a Cartesian coordinate system.

[0022] A plurality of first isolation structures 220 are disposed on the substrate 200. In some embodiments, the plurality of first isolation structures 220 are arranged at intervals along the second direction D2 and each first isolation structure 220 extends along the first direction D1. The first isolation structures 220 include but are not limited to nitride isolation structures, such as silicon nitride isolation structures.

[0023] In the third direction D3, the top surface of the first isolation structure 220 is higher than the top surface of the bit line structure 210. The third direction D3 is a direction perpendicular to the plane of the substrate 200 and is perpendicular to the first direction D1 and the second direction D2. In this embodiment, the third direction D3 is taken as the Z direction in the Cartesian coordinate system for illustration.

[0024] Two adjacent bit line structures 210 and two adjacent first isolation structures 220 form a first contact hole 230. For example, the bit line structure 210 includes an adjacent bit line structure 210A and a bit line structure 210B, the first isolation structure 220 includes an adjacent first isolation structure 220A and a first isolation structure 220B, and the adjacent bit line structures 210A and 210B, and the adjacent first isolation structures 220A and 220B form a first contact hole 230A.

[0025] In some embodiments, the substrate 200 includes first word lines 240 and second word lines 241 alternately arranged along the second direction D2. Since the first word lines 240 and the second word lines 241 are located inside the substrate 200, the second word lines 241 are depicted by dashed lines in FIG. (a), and the projection of the first isolation structure 220 on the substrate 200 at least partially overlaps with the projection of the first word line 240 on the substrate 200, and the projection of the second word line 241 on the substrate 200 is located between the projections of the adjacent first isolation structures 220 on the substrate 200. In this embodiment, the projection of the first isolation structure 220 on the substrate 200 completely overlaps with the projection of the first word line 240 on the substrate 200 for description.

[0026] See also Figure 2 , step S21, forming an initial conductive layer 250 in the first contact hole 230, and forming a mask pattern on the initial conductive layer 250, the top surface of the initial conductive layer 250 is lower than the top surface of the first isolation structure 220, the mask pattern is located on the side wall of the first isolation structure 220, and there is a first trench 260 between the mask patterns on the opposite side walls of adjacent first isolation structures 220. In this step, the initial conductive layer 250 also covers the surface of the bit line structure 210.

[0027] In some embodiments, Figure 3G As shown, Figure 3G In the figure, (a) is a top view, (b) is a cross-sectional view along the A-A1 line in (a), the mask pattern includes a first mask pattern 261 and a second mask pattern 262 arranged on the opposite side walls of two adjacent first isolation structures 220, and a first groove 260 is between the first mask pattern 261 and the second mask pattern 262, and the first groove 260 exposes the top surface of the initial conductive layer 250.

[0028] The first trench 260 exposes a portion of the top surface of the initial conductive layer 250, and if there is an air gap 251A in the initial conductive layer 250, the region of the initial conductive layer 250 where the air gap 251A is located is not blocked by the mask pattern, and the air gap 251A is usually located at the central axis of the initial conductive layer 250, that is, the region of the initial conductive layer 250 where the air gap 251A is located corresponds to the first trench 260. The material of the mask pattern can be a material having a higher etching selectivity ratio with the first isolation structure 220 and the initial conductive layer 250, so as to achieve selective etching in subsequent processes. In this embodiment, the material of the mask pattern is silicon dioxide, the material of the first isolation structure 220 is silicon nitride, and the material of the initial conductive layer 250 is polysilicon.

[0029] As an example, an embodiment of the present disclosure provides a method of forming an initial conductive layer 250 in a first contact hole 230 , and forming a first mask pattern 261 and a second mask pattern 262 on the initial conductive layer 250 .

[0030] See also Figure 3D , among which Figure 3D In the figure, (a) is a top view, and (b) is a cross-sectional view along the A-A1 line in (a). An initial conductive material layer 253 is formed in the first contact hole 230. The top of the initial conductive material layer 253 has a third protrusion 252, and a first sub-mask pattern 2611 is provided between the third protrusion 252 and a first isolation structure 220. A second sub-mask pattern 2621 is provided between the third protrusion 252 and another first isolation structure 220. The top surface of the third protrusion 252 is lower than the top surfaces of the first isolation structure 220, the first sub-mask pattern 2611 and the second sub-mask pattern 2621, and the initial conductive material layer 253 also covers the surface of the bit line structure 210.

[0031] Specifically, in some embodiments, forming the initial conductive material layer 253 in the first contact hole 230 includes:

[0032] See also Figure 3B , among which Figure 3B In the figure, (a) is a top view, (b) is a cross-sectional view along the line A-A1 in (a), a first conductive layer 251 is formed in the first contact hole 230, and the top surface of the first conductive layer 251 is lower than the top surface of the first isolation structure 220. In some embodiments, this step includes: filling the first contact hole 230 with a conductive material, the conductive material also covers the top surface of the first isolation structure 220 and the top surface of the bit line; etching back the conductive material to a set height to form the first conductive layer 251. The material of the first conductive layer 251 includes but is not limited to polysilicon (poly). In this step, the first conductive layer 251 extends along the first direction D1, and it also covers the surface of the bit line structure 210, and the first conductive layer 251 has an air gap 251A.

[0033] See also Figure 3C , among which Figure 3C In the figure, (a) is a top view, (b) is a cross-sectional view along the line A-A1 in (a), a first sub-mask pattern 2611 and a second sub-mask pattern 2621 are formed on the top surface of the first conductive layer 251 and arranged on the side wall of the first isolation structure 220, and a fourth groove 231 is provided between the first sub-mask pattern 2611 and the second sub-mask pattern 2621. For example, in this step, a first sub-mask pattern 2611 is provided on a side wall of the first isolation structure 220A, a second sub-mask pattern 2621 is provided on a side wall of another first isolation structure 22B0 adjacent to the first isolation structure 220A and facing the first isolation structure 220A, the first sub-mask pattern 2611 and the second sub-mask pattern 2621 both extend along the first direction D1, and the fourth groove 231 exposes a portion of the top surface of the first conductive layer 251. In some embodiments, in the third direction D3 , top surfaces of the first sub-mask pattern 2611 and the second sub-mask pattern 2621 are flush with a top surface of the first isolation structure 220 .

[0034] In some embodiments, this step includes: forming a mask material layer, the mask material layer covering the side walls and top surface of the first isolation structure 220 and the top surface of the first conductive layer 251; etching the mask material layer, retaining the mask material layer located on the side walls of the first isolation structure 220, and using it as the first sub-mask pattern 2611 and the second sub-mask pattern 2621.

[0035] See also Figure 3D , a third convex portion 252 is formed in the fourth trench 231, and the third convex portion 252 and the first conductive layer 251 constitute an initial conductive material layer 253. The third convex portion 252 is a conductive material, including but not limited to polysilicon. In some embodiments, in the third direction D3, the top surface of the third convex portion 252 is lower than the top surfaces of the first sub-mask pattern 2611 and the second sub-mask pattern 2621.

[0036] In some embodiments, the step includes: filling the conductive material layer, the conductive material layer fills the fourth groove 231 and covers the top surface of the first isolation structure 220, the first sub-mask pattern 2611 and the second sub-mask pattern 2621; etching the conductive material layer, retaining a portion of the conductive material layer located in the fourth groove 231, and using it as the third protrusion 252.

[0037] See also Figure 3E , among which Figure 3E, (a) is a top view, (b) is a cross-sectional view along line A-A1 in (a), a third sub-mask pattern 2612 and a fourth sub-mask pattern 2622 are formed on the third convex portion 252, and a second groove 232 is provided between the third sub-mask pattern 2612 and the fourth sub-mask pattern 2622. In this step, the third sub-mask pattern 2612 and the third sub-mask pattern 2612 cover a portion of the surface of the third convex portion 252, and the second groove 232 exposes a portion of the surface of the third convex portion 252.

[0038] See also Figure 3F , among which Figure 3F , (a) is a top view, (b) is a cross-sectional view along line A-A1 in (a), and a portion of the third convex portion 252 is removed along the second groove 232 to form the third groove 233, the first convex portion 254 and the second convex portion 255. In this step, the third convex portion 252 is etched with the first sub-mask pattern 2611, the first sub-mask pattern 2611, the third sub-mask pattern 2612, and the fourth sub-mask pattern 2622 as shielding, and the portion of the third convex portion 252 exposed to the second groove 232 is removed, and a portion of the top surface of the first conductive layer 251 is exposed, and the portion of the third convex portion 252 that is not removed constitutes the first convex portion 254 and the second convex portion 255.

[0039] See also Figure 3G A fifth sub-mask pattern 2613 and a sixth sub-mask pattern 2623 are formed on the sidewalls of the third trench 233. The first sub-mask pattern 2611, the third sub-mask pattern 2612 and the fifth sub-mask pattern 2613 are sequentially connected to form a first mask pattern 261. The second sub-mask pattern 2621, the fourth sub-mask pattern 2622 and the sixth sub-mask pattern 2623 are sequentially connected to form a second mask pattern 262. A first trench 260 is formed between the fifth sub-mask pattern 2613 and the sixth sub-mask pattern 2623.

[0040] In some embodiments, the step includes: forming a mask material layer, the mask material layer covering the side walls of the third trench 233, the first isolation structure 220, the first sub-mask pattern 2611, the second sub-mask pattern 2621, the third sub-mask pattern 2612, and the top surface of the fourth sub-mask pattern 2622; etching the mask material layer, retaining the mask material layer located on the side walls of the third trench 233, and using it as the fifth sub-mask pattern 2613 and the sixth sub-mask pattern 2623.

[0041] See also Figure 2 and Figure 3H , among which Figure 3HIn FIG. 2 , (a) is a top view, and (b) is a cross-sectional view along line A-A1 in FIG. 2 , step S22, removing a portion of the initial conductive layer 250 along the first trench 260 to form a first isolation trench 270. In this step, the initial conductive layer 250 is etched with the first mask pattern 261 and the second mask pattern 262 as shielding to form the first isolation trench 270.

[0042] If there is an air gap 251A in the initial conductive layer 250, in this step, as the initial conductive layer 250 is removed, the air gap 251A located in the area of ​​the initial conductive layer 250 is also removed. The first isolation groove 270 penetrates the initial conductive layer 250 and divides the initial conductive layer 250 into two independent parts located on both sides of the first isolation groove 270. The two parts are respectively used as the final conductive structure, and there is no air gap inside. The top surface of the conductive structure can be a plane or have a convex portion.

[0043] See also Figure 2 and Fig. 3I , among which Fig. 3I In FIG. 2 , (a) is a top view, and (b) is a cross-sectional view along line A-A1 in FIG. 2 . In step S23, an isolation material is filled in the first isolation trench 270 to form a second isolation structure 280. In some embodiments, the material of the second isolation structure 280 is the same as that of the first isolation structure 220 to improve the compatibility of the semiconductor structure; in other embodiments, the material of the second isolation structure 280 may be different from that of the first isolation structure 220. The material of the second isolation structure 280 includes, but is not limited to, nitride, such as silicon nitride.

[0044] The second isolation structure 280 extends along the first direction D1 and is intersected with the bit line structure 210 . The intersecting arrangement includes the second isolation structure 280 straddling the bit line structure 210 , or the second isolation structure 280 being segmented and disposed between the bit line structures 210 .

[0045] In some embodiments, the projection of the second isolation structure 280 on the substrate 200 at least partially overlaps with the projection of the second word line 241 on the substrate 200. In this embodiment, the projection of the second isolation structure 280 on the substrate 200 overlaps with the projection of the second word line 241 on the substrate 200, and the projection area of ​​the second isolation structure 280 on the substrate 200 is larger than the projection area of ​​the second word line 241 on the substrate 200.

[0046] In some embodiments, the size of the first isolation structure 220 is smaller than the size of the second isolation structure 280, so as to remove the air gap 251A to the greatest extent. The size of the first isolation structure 220 refers to the width of the first isolation structure 220 along the second direction D2, and the size of the second isolation structure 280 refers to the width of the second isolation structure 280 along the second direction D2.

[0047] The second isolation structure 280 separates the first contact hole 230 into two target contact holes, namely the first target contact hole 2301 and the second target contact hole 2302. A first isolation structure 220A, a second isolation structure 280 and a bit line structure 210A and a bit line structure 210B form the first target contact hole 2301, and another first isolation structure 220B, a second isolation structure 280 and a bit line structure 210A and a bit line structure 210B form the second target contact hole 2302.

[0048] The preparation method provided in the embodiment of the present disclosure can utilize the first isolation groove 270 to form the second isolation structure 280, that is, the second isolation structure 280 and the target contact hole located between the first isolation structure 220 and the second isolation structure 280 can be formed by a self-alignment method, which greatly reduces the process difficulty of the target contact hole.

[0049] After forming the second isolation structure 280, the preparation method further includes:

[0050] See also Figure 3J , among which Figure 3J In FIG. 2 , (a) is a top view, and (b) is a cross-sectional view along line A-A1 in FIG. (a), the mask pattern is removed to expose the remaining initial conductive layer 250. After removing the mask pattern and before forming the conductive contact material 290, the first isolation structure 220, the second isolation structure 280, and the initial conductive layer 250 are thinned to expose the bit line structure 210. After thinning, the initial conductive layer 250 located in the first target contact hole 2301 serves as the first conductive structure 256, and the initial conductive layer 250 located in the second target contact hole 2302 serves as the second conductive structure 257.

[0051] The top of the initial conductive layer 250 has a first convex portion 254 and a second convex portion 255 disposed in the first contact hole 230. Specifically, the first convex portion 254 is disposed between the second isolation structure 280 and a first isolation structure 220A, that is, the first convex portion 254 is located in the first target contact hole 2301, and the first convex portion 254 is located at the central axis position between the first isolation structure 220A and the second isolation structure 280; the second convex portion 255 is disposed between the second isolation structure 280 and another first isolation structure 220B, that is, the second convex portion 255 is located in the second target contact hole 2302, and the second convex portion 255 is located at the central axis position between another first isolation structure 220B and the second isolation structure 280.

[0052] In some embodiments, after this step, in the third direction D3 , top surfaces of the first isolation structure 220 and the second isolation structure 280 are flush with the top surface of the bit line structure 210 , and top surfaces of the first protrusion 254 and the second protrusion 255 are lower than the top surface of the bit line structure 210 .

[0053] See also Figure 3K , among which Figure 3K In FIG. 1 , (a) is a top view, and (b) is a cross-sectional view along line A-A1 in FIG. 1 , forming a conductive contact material 290, wherein Figure 3K The conductive contact material 290 is not shown in FIG. (a). The conductive contact material 290 is in contact with the initial conductive layer 250, and the conductive contact material 290 also covers the first convex portion 254 and the second convex portion 255, thereby increasing the contact area between the contact structure and the initial conductive layer 250, reducing the contact resistance, and improving the read and write speed of the semiconductor structure. Specifically, in this embodiment, the conductive contact material 290 is in contact with the first conductive structure 256 and the second conductive structure 257, and the conductive contact material 290 is used to form a conductive contact structure, which is used to electrically connect the conductive structure and the capacitor in a one-to-one correspondence.

[0054] In the above embodiments, a first protrusion 254 or a second protrusion 255 is formed between the first isolation structure and the second isolation structure 280, while in other embodiments, two protrusions, namely a first protrusion 4541 and a third protrusion 4542, are formed between a first isolation structure 420A and the second isolation structure 480, and two protrusions, namely a second protrusion 4551 and a fourth protrusion 4552, are formed between another first isolation structure 420B and the second isolation structure 480.

[0055] The mask pattern includes a first mask pattern 461 and a second mask pattern 462 disposed on opposite sidewalls of two adjacent first isolation structures 420A and 420B, and a first trench 460 is formed between the first mask pattern 461 and the second mask pattern 462. The first trench 460 exposes the top surface of the initial conductive layer 450. As an example, another embodiment of the present disclosure provides a method for forming an initial conductive layer 450 in a first contact hole and forming a mask pattern on the initial conductive layer 450.

[0056] Figure 4A to Figure 4I Schematic diagram of a semiconductor structure formed by the main steps of a preparation method provided by another embodiment of the present disclosure, the preparation method comprising:

[0057] See also Figure 4C An initial conductive material layer 453 is formed in the first contact hole, and the top of the initial conductive material layer 453 has a first protruding branch 4541 and a second protruding branch 4551 arranged on the side wall of the first isolation structure, a first branch mask pattern 4611 is provided on the first protruding branch 4541, and a second branch mask pattern 4621 is provided on the second protruding branch 4551, and the top surfaces of the first protruding branch 4541 and the second protruding branch 4551 are lower than the top surface of the first isolation structure.

[0058] Specifically, in some embodiments, forming the initial conductive material layer 453 in the first contact hole includes:

[0059] See also Figure 4A , its Figure 3A Based on the semiconductor structure shown in (b), a first conductive layer 451 is formed in the first contact hole, and the top surface of the first conductive layer 451 is lower than the top surface of the first isolation structure. For example, the adjacent first isolation structure 420A and the first isolation structure 420B and the two adjacent bit line structures surround the first contact hole 430A, and the first conductive layer 451 is formed in the first contact hole 430A, and the top surface of the first conductive layer 451 is lower than the top surface of the first isolation structure.

[0060] In this step, the first conductive layer 451 extends along the first direction D1, and also covers the surface of the bit line structure, and has an air gap 451A in the first conductive layer 451. The material of the first conductive layer 451 includes, but is not limited to, polysilicon (poly).

[0061] See also Figure 4B, a first branch mask pattern 4611 and a second branch mask pattern 4621 located on the side wall of the first isolation structure are formed on the surface of the first conductive layer 451, and a second groove 432 is provided between the first branch mask pattern 4611 and the second branch mask pattern 4621. For example, in this step, a first branch mask pattern 4611 is provided on a side wall of the first isolation structure 420A, and a second branch mask pattern 4621 is provided on a side wall of another first isolation structure 420B adjacent to the first isolation structure 420A and facing the first isolation structure 420A, and the first branch mask pattern 4611 and the second branch mask pattern 4621 both extend along the first direction D1, and the second groove 432 exposes a portion of the top surface of the first conductive layer 451. In some embodiments, in the third direction D3, the top surfaces of the first branch mask pattern 4611 and the second branch mask pattern 4621 are flush with the top surface of the first isolation structure.

[0062] In some embodiments, this step includes: forming a mask material layer, the mask material layer covering the side walls and top surface of the first isolation structure and the top surface of the first conductive layer 451; etching the mask material layer, retaining the mask material layer located on the side walls of the first isolation structure, and using it as the first branch mask pattern 4611 and the second branch mask pattern 4621.

[0063] See also Figure 4C , a portion of the first conductive layer 451 is removed along the second groove to form a first convex portion 4541 and a second convex portion 4551. In this step, the region of the first conductive layer 451 exposed to the second groove 432 is partially removed. The first convex portion 4541 is disposed on the sidewall of the first isolation structure 420A, and the second convex portion 4551 is disposed on the sidewall of the other first isolation structure 420B.

[0064] At this point, an initial conductive material layer 453 is formed in the first contact hole 430A.

[0065] See also Figure 4D A third branch mask pattern 4612 and a fourth branch mask pattern 4622 are formed on the initial conductive material layer 453, and a first groove 433 is provided between the third branch mask pattern 4612 and the fourth branch mask pattern 4622. The third branch mask pattern 4612 covers the sidewalls of the first branch mask pattern 4611 and the first convex branch portion 4541, and the fourth branch mask pattern 4622 covers the sidewalls of the second branch mask pattern 4621 and the second convex branch portion 4551, and the first groove 433 exposes a portion of the top surface of the initial conductive material layer 453.

[0066] In some embodiments, the step includes: forming a mask material layer, the mask material layer covering the top surface of the first isolation structure, the top surface of the initial conductive material layer 453, the side walls of the first branch mask pattern 4611 and the first convex branch 4541, and the side walls of the second branch mask pattern 4621 and the second convex branch 4551; etching the mask material layer, retaining the mask material layer located on the side walls of the first branch mask pattern 4611 and the first convex branch 4541, the second branch mask pattern 4621 and the side walls of the second convex branch 4551, and using it as the third branch mask pattern 4612 and the fourth branch mask pattern 4622.

[0067] See also Figure 4E A first conductive material layer 452 is formed in the first groove 433. In the third direction D3, the top surface of the first conductive material layer 452 is lower than the top surface of the first isolation structure. In this embodiment, the top surface of the first conductive material layer 452 is also lower than the top surfaces of the third branch mask pattern 4612 and the fourth branch mask pattern 4622.

[0068] In some embodiments, the step includes: forming a conductive material base layer, the conductive material base layer fills the first groove 433 and covers the top surfaces of the first isolation structure, the first branch mask pattern 4611, the second branch mask pattern 4621, the third branch mask pattern 4612, and the fourth branch mask pattern 4622; etching the conductive material base layer to a set height, and the remaining conductive material base layer serves as the first conductive material layer 452.

[0069] See also Figure 4F , a fifth branch mask pattern 4613 and a sixth branch mask pattern 4623 are formed on the top surface of the first conductive material layer 452, the first branch mask pattern 4611, the third branch mask pattern 4612 and the fifth branch mask pattern 4613 are sequentially connected and constitute the first mask pattern 461, the second branch mask pattern 4621, the fourth branch mask pattern 4622 and the sixth branch mask pattern 4623 are sequentially connected and constitute the second mask pattern 462, and the first trench 460 is formed between the fifth branch mask pattern 4613 and the sixth branch mask pattern 4623. The fifth branch mask pattern 4613 covers a portion of the sidewall of the third branch mask pattern 4612 and a portion of the top surface of the first conductive material layer 452, and the sixth branch mask pattern 4623 covers a portion of the sidewall of the fourth branch mask pattern 4622 and a portion of the top surface of the first conductive material layer 452.

[0070] See also Figure 4G, a portion of the initial conductive layer 450 is removed along the first trench 460 to form a first isolation trench 470. In this step, the initial conductive layer 450 is etched with the first mask pattern 461 and the second mask pattern 462 as shielding to form the first isolation trench 470. If there is an air gap in the initial conductive layer 450, in this step, as the initial conductive layer 450 is removed, the air gap located in the initial conductive layer 450 region is also removed.

[0071] In some embodiments, in this step, a portion of the first conductive material layer 452 is removed along the first groove 460 to form a third convex branch 4542 and a fourth convex branch 4552, and a first contact groove 4543 is formed between the first convex branch 4541 and the third convex branch 4542 (see Fig. 4I ), a second contact groove 4553 is formed between the second protruding branch 4551 and the fourth protruding branch 4552 (see Fig. 4I In some embodiments, the first conductive material layer 452 covered by the fifth mask pattern 4613 serves as the third convex branch 4542, and the first conductive material layer 452 covered by the sixth mask pattern 4623 serves as the fourth convex branch 4552. The third convex branch 4542, the fourth convex branch 4552 and the initial conductive material layer 453 constitute the initial conductive layer 450.

[0072] See also Figure 4H , an isolation material is filled in the first isolation trench 470 to form a second isolation structure 480. The material of the second isolation structure 480 includes but is not limited to nitride, such as silicon nitride. The second isolation structure 480 divides the first contact hole 430 into a first target contact hole 4301 and a second target contact hole 4302.

[0073] See also Fig. 4I , remove the mask pattern to expose the remaining initial conductive layer 450, and form a conductive contact material 290, the conductive contact material 290 is in contact with the initial conductive layer 450, and the conductive contact material 290 is also filled in the first contact groove 4543 between the first convex branch 4541 and the third convex branch 4542, and the second contact groove 4553 between the second convex branch 4551 and the fourth convex branch 4552, thereby increasing the contact area between the conductive contact material 290 and the initial conductive layer 450, reducing the contact resistance between the conductive contact material 290 and the initial conductive layer 450, and improving the read and write speed of the semiconductor structure.

[0074] The initial conductive layer 450 located in the first target contact hole 4301 serves as the first conductive structure 456 , and the initial conductive layer 450 located in the second target contact hole 4302 serves as the second conductive structure 457 .

[0075] After removing the mask pattern and before forming the conductive contact material 290 , the preparation method further includes thinning the first isolation structure, the second isolation structure 480 and the initial conductive layer 450 until the bit line structure is exposed.

[0076] The preparation method provided by the embodiment of the present disclosure can remove the air gap 451A in the initial conductive layer 450 and improve the performance of the semiconductor structure.

[0077] The present disclosure also provides a semiconductor structure prepared by the above-mentioned preparation method. Figure 3A to Figure 3K The semiconductor structure includes: a substrate 200, a bit line structure 210, a first isolation structure 220, a second isolation structure 280 and a conductive structure.

[0078] The bit line structure 210 is disposed on the substrate 200. In some embodiments, a plurality of bit line structures 210 are arranged at intervals along a first direction D1 and each bit line structure 210 extends along a second direction D2. The first direction D1 and the second direction D2 are directions parallel to the plane where the substrate 200 is located, and the first direction D1 is perpendicular to the second direction D2. In this embodiment, the first direction D1 is the X direction in the Cartesian coordinate system, and the second direction D2 is the Y direction in the Cartesian coordinate system.

[0079] The first isolation structure 220 is disposed on the substrate 200. In some embodiments, a plurality of first isolation structures 220 are arranged at intervals along the second direction D2 and each first isolation structure 220 extends along the first direction D1.

[0080] The first isolation structure 220 is arranged crosswise with the bit line structure 210. The first isolation structure 220 is arranged crosswise with the bit line structure 210, including the first isolation structure 220 straddling the bit line structure 210, or the first isolation structure 220 is arranged in sections between the bit line structures 210. In this embodiment, the first isolation structure 220 straddling the bit line structure 210 is taken as an example for description.

[0081] Two adjacent bit line structures 210 and two adjacent first isolation structures 220 form a first contact hole 230. For example, adjacent bit line structures 210A and 210B, and adjacent first isolation structures 220A and 220B form a first contact hole 230A.

[0082] The second isolation structure 280 is disposed in the first contact hole 230 and separates the first contact hole 230 into a target contact hole. For example, the second isolation structure 280 separates the first contact hole 230 into two target contact holes, namely, a first target contact hole 2301 and a second target contact hole 2302. A first isolation structure 220A, a second isolation structure 280 and a bit line structure 210A surround the first target contact hole 2301, and another first isolation structure 220B, a second isolation structure 280 and a bit line structure 210B surround the second target contact hole 2302.

[0083] The conductive structure is disposed in the target contact hole, and the top surface of the conductive structure is lower than the top surfaces of the first isolation structure 220, the second isolation structure 280, and the bit line structure 210. For example, the conductive structure includes a first conductive structure 256 and a second conductive structure 257, the first conductive structure 256 is located in the first target contact hole 2301, the second conductive structure 257 is located in the second target contact hole 2302, and the top surfaces of the first conductive structure 256 and the second conductive structure 257 are lower than the top surfaces of the first isolation structure 220, the second isolation structure 280, and the bit line structure 210.

[0084] In some embodiments, the top of the conductive structure has a convex portion disposed between the second isolation structure 280 and the first isolation structure 220, and the top surface of the convex portion is lower than the top surfaces of the first isolation structure 220, the second isolation structure 280, and the bit line structure 210. For example, the top of the first conductive structure 256 has a first convex portion 254 disposed between the second isolation structure 280 and the first isolation structure 220, and the top of the second conductive structure 257 has a second convex portion 255 disposed between the second isolation structure 280 and the first isolation structure 220, and the top surfaces of the first convex portion 254 and the second convex portion 255 are both lower than the top surfaces of the first isolation structure 220, the second isolation structure 280, and the bit line structure 210.

[0085] In some embodiments, the protrusion is located at the mid-axis position between the first isolation structure 220 and the second isolation structure 280. For example, the first protrusion 254 is located at the mid-axis position between the first isolation structure 220A and the second isolation structure 280, and the second protrusion 255 is located at the mid-axis position between another first isolation structure 220B and the second isolation structure 280.

[0086] In some embodiments, the semiconductor structure further includes a conductive contact material 290 covering the top of the conductive structure. For example, the conductive contact material 290 covers the top of the first conductive structure 256 and the second conductive structure 257, and the conductive contact material 290 is also located between the first convex portion 254 and the first isolation structure 220, between the first convex portion 254 and the second isolation structure 280, between the second convex portion 255 and the first isolation structure 220, and between the second convex portion 255 and the second isolation structure 280, thereby increasing the contact area between the conductive contact material 290 and the first conductive structure 256 and the second conductive structure 257, reducing the contact resistance between the two, and improving the read and write speed of the semiconductor structure.

[0087] In some embodiments, the substrate 200 includes alternately arranged first word lines 240 and second word lines 241; the projection of the first isolation structure 220 in the direction of the substrate 200 at least partially overlaps with the projection of the first word line 240 on the substrate 200, and the projection of the second isolation structure 280 on the substrate 200 at least partially overlaps with the projection of the second word line 241 on the substrate 200. In this embodiment, the projection of the first isolation structure 220 in the direction of the substrate 200 completely overlaps with the projection of the first word line 240 on the substrate 200, the projection of the second isolation structure 280 on the substrate 200 overlaps with the projection of the second word line 241 on the substrate 200, and the projection area of ​​the second isolation structure 280 on the substrate 200 is larger than the projection area of ​​the second word line 241 on the substrate 200.

[0088] In some embodiments, the size of the first isolation structure 220 is smaller than the size of the second isolation structure 280, wherein the size of the first isolation structure 220 refers to the width of the first isolation structure 220 along the second direction D2, and the size of the second isolation structure 280 refers to the width of the second isolation structure 280 along the second direction D2.

[0089] In the semiconductor structure provided by the embodiment of the present disclosure, there is no air gap in the conductive structure, which greatly improves the performance of the semiconductor structure.

[0090] In the above embodiment, the conductive structure includes a protrusion located at the central axis position between the first isolation structure 220 and the second isolation structure 280, while in another embodiment, the conductive structure includes two protrusions, and the two protrusions are respectively located on the opposite side walls of the first isolation structure and the second isolation structure 480, and a contact groove is formed between the two protrusions, and the conductive contact material 490 is also located in the contact groove.

[0091] For example, see Figure 4A to Figure 4IThe first conductive structure 456 includes a first protrusion 4541 and a third protrusion 4542 located on the side walls opposite to the first isolation structure 420A and the second isolation structure 480, a first contact groove 4543 is provided between the first protrusion 4541 and the third protrusion 4542, and the conductive contact material 490 is also located in the first contact groove 4543; the second conductive structure 457 includes a second protrusion 4551 and a fourth protrusion 4552 located on the side walls opposite to the first isolation structure 420B and the second isolation structure 480, a second contact groove 4553 is provided between the second protrusion 4551 and the fourth protrusion 4552, and the conductive contact material 490 is also located in the second contact groove 4553.

[0092] In some embodiments, the first contact groove 4543 is located at the mid-axis position between a first isolation structure 420A and a second isolation structure 480 ; the second contact groove 4553 is located at the mid-axis position between another first isolation structure 420B and the second isolation structure 480 .

[0093] In the semiconductor structure provided in this embodiment, there are no air gaps in the first conductive structure 456 and the second conductive structure 457, which improves the performance of the semiconductor structure, and the conductive contact material 490 is also located in the first contact groove 4543 and the second contact groove 4553, which increases the contact area between the contact structure and the first conductive structure 456 and the second conductive structure 457, reduces the contact resistance, and improves the reading and writing speed of the semiconductor structure.

[0094] The above are only preferred embodiments of the present disclosure. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present disclosure. These improvements and modifications should also be regarded as the protection scope of the present disclosure.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, on which a bit line structure and a first isolation structure are arranged, wherein the first isolation structure is arranged crosswise with the bit line structure and a top surface of the first isolation structure is higher than a top surface of the bit line structure, and two adjacent bit line structures and two adjacent first isolation structures form a first contact hole; Forming an initial conductive layer in the first contact hole, and forming a mask pattern on the initial conductive layer, wherein a top surface of the initial conductive layer is lower than a top surface of the first isolation structure, the mask pattern is located on a side wall of the first isolation structure, and a first trench is provided between the mask patterns on opposite side walls of adjacent first isolation structures; removing a portion of the initial conductive layer along the first trench to form a first isolation trench; The first isolation trench is filled with an isolation material to form a second isolation structure.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: After forming the second isolation structure, the method further includes: removing the mask pattern to expose the remaining initial conductive layer; forming a conductive contact material, wherein the conductive contact material is in contact with the initial conductive layer; The top of the initial conductive layer has a first protrusion and a second protrusion arranged in the first contact hole, the first protrusion is arranged between the second isolation structure and one of the first isolation structures, the second protrusion is arranged between the second isolation structure and another of the first isolation structures, and the conductive contact material also covers the first protrusion and the second protrusion.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The mask pattern includes a first mask pattern and a second mask pattern arranged on opposite side walls of two adjacent first isolation structures; Forming an initial conductive layer in the first contact hole, and forming a mask pattern on the initial conductive layer, comprising: An initial conductive material layer is formed in the first contact hole, wherein the initial conductive material layer has a third convex portion on the top, a first sub-mask pattern is provided between the third convex portion and one of the first isolation structures, and a second sub-mask pattern is provided between the third convex portion and another of the first isolation structures, and a top surface of the third convex portion is lower than top surfaces of the first isolation structure, the first sub-mask pattern, and the second sub-mask pattern; forming a third sub-mask pattern and a fourth sub-mask pattern on the third convex portion, wherein a second groove is provided between the third sub-mask pattern and the fourth sub-mask pattern; removing a portion of the third convex portion along the second groove to form the third groove, the first convex portion and the second convex portion; A fifth sub-mask pattern and a sixth sub-mask pattern are formed on the sidewalls of the third trench, the first sub-mask pattern, the third sub-mask pattern and the fifth sub-mask pattern are sequentially connected and constitute the first mask pattern, and the second sub-mask pattern, the fourth sub-mask pattern and the sixth sub-mask pattern are sequentially connected and constitute the second mask pattern.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that: Forming an initial conductive material layer in the first contact hole, comprising: forming a first conductive layer in the first contact hole, wherein a top surface of the first conductive layer is lower than a top surface of the first isolation structure; The first sub-mask pattern and the second sub-mask pattern are formed on the top surface of the first conductive layer and are arranged on the side walls of the first isolation structure, and a fourth groove is provided between the first sub-mask pattern and the second sub-mask pattern; a third protrusion is formed in the fourth groove, and the third protrusion and the first conductive layer constitute the initial conductive material layer.

5. The method for preparing a semiconductor structure according to claim 2, characterized in that: The mask pattern includes a first mask pattern and a second mask pattern arranged on opposite side walls of two adjacent first isolation structures; Forming an initial conductive layer in the first contact hole, and forming a mask pattern on the initial conductive layer, comprising: forming an initial conductive material layer in the first contact hole, wherein the top of the initial conductive material layer has a first convex branch and a second convex branch arranged on the side wall of the first isolation structure, a first branch mask pattern is provided on the first convex branch, and a second branch mask pattern is provided on the second convex branch, and the top surfaces of the first convex branch and the second convex branch are lower than the top surface of the first isolation structure; forming a third branch mask pattern and a fourth branch mask pattern on the initial conductive material layer, wherein a first groove is formed between the third branch mask pattern and the fourth branch mask pattern; forming a first conductive material layer in the first groove, wherein a top surface of the first conductive material layer is lower than a top surface of the first isolation structure; A fifth branch mask pattern and a sixth branch mask pattern are formed on the top surface of the first conductive material layer, the first branch mask pattern, the third branch mask pattern and the fifth branch mask pattern are connected in sequence and constitute the first mask pattern, the second branch mask pattern, the fourth branch mask pattern and the sixth branch mask pattern are connected in sequence and constitute the second mask pattern.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that: Removing at least a portion of the initial conductive layer along the first trench comprises: A portion of the first conductive material layer is removed along the first groove to form a third convex portion and a fourth convex portion, wherein the first convex portion and the third convex portion constitute the first convex portion, and the second convex portion and the fourth convex portion constitute the second convex portion.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that: Forming an initial conductive material layer in the first contact hole, comprising: forming a first conductive layer in the first contact hole, wherein a top surface of the first conductive layer is lower than a top surface of the first isolation structure; A first branch mask pattern and a second branch mask pattern are formed on the surface of the first conductive layer and are located on the sidewalls of the first isolation structure, wherein a second groove is provided between the first branch mask pattern and the second branch mask pattern; A portion of the first conductive layer is removed along the second groove to form the first protruding portion and the second protruding portion.

8. The method for preparing a semiconductor structure according to any one of claims 2 to 7, characterized in that: A plurality of the bit line structures are arranged at intervals along a first direction and each of the bit line structures extends along a second direction, a plurality of the first isolation structures are arranged at intervals along the second direction and each of the first isolation structures extends along the first direction, the first direction and the second direction are parallel to the plane where the substrate is located, and the first direction is perpendicular to the second direction; In the step of forming the initial conductive layer in the first contact hole, the initial conductive layer also covers the surface of the bit line structure; Before the step of forming the conductive contact material, the first isolation structure, the second isolation structure and the initial conductive layer are thinned until the bit line structure is exposed.

9. A semiconductor structure, characterized in that: include: substrate; A bit line structure is disposed on the substrate; A first isolation structure is disposed on the substrate, wherein the first isolation structure and the bit line structure are intersected, and two adjacent bit line structures and two adjacent first isolation structures form a first contact hole; a second isolation structure, disposed in the first contact hole and separating the first contact hole into target contact holes; A conductive structure is disposed in the target contact hole, wherein a top surface of the conductive structure is lower than top surfaces of the first isolation structure, the second isolation structure and the bit line structure.

10. The semiconductor structure according to claim 9, characterized in that: The top of the conductive structure has a convex portion disposed between the second isolation structure and the first isolation structure, and the top surface of the convex portion is lower than the top surfaces of the first isolation structure, the second isolation structure and the bit line structure; The semiconductor structure further comprises: A conductive contact material covers the top of the conductive structure.

11. The semiconductor structure according to claim 10, characterized in that: The convex portion is located at a mid-axis position between the first isolation structure and the second isolation structure, and the conductive contact material is also located between the convex portion and the first isolation structure and between the convex portion and the second isolation structure.

12. The semiconductor structure according to claim 10, characterized in that: The conductive structure includes two protrusions, and the two protrusions are respectively located on opposite side walls of the first isolation structure and the second isolation structure. A contact groove is formed between the two protrusions, and the conductive contact material is also located in the contact groove.

13. The semiconductor structure according to any one of claims 9 to 12, characterized in that: A plurality of the bit line structures are arranged at intervals along a first direction and each of the bit line structures extends along a second direction, a plurality of the first isolation structures are arranged at intervals along the second direction and each of the first isolation structures extends along the first direction, the first direction and the second direction are directions parallel to the plane where the substrate is located, and the first direction is perpendicular to the second direction.

14. The semiconductor structure according to any one of claims 9 to 12, characterized in that: The substrate includes first word lines and second word lines arranged alternately; a projection of the first isolation structure on the substrate at least partially overlaps with a projection of the first word line on the substrate, and a projection of the second isolation structure on the substrate at least partially overlaps with a projection of the second word line on the substrate.

15. The semiconductor structure according to any one of claims 9 to 12, characterized in that: The size of the first isolation structure is smaller than that of the second isolation structure.

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