Memory structure and forming method thereof

Abstract

The invention discloses a memory structure and a forming method thereof. The method comprises the steps of providing a substrate; forming a floating gate precursor layer on the substrate, wherein the material of the floating gate precursor layer is an MAX material; performing phase change processing on the floating gate precursor layer to form an initial floating gate, wherein the initial floating gate is made of an MXene material; and performing oxidation treatment on the initial floating gate to form a floating gate and a barrier layer surrounding the floating gate. Oxidation is not prone to occurring among the multiple layers of MXene materials, the lattice mismatch problem is small, reliability is high, the MXene materials serve as floating gate materials, the performance of the memory structure is improved, in addition, in the process of oxidation treatment on the initial floating gate, the outer layer of initial floating gate MXene material is oxidized to form metal oxide, and the performance of the memory structure is improved. And the metal oxide is used as a barrier layer to prevent metal ions of the inner floating gate from overflowing, so that the performance of the memory structure is further optimized.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a memory structure and a forming method thereof. Background Art

[0002] Microcontroller Unit (MCU), as a chip-level computer, is widely used in new energy vehicles, communication modules, smart homes and other fields. High-performance microcontrollers are inseparable from the support of high-performance embedded flash (EFlash) cores. As the mainstream structure of EFlash memory, the floating gate structure continues to shrink with the evolution of semiconductor processes.

[0003] However, the current floating gate structure still has many problems. Summary of the invention

[0004] The problem solved by the present invention is how to improve the floating gate reliability to optimize the performance of the memory structure.

[0005] To solve the above problems, the present invention provides a method for forming a memory structure, comprising: providing a substrate; forming a floating gate precursor layer on the substrate, wherein the material of the floating gate precursor layer is a MAX material; performing a phase change treatment on the floating gate precursor layer to form an initial floating gate, wherein the initial floating gate is a MXene material; and performing an oxidation treatment on the initial floating gate to form a floating gate and a barrier layer surrounding the floating gate.

[0006] Optionally, the molecular formula of the MAX material is M n+1 AX n , where M represents a transition metal, A represents a main group element, and X represents carbon or nitrogen.

[0007] Optionally, the molecular formula of the MXene material is M n+1 X n T x , wherein M represents a transition metal, X represents a carbon or nitrogen element, and T represents a capping group; the capping group includes: -F, -O and -OH.

[0008] Optionally, the molecular formula of the floating gate material is M n+1 X n , where M represents a transition metal and X represents carbon or nitrogen.

[0009] Optionally, the material of the barrier layer includes titanium oxide.

[0010] Optionally, the step of performing a phase change process on the floating gate precursor layer to form an initial floating gate includes:

[0011] Etching the floating gate precursor layer to form a floating gate precursor;

[0012] The floating gate precursor is subjected to a phase change process to form the initial floating gate.

[0013] Optionally, the step of performing a phase change process on the floating gate precursor layer to form an initial floating gate includes:

[0014] forming a floating gate precursor layer on the substrate;

[0015] Performing a phase change treatment on the floating gate precursor layer to form a transition floating gate layer, wherein the transition floating gate layer is made of MXene material;

[0016] The transition floating gate layer is etched to form the initial floating gate.

[0017] Optionally, in the step of forming a floating gate precursor layer on the substrate, the floating gate precursor layer is formed by magnetron sputtering.

[0018] Optionally, in the step of performing an oxidation treatment on the initial floating gate to form a floating gate and a barrier layer surrounding the floating gate, a process gas for the oxidation treatment includes at least one of nitrogen and air.

[0019] Optionally, in the step of performing oxidation treatment on the initial floating gate, the temperature range of the oxidation treatment is 50° C. to 200° C.; the time range of the oxidation treatment is 100 min to 300 min.

[0020] Optionally, in the step of oxidizing the initial floating gate, the thickness of the barrier layer is within the range.

[0021] Optionally, in the step of performing phase change treatment on the floating gate precursor layer, the phase change treatment method includes: wet etching.

[0022] Optionally, the etching solution of the wet etching includes hydrogen chloride and lithium fluoride; the etching temperature of the wet etching is 30° C. to 50° C.; and the etching time of the wet etching is 100 h to 150 h.

[0023] Optionally, the method further includes: forming a tunneling layer on the surface of the barrier layer.

[0024] Optionally, in the step of forming a tunneling layer on the surface of the barrier layer, the material of the tunneling layer is silicon oxide.

[0025] Optionally, in the step of forming a tunneling layer on the surface of the barrier layer, the tunneling layer is formed by chemical vapor deposition.

[0026] Optionally, the thickness of the tunneling layer is within the range.

[0027] Optionally, source and drain regions are formed in the substrate; and select gates, erase gates and control gates are formed on the substrate.

[0028] Correspondingly, an embodiment of the present invention further provides a memory structure, wherein the memory structure is formed by any of the above-mentioned methods for forming a memory structure.

[0029] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0030] In the method for forming a memory structure of the technical solution of the present invention, the initial floating gate of the MXene material is oxidized to form a floating gate and a barrier layer surrounding the floating gate. The multilayer MXene material is not easily oxidized, has a small lattice mismatch problem, and has high reliability. As a floating gate material, the performance of the memory structure is improved. In addition, in the process of oxidizing the initial floating gate, the initial floating gate MXene material of the outer layer is oxidized to form a metal oxide. The metal oxide acts as a barrier layer to prevent the metal ions of the inner floating gate from overflowing, further optimizing the performance of the memory structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a process flow chart of a formation process of a memory structure according to an embodiment of the present invention;

[0032] Figures 2 to 7 It is a schematic cross-sectional structure diagram of each step of a formation process of a memory structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] As can be seen from the background technology, with the evolution of semiconductor manufacturing process, the floating gate structure continues to shrink, and the reliability of the floating gate decreases. The reasons for the problem are analyzed below:

[0034] As the mainstream structure of EFlash memory, the floating gate structure is continuously miniaturized with the evolution of semiconductor process. At nodes below 32nm, the traditional charge storage dielectric layer material will lead to reduced reliability of the floating gate structure and severe leakage current.

[0035] In order to solve the technical problem, the present invention provides a method for forming a memory structure, comprising: providing a substrate; forming a floating gate precursor layer on the substrate, wherein the material of the floating gate precursor layer is a MAX material; performing a phase change treatment on the floating gate precursor layer to form an initial floating gate, wherein the initial floating gate is a MXene material; performing an oxidation treatment on the initial floating gate to form a floating gate and a barrier layer surrounding the floating gate.

[0036] In the method for forming a memory structure of the technical solution of the present invention, the initial floating gate of the MXene material is oxidized to form a floating gate and a barrier layer surrounding the floating gate. The multilayer MXene material is not easily oxidized, has a small lattice mismatch problem, and has high reliability. As a floating gate material, the performance of the memory structure is improved. In addition, in the process of oxidizing the initial floating gate, the initial floating gate MXene material of the outer layer is oxidized to form a metal oxide. The metal oxide acts as a barrier layer to prevent the metal ions of the inner floating gate from overflowing, further optimizing the performance of the memory structure.

[0037] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0038] Figure 1 is a process flow chart of the formation process of the memory structure of an embodiment of the present invention, combined with reference to Figures 2 to 7 , Figures 2 to 7 It is a schematic cross-sectional structure diagram of each step of a formation process of a memory structure according to an embodiment of the present invention.

[0039] The forming process of the memory structure includes:

[0040] Step S10, providing a substrate 100;

[0041] Step S11, forming a dielectric layer 101 on the substrate 100;

[0042] Step S12, forming a floating gate precursor layer 102 on the substrate 100, wherein the material of the floating gate precursor layer 102 is a MAX material;

[0043] Step S13, performing a phase change treatment on the floating gate precursor layer 102 to form an initial floating gate 104, wherein the initial floating gate 104 is made of MXene material;

[0044] Step S14, performing oxidation treatment on the initial floating gate 104 to form a floating gate 105 and a barrier layer 106 surrounding the floating gate 105;

[0045] Step S15, forming a tunneling layer 107 on the surface of the barrier layer 106;

[0046] Step S16, forming source and drain regions in the substrate 100;

[0047] Step S17 , forming a select gate 110 , an erase gate 111 and a control gate 112 on the substrate 100 .

[0048] The following will describe in detail the steps of the memory structure formation process.

[0049] Please refer to Figure 2 , in step S10 , a substrate 100 is provided.

[0050] The material of the substrate 100 includes: silicon, silicon carbide, silicon germanium, silicon on insulator (SOI) or germanium on insulator (GOI).

[0051] The substrate 100 provides a structural basis for forming a floating gate precursor layer 102 .

[0052] Please continue to refer to Figure 2 In step S11 , a dielectric layer 101 is formed on the substrate 100 .

[0053] The material of the dielectric layer 101 includes silicon oxide. Specifically, in some embodiments of the present invention, in the step of forming the dielectric layer 101 on the substrate 100, the dielectric layer 101 is formed by thermal oxidation.

[0054] Please continue to refer to Figure 2 In step S12, a floating gate precursor layer 102 is formed on the substrate 100, and the material of the floating gate precursor layer 102 is a MAX material.

[0055] The molecular formula of the MAX material is M n+1 AX n , wherein M represents a transition metal, A represents a main group element, and X represents a carbon or nitrogen element. Specifically, in some embodiments of the present invention, the material of the floating gate precursor layer 102 is titanium aluminum carbide (Ti3AlC2). The floating gate precursor layer 102 of MAX material provides a structural basis for forming an initial floating gate 104 of MXene material. Specifically, in some embodiments of the present invention, in the step of forming the floating gate precursor layer 102 on the substrate 100, the floating gate precursor layer 102 is formed by magnetron sputtering.

[0056] Please refer to Figure 3 to Figure 4 In step S13, the floating gate precursor layer 102 is subjected to a phase change treatment to form an initial floating gate 104, and the initial floating gate 104 is made of MXene material.

[0057] In some embodiments of the present invention, the step of performing a phase change treatment on the floating gate precursor layer 102 to form an initial floating gate 104 includes: Figure 3 As shown, the floating gate precursor layer 102 is etched to form a floating gate precursor 103; Figure 4 As shown, the floating gate precursor 103 is subjected to a phase change process to form the initial floating gate 104 .

[0058] In the step of etching the floating gate precursor layer 102 to form the floating gate precursor 103 , the floating gate precursor layer 102 is patterned to form the floating gate precursor 103 . The floating gate precursors 103 are separated from each other to provide a structural basis for the subsequent formation of the floating gate 105 .

[0059] The phase change treatment transforms the MAX material into a MXene material. In the step of performing phase change treatment on the floating gate precursor 103, the phase change treatment method includes: wet etching. The etching solution of the wet etching includes hydrogen chloride and lithium fluoride; the etching temperature of the wet etching is 30°C to 50°C; and the etching time of the wet etching is 100h to 150h.

[0060] The molecular formula of the MXene material is M n+1 X n T x , wherein M represents a transition metal, X represents a carbon or nitrogen element, and T represents a capping group; the capping group includes: -F, -O and -OH.

[0061] In MAX materials, the bond energy of MX bonds is higher than that of MA bonds. For example, in titanium aluminum carbide (Ti3AlC2), the bond energy of titanium-carbon (Ti-C) bonds is higher than that of titanium-aluminum (Ti-Al). MXene is synthesized by selectively removing aluminum (Al) from titanium aluminum carbide (Ti3AlC2) through phase change treatment. The resulting MXene is a two-dimensional material with a graphene-like structure. MXene materials have large specific surface area, excellent conductivity, good self-lubricating properties, and rich surface groups. MXene materials are composed of alternating carbon layers and transition metal layers, which give MXene materials good conductivity and pseudocapacitance characteristics, overcoming the problems of reduced floating gate reliability and severe leakage current in the process of memory miniaturization.

[0062] It should be noted that, in some embodiments, in the process of performing phase change treatment on the floating gate precursor layer to form an initial floating gate, the floating gate precursor layer is first etched, and the etched floating gate precursor layer is phase-changed to form an initial floating gate of MXene material. However, this approach is only an example. In other embodiments, the floating gate precursor layer of MAX material may be first phase-changed to transform the MAX material into MXene material, and then the floating gate precursor layer after the phase change is etched to form the initial floating gate layer. For example, in some other embodiments of the present invention, the step of performing phase change treatment on the floating gate precursor layer to form an initial floating gate includes: forming a floating gate precursor layer on the substrate; performing phase change treatment on the floating gate precursor layer to form a transition floating gate layer, wherein the transition floating gate layer is a MXene material; and etching the transition floating gate layer to form the initial floating gate.

[0063] The transition floating gate layer after the phase change treatment is patterned to form an initial floating gate, and the initial floating gates are separated from each other to provide a structural basis for the subsequent formation of floating gates.

[0064] Please refer to Figure 5 In step S14 , the initial floating gate 104 is oxidized to form a floating gate 105 and a barrier layer 106 surrounding the floating gate 105 .

[0065] The molecular formula of the material of the floating gate 105 is M n+1 X n , where M represents a transition metal and X represents carbon or nitrogen. Specifically, if titanium aluminum carbide (Ti3AlC2) is used as the material of the floating gate precursor layer 102, the material of the floating gate 105 is a two-dimensional material composed of titanium and. The introduction of two-dimensional materials as floating gate materials overcomes the problems of reduced reliability and severe leakage current of memory structures during miniaturization, and promotes the miniaturization of memory structures.

[0066] In the step of performing an oxidation treatment on the initial floating gate 104 to form the floating gate 105 and the barrier layer 106 surrounding the floating gate 105 , the process gas for the oxidation treatment includes at least one of nitrogen and air.

[0067] Specifically, in some embodiments of the present invention, in the step of oxidizing the initial floating gate 104, the temperature range of the oxidation treatment is 50° C. to 200° C.; the time range of the oxidation treatment is 100 min to 300 min.

[0068] In the step of oxidizing the initial floating gate 104, the thickness of the barrier layer 106 is The thickness of the barrier layer 106 is positively correlated with the duration of the oxidation treatment, and the thickness of the barrier layer 106 can be adjusted according to actual production needs. The material of the barrier layer 106 includes titanium oxide. The function of the barrier layer 106 is to prevent the metal ions of the floating gate 105 from overflowing.

[0069] Please refer to Figure 6 In step S15 , a tunneling layer 107 is formed on the surface of the barrier layer 106 .

[0070] In the step of forming the tunneling layer 107 on the surface of the barrier layer 106 , the material of the tunneling layer 107 is silicon oxide. The material of the tunneling layer 107 is different from that of the barrier layer 106 .

[0071] In the step of forming the tunneling layer 107 on the surface of the barrier layer 106, the tunneling layer 107 is formed by chemical vapor deposition. The thickness of the tunneling layer 107 is within the range.

[0072] Please refer to Figure 7 In step S16, source and drain regions are formed in the substrate 100. The source and drain regions include a source electrode 108 and a drain electrode 109.

[0073] Please continue to refer to Figure 7 In step S17 , a select gate 110 , an erase gate 111 and a control gate 112 are formed on the substrate 100 .

[0074] Correspondingly, an embodiment of the present invention further provides a memory structure, and the memory structure is formed by the above-mentioned method for forming the memory structure, which will not be described in detail here.

[0075] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a memory structure, characterized in that: include: providing a substrate; forming a floating gate precursor layer on the substrate, wherein the material of the floating gate precursor layer is a MAX material; Performing a phase change treatment on the floating gate precursor layer to form an initial floating gate, wherein the initial floating gate is made of MXene material; The initial floating gate is oxidized to form a floating gate and a barrier layer surrounding the floating gate.

2. The method for forming a memory structure according to claim 1, wherein: The molecular formula of the MAX material is M n+1 AX n , where M represents a transition metal, A represents a main group element, and X represents carbon or nitrogen.

3. The method for forming a memory structure according to claim 2, wherein: The molecular formula of the MXene material is M n+1 X n T x , wherein M represents a transition metal, X represents a carbon or nitrogen element, and T represents a capping group; the capping group includes: -F, -O and -OH.

4. The method for forming a memory structure according to claim 3, wherein: The molecular formula of the floating gate material is M n+1 X n , where M represents a transition metal and X represents carbon or nitrogen.

5. The method for forming a memory structure according to claim 3, wherein: The material of the barrier layer includes titanium oxide.

6. The method for forming a memory structure according to claim 1, wherein: The step of performing phase change treatment on the floating gate precursor layer to form an initial floating gate comprises: Etching the floating gate precursor layer to form a floating gate precursor; The floating gate precursor is subjected to a phase change process to form the initial floating gate.

7. The method for forming a memory structure according to claim 1, wherein: The step of performing phase change treatment on the floating gate precursor layer to form an initial floating gate comprises: forming a floating gate precursor layer on the substrate; Performing a phase change treatment on the floating gate precursor layer to form a transition floating gate layer, wherein the transition floating gate layer is made of MXene material; The transition floating gate layer is etched to form the initial floating gate.

8. The method for forming a memory structure according to claim 1, 6 or 7, characterized in that: In the step of forming a floating gate precursor layer on the substrate, the floating gate precursor layer is formed by magnetron sputtering.

9. The method for forming a memory structure according to claim 1, wherein: In the step of performing an oxidation treatment on the initial floating gate to form a floating gate and a barrier layer surrounding the floating gate, the process gas for the oxidation treatment includes at least one of nitrogen and air.

10. The method for forming a memory structure according to claim 1, wherein: In the step of performing oxidation treatment on the initial floating gate, the temperature range of the oxidation treatment is 50° C. to 200° C.; the time range of the oxidation treatment is 100 min to 300 min.

11. The method for forming a memory structure according to claim 1, wherein: In the step of oxidizing the initial floating gate, the thickness of the barrier layer is within the range.

12. The method for forming a memory structure according to claim 1, wherein: In the step of performing phase change treatment on the floating gate precursor layer, the phase change treatment method includes: wet etching.

13. The method for forming a memory structure according to claim 12, wherein: The etching solution of the wet etching includes hydrogen chloride and lithium fluoride; the etching temperature of the wet etching is 30° C. to 50° C.; The etching time of the wet etching is 100 hours to 150 hours.

14. The method for forming a memory structure according to claim 1, wherein: Also includes: A tunneling layer is formed on the surface of the barrier layer.

15. The method for forming a memory structure according to claim 14, wherein: In the step of forming a tunneling layer on the surface of the barrier layer, the material of the tunneling layer is silicon oxide.

16. The method for forming a memory structure according to claim 14 or 15, characterized in that: In the step of forming a tunneling layer on the surface of the barrier layer, the tunneling layer is formed by chemical vapor deposition.

17. The method for forming a memory structure according to claim 14, wherein: The thickness of the tunneling layer is within the range.

18. The method for forming a memory structure according to claim 14, wherein: Also includes: forming source and drain regions in the substrate; A select gate, an erase gate and a control gate are formed on the substrate.

19. A memory structure, characterized in that: The memory structure is formed by the method for forming a memory structure according to any one of claims 1 to 18.

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