Resistive random access memory device and preparation method of resistive random access memory device

Abstract

The invention relates to the technical field of storage, and provides a resistive random access memory device and a preparation method of the resistive random access memory device, the resistive random access memory device comprises a bottom electrode, a first dielectric layer, a first top electrode, a second dielectric layer and a second top electrode; the first dielectric layer is arranged on the bottom electrode; the first top electrode is arranged on the first dielectric layer, and the first top electrode is provided with at least one hole; the second dielectric layer is arranged in the hole, and the thickness of the second dielectric layer is lower than the depth of the hole; and the second top electrode is arranged on the second dielectric layer, and at least one part of the second top electrode is in contact with the upper surface of the first top electrode. According to the invention, the contact area of the first top electrode and the dielectric layer can be increased, the larger contact area can provide more current paths, more stable and uniform current transmission can be realized, the reliability and the performance consistency of the device can be improved, the larger contact area can provide wider current distribution, and the reliability and the performance consistency of the device can be improved. And a more reliable resistance switching characteristic can be realized.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a resistive memory device and a method for preparing the resistive memory device. Background Art

[0002] With the progress of industrialization, all walks of life are increasingly dependent on information science and technology, among which the performance requirements for memory are higher. In order to meet the demand for high performance of memory, a resistive random access memory (Resistive Random Access Memory) is proposed.

[0003] Resistive random access memory is a new type of non-volatile memory, and its structure usually includes a bottom electrode, a resistive switching layer, and a top electrode connected in sequence. Its working principle is to use the controllable change of the oxide resistance formed between the two electrodes to store information. It has the advantages of high speed, low power consumption, and high density, and is widely regarded as one of the future trends in the development of memory. With the continuous development of Moore's Law, memory devices are constantly developing towards small size and high stacking degree. The reduction in size will lead to a reduction in the area of ​​the resistive switching layer, which in turn reduces the connection area between the electrode and the resistive switching layer, thereby changing the performance of the resistive switching device. Summary of the invention

[0004] The present invention provides a resistive memory device and a method for preparing the resistive memory device. The present invention provides a method that can increase the contact area between an electrode and a resistive layer under the same process conditions, thereby solving the problem of small randomness of small-sized devices.

[0005] The present invention provides a resistive memory device, comprising:

[0006] bottom electrode;

[0007] A first dielectric layer, disposed on the bottom electrode;

[0008] A first top electrode is disposed on the first dielectric layer, and the first top electrode has at least one hole;

[0009] A second dielectric layer is disposed in the cavity, and a thickness of the second dielectric layer is lower than a depth of the cavity;

[0010] The second top electrode is disposed on the second dielectric layer, and at least a portion of the second top electrode contacts the upper surface of the first top electrode.

[0011] The resistive memory device provided by the present invention further includes:

[0012] A support structure is arranged on the bottom electrode, and a through hole is formed in the support structure; the first dielectric layer and the first top electrode are embedded in the through hole.

[0013] According to the resistive memory device provided by the present invention, the top of the first top electrode completely covers the supporting structure.

[0014] According to the resistive memory device provided by the present invention, the thickness of the first dielectric layer is 2 nanometers to 5 nanometers.

[0015] According to the resistive memory device provided by the present invention, the thickness of the second dielectric layer is 6 nanometers to 15 nanometers.

[0016] According to the resistive memory device provided by the present invention, the first dielectric layer and the second dielectric layer are made of the same material; or the first top electrode and the second top electrode are made of different materials.

[0017] The present invention also provides a method for preparing the resistive memory device provided in any of the above embodiments, comprising the steps of:

[0018] performing a patterning operation on the bottom electrode to form a through hole;

[0019] forming a first dielectric layer in the through hole by a deposition process;

[0020] On the first dielectric layer, forming a first top electrode in the through hole by using a deposition process;

[0021] forming a cavity in the first top electrode by a stripping or etching process;

[0022] forming two dielectric layers in the cavity by a deposition process, wherein the second dielectric layer is connected to the first dielectric layer;

[0023] On the second dielectric layer, a second top electrode is formed in the cavity by a deposition process, and the second top electrode is connected to the first top electrode.

[0024] According to the preparation method provided by the present invention, patterning operation is performed on the bottom electrode to form a through hole, which specifically includes:

[0025] forming a silicon dioxide layer on the bottom electrode by a deposition process;

[0026] The through hole is processed on the silicon dioxide layer by using an etching process.

[0027] According to the preparation method provided by the present invention, a first dielectric layer is formed in the through hole by a deposition process, specifically comprising: using one of an atomic layer deposition process, a physical vapor deposition process, a chemical vapor deposition process and an electron beam evaporation process to deposit at least one of titanium oxide, hafnium oxide, zirconium oxide, aluminum oxide, silicon oxide, tantalum oxide and perovskite oxide to the bottom of the through hole.

[0028] According to the preparation method provided by the present invention, a first top electrode is formed in the through hole by a deposition process, specifically comprising:

[0029] At least one of palladium, palladium alloy, titanium, titanium alloy, titanium nitride, zirconium alloy, ruthenium, ruthenium alloy, tantalum, tantalum alloy, tantalum nitride, single crystal silicon, polycrystalline silicon, platinum, platinum alloy, hafnium, hafnium alloy, aluminum, aluminum alloy, tungsten, tungsten alloy, iridium, and iridium alloy is deposited on the first dielectric layer using one of an atomic layer deposition process, a physical vapor deposition process, a chemical vapor deposition process, and an electron beam evaporation process.

[0030] According to any of the above embodiments, the present invention has at least the following beneficial effects:

[0031] The present invention provides a resistive memory device, which can simultaneously contact the first dielectric layer and the second dielectric layer by setting a hole in the first top electrode and setting a second dielectric layer in the hole. On the one hand, the contact area between the first top electrode and the dielectric layer can be increased. The larger contact area can provide more current paths, which is conducive to achieving more stable and uniform current transmission, which helps to improve the reliability and performance consistency of the device, and the larger contact area can provide a wider current distribution, which is conducive to achieving more reliable resistance switching characteristics. On the other hand, the top electrode can be in contact with dielectric layers of different materials to improve the resistance switching characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 is a schematic structural diagram of a resistive memory device provided by the present invention;

[0034] Figure 2 It is one of the structural diagrams in the preparation process of the resistive memory device provided by the present invention;

[0035] Figure 3 yes Figure 2 A top view of the structure is prepared;

[0036] Figure 4 This is the second structural diagram of the manufacturing process of the resistive memory device provided by the present invention;

[0037] Figure 5 yes Figure 4 A top view of the structure is prepared;

[0038] Figure 6 This is the third structural diagram of the manufacturing process of the resistive memory device provided by the present invention;

[0039] Figure 7 yes Figure 6 A top view of the structure is prepared;

[0040] Figure 8 This is the fourth structural diagram of the manufacturing process of the resistive memory device provided by the present invention;

[0041] Fig. 9 yes Figure 8 A top view of the structure is prepared;

[0042] Fig.10 It is a schematic flow chart of a method for preparing a resistive memory device provided by the present invention.

[0043] Reference numerals:

[0044] 1. bottom electrode; 2. support structure; 21. through hole; 3. first dielectric layer; 4. first top electrode; 41. hole; 5. second dielectric layer; 6. second top electrode. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0046] In the description of the embodiments of the present invention, it should be noted that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limitations on the embodiments of the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0047] In the description of the embodiments of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "connected" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present invention can be understood according to specific circumstances.

[0048] In the embodiments of the present invention, unless otherwise clearly specified and limited, the first feature being "above" or "below" the second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature being "above", "above" and "above" the second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. The first feature being "below", "below" and "below" the second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0049] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiment of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0050] In the related technology, resistive random access memory (RRAM) is a new type of non-volatile memory. Its working principle is to use the controllable change of the oxide resistance formed between two electrodes to store information. It has the advantages of high speed, low power consumption, high density, etc., and is widely regarded as one of the trends in the development of future memory. Usually, the resistive random access memory is set as a sandwich structure, which specifically includes a bottom electrode of the bottom metal, a resistive dielectric layer in the middle, and a top electrode of the top metal. By applying a voltage between the electrodes, the state of the oxide resistance in the resistive dielectric can be controlled, thereby realizing the writing and reading of information.

[0051] Among them, the bottom electrode serves as the basis of the resistive switching device, the resistive switching medium is the core of the entire resistive switching memory, the resistance state of the resistive switching medium layer can be controlled to realize the storage and reading of information, and the top electrode covers the top of the resistive switching medium layer. By applying a voltage difference between the top electrode and the bottom electrode, the resistance state of the dielectric layer can be controlled. With the development of Moore's Law, memory devices continue to develop towards small size and high stacking layer, which makes the area of ​​the resistive switching medium layer smaller, and then reduces the contact surface between the electrode and the resistive switching medium layer. When the contact area between the electrode and the resistive switching medium layer is reduced, the resistance volatility becomes smaller, that is, the random fluctuation range or distribution range of the resistance value inside the resistive switching memory becomes smaller, which is not conducive to some scenarios with high randomness. In view of the above, the present invention proposes a resistive switching memory device that can improve the resistance randomness of the resistive switching memory. See the description of the following embodiments for details.

[0052] Combine the following Figure 1 The present invention is described. The present invention provides a resistive memory device, which is configured to be suitable for a high randomness scenario, and includes a bottom electrode 1, a first dielectric layer 3, a first top electrode 4, a second dielectric layer 5, and a second top electrode 6. The first dielectric layer 3 is disposed on the bottom electrode 1; the first top electrode 4 is disposed on the first dielectric layer 3, and the first top electrode 4 has at least one hole 41; the second dielectric layer 5 is disposed in the hole 41, and the thickness of the second dielectric layer 5 is lower than the depth of the hole 41; the second top electrode 6 is disposed on the second dielectric layer 5, and at least a portion of the second top electrode 6 is in contact with the upper surface of the first top electrode 4.

[0053] Generally, when performing information storage operations, a voltage difference is applied to the top electrode and the bottom electrode, and the applied voltage difference excites a current path in the resistive dielectric layer, that is, the larger the area in contact with the top electrode, the more current paths it can provide, which can increase the resistance range between the low resistance state and the high resistance state. A larger resistance range means that the device can achieve a larger resistance difference between the two states, which is conducive to accurate reading and writing of data. In this embodiment, a hole 41 is provided in the first top electrode 4, and a second dielectric layer 5 is provided in the hole 41, that is, the bottom surface of the first top electrode 4 contacts the first dielectric layer 3, and the inner wall surface of the hole 41 of the first top electrode 4 contacts the outer wall surface of the second dielectric layer 5. Obviously, compared with the conventional connection structure, the contact area between the top electrode and the dielectric layer in this embodiment is larger, and a larger surface contact between the lower electrode and the resistive dielectric layer under the same process is achieved.

[0054] Furthermore, the second dielectric layer 5 is located in the cavity 41, the cavity 41 extends in the vertical direction of the first top electrode 4, and the top surface of the second dielectric layer 5 is located in the cavity 41, which makes the thickness of the second dielectric layer 5 less than the depth of the cavity 41, that is, there is a certain contact space above the second dielectric layer 5, and the second top electrode 6 is provided in the contact space. In the specific setting, at least a portion of the second top electrode 6 extends into the cavity 41 and contacts the second dielectric layer 5, and a portion of the second top electrode 6 contacts the upper surface of the first top electrode 4, so that the connection between the two top electrodes is stable. Moreover, compared with the conventional "sandwich" type resistive memory device, this embodiment can increase the contact surface of the inner wall of at least one cavity 41, thereby increasing the contact area between the electrode and the dielectric layer and improving the resistance randomness of the resistive memory device.

[0055] It can be understood that the solution of this embodiment increases the contact area between the top electrode and the dielectric layer, thereby enabling it to provide more current paths, which is conducive to achieving more stable and uniform current transmission, and the larger contact area can provide better contact quality, reduce the problem of local hot spots, and provide a larger heat conduction path, which is conducive to rapid heat dissipation, helping to improve the reliability and cycle life of the device, and reducing the risk of shortened life due to performance degradation. In this example, the first dielectric layer 3 and the second dielectric layer 5 have the same material. Of course, the first dielectric layer 3 and the second dielectric layer 5 can also have different materials.

[0056] In a specific example, the material of the dielectric layer is one of the important factors affecting the contact between the dielectric layer and the electrode. When dielectric layers of different materials are in contact with the electrode, the size and distribution of the contact resistance will be different. In this embodiment, the first top electrode 4 is in contact with the first dielectric layer 3 and the second dielectric layer 5 respectively. When the first dielectric layer 3 and the second dielectric layer 5 are made of different materials, the first top electrode 4 has dielectric contact with two different materials. Different dielectric materials make the contact resistance of the first top electrode 4 and the dielectric layer more differentiated, which can further increase the resistance range between the low resistance state and the high resistance state, thereby achieving an improvement in resistance randomness.

[0057] It can be understood that in this embodiment, the first dielectric layer 3 and the second dielectric layer 5 are configured with different materials, which can increase the random fluctuation range of the contact resistance inside the resistive memory device and further improve the performance of the randomness of the device resistance.

[0058] In this embodiment, the first top electrode 4 and the second top electrode 6 may also be made of different materials, and different materials may affect the performance of the device; wherein, by setting different materials in the same device, the device and the dielectric layer may have greater random fluctuation performance, further improving the volatility of the device. In other embodiments, the first top electrode 4 and the second top electrode 6 may also be made of the same material.

[0059] In the above embodiment, the first dielectric layer 3 and the second dielectric layer 5 are resistive dielectric layers made of oxide, and a plurality of current channels are formed in the first dielectric layer 3 and the second dielectric layer 5 by applying voltage to the first top electrode 4 and the second top electrode 6, thereby controlling the resistance state in the dielectric layer and realizing information storage.

[0060] According to an embodiment of the present invention, the resistive memory device further includes a support structure 2, which is disposed on the bottom electrode 1 and has a through hole 21 therein; the first dielectric layer 3 and the first top electrode 4 are embedded in the through hole 21. In this embodiment, the support structure 2 is used to constitute the main structure of the device, and can realize the preparation of various components, as well as the stacking and integration of multi-layer devices. The support structure 2 can improve the overall stability of the device.

[0061] In this embodiment, the support structure 2 is constructed as a closed-loop structure, with a through hole 21 in the middle of the support structure 2, and each device is arranged in the through hole 21, wherein the bottom of the support structure 2 is connected to the bottom electrode 1, and the support structure 2 is used to form the top electrode and the dielectric layer.

[0062] In the specific setting, the top of the first top electrode 4 completely covers the supporting structure 2, and the supporting structure 2 is a closed-loop cylindrical structure. The first top electrode 4 extends upward from the inner wall of the through hole 21 and forms an extension surface on the top surface of the supporting structure 2. The extension surface extends in all directions so that the first top electrode 4 can completely cover the top surface of the supporting structure 2, so that the supporting structure 2 can provide effective support for the first top electrode and improve the internal stability of the device.

[0063] The thickness of the first dielectric layer 3 is 2 nanometers to 5 nanometers, and the thickness of the second dielectric layer 5 is 6 nanometers to 15 nanometers.

[0064] The thickness of the dielectric layer is determined by the process design of the device itself and the device requirements. In this embodiment, the first dielectric layer 3 is located at the bottom of the through hole 21 and can contact the first top electrode 4, and the second dielectric layer 5 is in contact with the inner wall of the cavity 41 of the first top electrode 4. In order to effectively increase the contact area and consider the performance requirements, the thickness of the first dielectric layer 3 is limited to 2 nanometers to 5 nanometers in this embodiment, which makes the first dielectric layer 3 occupy less space in the through hole 21 and can have a larger contact area with the first top electrode. The second dielectric layer 5 is located in the cavity 41. In order to increase the contact area between the first top electrode 4 and the second dielectric layer 5, the thickness of the second dielectric layer 5 is higher than that of the first dielectric layer 3, and can contact the second top electrode 6 through the top surface of the second dielectric layer 5, thereby increasing the contact surface between the electrode and the dielectric layer.

[0065] The following is a description of a method for preparing a resistive memory device provided by any of the above embodiments. The following preparation method and the above resistive memory device can be described with reference to each other.

[0066] The present invention also provides a method for preparing a resistive memory device, comprising the steps of:

[0067] Step 100, forming a through hole 21 by patterning on the bottom electrode 1;

[0068] Step 200, forming a first dielectric layer 3 in the through hole 21 by using a deposition process;

[0069] Step 300 , forming a first top electrode 4 in the through hole 21 on the first dielectric layer 3 by using a deposition process;

[0070] Step 400, forming a cavity 41 in the first top electrode 4 by using a stripping or etching process;

[0071] Step 500: forming a second dielectric layer in the cavity 41 by a deposition process, wherein the second dielectric layer 5 is connected to the first dielectric layer 3;

[0072] Step 600 : On the second dielectric layer 5 , a second top electrode 6 is formed in the cavity 41 by a deposition process, and the second top electrode 6 is connected to the first top electrode 4 .

[0073] In the above-mentioned preparation method, Figure 2 , Figure 3 As shown, Figure 3 for Figure 2 In the top view of the structure, in step 100, a through hole 21 is formed on the upper surface of the bottom electrode 1 by micro-nano processing technology. Specifically, a silicon dioxide layer is formed on the bottom electrode 1 by a deposition process, and the through hole 21 is processed on the silicon dioxide layer by a stripping process or an etching process, so that a ring-shaped through hole 21 is formed.

[0074] In this embodiment, the through hole 21 can be formed into a rectangular, circular or any other shape by changing processing parameters. In this embodiment, a through hole 21 processed into a rectangular shape is selected for exemplary description. Figure 3 As shown, the silicon dioxide layer is constructed as a rectangular closed ring structure, the middle of which is a through hole 21. Operations are performed in the through hole 21 in subsequent processes to eventually form a memory device.

[0075] Among them, continue as Figure 2 , Figure 3 As shown, step 200 specifically includes: using one of an atomic layer deposition process, a physical vapor deposition process, a chemical vapor deposition process and an electron beam evaporation process to deposit at least one of titanium oxide, hafnium oxide, zirconium oxide, aluminum oxide, silicon oxide, tantalum oxide and perovskite oxide at the bottom of the through hole 21.

[0076] When setting specific Figure 4 , Figure 5 As shown, Figure 5 for Figure 4 In the top view of the structure, in step 300, a first top electrode 4 is formed in the through hole 21 by a deposition process, specifically comprising: using one of an atomic layer deposition process, a physical vapor deposition process, a chemical vapor deposition process and an electron beam evaporation process to deposit at least one of palladium, palladium alloy, titanium, titanium alloy, titanium nitride, zirconium alloy, ruthenium, ruthenium alloy, tantalum, tantalum alloy, tantalum nitride, single crystal silicon, polycrystalline silicon, platinum, platinum alloy, hafnium, hafnium alloy, aluminum, aluminum alloy, tungsten, tungsten alloy, iridium, and iridium alloy onto the first dielectric layer 3.

[0077] Further examples such as Figure 4 , Figure 5 As shown, in step 400 , a rectangular hole 41 is processed on the first top electrode 4 by an etching process, and the rectangular hole 41 runs through the entire first top electrode 4 .

[0078] Further examples such as Figure 6 , Figure 7 As shown, in step 500 , the second dielectric layer 5 is formed in the cavity 41 by a deposition process. It is understandable that the material of the second dielectric layer 5 can be the same as or different from that of the first dielectric layer 3 . The specific material range is consistent with that of the first dielectric layer 3 .

[0079] Further examples such as Figure 8 , Fig. 9 As shown, in step 600 , a second top electrode 6 is formed in the upper cavity 41 of the second dielectric layer 5 by a deposition process. It is understandable that the second top electrode 6 and the first top electrode 4 can be made of the same or different materials. The specific material range is consistent with that of the first top electrode 4 .

[0080] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can increase the contact area between the top electrode and the dielectric layer, thereby improving the randomness of the device resistance. Furthermore, by dividing the dielectric layer into the first dielectric layer 3 and the second dielectric layer 5, and dividing the top electrode into the first top electrode 4 and the second top electrode 6, the first dielectric layer 3 and the second dielectric layer 5 can be arranged with different materials, thereby achieving a greater resistance value difference, which can further improve the random resistance volatility of the resistive memory device.

[0081] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A resistive memory device, characterized in that: include: bottom electrode; A first dielectric layer is provided on the bottom electrode; a first top electrode disposed on the first dielectric layer, wherein the first top electrode has at least one hole; a second dielectric layer, disposed in the cavity of the first top electrode, wherein a thickness of the second dielectric layer is less than a depth of the cavity; The second top electrode is disposed on the second dielectric layer, and at least a portion of the second top electrode contacts an upper surface of the first top electrode.

2. The resistive memory device according to claim 1, wherein: Also includes: A support structure is provided on the bottom electrode, and a through hole is formed in the support structure; the first dielectric layer and the first top electrode are embedded in the through hole.

3. The resistive memory device according to claim 2, wherein: The top of the first top electrode completely covers the supporting structure.

4. The resistive memory device according to claim 1 or 2, wherein: The thickness of the first dielectric layer is 2 nanometers to 5 nanometers.

5. The resistive memory device according to claim 1 or 2, wherein: The thickness of the second dielectric layer is 6 nanometers to 15 nanometers.

6. The resistive memory device according to claim 1 or 2, wherein: The first dielectric layer and the second dielectric layer are made of the same material; or the first top electrode and the second top electrode are made of different materials.

7. A method for preparing the resistive memory device according to any one of claims 1 to 6, characterized in that: Including steps: performing a patterning operation on the bottom electrode to form a through hole; forming a first dielectric layer in the through hole by using a deposition process; forming a first top electrode in the through hole on the first dielectric layer by using a deposition process; forming a cavity in the first top electrode by a lift-off or etching process; forming a second dielectric layer in the cavity by a deposition process, wherein the second dielectric layer is in contact with the first dielectric layer; A second top electrode is formed in the cavity on the second dielectric layer by using a deposition process, and the second top electrode is connected to the first top electrode.

8. The preparation method according to claim 7, characterized in that The step of patterning the bottom electrode to form a through hole specifically includes: forming a silicon dioxide layer on the bottom electrode by a deposition process; The through hole is processed on the silicon dioxide layer by using an etching process.

9. The preparation method according to claim 7, characterized in that The step of forming the first dielectric layer in the through hole by using a deposition process specifically includes: At least one of titanium oxide, hafnium oxide, zirconium oxide, aluminum oxide, silicon oxide, tantalum oxide and perovskite oxide is deposited on the bottom of the through hole by using one of atomic layer deposition process, physical vapor deposition process, chemical vapor deposition process and electron beam evaporation process.

10. The preparation method according to claim 7, characterized in that The step of forming the first top electrode in the through hole by using a deposition process specifically includes: At least one of palladium, palladium alloy, titanium, titanium alloy, titanium nitride, zirconium alloy, ruthenium, ruthenium alloy, tantalum, tantalum alloy, tantalum nitride, single crystal silicon, polycrystalline silicon, platinum, platinum alloy, hafnium, hafnium alloy, aluminum, aluminum alloy, tungsten, tungsten alloy, iridium, and iridium alloy is deposited on the first dielectric layer using one of an atomic layer deposition process, a physical vapor deposition process, a chemical vapor deposition process, and an electron beam evaporation process.

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