Resistive random access memory device and preparation method thereof

Abstract

The invention relates to the technical field of storage, and provides a resistive random access memory device and a preparation method thereof, the resistive random access memory device comprises a bottom electrode, a first dielectric layer, a second dielectric layer and a top electrode; the first dielectric layer is arranged on the bottom electrode, and at least one hole is formed in the first dielectric layer; the second dielectric layer is arranged at the bottom of the hole; the bottom surface of the second dielectric layer is connected with the bottom electrode; the top electrode is arranged in the hole, and at least one part of the top electrode is in contact with the upper surface of the first dielectric layer. According to the invention, the contact area of the top electrode and the dielectric layer is increased, the larger contact area can provide more current paths, more stable and uniform current transmission can be realized, the reliability and the performance consistency of the device can be improved, the larger contact area can provide wider current distribution, and the reliability and the performance consistency of the device can be improved. And a more reliable resistance switching characteristic can be realized.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a resistive memory device and a preparation method thereof. Background Art

[0002] With the progress of industrialization, all walks of life are increasingly dependent on information science and technology, among which the performance requirements for memory are higher. In order to meet the demand for high performance of memory, a resistive random access memory (Resistive Random Access Memory) is proposed.

[0003] Resistive random access memory is a new type of non-volatile memory, and its structure usually includes a bottom electrode, a resistive switching layer, and a top electrode connected in sequence. Its working principle is to use the controllable change of the oxide resistance formed between the two electrodes to store information. It has the advantages of high speed, low power consumption, and high density, and is widely regarded as one of the future trends in the development of memory. With the continuous development of Moore's Law, memory devices are constantly developing towards small size and high stacking degree. The reduction in size will lead to a reduction in the area of ​​the resistive switching layer, which in turn makes the connection area between the electrode and the resistive switching layer seriously affect the performance of the resistive switching device. Summary of the invention

[0004] The present invention provides a resistive memory device and a preparation method thereof, which are used to solve the defect of small contact area between an electrode and a resistive dielectric layer in the prior art, and realize that the electrode and the dielectric layer have a larger contact area.

[0005] The present invention provides a resistive memory device, comprising:

[0006] bottom electrode;

[0007] A first dielectric layer is disposed on the bottom electrode, and the first dielectric layer has at least one hole;

[0008] A second dielectric layer, embedded in the bottom of the cavity, wherein the bottom surface of the second dielectric layer is in contact with the bottom electrode;

[0009] A top electrode is disposed in the cavity, and at least a portion of the top electrode contacts an upper surface of the first dielectric layer.

[0010] The resistive memory device provided according to the present invention further comprises a supporting structure, wherein the supporting structure is arranged on the bottom electrode and has a through hole therein; and the first dielectric layer is embedded in the through hole.

[0011] According to the resistive memory device provided by the present invention, the thickness of the second dielectric layer is lower than the depth of the hole, so that at least a portion of the top electrode is located in the hole and in contact with the second dielectric layer.

[0012] According to the resistive memory device provided by the present invention, the thickness of the first dielectric layer is 6 nanometers to 15 nanometers.

[0013] According to the resistive memory device provided by the present invention, the thickness of the second dielectric layer is 2 nanometers to 5 nanometers.

[0014] According to the resistive memory device provided by the present invention, the first dielectric layer and the second dielectric layer are made of different materials.

[0015] The present invention also provides a method for preparing the resistive memory device provided by any one of the above embodiments, comprising the steps of:

[0016] performing a patterning operation on the bottom electrode to form a through hole;

[0017] forming a first dielectric layer in the through hole by a deposition process;

[0018] forming at least one cavity in the first dielectric layer by using a stripping or etching process;

[0019] forming a second dielectric layer at the bottom of the cavity by a deposition process;

[0020] A top electrode is formed on the second dielectric layer by using a deposition process, and at least a portion of the top electrode is located in the cavity.

[0021] According to the preparation method provided by the present invention, the step of patterning the bottom electrode to form a through hole specifically includes:

[0022] forming a silicon dioxide layer on the bottom electrode by a deposition process;

[0023] The through hole is processed on the silicon dioxide layer by using a stripping process or an etching process.

[0024] According to the preparation method provided by the present invention, the first dielectric layer is formed in the through hole by using a deposition process;

[0025] and, forming a second dielectric layer at the bottom of the cavity by a deposition process, specifically comprising:

[0026] At least one of titanium oxide, fluorinated hydroxide, zirconium oxide, aluminum oxide, silicon oxide and perovskite oxide is deposited using one of atomic layer deposition, physical vapor deposition, chemical vapor deposition and electron beam evaporation processes.

[0027] According to the preparation method provided by the present invention, the step of forming the top electrode by a deposition process specifically comprises:

[0028] At least one of palladium, palladium alloy, titanium, titanium alloy, titanium nitride, zirconium alloy, ruthenium, ruthenium alloy, tantalum, tantalum alloy, tantalum nitride, single crystal silicon, polycrystalline silicon, platinum, platinum alloy, hafnium, hafnium alloy, aluminum, aluminum alloy, tungsten, tungsten alloy, iridium, and iridium alloy is deposited on the second dielectric layer using one of an atomic layer deposition process, a physical vapor deposition process, a chemical vapor deposition process, and an electron beam evaporation process.

[0029] According to any of the above embodiments, the present invention has at least the following beneficial effects:

[0030] The resistive memory device provided by the present invention has a hole formed in the first dielectric layer, and a second dielectric layer is provided at the bottom of the hole, and a top electrode is provided in the hole, thereby increasing the contact area between the top electrode and the dielectric layer. A larger contact area can provide more current paths, which is conducive to achieving more stable and uniform current transmission, which helps to improve the reliability and performance consistency of the device, and a larger contact area can provide a wider current distribution, which is conducive to achieving more reliable resistance switching characteristics. Moreover, the bottom electrode and the top electrode can contact the first dielectric layer and the second dielectric layer at the same time, providing an effective and feasible solution for the electrode to contact different dielectric layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 is a schematic structural diagram of a resistive memory device provided by the present invention;

[0033] Figure 2 It is one of the structural diagrams in the preparation process of the resistive memory device provided by the present invention;

[0034] Figure 3 The present invention Figure 2 A top view of the structure is prepared;

[0035] Figure 4 This is the second structural diagram of the manufacturing process of the resistive memory device provided by the present invention;

[0036] Figure 5 The present invention Figure 4 A top view of the structure is prepared;

[0037] Figure 6 This is the third structural diagram of the manufacturing process of the resistive memory device provided by the present invention;

[0038] Figure 7 The present invention Figure 6 A top view of the structure is prepared;

[0039] Figure 8 This is the fourth structural diagram of the manufacturing process of the resistive memory device provided by the present invention;

[0040] Fig. 9 The present invention Figure 8 A top view of the structure is prepared;

[0041] Fig.10 It is a schematic flow chart of a method for preparing a resistive memory device provided by the present invention.

[0042] Reference numerals:

[0043] 1. Bottom electrode; 2. Support structure; 21. Through hole; 3. First dielectric layer; 31. Hole; 4. Second dielectric layer; 5. Top electrode. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] In the description of the embodiments of the present invention, it should be noted that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limitations on the embodiments of the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0046] In the description of the embodiments of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "connected" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present invention can be understood according to specific circumstances.

[0047] In the embodiments of the present invention, unless otherwise clearly specified and limited, the first feature being "above" or "below" the second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature being "above", "above" and "above" the second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. The first feature being "below", "below" and "below" the second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0048] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiment of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0049] In the related technology, resistive random access memory (RRAM) is a new type of non-volatile memory. Its working principle is to use the controllable change of the oxide resistance formed between two electrodes to store information. It has the advantages of high speed, low power consumption, high density, etc., and is widely regarded as one of the trends in the development of future memory. Usually, the resistive random access memory is set as a sandwich structure, which specifically includes a bottom electrode of the bottom metal, a resistive dielectric layer in the middle, and a top electrode of the top metal. By applying a voltage between the electrodes, the state of the oxide resistance in the resistive dielectric can be controlled, thereby realizing the writing and reading of information.

[0050] Among them, the bottom electrode serves as the basis for information storage, the resistive medium is the core of the entire resistive memory, the resistance state of the resistive medium layer can be controlled to realize the storage and reading of information, and the top electrode covers the resistive medium layer. By applying voltage to the top electrode, the resistance state of the dielectric layer is realized. However, with the development of Moore's Law, memory devices continue to develop towards small size and high stacking layer, which makes the area of ​​the resistive dielectric layer smaller, and then reduces the contact surface between the electrode and the resistive dielectric layer. When the contact area between the electrode and the resistive dielectric layer is reduced, the resistance window becomes smaller, that is, the random fluctuation range or distribution range of the resistance value inside the resistive memory becomes smaller, which is not conducive to some scenarios with high randomness. In view of the above, the present invention proposes a resistive memory device that can improve the resistance randomness of the resistive memory. See the description of the following embodiments for details.

[0051] Combine the following Figure 1 A resistive memory device of the present invention is described. The resistive memory device is constructed to be suitable for a scenario requiring stability and reliability, and includes a bottom electrode 1, a first dielectric layer 3, a second dielectric layer 4, and a top electrode 5; the first dielectric layer 3 is disposed on the bottom electrode 1, and the first dielectric layer 3 has at least one hole 31; the second dielectric layer 4 is embedded in the bottom of the hole 31, and the bottom surface of the second dielectric layer 4 is connected to the bottom electrode 1; the top electrode 5 is disposed in the hole 31, and at least a portion of the top electrode 5 is in contact with the upper surface of the first dielectric layer 3.

[0052] Generally, when performing information storage operation, a voltage is applied to the top electrode 5, and the applied voltage forms a current path in the resistive dielectric layer. That is, the larger the area in contact with the top electrode 5, the more current paths it can provide, which can increase the resistance range between the low resistance state and the high resistance state. A larger resistance range means that the device can achieve a larger resistance difference between the two states, which is conducive to accurate reading and writing of data. In this embodiment, a cavity 31 is provided in the first dielectric layer 3, and a second dielectric layer 4 is provided at the bottom of the cavity 31. The thickness of the second dielectric layer 4 is lower than the depth of the cavity 31, so that the top electrode 5 can be provided in the cavity 31 on the second dielectric layer 4, so that the top electrode 5 can contact the second dielectric layer 4, and a part of the top electrode 5 contacts the inner wall surface of the cavity 31, and the upper part of the top electrode 5 contacts the upper surface of the first dielectric layer 3. Obviously, compared with the conventional connection structure, the contact area between the top electrode 5 and the dielectric layer in this embodiment is larger, and a larger area of ​​contact between the lower electrode and the resistive dielectric layer in the same process is achieved.

[0053] Further explanation, the second dielectric layer 4 is located in the cavity 31, the outer wall surface of the second dielectric layer 4 contacts the inner wall surface of the cavity 31 to realize an embedded arrangement, the cavity 31 extends along the vertical direction of the first dielectric layer 3, and the top surface of the second dielectric layer 4 is located in the cavity 31, so that the upper space of the cavity 31 can accommodate the extension of the top electrode 5, and the top electrode 5 can be respectively in contact with the first dielectric layer 3 and the second dielectric layer 4. And by extending the top electrode 5 into the cavity 31, the stability of the structure can be improved, and a larger contact area between the top electrode 5 and the dielectric layer can be achieved, thereby improving the resistance switching characteristics in the resistive memory device.

[0054] It can be understood that the solution of this embodiment increases the contact area between the top electrode 5 and the dielectric layer, so that it can provide more current paths, which is conducive to achieving more stable and uniform current transmission, and the larger contact area can provide improved contact quality, reduce the problem of local hot spots, and provide a larger heat conduction path, which is conducive to rapid heat dissipation, helping to improve the reliability and cycle life of the device, and reducing the risk of shortened life due to performance degradation. In this example, the first dielectric layer 33 and the second dielectric layer 45 have the same material. Of course, the first dielectric layer 33 and the second dielectric layer 45 can also have different materials.

[0055] In a specific example, the material of the dielectric layer is one of the important factors affecting the contact between the dielectric layer and the electrode. When dielectric layers of different materials are in contact with the electrode, the size and distribution of the contact resistance will be different. In this embodiment, the top electrode 5 is in contact with the first dielectric layer 3 and the second dielectric layer 4 respectively. When the first dielectric layer 3 and the second dielectric layer 4 are made of different materials, the first top electrode 5 can be in contact with two dielectrics of different materials at the same time. Different dielectric materials make the contact resistance of the top electrode 5 and the dielectric layer more differentiated, which can further improve the resistance range between the low resistance state and the high resistance state, thereby improving the switching characteristics of the resistance, and can improve the randomness range of the resistance through a larger resistance range.

[0056] It can be understood that in this embodiment, the first dielectric layer 3 and the second dielectric layer 4 are configured with different materials. Different materials can increase the random fluctuation range of the internal contact resistance of the resistive memory device. As the fluctuation range increases, the range of randomness of the resistance of the resistor device increases. Further, as the contact surface becomes larger, the current channel increases, thereby improving the resistance switching characteristics.

[0057] In the specific setting, the upper part of the top electrode 5 can completely cover the first dielectric layer 3, that is, one side of the upper part of the top electrode 5 is in contact with the upper surface of the entire first dielectric layer 3, and the thickness of the first dielectric layer 3 is lower than the depth of the through hole 21, so that the upper surface of the first dielectric layer 3 is located in the through hole 21, and the entire top electrode 5 is set to protrude from the through hole 21, which makes the top electrode 5 have better connection structure strength and can contact with the first dielectric layer 3 to increase the contact area of ​​the top electrode 5.

[0058] According to an embodiment of the present invention, the resistive memory device further includes a support structure 2, which is disposed on the bottom electrode 1 and has a through hole 21 therein; the first dielectric layer 3 is embedded in the through hole 21. In this embodiment, the support structure 2 is a main structure for forming a device during preparation, and can realize the preparation of various components, as well as the stacking and integration of multi-layer devices. The support structure 2 can improve the overall stability of the device and the structural strength of the overall device.

[0059] In the specific setting, the support structure 2 is constructed as a closed-loop structure, with a through hole 21 in the middle of the support structure 2, and each device is arranged in the through hole 21, wherein the bottom of the support structure 2 is connected to the bottom electrode 1, and the support structure 2 is used for the formation of the top electrode 5 and the dielectric layer.

[0060] like Figure 1 As shown, in a specific embodiment, the support structure 2 is constructed as a square structure, the bottom of the support structure 2 is connected to the bottom electrode 1, and the top edge of the support structure 2 is exposed, that is, the top electrode 5 extends along the edge of the support structure 2, and the top electrode 5 does not completely cover the top surface of the support structure 2, which enables the support structure 2 to provide better supporting strength for the top electrode 5 and effectively realize the stability inside the device.

[0061] In the above embodiment, the thickness of the first dielectric layer 3 is 6 nanometers to 15 nanometers, and the thickness of the second dielectric layer 4 is 2 nanometers to 5 nanometers.

[0062] The thickness of the dielectric layer is determined by the process design of the device itself and the device requirements. In this embodiment, the first dielectric layer 3 is located in the through hole 21 and extends along the extension direction of the through hole 21, that is, the first dielectric layer 3 can occupy a larger space of the through hole 21, the bottom of the first dielectric layer 3 contacts the bottom electrode 1, the top of the first dielectric layer 3 contacts the top electrode 5, and a through through hole 21 is provided in the middle of the first dielectric layer 3. In order to effectively increase the contact area and consider the performance requirements, in this embodiment, the thickness of the first dielectric layer 3 is limited to 6 nanometers to 15 nanometers, which makes the first dielectric layer 3 occupy more space in the through hole 21 and makes the hole 31 pass through the first dielectric layer 3. The second dielectric layer 4 is located in the hole 31. In order to increase the contact area between the top electrode 5 and the first dielectric layer 3, the thickness of the second dielectric layer 4 is set to be lower than the thickness of the first dielectric layer 3, and the inner wall of the hole 31 in the first dielectric layer 3 contacts the top electrode 5, thereby increasing the contact area between the top electrode 5 and the dielectric layer.

[0063] In the specific setting, the first dielectric layer 3 is set to 6 nanometers-15 nanometers, and the second dielectric layer 4 is set to 2 nanometers-5 nanometers. The thickness of the second dielectric layer 4 and the first dielectric layer 3 is restricted so that the second dielectric layer 4 is located at the bottom of the hole 31 of the first dielectric layer 3, which enables sufficient space in the first dielectric layer 3 to accommodate the top electrode 5, and can provide a larger contact area for the contact between the top electrode 5 and the first dielectric layer 3.

[0064] The following is a description of a method for preparing a resistive memory device provided by any of the above embodiments. The following preparation method and the above resistive memory device can be described with reference to each other.

[0065] The present invention also provides a method for preparing a resistive memory device, comprising the steps of:

[0066] Step 100, forming a through hole 21 by patterning on the bottom electrode 1;

[0067] Step 200, forming a first dielectric layer 3 in the through hole 21 by using a deposition process;

[0068] Step 300: forming at least one cavity 31 in the first dielectric layer 3 by using a stripping or etching process;

[0069] Step 400: forming a second dielectric layer 4 at the bottom of the cavity 31 by a deposition process;

[0070] Step 500 : forming a top electrode 5 on the second dielectric layer 4 by a deposition process, and at least a portion of the top electrode 5 is located in the cavity 31 .

[0071] In the above-mentioned preparation method, Figure 2 , Figure 3 As shown, Figure 3 for Figure 2 In the top view of the structure, in step 100, a through hole 21 is formed on the upper surface of the bottom electrode 1 by micro-nano processing technology. Specifically, a silicon dioxide layer is formed on the bottom electrode 1 by a deposition process, and the through hole 21 is processed on the silicon dioxide layer by a stripping process or an etching process, so that a ring-shaped through hole 21 is formed.

[0072] In this embodiment, the through hole 21 can be formed into a rectangular, circular or any other cross-sectional shape by changing processing parameters. In a specific example, a through hole 21 processed into a rectangular shape is used for exemplary description. Figure 3 As shown, the silicon dioxide layer is constructed as a rectangular closed ring structure, the middle of which is a through hole 21. In the subsequent process, operations are performed in the through hole 21 to finally form a memory device. That is, the silicon dioxide layer in the rectangular closed ring structure in the figure is the support structure 2 of the entire resistive memory device, and the support structure 2 can make the device structure more stable.

[0073] Continue as Figure 2 , Figure 3 As shown, step 200 specifically includes: using one of an atomic layer deposition process, a physical vapor deposition process, a chemical vapor deposition process and an electron beam evaporation process to deposit at least one of titanium oxide, fluoride hydroxide, zirconium oxide, aluminum oxide, silicon oxide and perovskite oxide into the through hole 21 to form a first dielectric layer 3.

[0074] like Figure 4 and Figure 5 As shown, Figure 5 yes Figure 4 The top view after the process preparation, step 300 specifically includes: using a stripping or etching process to process a hole 31 in the middle of the first dielectric layer 3, the hole 31 penetrates the first dielectric layer 3, so that the bottom electrode 1 can be exposed from the hole 31.

[0075] like Figure 6 and Figure 7 As shown, Figure 7 yes Figure 6 A top view after the process preparation, in step 400, at least one of titanium oxide, fluoride hydroxide, zirconium oxide, aluminum oxide, silicon oxide and perovskite oxide is deposited into the through hole 21 to form a second dielectric layer 4 by using one of an atomic layer deposition process, a physical vapor deposition process, a chemical vapor deposition process and an electron beam evaporation process, and the thickness of the second dielectric layer 4 is controlled so that the second dielectric layer 4 does not exceed the middle of the hole 31, and the bottom of the second dielectric layer 4 is connected to the bottom electrode 1.

[0076] It can be understood that the material deposited in the first dielectric layer 3 and the material deposited in the second dielectric layer 4 can be selected from the same material setting, or different materials can be selected for separate deposition. The solution of this embodiment provides an effective and feasible solution for the same electrode to contact two different dielectric materials at the same time, thereby improving the flexibility of the resistive switching device design and enabling contact between multiple materials and electrodes.

[0077] like Figure 8 and Fig. 9 As shown, Fig. 9 yes Figure 8 The top view after the process preparation, in step 500, at least one of palladium, palladium alloy, titanium, titanium alloy, titanium nitride, zirconium alloy, ruthenium, ruthenium alloy, tantalum, tantalum alloy, tantalum nitride, single crystal silicon, polycrystalline silicon, platinum, platinum alloy, hafnium, hafnium alloy, aluminum, aluminum alloy, tungsten, tungsten alloy, iridium, iridium alloy is deposited on the second dielectric layer 4 by using one of atomic layer deposition process, physical vapor deposition process, chemical vapor deposition process and electron beam evaporation process. In this embodiment, the second dielectric layer is located at the bottom of the cavity 31, the bottom of the top electrode 5 is located in the cavity 31 and connected to the second dielectric layer 4, and the inner wall of the cavity 31 is the first dielectric layer 3, and the top electrode 5 is also connected to the inner wall of the cavity 31, so that there is a large contact area between the top electrode 5 and the dielectric layer.

[0078] In the specific configuration, when the top electrode 5 is deposited, the upper surface of the top electrode 5 completely covers the upper surface of the first dielectric layer 3, so that the upper surface of the first dielectric layer 3 is in contact with the top electrode 5, and the upper surface of the second dielectric layer 4 is in contact with the lower surface of the top electrode 5. The configuration of this embodiment enables the top electrode 5 to increase the contact area by contacting the inner wall surface of the cavity 31, thereby increasing the contact area between the electrode and the dielectric layer.

[0079] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can increase the contact area between the top electrode 5 and the dielectric layer, thereby improving the switching characteristics of the device resistance. Furthermore, by dividing the dielectric layer into the first dielectric layer 3 and the second dielectric layer 4, the first dielectric layer 3 and the second dielectric layer 4 can be arranged with different materials, and the top electrode 5 can contact the first dielectric layer 3 and the second dielectric layer 4 at the same time, thereby achieving a greater resistance value difference, which can further improve the resistance random fluctuation range of the resistive memory device.

[0080] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A resistive memory device, characterized in that: include: bottom electrode; A first dielectric layer is disposed on the bottom electrode, and the first dielectric layer has at least one hole; A second dielectric layer, embedded in the bottom of the cavity, wherein the bottom surface of the second dielectric layer is in contact with the bottom electrode; A top electrode is disposed in the cavity, and at least a portion of the top electrode contacts an upper surface of the first dielectric layer.

2. The resistive memory device according to claim 1, characterized in that: It also includes a supporting structure, which is arranged on the bottom electrode and has a through hole in it; the first dielectric layer is embedded in the through hole.

3. The resistive memory device according to claim 1 or 2, characterized in that: The thickness of the second dielectric layer is smaller than the depth of the cavity, so that at least a portion of the top electrode is located in the cavity and contacts the second dielectric layer.

4. The resistive memory device according to claim 1 or 2, characterized in that: The thickness of the first dielectric layer is 6 nanometers to 15 nanometers.

5. The resistive memory device according to claim 4, characterized in that: The thickness of the second dielectric layer is 2 nanometers to 5 nanometers.

6. The resistive memory device according to claim 1, characterized in that: The first dielectric layer and the second dielectric layer are made of different materials.

7. A method for preparing the resistive memory device according to any one of claims 1 to 6, characterized in that: Includes steps: performing a patterning operation on the bottom electrode to form a through hole; forming a first dielectric layer in the through hole by a deposition process; forming at least one cavity in the first dielectric layer by using a stripping or etching process; forming a second dielectric layer at the bottom of the cavity by a deposition process; A top electrode is formed on the second dielectric layer by using a deposition process, and at least a portion of the top electrode is located in the cavity.

8. The preparation method according to claim 7, characterized in that: The step of patterning the bottom electrode to form a through hole specifically includes: forming a silicon dioxide layer on the bottom electrode by a deposition process; The through hole is processed on the silicon dioxide layer by using a stripping process or an etching process.

9. The preparation method according to claim 7, characterized in that: forming a first dielectric layer in the through hole by using a deposition process; and, forming a second dielectric layer at the bottom of the cavity by a deposition process, specifically comprising: At least one of titanium oxide, fluorinated hydroxide, zirconium oxide, aluminum oxide, silicon oxide and perovskite oxide is deposited using one of atomic layer deposition, physical vapor deposition, chemical vapor deposition and electron beam evaporation processes.

10. The preparation method according to claim 7, characterized in that: The step of forming the top electrode by a deposition process specifically comprises: At least one of palladium, palladium alloy, titanium, titanium alloy, titanium nitride, zirconium alloy, ruthenium, ruthenium alloy, tantalum, tantalum alloy, tantalum nitride, single crystal silicon, polycrystalline silicon, platinum, platinum alloy, hafnium, hafnium alloy, aluminum, aluminum alloy, tungsten, tungsten alloy, iridium, and iridium alloy is deposited on the second dielectric layer using one of an atomic layer deposition process, a physical vapor deposition process, a chemical vapor deposition process, and an electron beam evaporation process.

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