MRAM (Magnetic Random Access Memory) device with OTP (One Time Programmable) unit and preparation method

Abstract

The invention discloses an MRAM (Magnetic Random Access Memory) device with an OTP (One Time Programmable) unit and a preparation method, which are applied to the technical field of MRAM devices, and the preparation method comprises the following steps: arranging a top wiring mask on the surface of a chip provided with a magnetic tunnel junction; the top connection line mask corresponds to an etching position of a preset OTP region and comprises at least one side wall of a magnetic tunnel junction of the OTP region; the chip is etched based on the top connection line mask until the magnetic tunnel junction in the OTP area corresponds to the side wall of the etching position, and an insulating layer of the magnetic tunnel junction is damaged; and filling a top connecting line groove formed by etching the chip with a conductive medium to form a top connecting line. And the optimization of the MRAM OTP in the writing direction is realized by etching and damaging the insulating layer on at least one side of the magnetic tunnel junction. And the front-end process of the preparation process is compatible with other processes, and a photomask is not additionally added, so that the MRAM device with the OTP unit can be manufactured with lower cost.

Description

Technical Field

[0001] The present invention relates to the technical field of MRAM devices, and in particular to a method for preparing an MRAM device with an OTP unit and an MRAM device with an OTP unit. Background Art

[0002] The main component of spin-transfer torque magnetoresistive random access memory (STT-MRAM) is magnetic tunnel junctions (MTJ), which are composed of a magnetic free layer, a tunnel barrier insulating layer and a fixed magnetic layer. As a non-volatile memory, MRAM (Magnetoresistive Random Access Memory) has the advantages of low power, high speed and high write durability. Using MRAM as a one-time storage array unit (One Time Programmable, OTP) provides an ideal solution for coded storage, trimmed storage, encryption keys or any data that needs to be reliably stored throughout the life of the chip.

[0003] The one-time write and multiple-read method of MRAM OTP is as follows: by applying a breakdown voltage to the MTJ in the OTP array, the target MTJ is short-circuited and its state is rewritten to a low resistance value ("0"). The resistance of the MTJ that has not been broken down is higher ("1"), thereby storing information, and its breakdown state cannot be changed. Figure 1 Schematic diagram of a short circuit during OTP writing, where P indicates that the MTJ is in a parallel state, and AP indicates that the MTJ is in an anti-parallel state; Figure 2 This is a reference window diagram for reading OTP MRAM cells. Figure 2 As shown, when reading information, the resistance of the MRAM in the breakdown state is lower than the reference resistance of the OTP, and the resistance of the MRAM in the non-breakdown state is higher than the reference resistance of the OTP.

[0004] Therefore, in the prior art, if OTP MRAM and MTP (Multiple-Time Programmable) MRAM arrays are manufactured using the same process, the problem of insufficient programming voltage when writing to the OTP MRAM cell needs to be solved. Therefore, how to solve the problem of insufficient programming voltage when writing to the OTP MRAM cell is an urgent problem to be solved by those skilled in the art. Summary of the invention

[0005] The object of the present invention is to provide a method for preparing an MRAM device with an OTP unit, which can reduce the breakdown voltage required when the OTP MRAM unit is written; another object of the present invention is to provide an MRAM device with an OTP unit, which can reduce the breakdown voltage required when the OTP MRAM unit is written.

[0006] In order to solve the above technical problems, the present invention provides a method for preparing an MRAM device having an OTP unit, which is characterized by comprising:

[0007] A top wiring mask is arranged on the surface of a chip provided with a magnetic tunnel junction; the top wiring mask corresponds to an etching position of a preset OTP region, including at least one side wall of the magnetic tunnel junction of the OTP region;

[0008] Etching the chip based on the top wiring mask until the magnetic tunnel junction of the OTP region corresponds to the sidewall of the etching position, thereby damaging the insulating layer of the magnetic tunnel junction;

[0009] A conductive medium is filled in a top connection groove formed by etching the chip to form a top connection.

[0010] Optionally, the top connection mask corresponds to an etching position of a preset MTP region, and corresponds to a hard mask at the top of the magnetic tunnel junction of the MTP region;

[0011] The etching of the chip based on the top wiring mask comprises:

[0012] The chip is etched based on the top wiring mask to expose the hard mask.

[0013] Optionally, the top connection mask corresponds to an etching position of a preset OTP region and is offset toward one side of the magnetic tunnel junction in the OTP region so that the etching position includes the side wall of the magnetic tunnel junction in the OTP region in the offset direction and a portion of the hard mask on the top of the magnetic tunnel junction.

[0014] Optionally, the etching size of the top wiring mask corresponding to the preset OTP area is larger than the size of the hard mask at the top of the magnetic tunnel junction in the OTP area, so that the top wiring mask corresponds to the etching position of the OTP area, including the side walls around the magnetic tunnel junction in the OTP area, and the hard mask at the top of the magnetic tunnel junction.

[0015] Optionally, the step of providing a top connection mask on the surface of a chip provided with a magnetic tunnel junction includes:

[0016] Based on the photolithography process, a top connection mask is arranged on the surface of the chip where the magnetic tunnel junction is arranged.

[0017] Optionally, etching the chip based on the top wiring mask until a side wall of the magnetic tunnel junction in the OTP region corresponding to the etching position is damaged to damage the insulating layer of the magnetic tunnel junction comprises:

[0018] Performing a first etching on the chip based on the top wiring mask, so that the stop point of the first etching in the OTP region is located below the insulating layer in the magnetic tunnel junction, and removing the protective layer on the side wall surface of the magnetic tunnel junction corresponding to the etching position based on the first etching, and damaging the insulating layer from the side wall etching corresponding to the etching position;

[0019] After the insulating layer is damaged by etching, a dielectric protection layer is provided on the side wall surface of the magnetic tunnel junction corresponding to the etching position.

[0020] Optionally, the stopping point is located below the bottom protection layer of the magnetic tunnel junction.

[0021] Optionally, the stopping point is located at an upper surface of the bottom protection layer of the magnetic tunnel junction.

[0022] Optionally, the stopping point is located in a dielectric layer between the magnetic tunnel junction bottom protection layer and the insulating layer.

[0023] Optionally, after the insulating layer is damaged by etching, providing a dielectric protection layer on the side wall surface of the magnetic tunnel junction corresponding to the etching position includes:

[0024] depositing a dielectric protection layer in the top wiring groove;

[0025] The dielectric protection layer on the top surface of the hard mask is removed based on selective etching.

[0026] Optionally, etching the chip based on the top wiring mask until a side wall of the magnetic tunnel junction in the OTP region corresponding to the etching position is damaged to damage the insulating layer of the magnetic tunnel junction comprises:

[0027] Performing a second etching on the chip based on the top wiring mask, so that the stop point of the second etching in the OTP region is located below the insulating layer in the magnetic tunnel junction, while retaining a protective layer on the side wall surface of the magnetic tunnel junction corresponding to the etching position;

[0028] The insulating layer is damaged from the side wall corresponding to the etching position through the protection layer by means of ion implantation or plasma bombardment.

[0029] Optionally, the stopping point is located at an upper surface of the bottom protection layer of the magnetic tunnel junction.

[0030] Optionally, the stopping point is located in a dielectric layer between the magnetic tunnel junction bottom protection layer and the insulating layer.

[0031] Optionally, during operation, the breakdown position of the magnetic tunnel junction in the OTP region is located at the insulating layer of the magnetic tunnel junction, or at the sidewall dielectric layer of the magnetic tunnel junction corresponding to the etching position.

[0032] The present invention also provides an MRAM device having an OTP unit, including the OTP unit, wherein the OTP unit includes:

[0033] A substrate; the substrate is divided into an OTP area;

[0034] A magnetic tunnel junction located on the surface of the substrate and distributed in the OTP region; the magnetic tunnel junction comprises a fixed layer located on the surface of the substrate, an insulating layer located on a surface of the fixed layer facing away from the substrate, and a free layer located on a surface of the insulating layer facing away from the substrate; the insulating layer of the magnetic tunnel junction located in the OTP region has etching damage;

[0035] A hard mask film located on a surface of the magnetic tunnel junction facing away from the substrate;

[0036] A top connection line connected to the hard mask; the top connection line extends to the sidewall of the magnetic tunnel junction where the etching damage occurs.

[0037] The present invention provides a method for preparing an MRAM device with an OTP unit, comprising: setting a top connection mask on the surface of a chip provided with a magnetic tunnel junction; the top connection mask corresponds to an etching position of a preset OTP region, including at least one side wall of the magnetic tunnel junction of the OTP region; etching the chip based on the top connection mask until the side wall of the magnetic tunnel junction of the OTP region corresponds to the etching position, and etching the insulating layer of the magnetic tunnel junction; filling a conductive medium in a top connection groove formed by etching the chip to form a top connection.

[0038] When preparing the MRAM device, specifically when setting the top connection, by adjusting the etching position of the top connection mask, at least one side wall of the magnetic tunnel junction in the OTP area is etched, the insulating layer in the magnetic tunnel junction in the OTP area is damaged, the breakdown voltage of the OTP storage bit is reduced, and the MRAM OTP is optimized in the writing direction. The front-end process of the above-mentioned preparation process is compatible with other processes and does not require additional photomasks, thereby realizing the production of an MRAM device with an OTP unit at a lower cost based on the existing preparation process.

[0039] The present invention further provides an MRAM device having an OTP unit, which also has the above-mentioned beneficial effects, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0041] Figure 1 This is a schematic diagram of a short circuit during OTP writing;

[0042] Figure 2 Schematic diagram of the reference window when reading the OTP MRAM cell;

[0043] Figure 3 It is a structural schematic diagram of the first OTP MRAM unit in the prior art;

[0044] Figure 4 It is a structural schematic diagram of a second OTP MRAM cell in the prior art;

[0045] Figures 5 and 6 A process flow chart of a method for preparing an MRAM device with an OTP unit provided by an embodiment of the present invention;

[0046] Figures 7 to 9 A process flow chart of a first specific method for preparing an MRAM device with an OTP unit provided by an embodiment of the present invention;

[0047] Figures 10 to 15 for Figure 7 Schematic diagram of the structure corresponding to different stopping points;

[0048] Figures 16 to 18 A process flow chart of a second specific method for preparing an MRAM device with an OTP unit provided by an embodiment of the present invention;

[0049] Figures 19 to 22 for Fig.16 Schematic diagram of the structure corresponding to different stopping points.

[0050] In the figure: 1. magnetic tunnel junction, 2. hard mask, 3. protective layer, 4. top connection, 5. OTP area, 6. MTP area, 7. top connection mask, 8. top connection groove, 9. dielectric protection layer, 10. seed layer, 11. insulating layer. DETAILED DESCRIPTION

[0051] The core of the present invention is to provide a method for preparing an MRAM device with an OTP unit. In the prior art, there are two common optimization solutions to solve the problem of insufficient programming voltage when writing OTP MRAM cells. The first one, please refer to Figure 3 , Figure 3 Schematic diagram of the structure of the first OTP MRAM cell in the prior art. Figure 3 In order to increase the voltage division of the OTP MRAM cell and reduce the size of the OTP MRAM cell, the OTP MRAM cell size is smaller than the MTP MRAM cell size to increase the resistance of the OTP MRAM cell size. However, the miniaturization of the OTP MRAM cell size will lead to poor manufacturing uniformity and high process requirements.

[0052] For the second one, please refer to Figure 4 , Figure 4 FIG. 1 is a schematic diagram of the structure of the second OTP MRAM cell in the prior art. Figure 4 , this structure is to reduce the breakdown voltage of OTP MRAM memory devices. The MTJ part of the OTP MRAM cell is deposited on the bottom electrode, and a thinner insulating layer is formed by the height difference between the bottom electrode and the surrounding dielectric layer to reduce the breakdown voltage. However, when the MTJ is etched, a large area of ​​the bottom metal is exposed and splashed by etching, which can easily cause the MTJ to short-circuit.

[0053] The method for preparing an MRAM device with an OTP unit provided in an embodiment of the present invention includes: setting a top connection mask on the surface of a chip provided with a magnetic tunnel junction; the top connection mask corresponds to an etching position of a preset OTP area, including at least one side wall of the magnetic tunnel junction of the OTP area; etching the chip based on the top connection mask until the side wall of the magnetic tunnel junction of the OTP area corresponds to the etching position, thereby damaging the insulating layer of the magnetic tunnel junction; and filling a conductive medium in a top connection groove formed by etching the chip to form a top connection.

[0054] When preparing the MRAM device, specifically when setting the top connection, by adjusting the etching position of the top connection mask, at least one side wall of the magnetic tunnel junction in the OTP area is etched, and the insulating layer of the magnetic tunnel junction in the OTP area is damaged by etching, the breakdown voltage of the OTP storage bit is reduced, and the MRAM OTP is optimized in the writing direction. The front-end process of the above-mentioned preparation process is compatible with other processes and does not add additional masks, so that the MRAM device with OTP unit can be manufactured at a lower cost based on the existing preparation process.

[0055] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0056] Please refer to Figure 5 as well as Figure 6 , Figures 5 and 6 A process flow chart of a method for preparing an MRAM device with an OTP unit provided by an embodiment of the present invention.

[0057] See also Figure 5 In an embodiment of the present invention, a method for preparing an MRAM device having an OTP unit includes:

[0058] S101: a top connection mask is provided on the surface of the chip where the magnetic tunnel junction is provided.

[0059] In the embodiment of the present invention, the top connection mask 7 corresponds to the etching position of the preset OTP region 5 , including at least one side wall of the magnetic tunnel junction 1 of the OTP region 5 .

[0060] The magnetic tunnel junction 1 generally includes a fixed layer, a free layer, and an insulating layer 11 between the fixed layer and the free layer. The fixed layer is also generally referred to as a reference layer. The magnetization direction of the reference layer is fixed, and the device does not flip when the device is working; the magnetization direction of the free layer is collinear with the magnetization direction of the fixed layer (parallel P or antiparallel AP). By utilizing the spin torque of electrons, the magnetization direction of the free layer can be flipped to achieve parallel (lower resistance) or antiparallel (higher resistance) magnetization directions of the fixed layer and the free layer to achieve data "0" and "1" writing. The insulating layer 11 is also referred to as a barrier layer, which is generally composed of oxide. Generally speaking, the magnetic tunnel junction 1 is generally trapezoidal, and has sidewalls that extend obliquely. It should be noted that in the present application, the shape of the magnetic tunnel junction 1 is not limited to a trapezoid, and its sidewalls can also extend in a vertical direction, that is, the cross-section of the magnetic tunnel junction 1 can also be in other shapes with sidewalls such as a rectangle. For example, when the sidewalls of the magnetic tunnel junction 1 extend in a vertical direction, the subsequent etching process can also etch its sidewalls.

[0061] In this embodiment, the insulating layer 11 in the magnetic tunnel junction 1 is damaged by etching, resulting in poor quality of the sidewall of the insulating layer 11, which is more prone to breakdown, thereby reducing the breakdown voltage of the OTP storage bit. In this embodiment, the insulating layer 11 in the magnetic tunnel junction 1 is etched when the top connection 4 (top metal, TM) is made. It should be noted that in this application, only the insulating layer 11 in the magnetic tunnel junction 1 is etched and damaged, and the size of the magnetic tunnel junction 1 will not be actually reduced.

[0062] The chip provided with the magnetic tunnel junction 1 is pre-set with the magnetic tunnel junction 1, and a hard mask 2 (HM) is provided on the top of the magnetic tunnel junction 1, a protective layer 3 is provided on the surface around the magnetic tunnel junction 1, and a dielectric layer is filled between the magnetic tunnel junctions 1. The hard mask 2 is usually a metal mask, which is directly in contact with and electrically connected to the magnetic tunnel junction 1. The protective layer 3 at least needs to cover the sidewalls of the magnetic tunnel junction 1, and usually also covers the surface of the substrate on which the magnetic tunnel junction 1 is provided. The protective layer 3 can be specifically silicon nitride SiN, and of course the protective layer 3 can also be other materials, which are not specifically limited here.

[0063] In this step, a top wiring mask 7 will be set based on the surface of the above-mentioned chip, and the top wiring mask 7 is a mask for preparing the top wiring 4. Specifically, in this step, the mask can be set based on the photolithography process, so this step can specifically include: based on the photolithography process, a top wiring mask 7 is set on the surface of the chip with a magnetic tunnel junction 1. The top wiring mask 7 set based on the photolithography process usually includes spin-on carbon (SOC), low temperature oxide (LTO), bottom anti-reflective coating (BARC), and photoresist (PR) from bottom to top. The mask structure formed by the photolithography process can refer to the prior art and will not be repeated here. Of course, in this step, other structures of the top wiring mask 7 can also be set by other processes, which is not specifically limited here. In this step, it is usually necessary to use a photomask to achieve the setting of the top wiring mask 7.

[0064] In this embodiment, the MRAM device generally includes both an OTP MRAM unit, i.e., a unit for realizing a one-time storage function, and an MTP MRAM unit, i.e., a unit suitable for realizing a multiple-time storage function. Therefore, in this embodiment, the chip provided with a magnetic tunnel junction 1 is generally divided into an OTP region 5 and an MTP region 6. The OTP region 5 is used to set the OTP MRAM unit, and the MTP region 6 is used to set the MTP MRAM unit. In this embodiment, the top wiring mask 7 has an etching position corresponding to the preset OTP region 5, i.e., when the chip is etched based on the top wiring mask 7, the specific position to be etched, and the etching position needs to include at least one side wall of the magnetic tunnel junction 1 in the OTP region 5, so as to realize the etching of the insulating layer 11 of the magnetic tunnel junction 1 in the OTP region 5.

[0065] It should be noted that the preparation method provided in this embodiment can realize the simultaneous preparation of OTP MRAM cells and MTP MRAM cells, so the top wiring mask 7 can also have an etching position corresponding to the preset MTP region 6, and the etching position can only correspond to the hard mask 2 located at the top of the magnetic tunnel junction 1 in the MTP region 6, so as to avoid damaging the magnetic tunnel junction 1 in the MTP region 6 when etching the magnetic tunnel junction 1 in the OTP region 5. That is, in this embodiment, the top wiring mask 7 corresponds to the etching position of the preset MTP region 6, and corresponds to the hard mask 2 at the top of the magnetic tunnel junction 1 in the MTP region 6. In other words, in this embodiment, the hollow morphology of the top wiring mask 7 located in the OTP region 5 is usually different from the hollow morphology located in the MTP region 6.

[0066] S102: etching the chip based on the top wiring mask until the sidewall of the magnetic tunnel junction in the OTP region corresponds to the etching position, thereby damaging the insulating layer of the magnetic tunnel junction.

[0067] In this step, the chip will be etched based on the top connection mask 7. For the OTP region 5, the etching process will penetrate the dielectric layer between the magnetic tunnel junctions 1, and for the etching stop position of the OTP region 5, a part of it will stop on the surface of the hard mask 2 at the top of the magnetic tunnel junction 1 to ensure that the final top connection 4 can be electrically connected to the magnetic tunnel junction 1 through the hard mask 2; and the other part will continue to etch along the side wall of the magnetic tunnel junction 1 to the bottom of the magnetic tunnel junction 1, and this part needs to at least stop below the position of the insulating layer 11 in the magnetic tunnel junction 1, that is, expose the insulating layer 11 in the magnetic tunnel junction 1, so as to etch and damage the insulating layer 11.

[0068] After the above-mentioned insulating layer 11 is exposed, it is necessary to etch and damage the insulating layer 11 in this step, resulting in poor quality of the sidewalls of the insulating layer 11, which is more easily broken down, thereby reducing the breakdown voltage of the OTP MRAM unit to adapt to a lower programming voltage. The specific method of etching the insulating layer 11 will be described in detail in the following embodiments of the invention and will not be repeated here. During the etching process in this embodiment, due to the presence of the hard mask 2 in the OTP region 5 and the corresponding etching position of the above-mentioned top connection mask 7 in the OTP region 5, there are two cut-off positions for etching in the OTP region 5: one is located on the surface of the hard mask 2, and the other is located below the insulating layer 11 in the magnetic tunnel junction 1, so as to expose the insulating layer 11 from the sidewalls of the magnetic tunnel junction 1.

[0069] As for the above-mentioned MTP region 6, this step includes: etching the chip based on the top wiring mask 7 to expose the hard mask 2. That is, in the MTP region 6, the etching position of this step will be terminated on the surface of the hard mask 2 due to the existence of its hard mask 2, and the magnetic tunnel junction 1 will not be exposed. At this time, this etching step will form grooves with different morphologies in the MTP region 6 and the OTP region 5. The grooves located in the MTP region 6 only expose the hard mask 2, while the grooves in the OTP region 5 will expose at least part of the hard mask 2 and at least one side wall of the magnetic tunnel junction 1. It should be noted that the stopping point of etching in this step needs to be based on the above-mentioned stopping point at which the insulating layer 11 is exposed on the side wall of the magnetic tunnel junction 1, that is, in this step, the above-mentioned grooves are usually formed only by etching at this time.

[0070] S103: Filling a conductive medium in the top connection groove formed by etching the chip to form a top connection.

[0071] See also Figure 6 In this step, a conductive medium is filled in the top connection groove 8 formed by etching the above chip to form a top connection 4. The top connection 4 needs to be electrically connected to the magnetic tunnel junction 1 through the hard mask 2 set on the top of each magnetic tunnel junction 1, and the groove in the above OTP area 5 extends downward along the side wall of the magnetic tunnel junction 1. Therefore, for the OTP area 5, a protective layer 3 needs to be formed or retained between the side wall of the magnetic tunnel junction 1 and the top connection 4 for insulation, so that in the OTP area 5, the top connection 4 is still electrically connected to the magnetic tunnel junction 1 through the hard mask 2 set on the top of each magnetic tunnel junction 1.

[0072] The top connection line 4 is usually made of metal, but it can also be a conductive medium of other materials. There is no specific limitation on the specific material of the top connection line 4. The conductive medium includes but is not limited to Cu, Al, and the like.

[0073] It should be noted that in the present application, when the MRAM device is working, the breakdown position of the magnetic tunnel junction 1 in the OTP region 5 is located at the insulating layer 11 of the magnetic tunnel junction 1, or at the sidewall dielectric layer of the magnetic tunnel junction 1 corresponding to the etching position. That is, in the MRAM device with an OTP unit provided in this embodiment, when the OTP unit is working, the process of breaking down the magnetic tunnel junction 1 in the above-mentioned OTP region 5 can be specifically to break down from the sidewall of the magnetic tunnel junction 1, and it can specifically break down the protective layer 3 or the dielectric protective layer 9 located on the sidewall of the magnetic tunnel junction 1; that is, the above-mentioned sidewall dielectric layer generally includes the protective layer 3 or the dielectric protective layer 9 located on the sidewall of the magnetic tunnel junction 1. Of course, in this embodiment, the above-mentioned process of breaking down the magnetic tunnel junction 1 in the above-mentioned OTP region 5 can also be specifically to conventionally break down the insulating layer 11 of the magnetic tunnel junction 1 in the above-mentioned OTP region 5.

[0074] The method for preparing an MRAM device with an OTP unit provided in an embodiment of the present invention is to etch at least one side wall of the magnetic tunnel junction 1 of the OTP region 5 by adjusting the etching position of the top connection mask 7 when setting the top connection 4 during the preparation of the MRAM device, thereby damaging the insulating layer of the magnetic tunnel junction of the OTP MRAM unit, causing the poor quality of the side wall of the insulating layer 11 to be more easily broken down, thereby reducing the breakdown voltage of the OTP storage bit, and optimizing the MRAM OTP in the writing direction. The front-end process of the above-mentioned preparation process is compatible with other processes and does not require additional photomasks, thereby realizing the production of an MRAM device with an OTP unit at a lower cost based on the existing preparation process.

[0075] The specific process of the method for preparing an MRAM device with an OTP unit provided by the present invention will be described in detail in the following embodiments of the invention.

[0076] In the present application, two different top wiring masks 7 are specifically provided to form two different structures of top wiring grooves 8. At the same time, two different methods of etching the insulating layer 11 in the magnetic tunnel junction 1 and three different etching stop points are specifically provided. In the present application, the specific technical solutions of the present application are introduced by mainly distinguishing the etching methods.

[0077] Please refer to Figures 7 to 15 , Figures 7 to 9 A process flow chart of a first specific method for preparing an MRAM device with an OTP unit provided by an embodiment of the present invention; Figures 10 to 15 for Figure 7 Schematic diagram of the structure corresponding to different stopping points.

[0078] See also Figure 7 In an embodiment of the present invention, a method for preparing an MRAM device having an OTP unit includes:

[0079] S201: Setting a top connection mask on the surface of the chip where the magnetic tunnel junction is set.

[0080] In this embodiment, two specific top wiring masks 7 are provided, which differ in the size of the openings corresponding to the OTP region 5 and the corresponding etching positions. Figure 8 The top connection mask 7 corresponds to the etching position of the preset OTP region 5, and is offset to one side of the magnetic tunnel junction 1 in the OTP region 5, so that the etching position includes the side wall of the magnetic tunnel junction 1 of the OTP region 5 in the offset direction, and a portion of the hard mask 2 on the top of the magnetic tunnel junction 1.

[0081] In this structure, the window size of the top wiring mask 7 in the OTP region 5 is usually unchanged, and the window size of the top wiring mask 7 in the OTP region 5 can be the same as the window size in the MTP region 6. However, compared with the conventional etching position, the window position of the top wiring mask 7 in the OTP region 5 will be offset to one side of the magnetic tunnel junction 1, such as Figure 8 As shown, it can be shifted to the right, so that the etching position of the top connection mask 7 in the OTP area 5 is also shifted, so that a part of the etching position is located at the hard mask 2 on the top of the magnetic tunnel junction 1, and the other part is located at the side wall of the magnetic tunnel junction 1 in the offset direction, so as to ensure that the top connection 4 can be electrically connected to the magnetic tunnel junction 1 through the hard mask 2, while the insulating layer 11 can be damaged based on the etching of the side wall of the magnetic tunnel junction 1 exposed at the etching position.

[0082] The second one, see Fig. 9 The top wiring mask 7 corresponds to the etching size of the preset OTP area 5, which is larger than the size of the hard mask 2 at the top of the magnetic tunnel junction 1 in the OTP area 5, so that the top wiring mask 7 corresponds to the etching position of the OTP area 5, including the side walls around the magnetic tunnel junction 1 of the OTP area 5, and the hard mask 2 at the top of the magnetic tunnel junction 1.

[0083] In this structure, the window position of the top wiring mask 7 in the OTP region 5 is usually unchanged, and the center of the window position is usually aligned with the center of the hard mask 2 in this region. However, in this structure, the window size of the top wiring mask 7 in the OTP region 5 becomes larger, and the window size of the top wiring mask 7 in the OTP region 5 is usually larger than the window size in the MTP region 6. Fig. 9 As shown, since the window size of the top connection mask 7 in the OTP area 5 becomes larger, the corresponding etching position can not only include the surface of the hard mask 2, but also further include the side walls around the magnetic tunnel junction 1 in the area, so as to ensure that the top connection 4 can be electrically connected to the magnetic tunnel junction 1 through the hard mask 2, while the insulating layer 11 can be damaged based on the side wall etching of the magnetic tunnel junction 1 exposed at the etching position.

[0084] The specific process of setting the top wiring mask 7 has been described in detail in the above-mentioned embodiment of the invention, and will not be repeated here.

[0085] S202: Perform a first etching on the chip based on the top wiring mask, so that the stopping point of the first etching in the OTP area is located below the insulating layer in the magnetic tunnel junction, and at the same time, based on the first etching, remove the protective layer on the side wall surface of the magnetic tunnel junction corresponding to the etching position, and etch the damaged insulating layer from the side wall of the corresponding etching position.

[0086] In this step, the chip will be first etched through the top wiring mask 7, and the stop point of the first etching process needs to be located below the insulating layer 11 in the magnetic tunnel junction 1 of the OTP region 5 to form a top wiring groove 8. In the present application, the etching selectivity can be used to select whether the protective layer 3 around the magnetic tunnel junction 1 of the OTP region 5 is retained. The etching process introduced in this step can be used to select a suitable etching selectivity or other methods to etch away the protective layer 3 in the top wiring groove 8, exposing the side wall of the magnetic tunnel junction 1 of the OTP region 5 at the etching position, and in this etching process, the insulating layer 11 of the magnetic tunnel junction 1 is damaged by etching from the side wall of the corresponding etching position.

[0087] That is, in this step, the dielectric layer disposed on the chip surface will be etched first. Then, based on the determined etching selectivity, the exposed protection layer 3 will be etched away before etching to a preset stop point to expose the sidewall of the magnetic tunnel junction 1, and further etch the insulating layer 11 from the exposed sidewall. In this step, according to the different morphologies of the top wiring mask 7, the sidewall of the magnetic tunnel junction 1 etched in this step can be a sidewall on one side or a sidewall on all sides thereof, and the specific contents have been described in detail in the above content, and will not be repeated here.

[0088] Specifically, Fig.10 as well as Fig.11 As shown, the stop point may be located below the bottom protection layer 3 of the magnetic tunnel junction 1; Fig.12 as well as Fig.13 As shown, the stop point may be located on the upper surface of the bottom protective layer 3 of the magnetic tunnel junction 1; Fig.14 as well as Fig.15 As shown, the stop point may also be located in the dielectric layer between the bottom protection layer 3 of the magnetic tunnel junction 1 and the insulating layer 11. The specific position of the stop point can be set according to the actual situation, as long as it is located below the insulating layer 11 in the magnetic tunnel junction 1 to ensure that the insulating layer 11 can be etched and damaged. The different positions of the above stop points are usually achieved based on selecting different etching selectivities.

[0089] It should be emphasized that in this embodiment, the OTP region 5 and the MTP region 6 can be etched at the same time, and due to the blocking of the hard mask 2, part of the etching position in the OTP region 5 will stop at the top surface of the hard mask 2, and the etching position in the MTP region 6 will stop at the top surface of the hard mask 2. In this embodiment, whether through the first top wiring mask 7 or the second top wiring mask 7, the stop point can be at the above three positions.

[0090] S203: After etching the damaged insulating layer, a dielectric protection layer is provided on the side wall surface of the magnetic tunnel junction corresponding to the etching position.

[0091] Since the protective layer 3 on the side wall of the magnetic tunnel junction 1 will be removed in the above step, in order to avoid direct contact between the magnetic tunnel junction 1 and the top connection line 4, it is necessary to additionally set a dielectric protective layer 9 on the side wall of the magnetic tunnel junction 1. Therefore, in this step, after etching and damaging the insulating layer 11, a dielectric protective layer 9 is set on the side wall of the magnetic tunnel junction 1 corresponding to the etching position, that is, the side wall surface exposed in the above etching step. It should be noted that the dielectric protective layer 9 at least cannot cover the top surface of the hard mask 2, so as to ensure good contact between the top connection line 4 and the hard mask 2.

[0092] Specifically, this step may specifically include: depositing a dielectric protection layer 9 in the top wiring groove 8; and removing the dielectric protection layer 9 on the top surface of the hard mask 2 based on selective etching.

[0093] That is, in this step, a dielectric protection layer 9 can be first deposited in the top connection groove 8 by TEOS (tetraethoxysilane) or other materials. The deposition process can be carried out in the OTP area 5 and the MTP area 6 at the same time, that is, a dielectric protection layer 9 is deposited in the top connection groove 8 of the OTP area 5 and the top connection groove 8 of the MTP area 6 at the same time. Afterwards, based on selective etching, at least the dielectric protection layer 9 on the top surface of the hard mask 2 can be removed. It usually retains all the dielectric protection layers 9 deposited on the side and removes all the dielectric protection layers 9 deposited on the horizontal surface by selective etching. This process can remove the dielectric protection layer 9 deposited on the top surface of the hard mask 2 in the MTP area 6, the dielectric protection layer 9 deposited on the top surface of the hard mask 2 in the OTP area 5, and the dielectric protection layer 9 deposited on the bottom surface below the insulating layer 11 in the top connection groove 8; at least the dielectric protection layer 9 deposited on the side wall surface of the corresponding etching position of the magnetic tunnel junction 1 needs to be retained, and the dielectric protection layer 9 deposited on the inner side of the entire top connection groove 8 is usually retained. The dielectric protection layer 9 deposited on the sidewall of the non-magnetic tunnel junction 1 in the entire top connection groove 8 will not affect the interconnection between the top connection 4 and the hard mask 2 .

[0094] It should be noted that the material of the dielectric protection layer 9 can be the same as or different from the material of the protection layer 3 originally covering the side wall of the magnetic tunnel junction 1, depending on the specific situation, and is not specifically limited here. The material of the dielectric protection layer 9 includes but is not limited to TEOS, SiO2 and SiN. The method for depositing the dielectric protection layer 9 preferably uses atomic layer deposition, but chemical deposition, physical deposition, etc. can also be used for deposition.

[0095] S204: Filling a conductive medium in the top connection groove formed by etching the chip to form a top connection.

[0096] In this step, the top connection 4 can be completely made by first setting a seed layer 10 in the top connection groove 8, and then filling a conductive medium based on the seed layer 10 to form a top connection 4, so that the top connection 4 can be interconnected with the hard mask 2 and then interconnected with the magnetic tunnel junction 1. The specific process of filling the conductive medium can refer to the prior art and will not be repeated here. After the filling is completed in this step, the chip surface usually needs to be flattened, and the specific process of flattening is not specifically limited here.

[0097] The embodiment of the present invention provides a method for preparing an MRAM device with an OTP unit. The OTP MRAM and the MTPMRAM can be prepared simultaneously without requiring additional mask costs. The MTJs of the OTP region 5 and the MTP region 6 are of the same size, have good uniformity, and are stable in process. The characteristics of the MRAM itself can be used to obtain a faster read and write speed (greater unit density), and the application potential is great.

[0098] Please refer to Figures 16 to 22 , Figures 16 to 18 A process flow chart of a second specific method for preparing an MRAM device with an OTP unit provided by an embodiment of the present invention; Figures 19 to 22 for Fig.16 Schematic diagram of the structure corresponding to different stopping points.

[0099] See also Fig.16 In an embodiment of the present invention, a method for preparing an MRAM device having an OTP unit includes:

[0100] S301: Setting a top connection mask on the surface of the chip where the magnetic tunnel junction is set.

[0101] In this embodiment, two specific top wiring masks 7 are provided, which differ in the size of the openings corresponding to the OTP region 5 and the corresponding etching positions. Fig.17 The top connection mask 7 corresponds to the etching position of the preset OTP region 5, and is offset to one side of the magnetic tunnel junction 1 in the OTP region 5, so that the etching position includes the side wall of the magnetic tunnel junction 1 of the OTP region 5 in the offset direction, and a portion of the hard mask 2 on the top of the magnetic tunnel junction 1.

[0102] In this structure, the window size of the top wiring mask 7 in the OTP region 5 is usually unchanged, and the window size of the top wiring mask 7 in the OTP region 5 can be the same as the window size in the MTP region 6. However, compared with the conventional etching position, the window position of the top wiring mask 7 in the OTP region 5 will be offset to one side of the magnetic tunnel junction 1, such as Fig.17As shown, it can be shifted to the right, so that the etching position of the top connection mask 7 in the OTP area 5 is also shifted, so that a part of the etching position is located at the hard mask 2 on the top of the magnetic tunnel junction 1, and the other part is located at the side wall of the magnetic tunnel junction 1 in the offset direction, so as to ensure that the top connection 4 can be electrically connected to the magnetic tunnel junction 1 through the hard mask 2, while the insulating layer 11 can be damaged based on the etching of the side wall of the magnetic tunnel junction 1 exposed at the etching position.

[0103] The second one, see Fig.18 The top wiring mask 7 corresponds to the etching size of the preset OTP area 5, which is larger than the size of the hard mask 2 at the top of the magnetic tunnel junction 1 in the OTP area 5, so that the top wiring mask 7 corresponds to the etching position of the OTP area 5, including the side walls around the magnetic tunnel junction 1 of the OTP area 5, and the hard mask 2 at the top of the magnetic tunnel junction 1.

[0104] In this structure, the window position of the top wiring mask 7 in the OTP region 5 is usually unchanged, and the center of the window position is usually aligned with the center of the hard mask 2 in this region. However, in this structure, the window size of the top wiring mask 7 in the OTP region 5 becomes larger, and the window size of the top wiring mask 7 in the OTP region 5 is usually larger than the window size in the MTP region 6. Fig.18 As shown, since the window size of the top connection mask 7 in the OTP area 5 becomes larger, the corresponding etching position can not only include the surface of the hard mask 2, but also further include the side walls around the magnetic tunnel junction 1 in the area, so as to ensure that the top connection 4 can be electrically connected to the magnetic tunnel junction 1 through the hard mask 2, while the insulating layer 11 can be damaged based on the side wall etching of the magnetic tunnel junction 1 exposed at the etching position.

[0105] The specific process of setting the top wiring mask 7 has been described in detail in the above invention embodiment, and will not be repeated here. The specific structure of the top wiring mask 7 in this embodiment can refer to the specific structure of the top wiring mask 7 in the above invention embodiment, and will not be repeated here.

[0106] S302: performing a second etching on the chip based on the top wiring mask, so that the stop point of the second etching in the OTP region is located below the insulating layer in the magnetic tunnel junction, while retaining the protective layer on the side wall surface of the magnetic tunnel junction corresponding to the etching position.

[0107] In this step, the chip will be etched for the second time through the top wiring mask 7. The stop point of the second etching process needs to be located below the insulating layer 11 in the magnetic tunnel junction 1 of the OTP region 5 to form a top wiring groove 8. In this application, the etching selectivity can be used to select whether the protective layer 3 around the magnetic tunnel junction 1 of the OTP region 5 is retained, which is different from the first etching.

[0108] That is, in this step, the dielectric layer disposed on the chip surface will be etched first. Based on the determined etching selectivity, the exposed protection layer 3 will not be etched before etching to the preset stop point, the side wall of the magnetic tunnel junction 1 will not be directly exposed, and the insulating layer 11 will not be etched from the side wall. In this step, according to the different morphologies of the top wiring mask 7, the side wall of the magnetic tunnel junction 1 etched in the subsequent steps in this step can be a side wall on one side or a side wall on all sides, and the specific contents have been described in detail in the above content, and will not be repeated here.

[0109] Specifically, Fig.19 as well as Fig. 20 As shown, the stop point may be located on the upper surface of the bottom protective layer 3 of the magnetic tunnel junction 1; Fig.21 as well as Fig. 22 As shown, the stop point can also be located in the dielectric layer between the bottom protective layer 3 of the magnetic tunnel junction 1 and the insulating layer 11. The specific position of the stop point can be set according to the actual situation, as long as it is located below the insulating layer 11 in the magnetic tunnel junction 1 to ensure that the insulating layer 11 can be etched and damaged in subsequent steps. The different positions of the above-mentioned stop points are usually achieved based on the selection of different etching selectivity ratios. It should be emphasized that since the protective layer 3 needs to be retained when the second etching is performed in this embodiment, the stop point is usually not located below the bottom protective layer 3 of the magnetic tunnel junction 1.

[0110] It should be emphasized that in this embodiment, the OTP region 5 and the MTP region 6 can be etched at the same time, and due to the blocking of the hard mask 2, part of the etching position in the OTP region 5 will stop at the top surface of the hard mask 2, and the etching position in the MTP region 6 will stop at the top surface of the hard mask 2. In this embodiment, whether through the first top wiring mask 7 or the second top wiring mask 7, the stop point can be at the above three positions.

[0111] S303: Damaging the insulating layer from the sidewall of the corresponding etching position through the protective layer by means of ion implantation or plasma bombardment.

[0112] In this step, the top connection groove 8 can be processed by plasma bombardment or ion implantation to damage the insulating layer 11 of the magnetic tunnel junction 1 from the side wall corresponding to the etching position through the protective layer 3. It should be emphasized that this process will retain the protective layer 3 originally existing on the side wall surface of the magnetic tunnel junction 1 at the etching position, while damaging the insulating layer 11.

[0113] It should also be emphasized that in this step, the OTP region 5 and the MTP region 6 can be bombarded at the same time. Due to the blocking of the metal hard mask 2 with a certain thickness in both regions, the magnetic tunnel junction 1 in the OTP region 5 will not be damaged from its top; the magnetic tunnel junction 1 in the MTP region 6 will not be damaged.

[0114] S304: Filling a conductive medium in the top connection groove formed by etching the chip to form a top connection.

[0115] In this step, the top connection 4 can be completely made by first setting a seed layer 10 in the top connection groove 8, and then filling a conductive medium based on the seed layer 10 to form a top connection 4, so that the top connection 4 can be interconnected with the hard mask 2 and then interconnected with the magnetic tunnel junction 1. The specific process of filling the conductive medium can refer to the prior art and will not be repeated here. After the filling is completed in this step, the chip surface usually needs to be flattened, and the specific process of flattening is not specifically limited here.

[0116] The embodiment of the present invention provides a method for preparing an MRAM device with an OTP unit. The OTP MRAM and the MTPMRAM can be prepared simultaneously without requiring additional mask costs. The MTJs of the OTP region 5 and the MTP region 6 are of the same size, have good uniformity, and are stable in process. The characteristics of the MRAM itself can be used to obtain a faster read and write speed (greater unit density), and the application potential is great.

[0117] The present invention also provides an MRAM device with an OTP unit, which is specifically an MRAM device prepared by a method for preparing an MRAM device with an OTP unit provided by any of the above-mentioned embodiments of the invention. Compared with the existing MRAM device, it is mainly reflected in the size or position of the magnetic tunnel junction 1 and the difference in the cross section of the top connection 4. At the same time, in the magnetic tunnel junction 1 located in the OTP region 5 in this embodiment, the insulating layer 11 has etching damage.

[0118] Specifically, an MRAM device with an OTP unit provided in an embodiment of the present invention includes an OTP unit, wherein the OTP unit includes: a substrate; the substrate is divided into an OTP region 5; a magnetic tunnel junction 1 located on the surface of the substrate and distributed in the OTP region 5; the magnetic tunnel junction 1 includes a fixed layer located on the surface of the substrate, an insulating layer 11 located on the surface of the fixed layer facing away from the substrate, and a free layer located on the surface of the insulating layer 11 facing away from the substrate; the insulating layer 11 of the magnetic tunnel junction 1 located in the OTP region 5 has etching damage; a hard mask 2 located on the surface of the magnetic tunnel junction 1 facing away from the substrate; a top connection 4 connected to the hard mask 2; the top connection 4 extends to the side wall of the magnetic tunnel junction 1 where the etching damage occurs.

[0119] The above-mentioned substrate is a component that supports various structures in the MRAM device. The specific material of the substrate can be set according to actual conditions and is not specifically limited here. In this embodiment, the MRAM device is usually divided into an OTP area 5 and an MTP area 6, and the corresponding substrate is also divided into an OTP area 5 and an MTP area 6.

[0120] The magnetic tunnel junction 1 is arranged on the surface of one side of the substrate, and the magnetic tunnel junction 1 includes a fixed layer, an insulating layer 11 and a free layer arranged in sequence from bottom to top. The magnetic tunnel junction 1 has a side wall, and its structure can refer to the above embodiment, and will not be repeated here. The magnetic tunnel junction 1 needs to be distributed in the above OTP area 5, and the insulating layer 11 of the magnetic tunnel junction 1 located in the OTP area 5 needs to have etching damage, and the etching damage is specifically prepared by the preparation method provided in any of the above embodiments. The specific content can refer to the above invention embodiment, and will not be repeated here.

[0121] The top of the magnetic tunnel junction 1, that is, the surface of the magnetic tunnel junction 1 facing away from the substrate, is provided with a hard mask 2, and its specific content can be referred to the above-mentioned invention embodiment, and will not be repeated here. The top connection line 4 needs to be connected to the hard mask 2, and in the OTP area, due to the limitation of the above-mentioned preparation process, the top connection line 4 will extend to the side wall of the magnetic tunnel junction 1 in the OTP area 5 where the above-mentioned etching damage is generated. It can be seen from the above-mentioned embodiment that at this time, the side wall of the magnetic tunnel junction 1 where the etching damage is generated will be provided with a protective layer 3 or a dielectric protective layer 9, and the top connection line 4 will be in contact with the protective layer 3 or the dielectric protective layer 9.

[0122] Typically, an MRAM device with an OTP unit provided in an embodiment of the present invention includes an OTP memory array composed of a plurality of the above-mentioned OTP units, and the structure of each of the OTP units is as described above. The MRAM device will also include an MTP memory array composed of a plurality of MTP units. The structure of the MTP unit can refer to the specific structure set in the MTP area introduced in the above-mentioned embodiment. The structure of the MTP unit and the MTP memory array can refer to the prior art, and their structures are described in detail in the above-mentioned invention embodiments, and will not be described in detail here. In this embodiment, the remaining structures of the MRAM device can refer to the prior art, and will not be described in detail here.

[0123] The MRAM device with an OTP unit provided by the embodiment of the present invention is manufactured based on the above-mentioned manufacturing method, so it can have a lower manufacturing cost and a higher yield.

[0124] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0125] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0126] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0127] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0128] The above is a detailed introduction to an MRAM device with an OTP unit and a preparation method provided by the present invention. This article uses specific examples to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method and core ideas of the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A method for preparing an MRAM device having an OTP unit, characterized in that: include: A top wiring mask is arranged on the surface of a chip provided with a magnetic tunnel junction; the top wiring mask corresponds to an etching position of a preset OTP region, including at least one side wall of the magnetic tunnel junction of the OTP region; Etching the chip based on the top wiring mask until the magnetic tunnel junction of the OTP region corresponds to the sidewall of the etching position, thereby damaging the insulating layer of the magnetic tunnel junction; A conductive medium is filled in a top connection groove formed by etching the chip to form a top connection.

2. The preparation method according to claim 1, characterized in that: The top connection mask corresponds to the etching position of the preset MTP region, and corresponds to the hard mask on the top of the magnetic tunnel junction of the MTP region; The etching of the chip based on the top wiring mask comprises: The chip is etched based on the top wiring mask to expose the hard mask.

3. The preparation method according to claim 1, characterized in that: The top connection mask corresponds to the etching position of the preset OTP area and is offset to one side of the magnetic tunnel junction in the OTP area so that the etching position includes the side wall of the magnetic tunnel junction in the OTP area in the offset direction and a portion of the hard mask on the top of the magnetic tunnel junction.

4. The preparation method according to claim 1, characterized in that: The top connection mask corresponds to the etching size of the preset OTP area, which is larger than the size of the hard mask at the top of the magnetic tunnel junction in the OTP area, so that the top connection mask corresponds to the etching position of the OTP area, including the side walls around the magnetic tunnel junction in the OTP area and the hard mask at the top of the magnetic tunnel junction.

5. The preparation method according to claim 1, characterized in that: The step of providing a top connection mask on the surface of a chip provided with a magnetic tunnel junction comprises: Based on the photolithography process, a top connection mask is arranged on the surface of the chip where the magnetic tunnel junction is arranged.

6. The preparation method according to any one of claims 1 to 5, characterized in that: Etching the chip based on the top wiring mask until the sidewall of the magnetic tunnel junction in the OTP region corresponding to the etching position is damaged, and the insulating layer of the magnetic tunnel junction includes: Performing a first etching on the chip based on the top wiring mask, so that the stop point of the first etching in the OTP region is located below the insulating layer in the magnetic tunnel junction, and removing the protective layer on the side wall surface of the magnetic tunnel junction corresponding to the etching position based on the first etching, and damaging the insulating layer from the side wall etching corresponding to the etching position; After the insulating layer is damaged by etching, a dielectric protection layer is provided on the side wall surface of the magnetic tunnel junction corresponding to the etching position.

7. The preparation method according to claim 6, characterized in that: The stopping point is located below the magnetic tunnel junction bottom protection layer.

8. The preparation method according to claim 6, characterized in that: The stopping point is located on the upper surface of the magnetic tunnel junction bottom protection layer.

9. The preparation method according to claim 6, characterized in that: The stopping point is located in a dielectric layer between the magnetic tunnel junction bottom protection layer and the insulating layer.

10. The preparation method according to claim 6, characterized in that: After the insulating layer is damaged by etching, the dielectric protection layer is provided on the side wall surface of the magnetic tunnel junction corresponding to the etching position, comprising: depositing a dielectric protection layer in the top wiring groove; The dielectric protection layer on the top surface of the hard mask is removed based on selective etching.

11. The preparation method according to any one of claims 1 to 5, characterized in that: Etching the chip based on the top wiring mask until the sidewall of the magnetic tunnel junction in the OTP region corresponding to the etching position is damaged, and the insulating layer of the magnetic tunnel junction includes: Performing a second etching on the chip based on the top wiring mask, so that the stop point of the second etching in the OTP region is located below the insulating layer in the magnetic tunnel junction, and retaining a protective layer on the side wall surface of the magnetic tunnel junction corresponding to the etching position; The insulating layer is damaged from the side wall corresponding to the etching position through the protection layer by means of ion implantation or plasma bombardment.

12. The preparation method according to claim 11, characterized in that: The stopping point is located on the upper surface of the magnetic tunnel junction bottom protection layer.

13. The preparation method according to claim 11, characterized in that: The stopping point is located in a dielectric layer between the magnetic tunnel junction bottom protection layer and the insulating layer.

14. The preparation method according to claim 1, characterized in that: During operation, the breakdown position of the magnetic tunnel junction in the OTP region is located at the insulating layer of the magnetic tunnel junction, or at the sidewall dielectric layer of the magnetic tunnel junction corresponding to the etching position.

15. An MRAM device having an OTP cell, characterized in that: An OTP unit is included, wherein the OTP unit includes: A substrate; the substrate is divided into an OTP area; A magnetic tunnel junction located on the surface of the substrate and distributed in the OTP region; the magnetic tunnel junction comprises a fixed layer located on the surface of the substrate, an insulating layer located on a surface of the fixed layer facing away from the substrate, and a free layer located on a surface of the insulating layer facing away from the substrate; the insulating layer of the magnetic tunnel junction located in the OTP region has etching damage; A hard mask film located on a surface of the magnetic tunnel junction facing away from the substrate; A top connection line connected to the hard mask; the top connection line extends to the sidewall of the magnetic tunnel junction where the etching damage occurs.

Images