Array design photon integrated circuit based on reverse design component

Abstract

In some embodiments, a method for designing a photonic device is provided. The design optimization system receives an initial design of the photonic device. The initial design includes one or more inputs, one or more outputs, a plurality of sub-component regions, and a plurality of waveguides for connecting the sub-component regions. A design optimization system simulates each sub-component region to determine a simulated s parameter for each sub-component region. The design optimization system determines an overall s-parameter of the simulated photonic device based on the simulated s-parameter of each sub-component region and the s-parameter of the waveguide. The design optimization system determines an overall gradient associated with the overall s parameter. The design optimization system optimizes the one or more sub-component regions based on the overall gradient to create an updated design of the photonic device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Application No. 17 / 828,864, filed May 31, 2022, the contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to photonic devices and, in particular, but not exclusively, to photonic integrated circuits, photonic multiplexers and photonic demultiplexers. Background Art

[0004] Fiber optic communications are commonly used to transmit information from one location to another via light that has been modulated to carry the information. For example, many telecommunications companies use optical fiber to transmit telephone signals, Internet communications, and cable television signals. But the cost of deploying optical fiber for fiber optic communications can be prohibitive. Therefore, technologies have been developed that more efficiently use the bandwidth available within a single optical fiber. Wavelength division multiplexing is one such technology that bundles multiple optical carrier signals onto a single optical fiber using different wavelengths.

[0005] Furthermore, digital logic has historically been implemented by constructing logic circuits from electrical conductors and other electrical components. Other techniques have been sought to further increase the speed of digital logic, improve the efficiency of digital logic, and reduce the size of digital logic. One such technique is the use of photonic devices to create photonic integrated circuits that manipulate light rather than electricity to create logic circuits. Summary of the invention

[0006] In some embodiments, a non-transitory computer-readable medium is provided. The computer-readable medium has logic stored thereon, which causes the computing system to perform an action for designing a photonic device in response to execution by one or more processors of a computing system. The action includes receiving an initial design of a photonic device by a design optimization system, wherein the initial design includes one or more inputs, one or more outputs, multiple subcomponent regions, and multiple waveguides for connecting the subcomponent regions; simulating each subcomponent region by the design optimization system to determine a simulated S parameter for each subcomponent region; determining an overall S parameter of the simulated photonic device by the design optimization system based on the simulated S parameter of each subcomponent region and the S parameter of the waveguide; determining an overall gradient associated with the overall S parameter by the design optimization system; and optimizing one or more subcomponent regions by the design optimization system based on the overall gradient to create an updated design of the photonic device.

[0007] In some embodiments, a method for designing a photonic device is provided. A design optimization system receives an initial design of a photonic device. The initial design includes one or more inputs, one or more outputs, multiple subcomponent regions, and multiple waveguides for connecting the subcomponent regions. The design optimization system simulates each subcomponent region to determine a simulated S parameter for each subcomponent region. The design optimization system determines an overall S parameter of the simulated photonic device based on the simulated S parameter of each subcomponent region and the S parameter of the waveguide. The design optimization system determines an overall gradient associated with the overall S parameter. The design optimization system optimizes one or more subcomponent regions based on the overall gradient to create an updated design of the photonic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following drawings, in which, unless otherwise indicated, like reference numerals refer to like parts in the various views. Not all instances of an element must be labeled so as not to clutter the drawings where appropriate. The drawings are not necessarily drawn to scale, but emphasis is placed on illustrating the principles described. In order to easily identify the discussion of any particular element or action, one or more of the most significant digits or digits in the reference numeral refer to the figure number in which the element is first introduced.

[0009] Figure 1 is a functional block diagram illustrating a non-limiting example embodiment of a system for optical communication between two optical communication devices via optical signals in accordance with various aspects of the present disclosure.

[0010] Figure 2A and Figure 2B Non-limiting example embodiments of a demultiplexer and a multiplexer according to various aspects of the present disclosure are shown, respectively.

[0011] Figure 2C Non-limiting example embodiments of distinct wavelength channels of a multi-channel optical signal according to various aspects of the present disclosure are shown.

[0012] Figure 3A-3D Different views of non-limiting example embodiments of a photon demultiplexer according to various aspects of the present disclosure are shown.

[0013] Figure 4A and Figure 4B A more detailed cross-sectional view of a dispersion region of a non-limiting example embodiment of a photon demultiplexer according to various aspects of the present disclosure is shown.

[0014] Figure 5 is a functional block diagram illustrating a non-limiting example embodiment of a system for generating a design for a photonic integrated circuit in accordance with various aspects of the present disclosure.

[0015] Fig. 6A Non-limiting example embodiments describing a simulation environment for a photonic integrated circuit according to various aspects of the present disclosure are shown.

[0016] Figure 6B A non-limiting example embodiment of a simulation of the operation of a photonic integrated circuit according to various aspects of the present disclosure is shown.

[0017] Figure 6C A non-limiting example embodiment of adjoint simulation within a simulation environment by back-propagating loss values ​​according to various aspects of the present disclosure is shown.

[0018] Figure 7 is a schematic diagram illustrating a non-limiting example embodiment of a design area of ​​a photonic integrated circuit divided into sub-component areas according to various aspects of the present disclosure.

[0019] Figure 8 is a block diagram illustrating a non-limiting example embodiment of a system according to various aspects of the present disclosure.

[0020] Figure 9A-9B is a flow chart illustrating a non-limiting example embodiment of a method of optimizing the design of a photonic device according to various aspects of the present disclosure. DETAILED DESCRIPTION

[0021] Embodiments of techniques for reverse design of physical devices are described herein in the context of generating designs of photonic integrated circuits (including but not limited to multi-channel photonic demultiplexers, multi-channel photonic multiplexers, and photonic logic devices). In the following description, many specific details are set forth to provide a thorough understanding of the embodiments. However, those skilled in the relevant art will recognize that the techniques described herein may be practiced without one or more of the specific details or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

[0022] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0023] Wavelength division multiplexing and its variants (e.g., dense wavelength division multiplexing, coarse wavelength division multiplexing, etc.) utilize the bandwidth of optical fiber by bundling multiple optical carrier signals onto a single optical fiber. Once the multiple carrier signals are bundled together, they are transmitted from one location to another through a single optical fiber, where they can be demultiplexed to be read out by optical communication equipment. However, there are still limitations in terms of cost, size, etc. for equipment that decouples the carrier signals from each other.

[0024] Furthermore, the design of photonic devices, such as those used for optical communications, has traditionally been designed via conventional techniques, sometimes determined by simple guess-and-check methods or manually guided grid searches, where a small number of design parameters from predetermined designs or building blocks are adjusted to suit a particular application. However, in reality, these devices can have design parameters ranging from hundreds to billions or more, depending on device size and functionality. As the functionality of photonic devices increases and manufacturing tolerances improve to allow for smaller device feature sizes, it becomes increasingly important to take advantage of these improvements via optimized device designs.

[0025] Techniques for the inverse design of photonic integrated circuits (e.g., multi-channel photonic demultiplexers and / or multiplexers and / or logic devices) are described herein. More specifically, the techniques described in the embodiments herein combine first-principles simulations with gradient-based optimization to generate designs based on an understanding of the underlying physics that is expected to govern the operation of photonic integrated circuits. The embodiments and techniques described herein are not limited to conventional techniques for the design of photonic devices, in which a small number of design parameters of a predetermined building block are adjusted based on suitability for a particular application. In contrast, the first-principles-based designs described herein do not necessarily depend on human intuition, and can generally produce designs that exceed current state-of-the-art designs in terms of performance, size, robustness, or a combination thereof. In addition, the embodiments and techniques described herein can provide scalable optimization of an almost unlimited number of design parameters, rather than being limited to a small number of design parameters due to conventional techniques. It should also be understood that, although the design and manufacture of photonic integrated circuits are described throughout this article, similar inverse design techniques can be used to generate designs for other types of physical devices.

[0026] It should be noted that while providing a large design area with a large number of design parameters can increase the diversity of functions that can be implemented via inverse design of photonic devices, as the number of design parameters increases, the amount of computing power consumed to simulate performance and update the design increases rapidly. In some embodiments of the present disclosure, techniques are provided for partitioning a large design area into smaller sub-components that can be simulated in parallel, thereby greatly reducing the amount of computing power consumed and reducing the amount of time used to optimize the design.

[0027] Figure 11 is a functional block diagram illustrating a system 100 for optical communication between an optical communication device 102 and an optical communication device 120 (e.g., via wavelength division multiplexing or other techniques) via an optical signal 110 in accordance with various aspects of the present disclosure. More generally, the optical communication device 102 is configured to transmit information by modulating light from one or more light sources into a multi-channel optical signal 110 (e.g., a single optical signal including a plurality of distinct wavelength channels), which is then transmitted from the optical communication device 102 to the optical communication device 120 via an optical fiber, light guide, waveguide, or other photonic device. The optical communication device 120 receives the multi-channel optical signal 110 and demultiplexes each of the plurality of distinct wavelength channels from the multi-channel optical signal 110 to extract the transmitted information. It should be understood that in some embodiments, the optical communication device 102 and the optical communication device 120 may be different and separate devices (e.g., optical transceivers or transmitters communicatively coupled to separate optical transceivers or receivers via one or more optical fibers). However, in other embodiments, the optical communication device 102 and the optical communication device 120 may be part of a single component or device (e.g., a smartphone, a tablet, a computer, an optical device, etc.). For example, both the optical communication device 102 and the optical communication device 120 may be constituent components on a monolithic integrated circuit coupled to each other via a waveguide embedded within the monolithic integrated circuit and adapted to carry the optical signal 110 between the optical communication device 102 and the optical communication device 120 or otherwise transmit the optical signal between one location and another location. Furthermore, in other embodiments, at least one of the optical communication device 102 and the optical communication device 120 may implement logic other than or in addition to wavelength multiplexing or demultiplexing.

[0028] In the illustrated embodiment, the optical communication device 102 includes a controller 104, one or more interface devices 112 (e.g., fiber couplers, optical guides, waveguides, etc.), a multiplexer (MUX), a demultiplexer (DEMUX) or a combination thereof (MUX / DEMUX 114), one or more light sources 116 (e.g., light emitting diodes, lasers, etc.), and one or more light sensors 118 (e.g., photodiodes, phototransistors, photoresistors, etc.) coupled to each other. The controller includes one or more processors 106 (e.g., one or more central processing units, dedicated circuits, field programmable gate arrays, etc.) and a memory 108 (e.g., volatile memories such as DRAM and SAM, non-volatile memories such as ROM, flash memory, etc.). It should be understood that the optical communication device 120 may include the same or similar elements as the optical communication device 102, which have been omitted for clarity.

[0029] The controller 104 coordinates the operation of the optical communication device 102 to transmit and / or receive an optical signal 110 (e.g., a multi-channel optical signal having a plurality of distinct wavelength channels or otherwise). The controller 104 includes software (e.g., instructions included in a memory 108 coupled to the processor 106) and / or hardware logic (e.g., an application specific integrated circuit, a field programmable gate array, etc.) that, when executed by the controller 104, causes the controller 104 and / or the optical communication device 102 to perform operations.

[0030] In one embodiment, the controller 104 may orchestrate the operation of the optical communication device 102 so that the light source 116 generates a plurality of distinct wavelength channels, which are multiplexed into a multi-channel optical signal 110 via the MUX / DEMUX 114, which is then sent to the optical communication device 120 via the interface device 112. In other words, the light source 116 may output light having different wavelengths (e.g., 1271 nm, 1291 nm, 1311 nm, 1331 nm, 1506 nm, 1514 nm, 1551 nm, 1571 nm, or others), which may be modulated or pulsed via the controller 104 to generate a plurality of distinct wavelength channels representing information. The plurality of distinct wavelength channels are then combined or otherwise multiplexed into a multi-channel optical signal 110 via the MUX / DEMUX 114, which is then sent to the optical communication device 120 via the interface device 112. In the same or another embodiment, controller 104 may orchestrate operation of optical communication device 102 such that a plurality of distinct wavelength channels are demultiplexed via MUX / DEMUX 114 from multichannel optical signal 110 received from optical communication device 120 via interface device 112 .

[0031] It should be understood that in some embodiments, certain elements of the optical communication device 102 and / or the optical communication device 120 may have been omitted to avoid obscuring certain aspects of the present disclosure. For example, the optical communication device 102 and the optical communication device 120 may include amplification circuits, lenses, or components that facilitate sending and receiving the optical signal 110. It should also be understood that in some embodiments, the optical communication device 102 and / or the optical communication device 120 may not necessarily include Figure 1 For example, in one embodiment, the optical communication device 102 and / or the optical communication device 120 is a passive device operating as an intermediate device, which can passively multiplex a plurality of distinct wavelength channels into the multi-channel optical signal 110 and / or demultiplex a plurality of distinct wavelength channels from the multi-channel optical signal 110.

[0032] Figure 2A and Figure 2A2 and 3 show an example demultiplexer 206 and multiplexer 208, respectively, according to various aspects of the present disclosure. The demultiplexer 206 and multiplexer 208 are Figure 1 A possible embodiment of the MUX / DEMUX 114 is shown in FIG. 1 , and may be part of an integrated photonic circuit, a silicon photonic device, or the like.

[0033] like Figure 2A As shown in FIG. 1 , the demultiplexer 206 includes an input region 202 and a plurality of output regions 204. The demultiplexer 206 is configured to receive the plurality of output regions 204 via the input region 202 (e.g., the plurality of output regions 204 may correspond to the plurality of output regions 204). Figure 1 The waveguide of the interface device 112 shown in FIG. 1 receives a plurality of different wavelength channels (e.g., Ch.1, Ch.2, Ch.3, ..., Ch.N, each wavelength channel having a wavelength corresponding to λ1, λ2, λ3, ..., λ N The multi-channel optical signal 110 (corresponding to the central wavelength) is optically separated from the multi-channel optical signal 110, and each of the plurality of distinct wavelength channels is guided to a plurality of output regions 204 (for example, corresponding to the central wavelength) respectively. Figure 1 More specifically, in the illustrated embodiment, each of the output regions 204 receives a portion of the multi-channel optical signal that corresponds to or otherwise represents a portion of the optical signal that may be received as a plurality of optical signals (e.g., λ1, λ2, λ3, . . . , λ N ) outputs one of a plurality of distinct wavelength channels. The plurality of output regions 204 may each be coupled to a corresponding light sensor (eg, corresponding to Figure 1 The optical sensor 118 shown may be used to convert the optical signal demultiplexed from the multi-channel optical signal 110 into an electrical signal for further processing.

[0034] exist Figure 2B As shown in the embodiment of FIG. 1 , the multiplexer 208 includes a plurality of input regions 216 and an output region 210. The multiplexer 208 is configured to receive a plurality of distinct optical signals (eg, λ1, λ2, λ3, . . . , λ N ), each optical signal in a plurality of input regions 216 (eg, may correspond to Figure 1 The multiplexer 208 is constructed or otherwise configured to optically combine (i.e., multiplex) each of the plurality of distinct wavelength channels into a multi-channel optical signal 110 that is directed to an output region 210 (e.g., which may correspond to Figure 1 It should be understood that in some embodiments, Figure 2A The demultiplexer 206 and Figure 2BThe multiplexer 208 shown in FIG. 2 can be bidirectional such that each device can act as both a demultiplexer and a multiplexer.

[0035] Figure 2C 1 shows an example of differentiating wavelength channels (eg, Ch.N is a wavelength channel) of a multi-channel optical signal according to various aspects of the present disclosure. Figure 1 , Figure 2A and Figure 2B 110). Example channels may represent a multi-channel optical signal 110 that may be represented by Figure 2A The demultiplexer 206 and / or Figure 2B The multiplexer 208 demultiplexes and / or multiplexes the individual channels included in the plurality of distinct wavelength channels of the multi-channel optical signal. Each of the distinct wavelength channels may have a different central wavelength (λ N ), including at least one of 1271nm, 1291nm, 1311nm, 1331nm, 1506nm, 1514nm, 1551nm or 1571nm or others. Figure 2C In the illustrated embodiment of FIG. 1 , the distinct wavelength channels have a channel bandwidth 212 of approximately 13 nm wide. However, in other embodiments, the channel bandwidth may be different than 13 nm wide. Instead, the channel bandwidth may be considered to be dependent on Figure 1 MUX / DEMUX 114, Figure 2A The demultiplexer 206 and / or Figure 2B Configurable parameters of the structure of the multiplexer 208. For example, in some embodiments, each of the multiple distinct wavelength channels may share a common bandwidth that may correspond to 13 nm or other. Return to Reference Figure 2C , the channel bandwidth 212 may be defined as the width of a passband region 218 (i.e., defined as the region between PB1 and PB2). The passband region 218 may represent the approximate power transfer of a demultiplexer or multiplexer. It should be appreciated that in some embodiments, the passband region 218 may include, for example, Figure 2C , which corresponds to fluctuations within the passband region 218. In one or more embodiments, the ripple around the center value 214 within the passband region can be + / -2 dB or less, + / -1 dB or less, + / -0.5 dB or less, or other. In some embodiments, the channel bandwidth 212 can be defined by the passband region 218. In other embodiments, the channel bandwidth 212 can be defined as being above a threshold (e.g., dB th ) is the measured power. For example, Figure 2A The demultiplexer 206 shown in FIG. 1 can optically separate the channel N from the multi-channel optical signal 110 and has a corresponding channel bandwidth of the channel N, which is equal to the channel bandwidth transmitted to the channel mapped to the channel N (ie, λ N) of the output region 204 above the threshold. In the same or other embodiments, isolation of the channel (i.e., defined by the channel bandwidth 212) may also be considered when optimizing the design. Isolation may be defined as the ratio between the passband region 218 and the stopband region (e.g., a region less than SB1 and greater than SB2). It should also be understood that the transition band regions (e.g., a first transition region between SB1 and PB1 and a second transition region between PB2 and SB2) are exemplary and may be exaggerated for purposes of illustration. In some embodiments, optimization of the design of the photonic demultiplexer may also include target metrics for the slope, width, etc. of the transition band regions.

[0036] Figure 3A-3D 2 shows different views of an example photon demultiplexer according to an embodiment of the present disclosure. The photon demultiplexer 316 is Figure 1 The MUX / DEMUX 114 and Figure 2A A possible implementation of the demultiplexer 206 shown in FIG. 2 is also understood that, according to embodiments of the present disclosure, although the discussion hereafter may be directed to a photonic integrated circuit capable of demultiplexing a plurality of distinct wavelength channels from a multi-channel optical signal, in other embodiments, a demultiplexer (e.g., demultiplexer 316) may also or alternatively be capable of multiplexing a plurality of distinct wavelength channels into a multi-channel optical signal. Similarly, other embodiments may implement functions other than multiplexing / demultiplexing, including but not limited to digital logic.

[0037] Figure 3A A cross-sectional view of the demultiplexer 316 is shown along a side plane within the active layer defined by the width 320 and length 322 of the demultiplexer 316. As shown, the demultiplexer 316 includes an input region 302 (e.g., equivalent to Figure 2A ), a plurality of output regions 304 (e.g., equivalent to Figure 2A The input region 302 and the plurality of output regions 304 (e.g., the plurality of output regions 204 shown in FIG. 1 ) and a dispersion region optically disposed between the input region 302 and the plurality of output regions 304. The input region 302 and the plurality of output regions 304 (e.g., the output region 308, the output region 310, the output region 312, and the output region 314) can each be a waveguide (e.g., a slab waveguide, a strip waveguide, a slot waveguide, etc.) capable of propagating light along a path of the waveguide. The dispersion region 332 includes a first material and a second material dispersed in an inhomogeneous manner (see, e.g., Figure 3D ) to form a plurality of interfaces, each interface corresponding to a change in the refractive index of the dispersion region 332, and collectively configuring the dispersion region 332 to receive a multi-channel optical signal from the multi-channel optical signal (e.g., Figure 2A) into a plurality of distinct wavelength channels (e.g., Figure 2A 1, Ch. 2, Ch. 3, ..., Ch. N) shown in the chromatic dispersion region 332, and guides each of the plurality of distinct wavelength channels to a corresponding one of the plurality of output regions 304. In other words, the input region 302 is adapted to receive a multi-channel optical signal including a plurality of distinct wavelength channels, and the plurality of output regions 304 are adapted to each receive a corresponding one of the plurality of distinct wavelength channels demultiplexed from the multi-channel optical signal via the dispersion region 332.

[0038] like Figure 3A shown in and Figure 3D and Figure 4A-4B As more clearly shown in FIG. 3 , the shapes and arrangements of the heterogeneously dispersed first and second materials create a plurality of interfaces that collectively form a material interface pattern along a cross-sectional area of ​​a dispersion region 332, which is at least partially surrounded by a peripheral region 318 that includes the second material. In some embodiments, the peripheral region 318 has a substantially homogeneous composition that includes the second material. In the illustrated embodiment, the dispersion region 332 includes a first side 328 and a second side 330 that are each connected to an inner boundary (i.e., an unmarked dashed line of the peripheral region 318 disposed between the dispersion region 332 and a dashed line corresponding to an outer boundary of the peripheral region 318). The first side 328 and the second side 330 are disposed to correspond to opposite sides of the dispersion region 332. The input region 302 is disposed proximate to the first side 328 (e.g., one side of the input region 302 is adjacent to the first side 328 of the dispersion region 332), and each of the plurality of output regions 304 is disposed proximate to the second side 330 (e.g., one side of each of the plurality of output regions 304 is adjacent to the second side 330 of the dispersion region 332).

[0039] In the illustrated embodiment, each of the plurality of output regions 304 is parallel to each other of the plurality of output regions 304. However, in other embodiments, the plurality of output regions 304 may not be parallel to each other or even disposed on the same side (e.g., one or more of the plurality of output regions 304 and / or the input region 302 may be disposed proximate to a side of the dispersion region 332 adjacent to the first side 328 and / or the second side 330). In some embodiments, when the plurality of output regions includes at least three output regions, adjacent output regions in the plurality of output regions are separated from each other by a common separation distance. For example, as shown, adjacent output region 308 and output region 310 are separated from each other by a distance 306, which is common to the separation distances between other adjacent pairs of output regions.

[0040] like Figure 3AAs shown in the embodiment of FIG. 1 , the demultiplexer 316 includes four output regions 304 (e.g., output region 308, output region 310, output region 312, and output region 314), each of which is mapped to a corresponding one of four channels included in the plurality of distinct wavelength channels (i.e., by means of the structure of the dispersion region 332). More specifically, the plurality of interfaces defined by the inhomogeneous dispersion of the first material and the second material of the dispersion region 332 form a material interface pattern along a cross-sectional area of ​​the dispersion region 332 (e.g., Figure 3A , Figure 4A or Figure 4B ), so that when the input region 302 partitions the multi-channel optical signal, the dispersion region 332 optically separates each of the four channels from the multi-channel optical signal and routes each of the four channels to a corresponding one of the four output regions 304.

[0041] Note that the first material and the second material of the dispersion region 332 are arranged and shaped within the dispersion region so that the material interface pattern is substantially proportional to a design obtainable using an inverse design process, which will be discussed in more detail later in this disclosure. More specifically, in some embodiments, the inverse design process may include iterative gradient-based optimization of the design based at least in part on a loss function that includes performance losses (e.g., for implementing functionality) and manufacturing losses (e.g., for implementing manufacturability and binarization of the first and second materials), which are reduced or otherwise adjusted via iterative gradient-based optimization to generate a design. In the same or other embodiments, other optimization techniques may be used in place of or in conjunction with gradient-based optimization. Advantageously, this allows optimization of a nearly infinite number of design parameters to achieve functionality and performance within a predetermined area that may not be achievable with conventional design techniques.

[0042] For example, in one embodiment, the dispersion region 332 is configured to optically separate each of the four channels from the multi-channel optical signal within a predetermined area of ​​35 μm×35 μm (e.g., defined by the width 324 and the length 326 of the dispersion region 332) when the multi-channel optical signal is received at the input region 302. In the same or another embodiment, the dispersion region is configured to accommodate a common bandwidth for each of the four channels, each of the four channels having a different central wavelength. In one embodiment, the common bandwidth is about 13 nm wide, and the different central wavelengths are selected from the group consisting of 1271 nm, 1291 nm, 1311 nm, 1331 nm, 1506 nm, 1514 nm, 1551 nm, and 1571 nm. In some embodiments, the entire structure of the multiplexer 316 (e.g., including the input region 302, the peripheral region 318, the dispersion region 332, and the plurality of output regions 304) is accommodated within the predetermined area (e.g., as defined by the width 320 and the length 322). In one embodiment, the predetermined area is 35 μm×35 μm. It should be understood that in other embodiments, the dispersion region 332 and / or the demultiplexer 316 are accommodated in other areas greater than or less than 35 μm×35 μm, which may result in changes in the structure of the dispersion region 332 (e.g., the arrangement and shape of the first material and the second material) and / or other components of the demultiplexer 316.

[0043] In the same or other embodiments, the dispersion region is configured to have a power transmission of -2 dB or greater for a given wavelength within one of the plurality of distinct wavelength channels from the input region 302 to a corresponding one of the plurality of output regions 304 through the dispersion region 332. For example, if channel 1 of the multi-channel optical signal is mapped to the output region 308, then when the demultiplexer 316 receives the multi-channel optical signal at the input region 302, the dispersion region 332 will optically separate channel 1 from the multi-channel optical signal and direct the portion of the multi-channel optical signal corresponding to channel 1 to the output region 308 at a power transmission of -2 dB or greater. In the same or other embodiments, the dispersion region 332 is configured such that for a given wavelength, the adverse power transmission (i.e., isolation) from the input region to any of the plurality of output regions other than a corresponding one of the plurality of output regions is -30 dB or less, -22 dB or less, or other. For example, if channel 1 of the multi-channel optical signal is mapped to output region 308, the adverse power transfer from input region 302 to any other output region (e.g., output region 310, output region 312, output region 314) of the plurality of output regions except for a corresponding one of the plurality of output regions (e.g., output region 308) is -30 dB or less, -22 dB or less, or other. In some embodiments, the maximum power reflection from the demultiplexer 316 of the input signal (e.g., multi-channel optical signal) received at the input region (e.g., input region 302) by the dispersion region 332 or otherwise reflected back to the input region is -40 dB or less, -20 dB or less, -8 dB or less, or other. It should be understood that in other embodiments, the power transfer, adverse power transfer, maximum power, or other performance characteristics may be different from the various values ​​discussed herein, and the structure of the dispersion region 332 may be changed due to the inherent relationship between the structure, function, and performance of the demultiplexer 316.

[0044] Figure 3B A vertical schematic diagram or stacking of various layers included in the illustrated embodiment of the demultiplexer 316 is shown. However, it should be understood that the illustrated embodiment is not exhaustive and that certain features or elements may be omitted to avoid obscuring certain aspects of the invention. In the illustrated embodiment, the demultiplexer 316 includes a substrate 334, a dielectric layer 336, an active layer 338 (e.g., Figure 3A) and a cladding layer 340. In some embodiments, the demultiplexer 316 may be partially or otherwise a photonic integrated circuit or silicon photonic device compatible with conventional manufacturing techniques (e.g., lithography such as photolithography, electron-beam lithography, sputtering, thermal evaporation, physical and chemical vapor deposition, etc.).

[0045] In one embodiment, a silicon-on-insulator (SOI) wafer may initially be provided, comprising a support substrate (e.g., a silicon substrate) corresponding to substrate 334, a silicon dioxide dielectric layer corresponding to dielectric layer 336, a silicon layer (e.g., intrinsic, doped, or other), and an oxide layer (e.g., intrinsic, grown, or other). In one embodiment, the silicon in active layer 338 may be selectively etched by photolithographically creating a pattern on the SOI wafer, which is transferred to the SOI wafer via a dry etching process (e.g., via a photoresist mask or other hard mask) to remove portions of the silicon. The silicon may be etched all the way down to dielectric layer 336 to form a void, which may then be backfilled with silicon dioxide, which is then encapsulated with silicon dioxide to form cladding layer 340. In one embodiment, there may be several etch depths including a full etch depth of silicon to obtain a target structure. In one embodiment, the silicon may be 206 nm thick, so the full etch depth may be 206 nm. In some embodiments, this can be a two-step packaging process where two silicon dioxide depositions are performed with an intermediate chemical mechanical planarization used to produce a planar surface.

[0046] Figure 3C Shown along with Figure 3A The active layer 338 (relative to the active layer 338) of the peripheral region 318 of the input region 302 is cut out of the active layer 338 (relative to the active layer 338) of the input region 302 Figure 3B ). In the illustrated embodiment, the active layer 338 includes a first material 342 having a refractive index ε1 and a second material 344 having a refractive index ε2 different from ε1. The homogeneous regions of the first material 342 and the second material 344 can form a waveguide or a portion of a waveguide corresponding to the input region 302 and the plurality of output regions 304, such as Figure 3A and Figure 3C as shown in .

[0047] Figure 3D The active layer 338 (with respect to Figure 3B). As previously described, active layer 338 includes a first material 342 (e.g., silicon) and a second material 344 (e.g., silicon dioxide) that are dispersed inhomogeneously to form a plurality of interfaces 346 that collectively form a material interface pattern. Each of the plurality of interfaces 346 that form the interface pattern corresponds to a change in the refractive index of dispersion region 332 to configure the dispersion region (i.e., the shape and arrangement of first material 342 and second material 344) to at least partially provide the functionality of demultiplexer 316 (i.e., optical separation of a plurality of distinct wavelength channels from a multi-channel optical signal and corresponding guidance of each of the plurality of distinct wavelength channels to a corresponding output region in a plurality of output regions 304 when a multi-channel optical signal is received at input region 302).

[0048] It should be understood that in Figure 3A-3D In the illustrated embodiment of the demultiplexer 316 shown in , the change in refractive index is shown as being vertically consistent (i.e., the first material 342 and the second material 344 form an interface that is substantially vertical or perpendicular to a side plane or cross-section of the demultiplexer 316), however, in the same or other embodiments, multiple interfaces (e.g., Figure 3D The interface 346 shown in FIG. 34A may not be substantially perpendicular to a side plane or cross-section of the demultiplexer 316 .

[0049] Figure 4A A more detailed cross-sectional view of the dispersion region of an example photonic demultiplexer 400 is shown in accordance with an embodiment of the present disclosure. Figure 4B Shown by Figure 4A A more detailed view of the interface pattern formed by the shape and arrangement of the first material 410 and the second material 412 of the dispersion region of the photon demultiplexer 400. The photon demultiplexer 400 is Figure 1 The MUX / DEMUX 114 shown in Figure 2A The demultiplexer 206 and Figure 3A-3D A possible implementation of the demultiplexer 316 is shown in FIG.

[0050] like Figure 4A and Figure 4B As shown in , the photon demultiplexer 400 includes an input region 402, a plurality of output regions 404a-404d, and a dispersion region 406 optically disposed between the input region 402 and the plurality of output regions 404a-404d. The dispersion region 406 is at least partially surrounded by a peripheral region 408 including an inner boundary 414 and an outer boundary 416. It should be understood that the same named or labeled elements of the photon demultiplexer 400 can similarly correspond to the same named or labeled elements of other demultiplexers described in the embodiments of the present disclosure.

[0051] The first material 410 (ie, the black region within the dispersion region 406) and the second material 412 (ie, the white region within the dispersion region 406) of the photon demultiplexer 400 are dispersed inhomogeneously to create a plurality of interfaces that together form a material interface pattern 420, such as Figure 4B . More specifically, the inverse design process combines first-principles simulations with iterative gradient-based optimization, Markov chain Monte Carlo optimization, or other optimization techniques to generate a design that is substantially replicated by the dispersion region 406 in a proportional or scaled manner, so that the photonic demultiplexer 400 provides the desired functionality. In the illustrated embodiment, the dispersion region 406 is configured to optically separate each of a plurality of distinct wavelength channels from the multi-channel optical signal when the input region 402 receives the multi-channel optical signal, and guide each of the plurality of distinct wavelength channels to a corresponding one of the plurality of output regions 404a-404d, respectively. More specifically, the plurality of output regions 404a-404d are mapped to wavelength channels having center wavelengths corresponding to 1271 nm, 1291 nm, 1311 nm, and 1331 nm, respectively. In another embodiment, the output regions 404a-404d are mapped to wavelength channels having center wavelengths corresponding to 1506 nm, 1514 nm, 1551 nm, and 1571 nm, respectively.

[0052] like Figure 4B As shown in FIG. 4 , the material interface pattern 420 defined by the black lines within the dispersion region 406 and corresponding to the change in the refractive index within the dispersion region 406 includes a plurality of protrusions 422a-422b. The first protrusion 422a is formed by the first material 410 and extends from the peripheral region 408 into the dispersion region 406. Similarly, the second protrusion 422b is formed by the second material 412 and extends from the peripheral region 408 into the dispersion region 406. Further as shown in FIG. Figure 4B As shown in FIG. 4 , the dispersion region 406 includes a plurality of islands 424a-424b formed of a first material 410 or a second material 412. The plurality of islands 424a-424b include a first island 424a formed of the first material 410 and surrounded by the second material 412. The plurality of islands 424a-424b also include a second island 424b formed of the second material 412 and surrounded by the first material 410.

[0053] In some embodiments, the material interface pattern 420 includes one or more dendritic shapes, wherein each of the one or more dendritic shapes is defined as a branching structure formed by the first material 410 or the second material 412 and has a width that alternates between increasing and decreasing in size along a corresponding direction. Figure 4A, for clarity, the dendrites 418 are marked with white arrows with black borders. It can be seen that the width of the dendrites 418 alternately increases and decreases in size along the corresponding direction (i.e., the white marked arrows covering the length of the dendrites 418), thereby creating a branching structure. It should be understood that in other embodiments, there may be no protrusions, no islands, no dendrites, or there may be any number (including zero) of protrusions, islands of any material included in the dispersion region 406, dendrites, or combinations thereof.

[0054] In some embodiments, the reverse design process includes implementing a minimum feature size manufacturing penalty, for example, to ensure the manufacturability of the design. Figure 4A and Figure 4B In the illustrated embodiment of the photon demultiplexer 400 shown in FIG, the material interface pattern 420 is shaped to implement a minimum feature size within the dispersion region 406 such that the plurality of interfaces formed using the first material 410 and the second material 412 within the cross-sectional region do not have a radius of curvature having a size less than a threshold size. For example, if the minimum feature size is 150 nm, the radius of curvature of any of the plurality of interfaces has a size less than a threshold size corresponding to the inverse of half of the minimum feature size (i.e., 1 / 75 nm). -1 ). The implementation of such a minimum feature size prevents the reverse design process from generating a non-manufacturable design by taking into account manufacturing constraints, limitations and / or yield. In the same or other embodiments, a minimum width or spacing may be implemented as a minimum feature size using different or additional checks on manufacturability-related metrics.

[0055] Figure 5 is a functional block diagram illustrating a system 500 for generating a design of a photonic integrated circuit (i.e., a photonic device) according to an embodiment of the present disclosure. The system 500 can be used to perform an inverse design process that generates a design with an iterative gradient-based optimization that takes into account the underlying physics that governs the operation of the photonic integrated circuit. More specifically, the system 500 is a design tool that can be used to optimize structural parameters of the photonic integrated circuit (e.g., the shape and arrangement of the first material and the second material within the dispersion region of the embodiments described in the present disclosure) based on first principles simulations (e.g., electromagnetic simulations for determining the field response of the photonic device to an excitation source) and iterative gradient-based optimization. In other words, the system 500 can provide a design obtained via an inverse design process that is substantially composed of Figure 3A and Figure 4A The dispersion regions 332 and 406 of the demultiplexer 316 and the photonic demultiplexer 400, respectively, shown in FIG. 4 are reproduced (ie, scaled).

[0056] As shown, system 500 includes controller 512, display 502, input device 504, communication device 506, network 508, remote resource 510, bus 534, and bus 520. Controller 512 includes processor 514, memory 516, local storage 518, and photonic device simulator 522. Photonic device simulator 522 includes operation simulation engine 526, manufacturing loss calculation logic 528, calculation logic 524, adjoint simulation engine 530, and optimization engine 532. It should be understood that in some embodiments, controller 512 can be a distributed system.

[0057] The controller 512 is coupled to a display 502 (e.g., a light emitting diode display, a liquid crystal display, etc.) via a bus 520, and the display 502 is coupled to a bus 534 for displaying information to a user utilizing the system 500 to optimize the structural parameters of the photonic device (i.e., the demultiplexer). An input device 504 is coupled to the bus 534 to communicate information and command selections to the processor 514 via the bus 520. The input device 504 may include a mouse, a trackball, a keyboard, a stylus, or other computer peripheral device to facilitate interaction between a user and the controller 512. In response, the controller 512 may provide verification of the interaction via the display 502.

[0058] Another device that may be optionally coupled to the controller 512 is a communication device 506 for accessing remote resources 510 of the distributed system via a network 508. The communication device 506 may include any of a number of networked peripheral devices, such as those for coupling to an Ethernet network, the Internet, or a wide area network, etc. The communication device 506 may also include a mechanism to provide a connection between the controller 512 and the outside world. Note that Figure 5 Any or all components and associated hardware of the system 500 shown in FIG. 5 may be used in various embodiments of the present disclosure. Remote resources 510 may be part of a distributed system and include any number of processors, memory, and other resources for optimizing structural parameters of a photonic device.

[0059] The controller 512 coordinates the operation of the system 500 to optimize the structural parameters of the photonic device. The processor 514 (e.g., one or more central processing units, graphics processing units, and / or tensor processing units, etc.), the memory 516 (e.g., volatile memory such as DRAM and SRAM, non-volatile memory such as ROM, flash memory, etc.), the local storage device 518 (e.g., magnetic storage such as a computer disk drive), and the photonic device simulator 522 are coupled to each other via a bus 520. The controller 512 includes software (e.g., instructions included in the memory 516 coupled to the processor 514) and / or hardware logic (e.g., an application specific integrated circuit, a field programmable gate array, etc.) that, when executed by the controller 512, causes the controller 512 or the system 500 to perform operations. The operations may be based on instructions stored in any one or a combination of the memory 516, the local storage device 518, the photonic device simulator 522, and the remote resources 510 accessed via the network 508.

[0060] In the illustrated embodiment, components of the photonic device simulator 522 are used to optimize photonic devices (e.g., Figure 1 MUX / DEMUX 114, Figure 2A Demultiplexer 206, Figure 2B Multiplexer 208, Figure 3A-3D The demultiplexer 316 and Figure 4A-4BIn some embodiments, the system 500 can optimize the structural parameters of the photonic device via simulations (e.g., operational and adjoint simulations) that model field responses (e.g., electric and magnetic fields within the photonic device) using finite difference time domain (FDTD) methods, finite difference frequency domain (FDFD) methods, or any other suitable technique. The operational simulation engine 526 provides instructions for performing electromagnetic simulations of the photonic device operating in response to an excitation source within a simulation environment. In particular, the operational simulation determines the field response of the simulation environment (and therefore the photonic device described by the simulation environment) in response to the excitation source to determine performance metrics of the physical device (e.g., based on an initial description or input design of the photonic device, which describes the structural parameters of the photonic device within a simulation environment having a plurality of voxels). The structural parameters may correspond to, for example, a specific design, material composition, dimensions, etc. of the physical device. The manufacturing loss calculation logic 528 provides instructions for determining manufacturing losses, which are used to implement minimum feature sizes to ensure manufacturability. In some embodiments, the manufacturing losses are also used to implement binarization of the design (i.e., such that the photonic device includes a first material and a second material dispersed to form a plurality of interfaces). The computational logic 524 computes a loss metric determined via a loss function based on the performance metric and the manufacturing losses, the loss function including the performance losses. The adjoint simulation engine 530 is used in conjunction with the operational simulation engine 526 to perform an adjoint simulation of the photonic device to back-propagate the loss metric through the simulation environment via the loss function to determine how changes in the structural parameters of the photonic device affect the loss metric. The optimization engine 532 is used to update the structural parameters of the photonic device to reduce the loss metric and generate a revised description (i.e., a revised design) of the photonic device.

[0061] Figure 6A-6C 6, performing an operational simulation of a photonic device in response to an excitation source within a simulation environment 608, and performing a concomitant simulation of a photonic device within a simulation environment 610, respectively, according to various aspects of the present disclosure. The initial setup of the simulation environment, the 1-dimensional representation of the simulation environment, the operational simulation of a physical device, and the concomitant simulation of a physical device may be illustrated with reference to FIG. Figure 5 The system 500 shown in FIG.

[0062] like Figure 6A-6C As shown in FIG. 1 , the simulation environment is represented in two dimensions. However, it should be understood that other dimensions (e.g., 3-dimensional space) may also be used to describe the simulation environment and the photonic device. Figure 6A-6CThe optimization of the structural parameters of the photonic device shown in can be achieved via an inverse design process, which includes simulations (e.g., operational simulations and adjoint simulations) of modeling the field response (e.g., electric and magnetic fields) of the excitation source using a finite-difference time-domain (FDTD) method, a finite-difference frequency-domain (FDFD) method, or any other suitable technique.

[0063] Fig. 6A An illustrative simulation environment 606 for describing a photonic integrated circuit (i.e., a photonic device such as a waveguide, a demultiplexer, etc.) is shown in accordance with a non-limiting example embodiment of the present disclosure. More specifically, in response to receiving an initial description of a photonic device defined by one or more structural parameters (e.g., an input design), a system (e.g., Figure 5 The system 500 of the present invention configures the simulation environment 606 to represent the photonic device. As shown, the simulation environment 606 (and subsequently the photonic device) is described by a plurality of voxels 612, which represent individual elements (i.e., discretized) of a two-dimensional (or other dimensional) space. Each of the voxels 612 is shown as a two-dimensional square; however, it should be understood that the voxels can be represented as cubes or other shapes in a three-dimensional space. It should be understood that the specific shapes and dimensions of the plurality of voxels 612 can be adjusted depending on the simulation environment 606 and the photonic device being simulated. It should also be noted that only a portion of the plurality of voxels 612 is shown to avoid obscuring other aspects of the simulation environment 606.

[0064] Each of the plurality of voxels 612 may be associated with a structure value, a field value, and a source value. Collectively, the structure values ​​of the simulation environment 606 describe structural parameters of the photonic device. In one embodiment, the structure values ​​may correspond to a structure (i.e., material) boundary or interface (e.g., Figure 4B The relative permittivity, permeability, and / or refractive index of a material interface pattern 420 of the simulation environment 606 can be represented by an interface 616. For example, an interface 616 represents a location where the relative permittivity changes within the simulation environment 606 and can define a boundary of a photonic device where a first material contacts or otherwise interfaces with a second material. The field values ​​describe a field (or loss) response calculated (e.g., via Maxwell's equations) in response to an excitation source described by the source values. For example, a field response can correspond to a vector describing the electric field and / or magnetic field for each of a plurality of voxels 612 at a particular time step (e.g., in one or more orthogonal directions). Thus, the field response can be based at least in part on structural parameters and an excitation source of the photonic device.

[0065] In the illustrated embodiment, the photonic device corresponds to a device having a design region 614 (eg, corresponding to Figure 3A The dispersion region 332 and / or Figure 4A406) of the optical demultiplexer, wherein the structural parameters of the physical device can be updated or otherwise modified. More specifically, through the inverse design process, an iterative gradient-based optimization of the loss metric determined according to the loss function is performed to generate a design of the photonic device, which functionally enables the multi-channel optical signal to be demultiplexed and directed from the input port 602 to a corresponding one of the output ports 604. Therefore, the input port 602 of the photonic device (e.g., corresponding to Figure 3A Input area 302, Figure 4A The input region 402 of the simulation environment 606, etc.) corresponds to the location of the excitation source to provide an output (e.g., a Gaussian pulse, a wave, a waveguide mode response, etc.). The output of the excitation source interacts with the photonic device based on the structural parameters (e.g., when the wave propagates through the photonic device within the simulation environment 606, the electromagnetic wave corresponding to the excitation source can be disturbed, retransmitted, attenuated, refracted, reflected, diffracted, scattered, absorbed, spread, amplified, etc.). In other words, the excitation source can cause the field response of the photonic device to change, which depends on the underlying physics that governs the physical domain and structural parameters of the photonic device. The excitation source originates from the input port 602 or is otherwise close to the input port 602 and is positioned to propagate through the design region 614 toward the output port 604 of the photonic device (or otherwise affect the field values ​​of multiple voxels). In the illustrated embodiment, the input port 602 and the output port 604 are positioned outside the design region 614. In other words, in the illustrated embodiment, only a portion of the structural parameters of the photonic device are optimizable.

[0066] However, in other embodiments, the entirety of the photonic device may be placed within the design area 614 such that the structural parameters may represent any portion or the entirety of the design of the photonic device. The electric and magnetic fields within the simulation environment 606 (and subsequently the photonic device) may change in response to the excitation source (e.g., represented by field values ​​for individual voxels that collectively correspond to the field response of the simulation environment). The output port 604 of the optical demultiplexer may be used to determine a performance metric of the photonic device in response to the excitation source (e.g., power transfer from the input port 602 to a particular one of the output ports 604). An initial description of the photonic device (including initial structural parameters, excitation source, performance parameters or metrics, and other parameters describing the photonic device) is provided by a system (e.g., Figure 5 The system 500) is received and used to configure the simulation environment 606 to perform first-principles-based simulations of photonic devices. These specific values ​​and parameters can be determined by (e.g., Figure 5 The system 500 may be directly defined by a user of the system 500, indirectly defined (eg, via the controller 512 screening a predetermined value stored in the memory 516, the local storage device 518, or the remote resource 510), or a combination thereof.

[0067] Figure 6BA non-limiting example embodiment of an operational simulation of a photonic device in response to an excitation source within a simulation environment 608 according to various aspects of the present disclosure is shown. In the illustrated embodiment, the photonic device is an optical demultiplexer configured to optically separate each of a plurality of distinct wavelength channels included in a multi-channel optical signal received at an input port 602, and to direct each of the plurality of distinct wavelength channels to a corresponding one of a plurality of output ports 604, respectively. The excitation source may be selected (randomly or otherwise) from the plurality of distinct wavelength channels and originate from the input port 602 having a specified spatial, phase, and / or temporal profile. The operational simulation occurs over a plurality of time steps (including the illustrated time step). When the operational simulation is performed, changes in the field response (e.g., field value) of each of a plurality of voxels 612 are updated stepwise over a plurality of time steps in response to the excitation source. The changes in the field response at a particular time step are based at least in part on the structural parameters, excitation source, and field response of the simulation environment 610 at the immediately preceding time step included in the plurality of time steps. Similarly, in some embodiments, source values ​​for the plurality of voxels 612 are updated (e.g., based on describing the spatial distribution and / or temporal distribution of the excitation source). It should be appreciated that the operational simulation is step-wise, and the field values ​​(and source values) of the simulated environment 610 are updated step-wise at each of the plurality of time steps as time moves forward during the operational simulation. It should also be noted that in some embodiments, the updating is an iterative process, and the updating of each field value and source value is based at least in part on the previous update of each field value and source value.

[0068] Once the operational simulation reaches a steady state (e.g., the field values ​​are substantially stable or decrease to negligible values ​​in response to changes in the excitation source) or otherwise terminates, one or more performance metrics may be determined. In one embodiment, the performance metric corresponds to the power transfer at a corresponding one of the output ports 604, which is mapped to a distinct wavelength channel simulated by the excitation source. In other words, in some embodiments, the performance metric represents the power at a specific location of the output port 604 (at one or more frequencies of interest) in a target mode shape. A loss value or metric for an input design (e.g., an initial design and / or any improved design in which structural parameters have been updated) based at least in part on the performance metric may be determined via a loss function. The loss metric in conjunction with the adjoint simulation may be used to determine a structural gradient (e.g., the effect of the structural parameters on the loss metric) to update or otherwise modify the structural parameters to reduce the loss metric (i.e., increase the performance metric). Note that the loss metric may be further based on a manufacturing loss value and / or other loss values ​​that are used to implement a minimum feature size of the photonic device to improve the manufacturability of the device.

[0069] Figure 6C A non-limiting example embodiment of adjoint simulation within a simulation environment 610 by back-propagating a loss metric in accordance with various aspects of the present disclosure is shown. More specifically, the adjoint simulation is a time-backwards simulation in which the loss metric is treated as an excitation source that interacts with the photonic device and causes a loss response. In other words, an adjoint (or virtual source) based on the loss metric is placed at an output region (e.g., output port 604) or other location corresponding to the location used in determining the performance metric. The adjoint source is then treated as a physical stimulus or excitation source during the adjoint simulation. In response to the adjoint source, a loss response of the simulation environment 608 is calculated for each of a plurality of time steps (e.g., backward in time). The loss response collectively refers to the loss values ​​of a plurality of voxels 612 that are progressively updated in response to the adjoint source over a plurality of time steps. Changes in the loss response based on the loss metric may correspond to a loss gradient, which indicates how changes in the field response of the physical device affect the loss metric. The loss gradient and the field gradient may be combined in an appropriate manner to determine a structural gradient of the photonic device / simulation environment (e.g., how changes in structural parameters of the photonic device within the simulation environment affect the loss metric). Once the structural gradients for a particular cycle (eg, operation and accompanying simulations) are known, the structural parameters can be updated to reduce the loss metric and generate a revised description or design of the photonic device.

[0070] In some embodiments, an iterative loop of performing operational simulations and adjoint simulations, determining structural gradients, and updating structural parameters to reduce a loss metric is continuously performed as part of an inverse design process utilizing iterative gradient-based optimization. An optimization scheme such as gradient descent can be used to determine a specific amount or degree of change in a structural parameter of a photonic device to incrementally reduce the loss metric. More specifically, after each cycle, the structural parameters are updated (e.g., optimized) to reduce the loss metric. The operational simulations, adjoint simulations, and updating of the structural parameters are iteratively repeated until the loss metric substantially converges or is otherwise below a threshold or within a range such that the photonic device maintains manufacturability while providing desired performance.

[0071] Although the above-described inverse design process is effective, the amount of computational time consumed to perform operational simulations, adjoint simulations, gradient determinations, and structural parameter updates increases greatly as the size of the design area 614 increases. In addition, the number of iterations before the loss metric converges may increase as the size of the design area 614 increases. Unfortunately, for a certain desired functionality (e.g., multiplexing / demultiplexing specific wavelengths, and / or multiplexing / demultiplexing a specific number of wavelengths with each other, and / or implementing digital logic), a smaller design area 614 may not provide sufficient physical area for the desired functionality to be implemented. For example, given the physical properties of the propagation of waves through the design area 614, a minimum distance may be required to move the wave from a first position or orientation to a second position or orientation. That is, increasing the area of ​​the design area 614 too much may cause the simulation and gradient calculations to occupy more computing resources than will provide actual results.

[0072] Therefore, in some embodiments of the present disclosure, simulation and optimization of a large design area 614 can be achieved by dividing the design area into sub-assembly areas connected by waveguides. The simulation and optimization of each sub-assembly area can be calculated in parallel, and the simulation of the waveguide can be pre-calculated to speed up the simulation and optimization of the overall design. The total size of the design area can still be used to implement the function even when it is divided into sub-assembly areas, and thus the benefits of a large design area are maintained while significantly reducing the calculation time.

[0073] Figure 7 7 is a schematic diagram showing a non-limiting example embodiment of a design area of ​​a photonic integrated circuit divided into sub-component areas according to various aspects of the present disclosure. In the photonic integrated circuit 700, an input waveguide 704, a first output waveguide 706, a second output waveguide 708, and a third output waveguide 710 are arranged around the design area, similar to Figure 4A and Figure 4B The input area 402 and output areas 404a-404d shown in FIG. Figure 6A-6C However, instead of a single monolithic design area 614 as shown in the previous figures, the design area of ​​the photonic integrated circuit 700 is divided into a plurality of sub-component areas 702.

[0074] In the illustrated embodiment, each of the sub-assembly areas 702 has matching sizes. By selecting matching sizes for the sub-assembly areas 702, the parallel simulation of each of the sub-assembly areas 702 will be completed substantially simultaneously, and because each of the sub-assembly areas 702 is much smaller than the overall design area, the computational resources used to simulate each sub-assembly area 702 are significantly reduced compared to the entire design area (especially considering that the computational complexity of the simulation is exponential with respect to the simulation area).

[0075] The photonic integrated circuit 700 includes a plurality of internal waveguides 712 connecting the subassembly regions 702. The computational complexity of simulating the photonic integrated circuit 700 is further reduced by using standard shapes and sizes for the internal waveguides 712 and by excluding the internal waveguides 712 themselves from the optimization process. Thus, the s-parameters of a single internal waveguide 712 can be calculated once and then reused during future simulations of the entire photonic integrated circuit 700, significantly reducing the total area to be simulated while maintaining the overall size of the photonic integrated circuit 700, thereby allowing for the implementation of complex functionality that utilizes a larger overall size. Regions of the photonic integrated circuit 700 that are neither within the subassembly regions 702 nor within the internal waveguides 712 can be separated by an opaque barrier and can be ignored during optimization.

[0076] The internal waveguides 712 are defined by the structural parameters of the material within the region specifying the internal waveguides 712. Although the illustrated internal waveguides 712 are shown as having straight walls and a single material, in some embodiments, the internal waveguides 712 may have more complex structural parameters including, but not limited to, regular or irregular features along the walls of the internal waveguides 712 and / or within the middle of the internal waveguides 712. In addition, as described above, at least some of the internal waveguides 712 may be curved to connect subassembly regions 702 that are not horizontally or vertically adjacent.

[0077] Although a photonic integrated circuit 700 is shown in which multiple subassembly regions 702 are fully connected by pairs of straight internal waveguides 712, it should be understood that this is only a non-limiting example. In some embodiments, more or fewer internal waveguides 712 may be used, and more or fewer internal waveguides 712 may be arranged in an irregular pattern. Furthermore, in some embodiments, different shapes of internal waveguides 712 may be used, including but not limited to curved internal waveguides 712, so that subassembly regions 702 other than vertically or horizontally adjacent subassembly regions 702 can be connected. The s-parameters of the curved internal waveguides 712 will also be pre-simulated to be inserted into the overall simulation, as discussed above with respect to the straight internal waveguides 712 shown.

[0078] Figure 8 is a block diagram illustrating a non-limiting example embodiment of a system according to various aspects of the present disclosure. In general, the illustrated embodiment of system 800 is configured to generate a proposed segmentation design, to optimize the proposed segmentation design, and to fabricate a physical device based on the proposed segmentation design.

[0079] As shown, system 800 includes a design generation system 814, a manufacturing system 816, and a design optimization system 802. Communication between the design generation system 814, the design optimization system 802, and the manufacturing system 816 can occur via a network (not shown), via the exchange of removable computer-readable media (not shown), or via any other suitable technology. Although the design generation system 814, the manufacturing system 816, and the design optimization system 802 are shown as separate systems, in some embodiments, some parts of these systems can be combined. As a non-limiting example, the design generation system 814 and the design optimization system 802 can be combined in a single system. In addition, in some embodiments, Figure 8 A system shown as a single system may be divided into a plurality of systems.

[0080] In some embodiments, the design generation system 814 may include one or more computing devices configured to generate a proposed design that achieves a desired result. For example, the design generation system 814 may provide a user interface that accepts specifications for the number of input ports, the number of output ports, the desired functionality of the proposed design (including, but not limited to, given a specific input at each input port, an expected output at each output port), the size of the design area, the number and / or size of sub-component areas, and / or any other aspect of the proposed design. In some embodiments, the design generation system 814 may automatically generate some aspects of the proposed design, including, but not limited to, the size and / or number of sub-component areas 702, the number and / or location of internal waveguides 712 connecting sub-component areas 702, and the like.

[0081] In some embodiments, manufacturing system 816 may be any suitable system for manufacturing a segmentation design. In some embodiments, manufacturing system 816 may be a lithography system or an additive manufacturing system. In some embodiments, manufacturing system 816 may have characteristics including minimum feature size, minimum feature shape, and / or other constraints that help define the segmentation design that manufacturing system 816 can manufacture. To this end, manufacturing system 816 may provide a design rule checker that is configured to process a proposed segmentation design to determine whether the proposed segmentation design complies with the constraints of manufacturing system 816.

[0082] In some embodiments, the design optimization system 802 may be any suitable computing device or collection of computing devices configured to provide the described functionality. In some embodiments, the design optimization system 802 may be a server computing device, a desktop computing device, a laptop computing device, a mobile computing device, a tablet computing device, or one or more computing devices of a cloud computing system. In some embodiments, the design optimization system 802 may include Figure 5 The components of the system 500 shown and described above may provide information about Figure 5 The functionality of the system 500 shown in and described above, and / or Figure 5 System 500 may include components of design optimization system 802 or provide functionality described with respect to design optimization system 802 .

[0083] As shown, the design optimization system 802 includes one or more processors 810, a network interface 812, and a computer-readable medium 804. In some embodiments, the one or more processors 810 may include multiple processors and / or multiple processing cores to provide a large amount of computing power. In some embodiments, the network interface 812 may be configured to communicate with the design generation system 814 and / or the manufacturing system 816 via any suitable type of wired network (including but not limited to Ethernet, FireWire, and USB), wireless network (including but not limited to 2G, 3G, 4G, 5G, LTE, Wi-Fi, WiMAX, and Bluetooth), or a combination thereof. In some embodiments, instead of the network interface 812, the design optimization system 802 may be configured to communicate with the design generation system 814 and / or the manufacturing system 816 via the transmission of a removable computer-readable medium (not shown).

[0084] As shown, the computer readable medium 804 has stored thereon logic that, in response to execution by one or more processors 810 , causes the design optimization system 802 to provide a subcomponent optimization engine 806 and an overall optimization engine 808 .

[0085] In some embodiments, the subassembly optimization engine 806 is configured to simulate the subassembly area 702 of the proposed segmented design in parallel to determine the gradient of the subassembly area 702, and optimize the subassembly area 702 based on the gradient. In some embodiments, the overall optimization engine 808 is configured to use the simulation of the subassembly area 702 and the pre-calculated simulation of the internal waveguide 712 to determine the overall s-parameters of the proposed segmented design, and determine the overall gradient of the proposed segmented design. In some embodiments, the overall optimization engine 808 is also configured to optimize the position of one or more internal waveguides 712 as part of the optimization process. Further details about the actions performed by the subassembly optimization engine 806 and the overall optimization engine 808 are provided below.

[0086] As used herein, an "engine" refers to logic embodied in hardware or software instructions, which can be written in a programming language (such as C, C++, C#, COBOL, JAVA TM, PHP, Perl, HTML, CSS, JavaScript, VBScript, ASPX, Go, Python, etc.). The engine can be compiled into an executable program or written in an interpreted programming language. The software engine can be callable from other engines or from itself. Generally, the engine described herein refers to a logical module that can be merged with other engines, or can be divided into sub-engines. The engine can be implemented by logic stored in any type of computer-readable medium or computer storage device, and can be stored on and executed by one or more general-purpose computers to create a special-purpose computer configured to provide the engine or its functions. The engine can be implemented by logic programmed into an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or another hardware device.

[0087] As used herein, the term "computer-readable medium" refers to a removable or non-removable device that implements any technology capable of storing information in a volatile or non-volatile manner to be read by a processor of a computing device, including but not limited to: hard disk drives; flash memory; solid-state drives; random access memory (RAM); read-only memory (ROM); CD-ROM, DVD or other disk storage; magnetic tape cartridges; magnetic tape; and magnetic disk storage. A computer-readable medium may also include multiple devices configured to collectively store the described information.

[0088] Figure 9A-9B is a flow chart illustrating a non-limiting example embodiment of a method for optimizing a design of a photonic device according to various aspects of the present disclosure. In method 900, design optimization system 802 uses simulation and optimization of subassembly region 702 and pre-computed performance characteristics of internal waveguide 712 to accelerate simulation and optimization of a proposed segmented design for a photonic device.

[0089] From the start block, the method 900 proceeds to block 902, where the design generation system 814 generates a proposed design including a plurality of input ports and a plurality of output ports, and provides the proposed design to the design optimization system 802. The proposed design may also include one or more desired performance characteristics associated with each output port for various expected inputs for each input port, so that simulated performance can be compared to the desired performance characteristics for optimization purposes. In some embodiments, the proposed design may indicate one or more constraints for the overall design, including but not limited to a size and / or shape of the overall design, constraints for the location of one or more of the input ports and / or one or more of the output ports, and / or other constraints.

[0090] At block 904, the overall optimization engine 808 of the design optimization system 802 determines an initial design based on the proposed design including the plurality of subassembly areas 702 and the plurality of internal waveguides 712. In some embodiments, the number of subassembly areas 702 may be automatically determined by the overall optimization engine 808. For example, the overall optimization engine 808 may retrieve the size and / or shape of the overall design from the proposed design, and may automatically divide the initial design into subassembly areas 702 of predetermined sizes based on the size and / or shape. As another example, the overall optimization engine 808 may retrieve the size and / or shape of the overall design from the proposed design, and may automatically divide the initial design into a predetermined number of subassembly areas 702 spaced apart by a predetermined amount based on the size and / or shape. In some embodiments, specifications for the subassembly areas 702 and / or internal waveguides 712 may be provided within the proposed design.

[0091] In some embodiments, the proposed design may provide multiple internal waveguides 712 for connecting each of the subassembly regions 702. For example, for Figure 7 In the proposed design of the photonic integrated circuit 700 shown in , two internal waveguides 712 will be specified to connect each of the sub-component regions 702. In some embodiments, the proposed design may indicate that more or fewer internal waveguides 712 connect each of the sub-component regions 702. In some embodiments, the proposed design may also specify the shape of the internal waveguides 712 (e.g., straight, curved, etc.). In some embodiments, the proposed design may indicate that less than all of the sub-component regions 702 should be fully connected in the initial design, so that some sub-component regions 702 can be connected by more or fewer internal waveguides 712 than other sub-component regions. In some embodiments, the proposed design may provide specific locations of the internal waveguides 712. In some embodiments, the overall optimization engine 808 can determine the specific locations of the internal waveguides 712 based on the guidance provided by the proposed design. In some embodiments, the overall optimization engine 808 can automatically determine the number and location of the internal waveguides 712.

[0092] At block 906, the subassembly optimization engine 806 of the design optimization system 802 initializes each subassembly region. In some embodiments, the initialization includes determining an initial set of structural parameters (e.g., material patterns in voxels 612 (e.g., pixels, segments)) for each subassembly region 702. In some embodiments, the initialization may set the material in the voxel 612 to a single value. In some embodiments, the initialization may set the material in the voxel 612 to a random value. In some embodiments, the initialization may set the material in the voxel 612 to match the structural parameters of a previously designed physical device.

[0093] At block 908, the overall optimization engine 808 determines the s-parameters of the internal waveguide 712. In some embodiments, the overall optimization engine 808 may determine the s-parameters by simulating the performance of a sample internal waveguide using an FDTD method, an FDFD method, or any other suitable method for generating s-parameters for the sample internal waveguide. The s-parameters determined for the sample internal waveguide may then be used for each of the internal waveguides 712 used in the design. The s-parameters may be determined separately for each type of internal waveguide used in the design (e.g., a straight internal waveguide of a given length, a curved internal waveguide, etc.), but the s-parameters may be reused each time an internal waveguide of the same size and shape is used in the design. In some embodiments, the overall optimization engine 808 may store the s-parameters of the internal waveguide in a reference data store. In some embodiments, the overall optimization engine 808 may determine the s-parameters of the internal waveguide 712 by retrieving previously determined s-parameters from the reference data store.

[0094] Then, method 900 proceeds to box 910 by continuing the connection end ("connection end A"), where the sub-component optimization engine 806 simulates the sub-component areas in parallel to obtain the simulated s parameters of each sub-component area. The structural parameters of each sub-component area 702 can be used for simulation using the FDTD method, the FDFD method, or any other suitable method to generate the simulated s parameters. Any suitable technique can be used to simulate the sub-component areas 702 in parallel. For example, a multi-threaded approach can be used to perform multiple simulations in parallel on one or more processing cores. As another example, serverless functions or other distributed computing techniques can be used to distribute the simulation for each sub-component area 702 between multiple cloud-based computing devices. By using sub-component areas 702 of matching size, the simulation will take substantially similar amounts of time to complete, and no one simulation will become a bottleneck.

[0095] At block 912, the overall optimization engine 808 combines the simulated S-parameters and the S-parameters of the internal waveguide 712 to determine the overall S-parameters of the initial design. One property of S-parameters known to those of ordinary skill in the art is that the S-parameters of a complex circuit can be modeled by combining the S-parameters of the individual components with simple operations such as matrix multiplication, more complex techniques such as the Gunnar algorithm described in Filipsson, Gunnar, "A new general computer algorithm for S-matrix calculation of interconnected multiports", 11th European Microwave Conference, IEEE, 1981 (which is incorporated herein by reference in its entirety), or any other suitable technique. Therefore, by appropriately combining the simulated S-parameters of the subcomponent region 702 and the S-parameters of the internal waveguide 712, the overall S-parameters can be easily determined. In some embodiments, the S-parameters for the input ports and output ports may also be considered.

[0096] Then, method 900 proceeds to the next connection end ("connection end B"). Fig. 9B ), the method 900 proceeds to block 914, where the overall optimization engine 808 determines the overall gradient of the total loss function based on the expected performance characteristics. In some embodiments, a comparison between the expected performance and the overall s parameters can be performed to determine the performance loss value. The derivative of the performance loss value can be determined to calculate the overall gradient.

[0097] At block 916, the subassembly optimization engine 806 updates the structural parameters of one or more subassembly regions based on the overall gradient. In some embodiments, the overall gradient indicates changes to be made to the structural parameters within the entire design region 614 to reduce the difference between the total performance loss value and the desired performance. The changes indicated by the overall gradient are mapped to the appropriate subassembly regions 702 so that appropriate changes can be made to the subassembly regions 702. Since a single overall gradient can be used to update all subassembly regions 702, the effect is to optimize all subassembly regions 702 at once, rather than using individual optimizations for each subassembly region 702. Therefore, significant savings in computing resources are obtained by eliminating individual optimizations for subassembly regions 702.

[0098] In some embodiments, all of the sub-component areas 702 may be optimized each time block 916 is reached in method 900. In some embodiments, a subset of the sub-component areas 702 may be optimized during each iteration of block 916. For example, the first level sub-component areas 702 (i.e., the sub-component areas 702 closest to the output port) may be optimized during a first iteration, the second level sub-component areas 702 (i.e., a set of sub-component areas 702 immediately upstream of the first level sub-component areas 702) may be optimized during a second iteration, and so on. Similarly, each subset may be processed for more than one iteration before moving on to the next subset.

[0099] At optional block 918, the overall optimization engine 808 optimizes the position of one or more waveguides. In some embodiments, the overall optimization engine 808 may determine whether to improve overall performance by moving the position of one or more of the internal waveguides 712, input ports, and / or output ports. This may be accomplished by monitoring performance values ​​along the perimeter of the photonic integrated circuit 700 and / or the various subassembly regions 702, and moving the waveguide if the overall optimization engine 808 determines that the waveguide performs better at a different position. A detailed description of techniques for moving the position of a waveguide is provided in commonly owned co-pending U.S. Application No. 17 / 586,370, filed on January 27, 2022, the entire disclosure of which is incorporated herein by reference in its entirety for all purposes.

[0100] In some embodiments, the overall optimization engine 808 can review the field values ​​within the adjacent subassembly region 702, and if it is determined that the signal strength through the waveguide is less than a threshold amount, the associated waveguide can be removed from the design to simplify future calculations. Optional block 918 is shown as optional because, in some embodiments, the position of the waveguide can be fixed, and / or because optimization of the waveguide position may not be performed during every iteration of the method 900.

[0101] The method 900 then proceeds to decision block 920 where a determination is made as to whether the method 900 has completed the optimized design. In some embodiments, the optimization may continue until the desired performance level is achieved. In some embodiments, the optimization may continue until the performance loss value converges to a local minimum (i.e., further iterations are not expected to further improve performance). In some embodiments, the optimization may be performed for a predetermined number of iterations, and the determination may check whether that number of iterations has been performed.

[0102] If it is determined at decision block 920 that method 900 is not complete, the result of decision block 920 is no, and method 900 returns to block 910 via connection A to perform a subsequent optimization iteration. Otherwise, if method 900 is complete, the result of decision block 920 is yes, and method 900 proceeds to optional block 922.

[0103] At optional block 922, the overall optimization engine 808 identifies unused subassembly regions. In some embodiments, the overall optimization engine 808 may review simulated field values ​​within the subassembly regions 702 (as determined during simulation at block 910) to determine if there are subassembly regions 702 that did not receive any signals during operation of the photonic integrated circuit 700. In some embodiments, the overall optimization engine 808 may identify unused subassembly regions 702 by finding subassembly regions 702 that have had all waveguides removed by processing at optional block 918.

[0104] At optional block 924, the overall optimization engine 808 removes any waveguides connected to the unused subassembly region 702 and structural parameters of the unused subassembly region 702. Since no signal reaches the unused subassembly region 702, the structural parameters and waveguides leading to that region (if any remain after processing at optional block 918) may be removed without affecting the performance of the rest of the photonic integrated circuit 700.

[0105] At optional block 926, the overall optimization engine 808 inserts other functions into the unused sub-assembly area. In some embodiments, a predetermined test structure with its own input port and output port may be inserted to replace the removed sub-assembly area 702. This is advantageous because it provides a structure that can be used to test the manufacturing process of the rest of the photonic integrated circuit 700 while being as close to the photonic integrated circuit 700 as physically possible, and without reserving space inside the photonic integrated circuit 700 that would otherwise be used to provide the functions of the photonic integrated circuit 700. In some embodiments, the "other functions" may be inserted by laying out multiple photonic integrated circuits 700 on a single wafer, such that the unused portions of the photonic integrated circuits 700 are interleaved with each other to accommodate more photonic integrated circuits 700 onto a single wafer. Optional blocks 922, 924, and 926 are shown as optional because, in some embodiments, the method 900 may leave unused sub-assembly areas 702 within the photonic integrated circuit 700.

[0106] At block 928, the design optimization system 802 sends the updated design to the manufacturing system 816 to manufacture the photonic device. The manufacturing system 816 can then manufacture the photonic device as defined by the updated design.

[0107] The method 900 then proceeds to an end block and terminates.

[0108] In the foregoing description, many specific details are set forth to provide a thorough understanding of various embodiments of the present disclosure. However, those skilled in the relevant art will recognize that the techniques described herein may be practiced without one or more of the specific details or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

[0109] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0110] The order of some or all of the blocks appearing in each method flow chart should not be considered as limiting. On the contrary, those skilled in the art will appreciate that, with the benefit of this disclosure, actions associated with some of the blocks may be performed in various orders not shown, or even in parallel.

[0111] The processes explained above are described in terms of computer software and hardware. The described techniques may constitute machine-executable instructions embodied in a tangible or non-transitory machine (e.g., computer) readable storage medium, which, when executed by a machine, will cause the machine to perform the described operations. In addition, the processes may be embodied in hardware, such as an application specific integrated circuit (ASIC) or other.

[0112] The above description of the illustrated embodiments of the present invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Although specific embodiments and examples of the present invention are described herein for illustrative purposes, various modifications within the scope of the present invention are possible as will be appreciated by those skilled in the relevant art.

[0113] Based on the above detailed description, these modifications can be made to the present invention. The terms used in the appended claims should not be interpreted as limiting the present invention to the specific embodiments disclosed in the specification. On the contrary, the scope of the present invention will be determined entirely by the appended claims, and the claims will be interpreted according to the established principles of claim interpretation.

Claims

1. A non-transitory computer-readable medium having stored thereon logic, the logic, in response to execution by one or more processors of a computing system, causing the computing system to perform actions for designing a photonic device, the actions comprising: Receiving, by a design optimization system, an initial design of a photonic device, wherein the initial design includes one or more inputs, one or more outputs, a plurality of subassembly regions, and a plurality of waveguides for connecting the subassembly regions; simulating each sub-component region by the design optimization system to determine simulated s-parameters for each sub-component region; determining, by the design optimization system, an overall S-parameter of the simulated photonic device based on the simulated S-parameters of each subassembly region and the S-parameters of the waveguide; determining, by the design optimization system, an overall gradient associated with an overall s-parameter; and One or more sub-component regions are optimized by the design optimization system based on the overall gradient to create an updated design for the photonic device.

2. The non-transitory computer-readable medium of claim 1, wherein: The actions also include: The simulation, determination and optimization actions are repeated until the simulated performance of the simulated photonic device reaches a predetermined threshold or until a predetermined number of iterations have been performed.

3. The non-transitory computer-readable medium of claim 1, wherein: The actions also include: The updated design is provided to a manufacturing system to fabricate the photonic device.

4. The non-transitory computer-readable medium of claim 1, wherein: The actions also include: retrieving predetermined s-parameters of the waveguide; And wherein determining the overall s-parameters of the simulated photonic device based on the simulated s-parameters of each subassembly region and the s-parameters of the waveguide comprises: using the retrieved predetermined s-parameters of the waveguide.

5. The non-transitory computer readable medium of claim 1, wherein: Simulating each subcomponent region to determine simulated s-parameters for each subcomponent region includes simulating each subcomponent region in parallel.

6. The non-transitory computer-readable medium of claim 1, wherein: Optimizing the subassembly region includes updating at least one of a size of the subassembly region and a structural parameter of the subassembly region.

7. The non-transitory computer-readable medium of claim 1, wherein: The actions also include: At least one of a position and a shape of at least one waveguide is optimized.

8. The non-transitory computer readable medium of claim 7, wherein: Optimizing the position of at least one waveguide includes removing at least one waveguide.

9. The non-transitory computer readable medium of claim 8, wherein: The actions also include: In response to determining that the subassembly region is not connected to any waveguide, the subassembly region is removed from the updated design.

10. The non-transitory computer readable medium of claim 9, wherein: The actions also include: A predetermined test structure is inserted to replace the removed subassembly area.

11. A method for designing a photonic device, the method comprising: Receiving, by a design optimization system, an initial design of a photonic device, wherein the initial design includes one or more inputs, one or more outputs, a plurality of subassembly regions, and a plurality of waveguides for connecting the subassembly regions; simulating each sub-component region by the design optimization system to determine simulated s-parameters for each sub-component region; determining, by the design optimization system, an overall S-parameter of the simulated photonic device based on the simulated S-parameters of each subassembly region and the S-parameters of the waveguide; determining, by the design optimization system, an overall gradient associated with an overall s-parameter; and One or more sub-component regions are optimized by the design optimization system based on the overall gradient to create an updated design for the photonic device.

12. The method according to claim 11, further comprising: The simulation, determination and optimization actions are repeated until the simulated performance of the simulated photonic device reaches a predetermined threshold or until a predetermined number of iterations have been performed.

13. The method according to claim 11, further comprising: The updated design is provided to a manufacturing system to fabricate the photonic device.

14. The method according to claim 11, further comprising: retrieving predetermined s-parameters of the waveguide; And wherein determining the overall s-parameters of the simulated photonic device based on the simulated s-parameters of each subassembly region and the s-parameters of the waveguide comprises: using the retrieved predetermined s-parameters of the waveguide.

15. The method according to claim 11, wherein: Simulating each subcomponent region to determine simulated s-parameters for each subcomponent region includes simulating each subcomponent region in parallel.

16. The method according to claim 11, wherein: Optimizing the subassembly region includes updating at least one of a size of the subassembly region and a structural parameter of the subassembly region.

17. The method according to claim 11, further comprising: At least one of a position and a shape of at least one waveguide is optimized.

18. The method according to claim 17, wherein: Optimizing the position of at least one waveguide includes removing at least one waveguide.

19. The method according to claim 18, further comprising: In response to determining that the subassembly region is no longer connected to any waveguide, the subassembly region is removed from the updated design.

20. The method according to claim 19, further comprising: Predetermined test structures are added to replace the removed sub-assembly areas.

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