Laser chip preparation method, laser chip and optical module

Abstract

The invention discloses a laser chip (600) preparation method, a laser chip (600) and an optical module (200). A substrate (620) containing an aluminum-indium-gallium-arsenic quantum well structure is grown on a substrate layer (610) made of an InP material; forming a SiO2 mask layer (630) on the upper surface of the substrate (620) through photoetching, and performing mask etching on the substrate (620) to obtain a mesa structure (640); growing a buried layer (650) along the mesa structure (640) by using MOCVD CBr4 in-situ cleaning; growing a barrier layer (660) along the buried layer (650) using MOCVD; then continuing to grow to obtain a laser chip (600) of a preset thickness; the etching surface of the mesa structure (640) can be protected by the buried layer (650), so that the outer surface of the mesa structure (640) is prevented from being oxidized by air, the difficulty of regrowth and facet coating in the subsequent process of obtaining the mesa structure (640) is reduced, and meanwhile, the surface appearance can be improved due to the fact that the degree of air oxidation of the outer surface of the mesa structure (640) is reduced, and the performance of the mesa structure (640) is improved. And thus, the performance of the AlInGaAs quantum well laser chip (600) is ensured.

Description

Laser chip preparation method, laser chip and optical module

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on May 30, 2022, with application number 202210601931.1 and application name “A laser chip preparation method, laser chip and optical module”, the entire contents of which are incorporated by reference into this application; this application claims priority to the Chinese patent application filed with the China Patent Office on May 30, 2022, with application number 2022221333511.1 and application name “A laser chip and optical module”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of optical communication technology, and in particular to a laser chip preparation method, a laser chip, and an optical module. Background Art

[0004] Among the many types of laser chips are semiconductor quantum well laser chips, including AlInGaAs (aluminum indium gallium arsenide) quantum well lasers.

[0005] AlInGaAs quantum well laser chips have small lattice mismatch and high differential gain, but aluminum is easily oxidized in air, making regrowth and facet coating more difficult during the manufacturing process of AlInGaAs quantum well laser chips. At the same time, oxidation increases surface roughness and degrades surface morphology, thereby reducing the reliability of this type of laser chip.

[0006] Summary of the Invention

[0007] The laser chip preparation method provided in this application includes:

[0008] Growing a substrate containing an AlInGaAs quantum dot structure on an InP substrate layer;

[0009] forming a SiO2 mask layer on the upper surface of the substrate by photolithography, and performing mask etching on the substrate to obtain a mesa structure;

[0010] Using MOCVD CBr4 in-situ cleaning, a buried layer is grown along the mesa structure, wherein the buried layer includes a first connecting surface and a second connecting surface, wherein the first connecting surface is flush with the height of the mesa structure, and the second connecting surface is flush with the corresponding end of the substrate layer;

[0011] Growing a barrier layer along the buried layer using MOCVD, the barrier layer being close to the outer surface of the buried layer, one end surface of the barrier layer being connected to the outer surface of the first connecting surface, and the other end surface being connected to the top of the second connecting surface; the barrier layer being flush with the mesa structure in height, and being flush with the corresponding end of the substrate layer in length;

[0012] The SiO2 mask layer is cleaned, and the growth is continued along the surfaces of the barrier layer, the buried layer and the mesa structure to obtain a laser chip with a preset thickness.

[0013] The laser chip provided in this application includes:

[0014] substrate layer;

[0015] a mesa structure, provided on the upper surface of the substrate layer;

[0016] a buried layer, arranged flush with the mesa structure, comprising a first connecting surface and a second connecting surface, wherein the inner side of the first connecting surface is connected to the outer surface of the mesa structure, and the bottom end of the second connecting surface is connected to the upper surface of the substrate layer not covered by the mesa structure;

[0017] a barrier layer, arranged flush with the table structure, with one end surface connected to the outer side of the first connecting surface and the other end surface connected to the top of the second connecting surface;

[0018] The cladding layer and the contact layer are arranged on the barrier layer, the buried layer and the mesa structure.

[0019] The optical module provided in this application includes:

[0020] circuit boards;

[0021] a light emitting component, electrically connected to the circuit board, for generating and outputting signal light, comprising a laser chip;

[0022] Wherein, the laser chip includes the laser chip prepared by the above laser chip preparation method, or the above laser chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] FIG1 is a connection diagram of an optical communication system according to some embodiments;

[0024] FIG2 is a block diagram of an optical network terminal according to some embodiments;

[0025] FIG3 is a structural diagram of an optical module according to some embodiments;

[0026] FIG4 is an exploded view of an optical module according to some embodiments;

[0027] FIG5 is a schematic diagram of the internal structure of an optical module according to some embodiments;

[0028] FIG6 is a structural diagram of an optical emission sub-module according to some embodiments;

[0029] FIG7 is a schematic diagram showing a structure in which a tube base and a tube cap are separated in a light emitting component according to some embodiments;

[0030] FIG8 is a schematic flow chart of a method for preparing a laser chip according to some embodiments;

[0031] FIG9 is a schematic diagram of a partial morphological structure of a chip after laser etching according to some embodiments;

[0032] FIG10 is a schematic diagram of a partial morphological structure of a chip after laser etching according to some embodiments;

[0033] FIG11 is a schematic diagram of a partial morphological structure of a chip after laser etching according to some embodiments;

[0034] FIG12 is a schematic diagram of a partial morphological structure of a chip after laser etching according to some embodiments;

[0035] FIG13 is a schematic diagram of a partial morphological structure of a chip after laser etching according to some embodiments;

[0036] FIG14 is a schematic diagram of a partial morphological structure of a chip after laser etching according to some embodiments;

[0037] FIG15 is a schematic diagram of the overall morphological structure of a laser chip according to some embodiments. DETAILED DESCRIPTION

[0038] In the field of fiber-optic communication technology, the signals transmitted by information transmission equipment such as optical fibers or optical waveguides are optical signals, while the signals that can be recognized and processed by information processing equipment such as computers are electrical signals. Therefore, optical modules are required to realize the mutual conversion between the above optical and electrical signals.

[0039] Figure 1 is a connection diagram of an optical communication system according to some embodiments. As shown in Figure 1, a remote server 1000 establishes a bidirectional optical communication system with a local information processing device 2000 via an optical fiber 101, an optical module 200, an optical network terminal 100, and a network cable 103.

[0040] One end of the optical fiber 101 is connected to the remote server 1000, and the other end is connected to the optical network terminal 100 through the optical module 200. One end of the network cable 103 is connected to the local information processing device 2000, and the other end is connected to the optical network terminal 100.

[0041] The connection between the local information processing device 2000 and the remote server 1000 is completed by the optical fiber 101 and the network cable 103 ; and the connection between the optical fiber 101 and the network cable 103 is completed by the optical module 200 and the optical network terminal 100 .

[0042] In optical module 200, the optical port is configured to connect to optical fiber 101, thereby establishing a bidirectional optical signal connection between optical module 200 and optical fiber 101; the electrical port is configured to connect to optical network terminal 100, thereby establishing a bidirectional electrical signal connection between optical module 200 and optical network terminal 100. Optical module 200 performs mutual conversion between optical and electrical signals, thereby establishing a connection between optical fiber 101 and optical network terminal 100.

[0043] The optical network terminal 100 is provided with an optical module interface 102 and a network cable interface 104. The optical module interface 102 is configured to connect to the optical module 200, thereby establishing a bidirectional electrical signal connection between the optical network terminal 100 and the optical module 200. The network cable interface 104 is configured to connect to the network cable 103, thereby establishing a bidirectional electrical signal connection between the optical network terminal 100 and the network cable 103. The connection between the optical module 200 and the network cable 103 is established through the optical network terminal 100. In addition to the optical network terminal 100, the host computer of the optical module 200 may also include an optical line terminal (OLT) and the like.

[0044] FIG2 is a block diagram of an optical network terminal according to some embodiments. As shown in FIG2 , the optical network terminal 100 further includes a PCB 105 disposed within a housing, a cage 106 disposed on a surface of the PCB 105, and an electrical connector disposed within the cage 106. The electrical connector is configured to connect to the electrical port of the optical module 200; the heat sink 107 has raised portions, such as fins, that increase the heat dissipation area.

[0045] The optical module 200 is inserted into the cage 106 of the optical network terminal 100. The cage 106 secures the optical module 200, and the heat generated by the optical module 200 is transferred to the cage 106 and then dissipated through the heat sink 107. After the optical module 200 is inserted into the cage 106, the electrical port of the optical module 200 connects to the electrical connector inside the cage 106, thereby establishing a bidirectional electrical signal connection between the optical module 200 and the optical network terminal 100.

[0046] Figure 3 is a structural diagram of an optical module according to some embodiments, and Figure 4 is an exploded diagram of an optical module according to some embodiments. As shown in Figures 3 and 4 , the optical module 200 includes a housing and a circuit board 105 disposed in the housing.

[0047] The housing includes an upper housing 201 and a lower housing 202 . The upper housing 201 covers the lower housing 202 to form the housing having two openings 204 and 205 . The outer contour of the housing is generally a square.

[0048] The direction of the line connecting the two openings 204 and 205 can be aligned with or inconsistent with the length of the optical module 200. Opening 204 is an electrical port, through which the gold finger of the circuit board 105 extends and is inserted into the host computer. Opening 205 is an optical port, configured to receive an external optical fiber 101, thereby connecting the optical fiber 101 to the interior of the optical module 200.

[0049] The upper housing 201 and the lower housing 202 are combined to facilitate installation of components such as the circuit board 105 into the housing, and these components can be encapsulated and protected by the upper housing 201 and the lower housing 202. According to some embodiments, the upper housing 201 and the lower housing 202 are generally made of metal materials to facilitate electromagnetic shielding and heat dissipation.

[0050] According to some embodiments, the optical module 200 further includes an unlocking component 203 located on the outer wall of its housing. When the optical module 200 is inserted into the cage of the host computer, the locking components of the unlocking component 203 lock the optical module 200 into the cage of the host computer. When the unlocking component 203 is pulled, the locking components of the unlocking component 203 move accordingly, thereby changing the connection between the locking components and the host computer, thereby releasing the optical module 200 from the host computer.

[0051] The circuit board 105 includes circuit traces, electronic components and chips, and the electronic components and chips are connected together according to the circuit design through the circuit traces.

[0052] The circuit board 105 is generally a rigid circuit board. Due to its relatively hard material, the rigid circuit board can also realize the bearing function. For example, the rigid circuit board can stably carry the chip. The rigid circuit board can also be inserted into the electrical connector in the upper computer cage.

[0053] Circuit board 105 also includes gold fingers formed on its end surfaces. These gold fingers consist of multiple independent pins. Circuit board 105 is inserted into cage 106, where the gold fingers provide electrical connection to the electrical connector within cage 106. These gold fingers are configured to establish an electrical connection with the host computer for power supply, grounding, I2C signal transmission, data signal transmission, and more. Of course, some optical modules also utilize flexible printed circuit boards in conjunction with circuit board 105.

[0054] According to some embodiments, the optical transceiver assembly includes an optical transmitting assembly 400 and an optical receiving assembly 500. The optical transmitting assembly 400 and the optical receiving assembly 500 are both arranged on the round square tube body 300. The optical transmitting assembly 400 is used to generate and output signal light, and the optical receiving assembly 500 is used to receive signal light from outside the optical module. An optical fiber adapter is provided on the round square tube body 300, and the optical fiber adapter is used to connect the optical module to the external optical fiber. A lens assembly is usually provided in the round square tube body 300, and the lens assembly is used to change the propagation direction of the signal light output by the optical transmitting assembly 400 or the signal light input by the external optical fiber. The optical transmitting assembly 400 and the optical receiving assembly 500 are physically separated from the circuit board 105. Therefore, it is difficult for the optical transmitting assembly 400 and the optical receiving assembly 500 to be directly connected to the circuit board 105. Therefore, in the embodiment of the present application, the optical transmitting assembly 400 and the optical receiving assembly 500 are electrically connected respectively through a flexible circuit board. However, in the embodiment of the present application, the assembly structure of the optical emitting component 400 and the optical receiving component 500 is not limited to the structure shown in Figures 3 and 4, and can also be other assembly combination structures, such as the optical emitting component 400 and the optical receiving component 500 are set on different tubes. This embodiment only takes the structure shown in Figures 3 and 4 as an example.

[0055] FIG5 is a schematic diagram of the internal structure of an optical module provided in accordance with some embodiments, FIG6 is a schematic diagram of the external structure of an optical emitting device provided in accordance with some embodiments, and FIG7 is a schematic diagram of an exploded view of an optical emitting device provided in accordance with some embodiments. As shown in FIG5-7, in some embodiments of the present application, an optical emitting assembly 400 includes a socket 410, a cap 420, and other components disposed within the cap 420 and the socket 410. The cap 420 is disposed on one end of the socket 410. The socket 410 includes a plurality of pins, which are used to electrically connect the flexible circuit board to other electrical components within the optical emitting assembly 400, thereby electrically connecting the optical emitting assembly 400 to the circuit board 105. The optical emitting assembly 400 includes a laser chip 600, which is used to generate an optical signal, and the generated optical signal passes through the cap 420. Of course, the use of the laser chip 600 in the embodiments of the present application is not limited to the optical emitting device shown in FIG5-7.

[0056] The laser chip 600 of the present application includes a semiconductor quantum well structure laser chip, and the semiconductor quantum well structure laser chip includes an AlInGaAs quantum well laser chip. In the embodiments of the present application, the AlInGaAs quantum well laser chip is used as an example for explanation.

[0057] FIG8 is a schematic diagram of the process of preparing a laser chip, and FIG9 to FIG15 are schematic diagrams of various growth morphological structures during the preparation process of the laser chip.

[0058] As shown in FIG8 , the embodiment of the present application provides a method for preparing a laser chip, comprising:

[0059] S110: growing a substrate containing an AlInGaAs quantum dot structure on a substrate layer of InP material.

[0060] Specifically, epitaxially growing an N-InP buffer layer on the surface of the substrate layer;

[0061] Growing an AlInGaAs lower waveguide layer with a bandgap width and a refractive index gradient on the N-InP buffer layer;

[0062] Growing an AlInGaAs multi-quantum well active layer on the AlInGaAs lower waveguide layer;

[0063] Growing an AlInGaAs upper waveguide layer on the AlInGaAs multi-quantum well active layer;

[0064] sequentially growing a low-doped P-InP transition layer and a P-InGaAsP transition layer on the AlInGaAs upper waveguide layer;

[0065] Growing a low-doped P-InP space layer on the P-InGaAsP transition layer;

[0066] Growing an AlInGaAs grating layer on the P-InP space layer;

[0067] A P-InP protective layer is grown on the AlInGaAs grating layer.

[0068] The structure after growth is shown in FIG9 .

[0069] S120: forming a SiO2 mask layer on the upper surface of the substrate by photolithography, and performing mask etching on the substrate to obtain a mesa structure.

[0070] Specifically, a SiO2 mask layer is formed on the upper surface of the substrate by photolithography using photolithography technology;

[0071] performing mask etching on the substrate to obtain a mesa structure;

[0072] The mesa structure includes, from bottom to top, an N-InP buffer layer, an AlInGaAs lower waveguide layer with a gradient bandgap width and refractive index, an AlInGaAs multi-quantum well active layer, an AlInGaAs upper waveguide layer, a P-InP transition layer and a P-InGaAsP transition layer, a low-doped P-InP space layer, an AlInGaAs grating layer, and a P-InP protective layer.

[0073] The structure during growth is shown in Figures 10 and 11.

[0074] S130: Use MOCVD CBr4 for in-situ cleaning and grow a buried layer along the mesa structure.

[0075] Specifically, 30 minutes before the laser chip is placed in the MOCVD reaction chamber, it is etched with HBr:H2O (1:20) for 1 minute and then etched with Br2:HBr:H2O (1:17:216) solution for 30 seconds for preliminary deoxidation; then CBr4 in-situ cleaning is performed. Through CBr4 in-situ cleaning, the impurities and oxygen content on the surface of the mesa structure 640 can be reduced, and the first connecting surface 6501 and the second connecting surface 6502 can be grown at the same time. During the specific growth, the growth extends along the upper surface of the substrate layer 610 until the second connecting surface 6502 is generated, and then the growth continues along the second connecting surface 6502 until the first connecting surface 6501 is generated. The etched surface of the mesa structure 640 can be protected by the first connecting surface 6501 and the second connecting surface 6502 to prevent the aluminum element in the mesa structure 640 from being oxidized by the air, thereby reducing the difficulty of regrowth and facet coating in the subsequent process of obtaining the mesa structure 640. At the same time, a barrier layer 660 is filled in the blank area of ​​the buried layer 650, and the barrier layer 660 can further protect the etched surface of the mesa structure 640. At the same time, since the degree of air strengthening on the outer surface of the mesa structure 640 is reduced, the surface morphology can be improved, the roughness can be reduced, and the luminous intensity of the regrown layer on the wafer surface can be increased, thereby ensuring the performance of the AlInGaAs quantum well laser chip.

[0076] It should be noted that the 30 minutes and 30 seconds in the above description of this application are both examples provided by this application. During specific implementation, the specific duration can be set by the technicians themselves.

[0077] In some embodiments of the present application, in order to achieve regrowth of a laser chip quality layer, the CBr4 etching process includes:

[0078] A protective gas and an etching gas are filled into an MOCVD reaction chamber. By controlling the flow of the protective gas and the etching gas and parameters such as the growth temperature, the etching rate of the etching gas is precisely controlled until a specific buried heterostructure growth layer is obtained. Specifically, phosphine PH3 is used as the protective gas, trimethylindium TMIn is used as the source gas, and CBr4 is used as the etching gas. The flow rate of phosphine PH3 is kept constant. The surface growth and optical properties of the wafers are compared when the source gas trimethylindium TMIn and the etching gas CBr4 are introduced simultaneously and when the source gas trimethylindium TMIn and the etching gas CBr4 are introduced alternately. The results show that the result of introducing the source gas trimethylindium TMIn and the etching gas CBr4 simultaneously is better. The growth temperature is 685°C, and CBr4 is used as the etching gas at 685°C. After in-situ cleaning with etching gas, the orange peel, haze, and surface defects on the wafer surface are at their lowest levels, so the growth temperature is 685°C. At a growth temperature of 685°C, source gas trimethylindium (TMIn) flow rates of 40cc, 100cc, 200cc, 300cc, and 400cc were used, respectively. The surface morphology and optical properties were then measured using a high-resolution microscope. The results showed that when the source gas trimethylindium (TMIn) flow rate was 400cc, both the surface morphology and optical properties were superior. At 685°C and with a source gas flow rate of 400cc, source gas trimethylindium (TMIn) and etching gas CBr4 were introduced simultaneously. While cleaning the etched surface, slow growth was performed for 1 minute, achieving a relatively ideal buried heterostructure growth. In this embodiment of the present application, a thin InP buried layer was grown in an MOCVD reaction chamber using a CBr4 in-situ cleaning method, while simultaneously reducing the impurities and oxygen content on the sidewalls of the laser mesa.

[0079] The structure after growth is shown in FIG12 .

[0080] S140: using MOCVD to grow a barrier layer along the buried layer.

[0081] Growing a barrier layer along the buried layer by MOCVD according to a conventional growth method, comprising:

[0082] A barrier layer is grown along the buried layer in MOCVD without introducing CBr4 gas during the growth.

[0083] The structure after growth is shown in FIG13 .

[0084] S150: Clean the SiO2 mask layer and continue growing along the surfaces of the barrier layer, the buried layer and the mesa structure to obtain a laser chip with a preset thickness.

[0085] Specifically, the laser chip is taken out of the MOCVD reaction chamber, and the SiO2 mask layer 630 is removed by a cleaning solution; as shown in FIG15 , a cladding layer and a contact layer 670 are provided above the mesa structure 640, the buried layer 650 and the barrier layer 660, and the cladding layer and the contact layer 670 are mainly used as ohmic contacts; the length of the cladding layer and the contact layer 670 is consistent with the length of the substrate layer 610.

[0086] The structure during growth is shown in Figures 14 and 15.

[0087] The final structure of the laser chip prepared according to the above growth method is shown in FIG15 . As shown in FIG15 , the bottom layer of the laser chip is provided with a substrate layer 610, which is an InP substrate layer; the upper surface of the substrate layer 610 includes a table structure 640, a buried layer 650 and a barrier layer 660 from the inside to the outside; the top layer of the laser chip is provided with a cladding layer and a contact layer 670; the growth order of these growth layers is substrate layer 610, table structure 640, buried layer 650, barrier layer 660, cladding layer and contact layer 670; after the table structure 640 is grown, since the table structure 640 contains aluminum, it is easily oxidized by air, which affects the subsequent The growth of the subsequent growth layer, the etched surface of the mesa structure 640 can be protected by the buried layer 650 to prevent the aluminum element in the mesa structure 640 from being oxidized by the air, reducing the difficulty of regrowth and facet coating in the subsequent process of obtaining the mesa structure 640. At the same time, the blank area of ​​the buried layer 650 is filled with a barrier layer 660, and the barrier layer 660 can further protect the etched surface of the mesa structure 640; at the same time, since the outer surface of the mesa structure 640 is less strengthened by the air, the surface morphology can be improved, the roughness can be reduced, and the luminous intensity of the regrown layer on the wafer surface can be increased, thereby ensuring the performance of the AlInGaAs quantum well laser chip.

[0088] Furthermore, the bottom layer of the laser chip provided in the embodiment of the present application includes a substrate layer 610. The middle layers of the laser chip include, from the inside out, a mesa structure 640, a buried layer 650, and a barrier layer 660. The top layer of the laser chip includes a cladding layer and a contact layer 670. The height of the buried layer 650 and the barrier layer is set to be flush with the height of the mesa structure 640. The length of the substrate layer 610 is consistent with the length of the cladding layer and the contact layer 670. The thickness of the buried layer 650 is less than that of the barrier layer 660. Specifically, the buried layer 650 is a thin layer. The buried layer 650 includes a first connecting surface 6501 and a second connecting surface 6502. The inner wall of the first connecting surface 6501 is connected to the outer surface of the mesa structure 640, and the outer wall is connected to the inner surface of the barrier layer 660. The bottom end of the second connecting surface 6502 is connected to the upper surface of the mesa structure 640, and the top end is connected to the lower surface of the barrier layer 660. The height of the first connecting surface 6501 is flush with the mesa structure 640, and the length of the second connecting surface 6502 is flush with the corresponding end of the substrate layer 610. The first connecting surface 6501 and the second connecting surface 6502 are connected to form a buried layer 650. The buried layer 650 can tightly wrap the mesa structure 640, thereby preventing the aluminum elements in the mesa structure 640 from being oxidized by air, reducing the surface roughness of the mesa structure 640, ensuring the surface morphology of the mesa structure 640, and ensuring the growth of subsequent growth layers. In some embodiments of the present application, the cross-section of the mesa structure 640 can be cylindrical or trapezoidal. When the cross-section of the mesa structure 640 is cylindrical, the first connecting surface 6501 and the second connecting surface 6502 are perpendicular to each other, forming the buried layer 650.

[0089] The final state of the barrier layer 660 during the growth process is that it is filled in the blank area surrounded by the first connecting surface 6501 and the second connecting surface 6502. As shown in Figure 14, the blank area surrounded by the first connecting surface 6501 and the second connecting surface 6502 is a rectangular space. Therefore, the final state of the barrier layer 660 is that it is filled in the rectangular area surrounded by the first connecting surface 6501 and the second connecting surface 6502.

[0090] The mesa structure 640, the buried layer 650 and the barrier layer 660 are arranged in sequence from the inside to the outside and are highly aligned. The etched surface of the mesa structure 640 is wrapped by the buried layer 650, which can reduce the degree of oxidation of the etched surface of the mesa structure 640, ensure the surface morphology of the etched surface of the mesa structure 640, facilitate the subsequent growth of the barrier layer 660, and also facilitate reducing the roughness and increasing the luminous intensity of the regrown layer on the wafer surface, thereby ensuring the performance of the AlInGaAs quantum well laser chip. The barrier layer 660 mainly functions as a current blocking layer. Secondly, it can also surround the buried layer 650, thereby assisting the buried layer 650 in protecting the surface morphology of the etched surface of the mesa structure 640.

[0091] The cladding layer and contact layer 670 are covered on top of the mesa structure 640, the buried layer 650 and the barrier layer 660. The cladding layer and contact layer 670 are mainly used for ohmic contact. The length of the cladding layer and contact layer 670 is consistent with the length of the substrate layer 610, and is also consistent with the length of the layer structure jointly formed by the mesa structure 640, the buried layer 650 and the barrier layer 660.

[0092] The etched surface of the mesa structure 640 can be protected by the first connecting surface 6501 and the second connecting surface 6502 to prevent the aluminum element in the mesa structure 640 from being oxidized by air, thereby reducing the difficulty of regrowth and facet coating in the subsequent process of obtaining the mesa structure 640. At the same time, a barrier layer 660 is filled in the blank area of ​​the buried layer 650, and the barrier layer 660 can further protect the etched surface of the mesa structure 640; at the same time, since the degree of air strengthening on the outer surface of the mesa structure 640 is reduced, the surface morphology can be improved, the roughness can be reduced, and the luminous intensity of the regrown layer on the wafer surface can be increased, thereby ensuring the performance of the AlInGaAs quantum well laser chip.

[0093] In some embodiments of the present application, a suitable substrate layer 610 is selected, and an epitaxial layer can be grown on the substrate layer 610 using a MOCVD (metal organic chemical vapor deposition) method to obtain an epitaxial substrate. For example, an N-type InP substrate layer can be used, and an epitaxial layer can be grown on the N-type InP substrate layer using MOCVD. Specifically, in the embodiments of the present application, cleaning the impurities and oxygen content of the sidewalls of a buried structure aluminum indium gallium arsenide (AlInGaAs) laser mesa in an MOCVD reaction chamber not only reduces the oxygen content of the sidewalls of the AlInGaAs laser mesa, but also simplifies the process and has high repeatability.

[0094] The morphology of each growth layer of the laser chip provided in this application is described in conjunction with Figures 9-15. As shown in Figure 9, a substrate 620 containing an AlInGaAs quantum-horizon structure is grown on an InP substrate layer. The substrate 620 containing the AlInGaAs quantum-horizon structure is grown using MOCVD. The substrate 620 containing the AlInGaAs quantum-horizon structure includes, from bottom to top, an N-InP buffer layer, an AlInGaAs lower waveguide layer with a gradient bandgap and refractive index, an AlInGaAs multi-quantum well active layer, an AlInGaAs upper waveguide layer, a P-InP transition layer and a P-InGaAsP transition layer, a low-doped P-InP space layer, an AlInGaAs grating layer, and a P-InP protective layer.

[0095] As shown in FIG10 , a SiO2 mask layer 630 is provided on the upper surface of a substrate 620 containing an AlInGaAs quantum dot structure. Specifically, the SiO2 mask layer 630 is formed on the upper surface of the substrate 620 by photolithography using photolithography technology. The SiO2 mask layer 630 mainly serves as a mask during ridge waveguide etching, and may also be silicon oxynitride (SiON) or silicon nitride (SiN).

[0096] As shown in Figure 11, a mesa structure 640 is provided on the upper surface of substrate layer 610. Specifically, the substrate 620 is masked and etched to form mesa structure 640. The layers of mesa structure 640 are identical to those of substrate 620. From bottom to top, mesa structure 640 comprises: an N-InP buffer layer, an AlInGaAs lower waveguide layer with a graded bandgap and refractive index, an AlInGaAs multi-quantum well active layer, an AlInGaAs upper waveguide layer, a P-InP transition layer and a P-InGaAsP transition layer, a low-doped P-InP spacer layer, an AlInGaAs grating layer, and a P-InP protective layer. At this point, the Al-doped quantum wells are exposed to air and oxidize, resulting in reduced device reliability.

[0097] As shown in Figure 12, the mesa structure 640 covers the middle of the substrate layer 610, and a buried layer 650 is provided on the periphery of the mesa structure 640. The buried layer 650 wraps the periphery of the mesa structure 640 to protect the outer surface of the mesa structure 640 and isolate it from the air around the mesa structure 640; the middle of the substrate layer 610 is covered by the mesa structure 640, and the two ends of the substrate layer 610 except the middle part are respectively connected to the second connecting surface 6502, and the second connecting surface 6502 is covered in the area of ​​the substrate layer 610 not covered by the mesa structure 640. The mesa structure 640 is protected by the buried layer 650, thereby preventing the aluminum element in the mesa structure 640 from being oxidized by the air, reducing the surface roughness of the mesa structure 640, and ensuring the surface morphology of the mesa structure 640; under the condition of ensuring the surface morphology of the mesa structure 640, the difficulty and complexity of subsequent growth layer and etching coating can be reduced.

[0098] The height of the first connecting surface 6501 is flush with the mesa structure 640, and the length of the second connecting surface 6502 is flush with the corresponding end of the substrate layer 610. The first connecting surface 6501 and the second connecting surface 6502 are connected to form a buried layer 650. The buried layer 650 can tightly wrap the mesa structure 640, thereby preventing the aluminum elements in the mesa structure 640 from being oxidized by air, reducing the surface roughness of the mesa structure 640, ensuring the surface morphology of the mesa structure 640, and ensuring the growth of subsequent growth layers. In some embodiments of the present application, the cross-section of the mesa structure 640 can be cylindrical or trapezoidal. When the cross-section of the mesa structure 640 is cylindrical, the first connecting surface 6501 and the second connecting surface 6502 are perpendicular to each other, forming the buried layer 650.

[0099] As shown in Figure 13, a blocking layer 660 is provided in the blank area of ​​the buried layer, one end face of the blocking layer 660 is connected to the outer surface of the first connecting surface 6501, and the other end face is connected to the top of the second connecting surface 6502; the height of the blocking layer 660 is set flush with the mesa structure 640, and the length of the blocking layer 660 is set flush with the end of the corresponding substrate layer 610; the blocking layer 660 is a current blocking layer, which relies on its reverse PN junction to limit the current; at the same time, the blocking layer 660 can further protect the etched surface of the mesa structure; to prevent the outer surface of the mesa structure from being oxidized by air, and to ensure the surface morphology of the mesa structure 640.

[0100] As shown in FIG14 , the SiO2 mask layer 630 has been removed. Specifically, the laser chip in FIG12 is taken out of the MOCVD reaction chamber, and the SiO2 mask layer 630 is removed by a cleaning solution. As shown in FIG15 , a cladding layer and a contact layer 670 are provided above the mesa structure 640, the buried layer 650, and the barrier layer 660. The cladding layer and the contact layer 670 are mainly used as ohmic contacts. The length of the cladding layer and the contact layer 670 is consistent with the length of the substrate layer 610.

[0101] Therefore, after the above growth process, the bottom layer of the laser chip provided by the embodiment of the present application is provided with a substrate layer 610, and the substrate layer 610 is an InP substrate layer; the upper surface of the substrate layer 610 includes a table structure 640, a buried layer 650 and a barrier layer 660 from the inside to the outside; the top layer of the laser chip is provided with a cladding layer and a contact layer 670; the height of the buried layer 650 and the barrier layer 660 is flush with the height of the table structure 640; the thickness of the buried layer 650 is less than the thickness of the barrier layer 660; the length of the substrate layer 610 is consistent with that of the cladding layer and the contact layer 670; the surface structure 640 covers the middle of the substrate layer 610, and the periphery of the table structure 640 is provided with a first connecting surface 6501, and the first connecting surface 6501 wraps the periphery of the table structure 640 to protect the outer surface of the table structure 640 and is in contact with the table structure 640 is isolated from the air around it; the middle of the substrate layer 610 is covered by the mesa structure 640, and the two ends of the substrate layer 610 excluding the middle part are provided with a second connecting surface 6502, and the second connecting surface 6502 is covered in the area of ​​the substrate layer 610 not covered by the mesa structure 640. The second connecting surface 6502 can cover the structure of the substrate layer 610 exposed to the outside of the air, protect the substrate layer 610, and isolate it from the air around the substrate layer 610, further protect the mesa structure 640, and thus prevent the aluminum element in the mesa structure 640 from being oxidized by the air, reduce the surface roughness of the mesa structure 640, and ensure the surface morphology of the mesa structure 640; under the condition of ensuring the surface morphology of the mesa structure 640, the difficulty and complexity of subsequent growth layer and etching coating can be reduced. The first connecting surface 6501 and the second connecting surface 6502 are connected to form a buried layer 650. The buried layer 650 can tightly wrap the mesa structure 640, thereby preventing the aluminum element in the mesa structure 640 from being oxidized by air, reducing the surface roughness of the mesa structure 640, ensuring the surface morphology of the mesa structure 640, and ensuring the growth of subsequent growth layers.

[0102] The present application can wrap the outer surface of the mesa structure through the buried layer. In this way, after the mesa structure is obtained, the etched surface of the mesa structure can be protected by the buried layer to prevent the aluminum element in the mesa structure from being oxidized by the air, thereby reducing the difficulty of regrowth and facet coating in the subsequent process of obtaining the mesa structure. At the same time, a barrier layer is filled in the blank area of ​​the buried layer, and the barrier layer can further protect the etched surface of the mesa structure. At the same time, since the degree of air strengthening of the outer surface of the mesa structure is reduced, the surface morphology can be improved, the roughness can be reduced, and the luminous intensity of the regrown layer on the wafer surface can be increased, thereby ensuring the performance of the AlInGaAs quantum well laser chip.

[0103] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A method for preparing a laser chip, comprising: Growing a substrate containing an AlInGaAs quantum dot structure on an InP substrate layer; forming a SiO2 mask layer on the upper surface of the substrate by photolithography, and performing mask etching on the substrate to obtain a mesa structure; Using MOCVD CBr4 in-situ cleaning, a buried layer is grown along the mesa structure, wherein the buried layer includes a first connecting surface and a second connecting surface, wherein the first connecting surface is flush with the height of the mesa structure, and the second connecting surface is flush with the corresponding end of the substrate layer; Growing a barrier layer along the buried layer using MOCVD, the barrier layer being close to the outer surface of the buried layer, one end surface of the barrier layer being connected to the outer surface of the first connecting surface, and the other end surface being connected to the top of the second connecting surface; the barrier layer being flush with the mesa structure in height, and being flush with the corresponding end of the substrate layer in length; The SiO2 mask layer is cleaned, and the growth is continued along the surfaces of the barrier layer, the buried layer and the mesa structure to obtain a laser chip with a preset thickness.

2. The laser chip preparation method according to claim 1, wherein growing a substrate containing an AlInGaAs quantum-bridge structure on an InP substrate layer comprises: Epitaxially growing an N-InP buffer layer on the surface of the substrate layer; Growing an AlInGaAs lower waveguide layer with a bandgap width and a refractive index gradient on the N-InP buffer layer; Growing an AlInGaAs multi-quantum well active layer on the AlInGaAs lower waveguide layer; Growing an AlInGaAs upper waveguide layer on the AlInGaAs multi-quantum well active layer; sequentially growing a low-doped P-InP transition layer and a P-InGaAsP transition layer on the AlInGaAs upper waveguide layer; Growing a low-doped P-InP space layer on the P-InGaAsP transition layer; Growing an AlInGaAs grating layer on the P-InP space layer; A P-InP protective layer is grown on the AlInGaAs grating layer.

3. The laser chip preparation method according to claim 1, wherein forming a SiO2 mask layer on the upper surface of the substrate by photolithography and performing mask etching on the substrate to obtain a mesa structure comprises: forming a SiO2 mask layer on the upper surface of the substrate by photolithography using photolithography technology; performing mask etching on the substrate to obtain a mesa structure; The mesa structure includes, from bottom to top, an N-InP buffer layer, an AlInGaAs lower waveguide layer with a gradient bandgap width and refractive index, an AlInGaAs multi-quantum well active layer, an AlInGaAs upper waveguide layer, a P-InP transition layer and a P-InGaAsP transition layer, a low-doped P-InP space layer, an AlInGaAs grating layer, and a P-InP protective layer.

4. The laser chip fabrication method according to claim 1, wherein the step of using MOCVD CBr4 in-situ cleaning to grow a buried layer along the mesa structure comprises: Phosphine PH3 is used as the protective gas, trimethyl indium TMIn is used as the source gas, and CBr4 is used as the etching gas; The etched surface of the mesa structure is cleaned in MOCVD and slowly grown for a preset time to obtain a buried layer, wherein the growth temperature is 685° C. during the growth.

5. The laser chip manufacturing method according to claim 1, wherein the step of growing a barrier layer along the buried layer by MOCVD comprises: A barrier layer is grown along the buried layer in MOCVD without introducing CBr4 gas during the growth.

6. The laser chip preparation method according to claim 1, wherein the cleaning of the SiO2 mask layer and the continued growth along the surfaces of the barrier layer, the buried layer, and the mesa structure to obtain a laser chip of a predetermined thickness comprises: Remove from MOCVD and clean the SiO2 mask layer; The structure after cleaning the SiO2 mask layer is placed in MOCVD, and growth continues along the surfaces of the barrier layer, the buried layer and the mesa structure until a laser chip with a preset thickness is obtained.

7. A laser chip, comprising: substrate layer; a mesa structure, provided on the upper surface of the substrate layer; a buried layer, arranged flush with the mesa structure, comprising a first connecting surface and a second connecting surface, wherein the inner side of the first connecting surface is connected to the outer surface of the mesa structure, and the bottom end of the second connecting surface is connected to the upper surface of the substrate layer not covered by the mesa structure; a barrier layer, arranged flush with the table structure, with one end surface connected to the outer side of the first connecting surface and the other end surface connected to the top of the second connecting surface; The cladding layer and the contact layer are arranged on the barrier layer, the buried layer and the mesa structure.

8. The laser chip according to claim 7, wherein the buried layer comprises a first connecting surface and a second connecting surface, wherein the first connecting surface is flush with the mesa structure, and the second connecting surface is flush with the corresponding end of the substrate layer; The barrier layer is close to the outer surface of the buried layer, one end surface of the barrier layer is connected to the outer surface of the first connecting surface, and the other end surface is connected to the top of the second connecting surface; the height of the barrier layer is flush with the mesa structure, and the length of the barrier layer is flush with the corresponding end of the substrate layer.

9. The laser chip according to claim 7, wherein the laser chip comprises a mesa structure, wherein the mesa structure comprises, from bottom to top: N-InP buffer layer, AlInGaAs lower waveguide layer with graded bandgap width and refractive index, AlInGaAs multi-quantum well active layer, AlInGaAs upper waveguide layer, P-InP transition layer and P-InGaAsP transition layer, low-doped P-InP space layer, AlInGaAs grating layer, P-InP protective layer; The two ends of the mesa structure are provided with a buried layer and a barrier layer in sequence; A substrate layer is provided at the bottom end of the mesa structure.

10. The laser chip according to claim 7, wherein the substrate layer is located at the bottom layer of the laser chip; the mesa structure, the buried layer and the barrier layer are located at the middle layer of the laser chip; the cladding layer and the contact layer are located at the top layer of the laser chip, wherein the mesa structure, the buried layer and the barrier layer are arranged in sequence from the inside to the outside.

11. The laser chip according to claim 7, wherein the mesa structure comprises, from bottom to top: InP buffer layer, AlInGaAs lower waveguide layer, AlInGaAs multi-quantum well active layer, AlInGaAs upper waveguide layer, InP transition layer and InGaAsP transition layer, InP space layer, AlInGaAs grating layer, InP protective layer.

12. The laser chip according to claim 7, wherein the mesa structure is a cylindrical mesa; The first connecting surface and the second connecting surface are perpendicular to each other; The first connecting surface wraps the outer surface of the mesa structure, and the second connecting surface is covered on the surface of the substrate layer not covered by the mesa structure. 13 . The laser chip according to claim 7 , wherein the buried layer has a thickness smaller than that of the barrier layer. The laser chip according to claim 7 , wherein the buried layer is obtained by CBr 4 etching. 15 . The laser chip according to claim 7 , wherein the substrate layer is an InP substrate layer, and the cladding layer and the contact layer are InP cladding layer and contact layer. The laser chip according to claim 7 , wherein the mesa structure, the buried layer, and the barrier layer are all at the same height. The laser chip according to claim 7 , wherein the mesa structure comprises a quantum well structure.

18. An optical module, comprising: circuit boards; a light emitting component, electrically connected to the circuit board, for generating and outputting signal light, comprising a laser chip; Wherein, the laser chip includes a laser chip prepared by the laser chip preparation method according to any one of claims 1 to 6, or a laser chip according to any one of claims 7 to 17.

Images