A capacitance detection circuit based on peak detection and its measurement method

Abstract

This invention proposes a capacitance detection circuit based on peak detection and its operation method. The circuit includes a signal generation circuit (101), a signal conversion circuit (102), a peak detection circuit (103), and an analog-to-digital conversion circuit (104). The input terminal of the signal generation circuit is used to receive the capacitance to be measured. The output terminal of the signal generation circuit is connected to the input terminal of the signal conversion circuit through the capacitance to be measured. The output terminal of the signal conversion circuit is connected to the input terminal of the peak detection circuit. The output terminal of the peak detection circuit is connected to the input terminal of the analog-to-digital conversion circuit. The analog-to-digital conversion circuit outputs the capacitance detection result. The capacitance detection circuit designed in this invention has a simple circuit structure, is easy to build, and has intuitive circuit connections. The overall power consumption of the system is low. Furthermore, the circuit is easy to implement physically, and the final analog-to-digital converter and the host computer can be easily interconnected, making it suitable for various capacitance measurement applications.

Description

Technical Field

[0001] This invention relates to a capacitance detection circuit based on peak detection and its measurement method, belonging to the technical field of capacitance detection interface circuits. Background Art

[0002] The technical background of capacitance detection circuits involves multiple aspects, mainly including the working principle, application areas, technical challenges, and corresponding measurement circuit design and development of capacitance sensors. Capacitive sensors have important applications in many fields, including but not limited to: Industrial automation: used to detect parameters such as position, velocity, and acceleration of mechanical parts for precise control; Aerospace: playing a crucial role in attitude control and navigation systems of aircraft, rockets, and other equipment; Environmental monitoring: used to measure environmental parameters such as liquid level, humidity, and gas concentration; Biomedicine: used in medical devices to detect physiological parameters of organisms, such as heartbeat and respiration.

[0003] Despite the numerous advantages of capacitive sensors, several technical challenges exist in practical applications: First, parasitic capacitance plays a role. In actual circuits, besides the sensor's inherent capacitance, various parasitic capacitances exist, which can interfere with measurement results and reduce accuracy. Second, power supply voltage stability is crucial; fluctuations in the power supply voltage directly affect the accuracy of the measurement results. Third, detecting minute capacitances requires high-precision measurement circuits and signal processing techniques to achieve high sensitivity and high resolution.

[0004] To overcome the aforementioned technical challenges, researchers have designed various capacitance detection circuits and continuously improved and optimized their performance. Common capacitance detection circuits include: operational amplifier circuits, which utilize the high amplification factor and low noise characteristics of operational amplifiers to amplify and process capacitance signals; bridge circuits, which convert capacitance changes into voltage or current changes for easy measurement and recording; frequency modulation circuits, which convert capacitance changes into frequency changes, leveraging the high precision of frequency measurements to improve measurement accuracy; and resonant circuits, which utilize a resonant circuit composed of a capacitor and an inductor to indirectly measure capacitance changes by measuring changes in the resonant frequency.

[0005] Furthermore, with the development of microelectronics technology and digital signal processing technology, capacitance detection circuits are also evolving towards digitalization and intelligence. For example, digital intelligent capacitance sensors integrate measurement component technology with the computing capabilities of microprocessors, making the measuring instrument and control instrument a fully digital system, greatly improving measurement accuracy and stability.

[0006] In summary, the technical background of capacitance detection circuits involves multiple aspects, including the working principle of capacitance sensors, application fields, technical challenges, and the design and development of measurement circuits. With continuous technological advancements and innovation, the performance of capacitance detection circuits will continue to improve and be perfected, providing more reliable and accurate technical support for various industrial measurement and automation control systems. The performance of the capacitance sensor detection circuit determines the quality of the entire capacitance sensor chain, from the natural signal to the final signal processing and display results, and is one of the bottlenecks that capacitance sensor technology often needs to overcome for its continued development. Therefore, the design of capacitance sensor detection circuits has always been highly valued.

[0007] In response to this, this patent proposes a capacitance detection circuit and its measurement method based on peak detection. Compared with other capacitance sensor interface circuits, it can not only perform capacitance detection, but also has excellent characteristics such as simple principle, small area, low power consumption and low noise. Summary of the Invention

[0008] To address the technical problem of low measurement accuracy caused by the inability of existing capacitive sensors to overcome parasitic capacitance, this invention proposes a capacitance detection circuit and its measurement method based on peak detection.

[0009] The technical solution adopted by the present invention to solve the above problems is as follows: The present invention proposes a capacitance detection circuit based on peak detection, comprising:

[0010] The circuit includes a signal generation circuit (101), a signal conversion circuit (102), a peak detection circuit (103), and an analog-to-digital conversion circuit (104).

[0011] The input terminal of the signal generation circuit (101) is used to receive the capacitor under test. The output terminal of the signal generation circuit (101) is connected to the input terminal of the signal conversion circuit (102) through the capacitor under test. The output terminal of the signal conversion circuit (102) is connected to the input terminal of the peak detection circuit (103). The output terminal of the peak detection circuit (103) is connected to the input terminal of the analog-to-digital conversion circuit (104). The analog-to-digital conversion circuit outputs the capacitance detection result.

[0012] Optionally, the signal generation circuit (101) includes a sine wave module and an excitation signal module;

[0013] The sine wave module is used to obtain sine waves;

[0014] The excitation signal module acquires a sinusoidal excitation signal based on the acquired sine wave.

[0015] Optionally, the signal conversion circuit (102) is a low-noise charge-type device containing a three-stage amplification structure, used to amplify the sinusoidal excitation signal according to the conversion ratio of the capacitance value;

[0016] The first stage of the three-stage amplification structure is a five-transistor OTA, the second stage is a folded common source and common gate structure, and the third stage is a common source stage.

[0017] Optionally, the peak detection circuit (103) is a transistor-level circuit with a five-transistor OTA structure, used for real-time acquisition of voltage peak values.

[0018] Optionally, the analog-to-digital conversion circuit (104) includes: a sample-and-hold circuit, a DAC capacitor array circuit, a comparator circuit, and a SAR logic circuit;

[0019] The sample-and-hold circuit is a bootstrap switching circuit used to accurately sample the input signal under the control of the sampling clock.

[0020] The DAC capacitor array circuit is a fully differential segmented structure used to store sampled information and is controlled by the SAR logic circuit to perform a successive approximation process.

[0021] The comparator circuit is a pre-amplifier plus latch dynamic comparator structure, used to compare the high and low levels at the two ends of the input, thereby obtaining the quantization result through repeated comparisons;

[0022] The SAR logic circuit consists of combinational logic and sequential logic circuits, used to store the comparison results for each comparison and control the potential transition of the upper plates of the capacitor array according to a suitable switching strategy.

[0023] A measurement method for capacitance detection circuit based on peak detection, comprising:

[0024] Step 1: The signal generation circuit (101) outputs a sinusoidal excitation signal, and the output terminal of the signal generation circuit (101) is connected to the input terminal of the signal conversion circuit (102) through the capacitor under test;

[0025] Step 2: The signal conversion circuit (102) amplifies the input sinusoidal excitation signal according to the capacitance value, and connects it to the input terminal of the peak detection circuit (103) through the buffer circuit, so that the amplified sinusoidal excitation signal is input to the peak detection circuit (103);

[0026] Step 3: The peak voltage of the amplified sinusoidal excitation signal is acquired in real time by the peak detection circuit (103), the capacitance value of the capacitor under test is calculated based on the peak voltage, and the capacitance value is transmitted to the analog-to-digital conversion circuit (104).

[0027] Step 4: The analog-to-digital converter (104) performs high-precision digitization on the input capacitance value and outputs the capacitance detection result;

[0028] The expression for amplifying a sinusoidal excitation signal according to the capacitance ratio is:

[0029]

[0030] In formula (1), V x For the amplified sinusoidal excitation signal, C f As the reference capacitor, V in To input the peak value of the sine wave, C x The capacitance value of the capacitor to be tested;

[0031] The expression for the capacitance value of the capacitor under test is:

[0032]

[0033] In formula (2), V peakout Given the peak value of the sinusoidal excitation signal, V cm The common-mode level is known.

[0034] Optionally, in step 1, the frequency range of the sine wave in the sinusoidal excitation signal is 1Hz-120MHz, and the frequency of the sinusoidal excitation signal is 100Hz, 1KHz, 10KHz and 100KHz, with a frequency accuracy of 0.02%.

[0035] Optionally, the peak value of the amplified sinusoidal excitation signal acquired in real time in step 3 specifically includes:

[0036] The amplified sinusoidal excitation signal is used as the input voltage value Vip. When the input voltage value Vip and the output voltage Vpeak are equal, the current of NM2 flows equally through NM0 and NM1. Vpeak charges the load capacitor Co, so that the output voltage reaches the Vpeak value. If Vip increases, the current value of the NM0 branch will increase. The excess current will be obtained from the PM2 branch. Through the current mirror effect, a downward current is generated in PM5. The downward current charges Co, so that the voltage of Co increases. When the voltage value is equal to the input voltage Vip, the charging stops, the circuit returns to the equilibrium state, and the voltage peak value of the amplified sinusoidal excitation signal is obtained.

[0037] Optionally, step 4, which involves outputting the capacitance detection result, includes:

[0038] Step 4.1: Input the capacitor value as the input signal Vin into the analog-to-digital converter circuit (104). The input signal Vin passes through the sample-and-hold circuit and reaches the positive input terminal of the comparator circuit. The highest bit MSB of the digital control SAR logic circuit is set to 1, and the other bits are cleared to zero. Under the control of the SAR logic circuit and the reference voltage Vref, the output of the DAC capacitor array circuit is 1 / 2Vref and sent to the negative input terminal of the comparator. If Vin>1 / 2Vref, the output of the comparator circuit is 1, and the highest bit of the digital code is also 1; if Vin<1 / 2Vref, the output of the comparator circuit is 0, and the highest bit of the digital code is also 0.

[0039] Step 4.2: Set the second most important bit MSB of the numerical control SAR logic circuit to 1. If MSB = 1, the output of the DAC capacitor array circuit is 3 / 4Vref. Compare Vin with 3 / 4Vref to determine the second most important bit. If MSB = 0, the output of the DAC capacitor array circuit is 1 / 4Vref. Compare Vin with 1 / 4Vref to determine the second most important bit.

[0040] Step 4.3: Following the logic of Steps 4.1 and 4.2, continue until all the digital codes of the SAR are determined, complete the digitization of the voltage peak, and output the capacitance detection result.

[0041] The beneficial effects of the present invention are:

[0042] 1. The capacitance detection circuit designed in this invention has high measurement accuracy and a resolution of over 12 bits. The measurement accuracy is mainly limited by the operational amplifier offset and the accuracy of the analog-to-digital conversion circuit.

[0043] 2. The high gain of the low-noise three-stage operational amplifier in the capacitor detection circuit designed in this invention results in high accuracy of closed-loop amplification. Furthermore, the comparator in the final analog-to-digital converter uses offset storage technology to reduce offset, and the addition of redundant bits to the capacitor array increases the final effective number of bits.

[0044] 3. The capacitance detection circuit designed in this invention has a simple structure, is easy to build, and has intuitive connections, resulting in low overall system power consumption. Furthermore, the circuit is easy to physically implement, and the final analog-to-digital converter and host computer can be easily interconnected, making it suitable for various capacitance measurement applications.

[0045] 4. The analog-to-digital converter circuit in this invention has low power consumption and high speed, and can achieve a sampling rate of 1MSPS. Generally, the frequency measured by the sensor at the front end of the capacitor is relatively low. The speed of the analog-to-digital converter can perform high-precision digitization of the peak detection output and has a wide measurement frequency range, all of which can satisfy the Nyquist sampling theorem. Attached Figure Description

[0046] Figure 1A logic block diagram of a capacitance detection circuit based on peak detection provided by the present invention;

[0047] Figure 2 A logic block diagram of the peak detection circuit provided by the present invention;

[0048] Figure 3 The logic block diagram of the analog-to-digital conversion circuit provided by the present invention;

[0049] Figure 4 The logic block diagram of the DAC capacitor array circuit in the analog-to-digital converter circuit provided by the present invention;

[0050] Figure 5 The flowchart shows a measurement method for a capacitance detection circuit based on peak detection provided by the present invention. Detailed Implementation

[0051] Specific implementation method 1: Combination Figure 1 This embodiment describes a capacitance detection circuit based on peak detection, the structure of which includes:

[0052] The circuit includes a signal generation circuit (101), a signal conversion circuit (102), a peak detection circuit (103), and an analog-to-digital conversion circuit (104).

[0053] The input terminal of the signal generation circuit (101) is used to receive the capacitor under test. The output terminal of the signal generation circuit (101) is connected to the input terminal of the signal conversion circuit (102) through the capacitor under test. The output terminal of the signal conversion circuit (102) is connected to the input terminal of the peak detection circuit (103). The output terminal of the peak detection circuit is connected to the input terminal of the analog-to-digital conversion circuit (104). The analog-to-digital conversion circuit outputs the capacitance detection result.

[0054] The capacitance detection circuit designed in this invention has a simple structure, is easy to build, and has intuitive connections, resulting in low overall system power consumption. Furthermore, the circuit is easy to physically implement, and the final analog-to-digital converter and host computer can be easily interconnected, making it suitable for various capacitance measurement applications.

[0055] The signal generation circuit (101) is implemented by the AD9854 board-level high-speed DDS module, which can generate sine waves in the frequency range of 1Hz to 120MHz, and uses sine waves to generate excitation signals of 100Hz, 1KHz, 10KHz and 100KHz with a frequency accuracy of 0.02%.

[0056] The signal conversion circuit (102) includes a low-noise charge amplifier that amplifies the sinusoidal excitation signal according to the conversion ratio of the capacitor value. It uses a three-stage amplification structure with a proportional capacitor connected across it to form a capacitor proportional amplification structure. The first stage of the three-stage op-amp is a five-transistor OTA, the second stage is a folded common-source common-gate structure, and the last stage is a common-source stage. The input terminal of the capacitor voltage conversion circuit is connected to the output terminal of the signal generation circuit (101), and the output voltage of the capacitor voltage conversion circuit is connected to the input of the peak detection circuit (103) through the buffer circuit.

[0057] The peak detection circuit (103) is implemented by a transistor-level circuit. Its main structure is similar to a five-transistor OTA structure. It has a fully differential input and the tail current is realized by the current mirror to replicate the current, which is used to collect the voltage peak value in real time.

[0058] The analog-to-digital converter circuit (104) consists of a sample-and-hold circuit, a comparator circuit, a SAR logic circuit, and a DAC capacitor array circuit. The sample-and-hold circuit is a bootstrap switch circuit used to accurately sample the input signal under the control of the sampling clock. The DAC capacitor array circuit is a fully differential segmented structure used to store the sampled information and to perform a successive approximation process under the control of the SAR logic circuit. The comparator circuit is a pre-amplified Latch dynamic comparator structure used to compare the high and low levels at both ends of the input, thereby obtaining the quantization result through repeated comparisons. The SAR logic circuit consists of combinational logic and sequential logic circuits used to store the comparison result each time and to control the potential transition of the upper plate of the capacitor array according to a suitable switching strategy.

[0059] Specific implementation method 2: Combination Figure 2-5 This embodiment will be described as follows: Figure 5 As shown, the steps of the measurement method of the capacitance detection circuit based on peak detection described in this embodiment include:

[0060] S1: The signal generation circuit (101) outputs a sinusoidal excitation signal, and the output terminal of the signal generation circuit (101) is connected to the input terminal of the signal conversion circuit (102) through the capacitor under test;

[0061] S101: The frequency range of the sine wave in the sinusoidal excitation signal is 1Hz-120MHz, and the frequency of the sinusoidal excitation signal is 100Hz, 1KHz, 10KHz and 100KHz, with a frequency accuracy of 0.02%.

[0062] S2: The signal conversion circuit (102) amplifies the input sinusoidal excitation signal according to the capacitance value, and connects it to the input terminal of the peak detection circuit (103) through the buffer circuit, so that the amplified sinusoidal excitation signal is input to the peak detection circuit (103);

[0063] The expression for amplifying a sinusoidal excitation signal according to the capacitance ratio is:

[0064]

[0065] In formula (1), V x For the amplified sinusoidal excitation signal, C f As the reference capacitor, V in To input the peak value of the sine wave, C x The capacitance value of the capacitor to be tested;

[0066] S3: The peak voltage of the amplified sinusoidal excitation signal is collected in real time by the peak detection circuit (103), the capacitance value of the capacitor under test is calculated based on the peak voltage, and the capacitance value is transmitted to the analog-to-digital conversion circuit (104).

[0067] Since the reference capacitor Cf, the common-mode level Vcm, and the peak value Vpeakin of the input sine wave are known, the linear relationship between the capacitor Cx to be measured and the peak value Vpeakout of the output sine wave is shown in formula (2). The expression for the capacitance value of the capacitor to be measured is:

[0068]

[0069] In formula (2), V peakout Given the peak value of the sinusoidal excitation signal, V cm The common-mode level is known.

[0070] S301: As Figure 2 As shown, the amplified sinusoidal excitation signal is used as the input voltage value Vip. When the input voltage value Vip and the output voltage Vpeak are equal, the current of NM2 flows equally through NM0 and NM1. Vpeak charges the load capacitor Co, so that the output voltage reaches the Vpeak value. If Vip increases, the current value of the NM0 branch will increase. The excess current will be obtained from the PM2 branch. Through the current mirror effect, a downward current is generated in PM5. The downward current charges Co, so that the voltage of Co increases. When the voltage value is equal to the input voltage Vip, the charging stops, and the circuit returns to the equilibrium state, obtaining the voltage peak of the amplified sinusoidal excitation signal. The large resistance can be implemented by the MOSFET in the cutoff region, and the capacitor Co is directly integrated on the chip.

[0071] The peak detection circuit (103) is built with a transistor-level structure. The peak voltage detection circuit is mainly used to track the peak value of the constantly fluctuating voltage in the circuit. Under normal circumstances, the peak voltage in the circuit can be used for logical judgment, thereby realizing the control and regulation of the circuit. The peak detector is usually composed of diodes and capacitors to complete the measurement of peak voltage. While using the capacitor to store the peak voltage in the circuit, due to the forward conduction effect of the diode, the voltage can be stably stored on the capacitor. The principle of the peak detection circuit (103) in this embodiment is that when the circuit is in a balanced state, the voltages at both ends of the circuit input are equal. At this time, the current signals flowing through the two branches are equal, and the voltage across the capacitor CL will track the voltage value of one input. At this point, if the input voltage at one end increases, the current flowing through that branch will increase. The extra current will charge capacitor CL through the mirror effect until the potential of CL equals the potential of the increased input voltage. When the input voltage at one end decreases, since the current in the mirror can only flow from the power supply to ground, the voltage across the capacitor remains unchanged, thus achieving peak detection. However, due to various non-ideal effects in the circuit, the voltage across capacitor CL needs to be reset periodically to ensure that the voltage across the capacitor always follows the peak value of the input voltage. A large resistor is connected in parallel between the output and ground to establish a DC operating point, and a switch is connected in parallel to provide a reset / refresh circuit to ensure normal circuit operation.

[0072] S4: The analog-to-digital converter circuit (104) performs high-precision digitization of the input capacitance value and outputs the capacitance detection result;

[0073] The capacitance detection circuit designed in this invention has high measurement accuracy, with a resolution of over 12 bits. The measurement accuracy is mainly limited by the operational amplifier offset and the accuracy of the analog-to-digital converter circuit (104).

[0074] S401: The sample-and-hold circuit is a bootstrap switch circuit. When the sampling clock CLK is low, the bootstrap switch operates in the hold phase, and Vboost is pulled to GND. When CLK is high, the bootstrap switch operates in the sampling phase, and the bootstrap clock signal Vboost voltage is VDD+Vin. The VGS of the sampling switch M1 is fixed at VDD, significantly reducing the nonlinearity of the equivalent resistance RON of M1 and improving the linearity of the sampling switch M1. In the actual circuit design, the capacitor value is selected as 0.5pF. The charge pump of the three capacitors can realize the function of raising the gate voltage of the switching transistor to VDD+Vin. The size of the last switching transistor should be designed to be relatively large in order to improve the establishment accuracy of the gate voltage bootstrap switch and make the deviation between Vs and Vin smaller. This allows the potential at each point of the capacitor array to be established more accurately, thus making the capacitor array establishment more accurate. The comparator in this embodiment combines the open-loop amplifier structure and the latch, utilizing the advantages of these two structures for complementary design. The advantages of open-loop amplifiers can be used to increase the difference in the input signal, which is then added to the latch structure. This structure improves the comparator's speed and accuracy. The pre-amplification stage uses a fully differential single-pole amplifier. Based on a five-transistor OTA, cross-coupled load pairs are added to introduce appropriate positive feedback. The principle of current cancellation effectively increases the operational amplifier's gain. The latch uses a traditional dynamic comparator structure, with the gate of the tail current transistor connected to the comparator clock and a reset transistor to reset the comparison result. The latch output is connected to an inverter to enhance the comparator's output drive capability and improve waveform quality. This structure has low power consumption; the latch has no static power consumption, only dynamic power consumption, and uses only one pre-amplification stage, thus maintaining sufficient speed while ensuring a certain level of accuracy. Comparator offset affects the comparison result. After amplification, the offset equivalent to the input of the latch is greatly reduced. The main offset comes from the offset of the input pair transistors in the pre-amplification stage, which is further reduced using offset storage technology such as OOS or IOS.

[0075] S402: As Figure 4As shown, the capacitor array in the DAC adopts a fully differential segmented structure. Fully differential input offers better suppression of temperature drift and mismatch compared to single-ended input. A Vcm-based switching strategy is employed. Through the conservation of capacitance at capacitor nodes, and in conjunction with the appropriate switching action of the lower capacitor plate, the upper plate of the capacitor array changes the correct voltage value due to capacitance conservation. Therefore, the voltage comparison at the upper plate of the capacitor array can be converted into the difference between the differential inputs and compared with the corresponding values ​​in each transition of the successive approximation logic. The value of the unit capacitor is crucial. A large value increases the chip area and the settling time for each transition voltage, but it can relatively improve the settling accuracy. A small value leads to poor settling accuracy, requiring iterative compromise to select a suitable unit capacitor value. The segmented structure reduces the overall size of the capacitor array, saving area. Simultaneously, the inclusion of redundant bits and the digital combinational logic module to convert the output code back to binary improves fault tolerance. The SAR logic circuit is used to control the successive approximation process. In this design, the SAR logic, based on a traditional shift register, can generate the output of the shift register at each rising edge of the clock cycle. It can store the two results of each comparison in separate DFFs and output them using appropriate digital circuitry. Simultaneously, by properly processing each comparison result, the correct control timing for the DAC array switches is obtained. Redundancy techniques in the SAR DAC are implemented by increasing the number of quantization iterations for internal fault tolerance correction. To address setup problems and comparison errors caused by limited resolution in the SAR DAC, a non-binary DAC array is used to achieve redundancy.

[0076] S403: As Figure 3 As shown, the capacitance value is used as the input signal Vin to the analog-to-digital converter circuit (104). The input signal Vin passes through the sample-and-hold circuit to the positive input terminal of the comparator circuit. The highest bit MSB of the digital control SAR logic circuit is set to 1, and the other bits are cleared to zero. Under the control of the SAR logic circuit and the reference voltage Vref, the output of the DAC capacitor array circuit is 1 / 2Vref sent to the negative input terminal of the comparator. If Vin>1 / 2Vref, the output of the comparator circuit is 1, and the highest bit of the digital code is also 1; if Vin<1 / 2Vref, the output of the comparator circuit is 0, and the highest bit of the digital code is also 0. The second highest bit MSB of the numerical control SAR logic circuit is set to 1. If MSB=1, the output of the DAC capacitor array circuit is 3 / 4Vref. The second highest bit is determined by comparing the magnitude of Vin with 3 / 4Vref. If MSB=0, the output of the DAC capacitor array circuit is 1 / 4Vref. The second highest bit is determined by comparing the magnitude of Vin with 1 / 4Vref. The above logic is repeated and analogous until all the digital codes of the SAR are determined, the voltage peak is digitized, and the capacitance detection result is output.

[0077] The high gain of the low-noise three-stage operational amplifier in this invention results in high accuracy of closed-loop amplification. Furthermore, the comparator in the final analog-to-digital converter uses offset storage technology to reduce offset, and the addition of redundant bits to the capacitor array increases the final effective number of bits. The analog-to-digital converter circuit (104) has low power consumption and high speed, and can achieve a sampling rate of 1MSPS. Generally, the frequency measured by the sensor at the capacitor front end is relatively low. The speed of this analog-to-digital converter can perform high-precision digitization of the peak detection output, and the measurement frequency range is wide, all of which can satisfy the Nyquist sampling theorem.

[0078] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the present profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical content disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement of the above embodiments made according to the technical essence of the present invention, within the spirit and principles of the present invention, without departing from the content of the technical solution of the present invention, shall still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A capacitance detection circuit based on peak detection, characterized in that, The structure of the capacitance detection circuit based on peak detection includes: Signal generation circuit (101), signal conversion circuit (102), peak detection circuit (103), and analog-to-digital conversion circuit (104); The input terminal of the signal generation circuit (101) is used to receive the capacitor under test. The output terminal of the signal generation circuit (101) is connected to the input terminal of the signal conversion circuit (102) through the capacitor under test. The output terminal of the signal conversion circuit (102) is connected to the input terminal of the peak detection circuit (103). The output terminal of the peak detection circuit (103) is connected to the input terminal of the analog-to-digital conversion circuit (104). The analog-to-digital conversion circuit (104) outputs the capacitance detection result. The signal generation circuit (101) includes a sine wave module and an excitation signal module; The sine wave module is used to acquire sine waves; The excitation signal module acquires a sinusoidal excitation signal based on the acquired sine wave; The signal conversion circuit (102) is connected to the input terminal of the peak detection circuit (103) through the buffer circuit. The amplified sinusoidal excitation signal is input to the peak detection circuit (103). The peak detection circuit (103) collects the voltage peak value of the amplified sinusoidal excitation signal in real time, calculates the capacitance value of the capacitor under test based on the voltage peak value, and transmits it to the analog-to-digital conversion circuit (104). The peak detection circuit (103) includes PMOS devices PM0, PM1, PM2, and PM5; NMOS devices NM0, NM1, NM2, and NM3; a current source; a resistor Ro; and a load capacitor Co. The gate of transistor PM1 is connected to the gate of transistor PM0. The source of transistor PM1 is connected to the source of transistor PM0. The gate and drain of transistor PM0 are connected. The drain of transistor PM5 is connected to the output voltage Vpeak. The source of transistor PM5 is connected to the source of transistor PM2. The gate of transistor PM5 is connected to the gate of transistor PM2. The drain of transistor PM1 is connected to the drain of transistor PM2. The gate of transistor NM0 is connected to the input voltage Vip. The source of transistor NM0 is connected to the source of transistor NM1 and then to the drain of transistor NM2. The drain of transistor NM0... The drain of transistor PM1 is connected to the drain of transistor PM2, the source of transistor PM2 is connected to the source of transistor PM0, the gate of transistor NM1 is connected to the output voltage Vpeak, the drain of transistor NM1 is connected to the drain of transistor PM0, the gate of transistor NM3 is connected to the gate of transistor NM2, the gate and drain of transistor NM3 are connected, the drain of transistor NM3 is connected to one end of the current source, and the source of transistor PM1 is connected to the other end of the current source; one end of resistor Ro and load capacitor Co is connected to the output voltage Vpeak, and the other end is grounded; the sources of transistors NM3 and NM2 are grounded. The analog-to-digital conversion circuit (104) includes: a sample-and-hold circuit, a DAC capacitor array circuit, a comparator circuit, and a SAR logic circuit; The sample-and-hold circuit is a bootstrap switching circuit, used to accurately sample the input signal under the control of the sampling clock. The DAC capacitor array circuit is a fully differential segmented structure used to store sampled information and is controlled by the SAR logic circuit to perform a successive approximation process. The comparator circuit is a pre-amplified dynamic comparator with a latch, used to compare the high and low levels at the two ends of the input, thereby obtaining the quantization result through repeated comparisons; The SAR logic circuit consists of combinational logic and sequential logic circuits, used to store the comparison results for each time, and to control the potential transition of the upper plates of the capacitor array according to a suitable switching strategy.

2. The capacitance detection circuit based on peak detection according to claim 1, characterized in that, The signal conversion circuit (102) is a low-noise charge-type device containing a three-stage amplification structure, used to amplify the sinusoidal excitation signal according to the conversion ratio of the capacitance value; The first stage of the three-stage amplification structure is a five-transistor OTA, the second stage is a folded common source and common gate structure, and the third stage is a common source stage.

3. A measurement method for a capacitance detection circuit based on peak detection, applied to the capacitance detection circuit based on peak detection as described in any one of claims 1-2, characterized in that, include: Step 1: The signal generation circuit (101) outputs a sinusoidal excitation signal, and the output terminal of the signal generation circuit (101) is connected to the input terminal of the signal conversion circuit (102) through the capacitor under test; Step 2: The signal conversion circuit (102) amplifies the input sinusoidal excitation signal according to the capacitance value, and connects it to the input terminal of the peak detection circuit (103) through the buffer circuit, so that the amplified sinusoidal excitation signal is input to the peak detection circuit (103). Step 3: The peak voltage of the amplified sinusoidal excitation signal is acquired in real time by the peak detection circuit (103), the capacitance value of the capacitor under test is calculated based on the peak voltage, and the capacitance value is transmitted to the analog-to-digital conversion circuit (104). The peak value of the amplified sinusoidal excitation signal acquired in real time in step 3 specifically includes: The amplified sinusoidal excitation signal is used as the input voltage value Vip. When the input voltage value Vip and the output voltage Vpeak are equal, the current of NM2 flows equally through NM0 and NM1. Vpeak charges the load capacitor Co, so that the output voltage reaches the Vpeak value. If Vip increases, the current value of the NM0 branch will increase. The excess current will be obtained from the PM2 branch. Through the current mirror effect, a downward current is generated in PM5. The downward current charges Co, so that the voltage of Co increases. When the voltage value is equal to the input voltage Vip, the charging stops, the circuit returns to the equilibrium state, and the voltage peak value of the amplified sinusoidal excitation signal is obtained. Step 4: The analog-to-digital converter (104) performs high-precision digitization on the input capacitance value and outputs the capacitance detection result; The expression for amplifying a sinusoidal excitation signal according to the capacitance ratio is: （1）； In formula (1), This is the amplified sinusoidal excitation signal. As a reference capacitor, To input the peak value of the sine wave, The capacitance value of the capacitor to be tested; The expression for the capacitance value of the capacitor under test is: （2）； In formula (2), Given the peak value of the sinusoidal excitation signal, The common-mode level is known.

4. The measurement method of a capacitance detection circuit based on peak detection according to claim 3, characterized in that, In step 1, the frequency range of the sine wave in the sinusoidal excitation signal is 1Hz-120MHz, and the frequencies of the sinusoidal excitation signal are 100Hz, 1KHz, 10KHz and 100KHz, with a frequency accuracy of 0.02%.

5. The measurement method of a capacitance detection circuit based on peak detection according to claim 3, characterized in that, Step 4, which outputs the capacitance detection result, includes the following steps: Step 4.1: Input the capacitor value as the input signal Vin into the analog-to-digital converter circuit (104). The input signal Vin passes through the sample-and-hold circuit and reaches the positive input terminal of the comparator circuit. The highest bit MSB of the digital control SAR logic circuit is set to 1, and the other bits are cleared to zero. Under the control of the SAR logic circuit and the reference voltage Vref, the output of the DAC capacitor array circuit is 1 / 2Vref and sent to the negative input terminal of the comparator. If Vin>1 / 2Vref, the output of the comparator circuit is 1, and the highest bit of the digital code is also 1; if Vin<1 / 2Vref, the output of the comparator circuit is 0, and the highest bit of the digital code is also 0. Step 4.2: Set the second most important bit MSB of the numerical control SAR logic circuit to 1. If MSB=1, the output of the DAC capacitor array circuit is 3 / 4Vref. Compare Vin with the size of 3 / 4Vref to determine the second most important bit. If MSB=0, the output of the DAC capacitor array circuit is 1 / 4Vref. Compare Vin with the size of 1 / 4Vref to determine the second most important bit. Step 4.3: Following the logic of Steps 4.1 and 4.2, continue until all the digital codes of the SAR are determined, complete the digitization of the voltage peak, and output the capacitance detection result.

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