Manufacturing method of multi-layer grating structure

Abstract

The invention provides a manufacturing method of a multi-layer grating structure, which comprises the following steps of: performing primary main pattern exposure on a groove pattern required by a multi-layer grating, etching to transfer the pattern to a hard mask, subsequently forming a large-line-width etching window by adopting a mask plate with a lower precision requirement in sequence, shielding an etched groove, and then forming the multi-layer grating structure. And etching the to-be-etched groove to form a multi-layer groove grating structure with different depths. As the main pattern of the groove is formed in the same exposure, the problems of position error and the like in the subsequent preparation of the groove are solved, and the requirement on overlay error is reduced. Therefore, the exposure times of the main pattern can be reduced, and meanwhile, the consistency of the device can be improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuit design and manufacturing, and in particular relates to a method for manufacturing a multi-layer grating structure. Background Art

[0002] With the rapid development of micro-nano photonics technology, silicon wafer processing technology has been able to achieve the production of sub-micron silicon grating periods. Silicon gratings have received extensive attention in the field of optics due to their small size, good device consistency, and high beam quality. Especially in the case of large-scale mass production, the cost advantage of silicon gratings is more significant, which makes them play an increasingly important role in the manufacture of optical devices.

[0003] Existing silicon wafer processing technology mainly relies on multiple exposure and etching processes to achieve high-precision pattern transfer. Although this multiple exposure technology can achieve fine pattern production, the multiple exposure steps in the process may introduce alignment errors and overlay errors. In the process of making multi-layer gratings, usually a fine main pattern exposure and etching are performed to form a separate grating. This method may introduce additional errors for each exposure. These errors may cause large fluctuations in the performance of the final product after multiple accumulations, thereby affecting the performance consistency of the final device. In addition, multiple fine main pattern exposures will also lead to reduced production efficiency and increased costs, which is a problem that cannot be ignored for large-scale production.

[0004] In order to solve the above problems, the industry urgently needs a new manufacturing method that can increase the process window, simplify the production process and reduce production costs while maintaining or improving grating performance.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for manufacturing a multi-layer grating structure, which is used to solve the problem that multiple fine main pattern exposures in the prior art to manufacture multi-layer gratings easily introduce additional errors that affect device consistency.

[0007] To achieve the above-mentioned purpose and other related purposes, the present invention provides a method for manufacturing a multi-layer grating structure, the manufacturing method comprising: providing a substrate, depositing a first dielectric layer, a second dielectric layer and a hard mask layer on the substrate in sequence; forming an anti-reflection layer and a first photoresist layer on the hard mask layer in sequence, forming a first photoresist window, a second photoresist window and a third photoresist window arranged at intervals in the first photoresist layer by a photolithography process; transferring the first photoresist window, the second photoresist window and the third photoresist window to the hard mask layer by etching to form a first window, a second window and a third window in the hard mask layer; forming a second photoresist layer on the hard mask layer, forming a first etching window on the second photoresist layer by a photolithography process, the first etching window exposing the first window, and the second photoresist layer shielding the second window and the third window; etching the second dielectric layer, the first dielectric layer and the substrate in the first window based on the first etching window to form a first groove extending to the inside of the substrate, and removing the first groove by an ashing process. The second photoresist layer is removed; a third photoresist layer is formed on the hard mask layer, and a second etching window is formed on the third photoresist layer by a photolithography process, wherein the second etching window reveals the second window, and the third photoresist layer blocks the first window and the third window; based on the second etching window, the second dielectric layer and the first dielectric layer in the second window are etched to form a second groove that stops on the surface of the substrate, and the third photoresist layer is removed by an ashing process; a fourth photoresist layer is formed on the hard mask layer, and a third etching window is formed on the fourth photoresist layer by a photolithography process, wherein the third etching window reveals the third window, and the fourth photoresist layer blocks the first window and the second window; based on the third etching window, the second dielectric layer in the third window is etched to form a third groove that stops on the surface of the first dielectric layer, and the fourth photoresist layer is removed by an ashing process; the hard mask layer is removed by wet etching, and the wet etching solution used has a high etching selectivity ratio between the hard mask layer and the second dielectric layer, the first dielectric layer and the substrate.

[0008] Optionally, the exposure accuracy required for the second photoresist layer, the third photoresist layer, and the fourth photoresist layer is lower than the exposure accuracy required for the first photoresist layer, so as to increase the exposure process window of the second photoresist layer, the third photoresist layer, and the fourth photoresist layer.

[0009] Optionally, the width of the first etching window is greater than the width of the first window, the width of the second etching window is greater than the width of the second window, and the width of the third etching window is greater than the width of the third window.

[0010] Optionally, the substrate includes one of a silicon substrate, a germanium substrate, a germanium silicon substrate, a silicon carbide substrate, a glass substrate and a III-V compound substrate.

[0011] Optionally, an etching selectivity ratio of the hard mask layer to the second dielectric layer, the first dielectric layer and the substrate is greater than or equal to 100:1.

[0012] Optionally, the first dielectric layer is one of oxide and nitride, the second dielectric layer is the other of oxide and nitride, and the hard mask layer is polysilicon.

[0013] Optionally, the etching solution for removing the hard mask layer is a 1-5 wt. % TMAH solution or a KOH solution.

[0014] Optionally, the oxide includes one of silicon oxide and aluminum oxide, and the nitride includes one of silicon nitride and silicon carbide nitride.

[0015] Optionally, the thickness of the first dielectric layer is between 10 nanometers and 100 nanometers, the thickness of the second dielectric layer is between 10 nanometers and 100 nanometers, and the thickness of the hard mask layer is between 100 nanometers and 500 nanometers.

[0016] Optionally, the depth of the first groove is between 30 nanometers and 500 nanometers, the depth of the second groove is between 20 nanometers and 200 nanometers, and the depth of the third groove is between 10 nanometers and 100 nanometers.

[0017] As described above, the method for manufacturing a multi-layer grating structure of the present invention has the following beneficial effects: The present invention performs a main pattern exposure and etching of the groove pattern required for the multi-layer grating to transfer the pattern to the hard mask, and then sequentially uses a mask with lower precision requirements to form an etching window with a large line width and shield the etched grooves, and then etches the grooves to be etched, so as to form a multi-layer groove grating structure with different depths. Since the main pattern of the grooves is formed in the same exposure, the subsequent preparation of the grooves will not have problems such as position errors, and the requirements for overlay errors are reduced. Therefore, the present invention can reduce the number of exposures of the main pattern and improve the consistency of the device.

[0018] The present invention forms a multi-layer groove grating structure through a dielectric stack structure, and etching can be set to automatically stop at the surface of different dielectric layers, so that the depth of the groove can be controlled by the deposition thickness of the dielectric layer, which greatly improves the control accuracy of the groove depth, simplifies the process control difficulty, and reduces the process cost.

[0019] The present invention utilizes a wet etching solution with a high selectivity ratio to remove the hard mask layer, which will not cause damage to each groove, greatly improves process stability, and can effectively improve device yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application.

[0021] Figure 1 It is a schematic structural diagram presented in step 1) of the method for manufacturing a multi-layer grating structure according to an embodiment of the present invention.

[0022] Figure 2 It is a schematic structural diagram presented in step 2) of the method for manufacturing a multi-layer grating structure according to an embodiment of the present invention.

[0023] Figure 3 It is a schematic structural diagram presented in step 3) of the method for manufacturing a multi-layer grating structure according to an embodiment of the present invention.

[0024] Figure 4 It is a schematic structural diagram presented in step 4) of the method for manufacturing a multi-layer grating structure according to an embodiment of the present invention.

[0025] Figure 5 It is a schematic structural diagram presented in step 5) of the method for manufacturing a multi-layer grating structure according to an embodiment of the present invention.

[0026] Figure 6 It is a schematic structural diagram presented in step 6) of the method for manufacturing a multi-layer grating structure according to an embodiment of the present invention.

[0027] Figure 7 It is a schematic structural diagram presented in step 7) of the method for manufacturing a multi-layer grating structure according to an embodiment of the present invention.

[0028] Figure 8 It is a schematic structural diagram presented in step 8) of the method for manufacturing a multi-layer grating structure according to an embodiment of the present invention.

[0029] Figure 9~Figure 10 It is a schematic structural diagram presented in step 9) of the method for manufacturing a multi-layer grating structure according to an embodiment of the present invention.

[0030] Fig.11 It is a schematic structural diagram presented in step 10) of the method for manufacturing a multi-layer grating structure according to an embodiment of the present invention.

[0031] Description of component numbers: 101 substrate, 102 first dielectric layer, 103 second dielectric layer, 104 hard mask layer, 105 durable anti-reflection layer, 106 bottom anti-reflection layer, 107 first photoresist layer, 108 first photolithography window, 109 second photolithography window, 110 third photolithography window, 111 first window, 112 second window, 113 third window, 114 second photoresist layer, 115 first etching window, 116 first groove, 117 third photoresist layer, 118 second etching window, 119 second groove, 120 fourth photoresist layer, 121 third etching window, 122 third groove. DETAILED DESCRIPTION

[0032] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0033] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0034] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0035] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0036] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0037] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0038] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0039] like Figure 1 to Figure 11 As shown, this embodiment provides a method for manufacturing a multi-layer grating structure, and the manufacturing method includes the following steps: like Figure 1 As shown, firstly, step 1 is performed to provide a substrate 101 , and a first dielectric layer 102 , a second dielectric layer 103 and a hard mask layer 104 are sequentially deposited on the substrate 101 .

[0040] In some embodiments, the substrate is a wafer, and when a multi-layer grating structure is subsequently manufactured, the entire wafer is used to prepare one of the multi-layer grating structures. The substrate 101 includes one of a silicon substrate, a germanium substrate, a germanium silicon substrate, a silicon carbide substrate, a glass substrate, and a III-V compound substrate. The substrate 101 may be doped or undoped, and may be selected according to actual needs. A device structure, a circuit structure, or a mechanical structure may be pre-formed in the substrate 101, such as a MOS device, a capacitor, an inductor, a photodetector, a microcavity, a sensor, etc., and is not limited to the examples listed here. In the present embodiment, the substrate 101 is a single crystal silicon substrate. Of course, the substrate 101 may also be other types of semiconductor substrates or insulating substrates, and is not limited to the examples listed here.

[0041] In some embodiments, the hard mask layer 104, the second dielectric layer 103, the first dielectric layer 102 and the substrate 101 are selected so that the hard mask layer 104 has a high etching selectivity with the second dielectric layer 103, the first dielectric layer 102 and the substrate 101 in the wet etching solution. In this embodiment, the etching selectivity of the hard mask layer 104 with the second dielectric layer 103, the first dielectric layer 102 and the substrate 101 is preferably greater than or equal to 100:1. In one embodiment, the first dielectric layer 102 is one of oxide and nitride, the second dielectric layer 103 is the other of oxide and nitride, and the hard mask layer 104 is polysilicon. Preferably, the oxide includes one of silicon oxide and aluminum oxide, and the nitride includes one of silicon nitride and silicon carbide. In a specific example, the first dielectric layer 102 is silicon oxide, the second dielectric layer 103 is silicon nitride, and the hard mask layer 104 is polysilicon.

[0042] By controlling the thickness of the first dielectric layer 102 and the second dielectric layer 103, the depth of the subsequent corresponding grooves can be controlled, thereby simplifying the difficulty of controlling the groove depth, improving the accuracy of the groove depth and reducing the process cost. In one embodiment, the thickness of the first dielectric layer 102 is between 10 nanometers and 100 nanometers, for example, 10 nanometers, 20 nanometers, 50 nanometers, 80 nanometers, 100 nanometers, etc., and the thickness of the second dielectric layer 103 is between 10 nanometers and 100 nanometers, for example, 10 nanometers, 30 nanometers, 40 nanometers, 70 nanometers, 100 nanometers, etc.

[0043] In one embodiment, the thickness of the hard mask layer 104 is between 100 nanometers and 500 nanometers. The present application controls the thickness of the hard mask layer 104 so that it has a sufficiently good shielding ability and can be efficiently removed later.

[0044] like Figure 2 As shown, step 2 is then performed), an anti-reflection layer and a first photoresist layer 107 are sequentially formed on the hard mask layer 104, and a first photoresist window 108, a second photoresist window 109 and a third photoresist window 110 arranged at intervals are formed in the first photoresist layer 107 by a photolithography process.

[0045] like Figure 2 As shown, the anti-reflection layer may include a durable anti-reflection layer (DARC) 106 and a bottom anti-reflection layer (BARC) 106 that are stacked to reduce the impact of reflected light on the photoresist layer and improve exposure accuracy.

[0046] In one embodiment, an anti-reflection layer and a first photoresist layer 107 may be sequentially formed on the hard mask layer 104 by a spin coating process, and then a baking process and the like are further included.

[0047] like Figure 3 As shown, step 3 is then performed to transfer the first photolithography window 108 , the second photolithography window 109 and the third photolithography window 110 to the hard mask layer 104 by etching to form a first window 111 , a second window 112 and a third window 113 in the hard mask layer 104 .

[0048] like Figure 4 As shown, step 4 is then performed), a second photoresist layer 114 is formed on the hard mask layer 104, and a first etching window 115 is formed on the second photoresist layer 114 by a photolithography process, wherein the first etching window 115 reveals the first window 111, and the second photoresist layer 114 covers the second window 112 and the third window 113.

[0049] In one embodiment, the exposure accuracy required for the second photoresist layer 114 is lower than the exposure accuracy required for the first photoresist layer 107 , so as to increase the exposure process window of the second photoresist layer 114 . Since the second photoresist layer 114 only needs to block the second window 112 and the third window 113 and expose the first window 111, the first etching window 115 does not need to be strictly aligned with the first window 111, so the width of the first etching window 115 can be designed to be larger than the width of the first window 111. When the first groove 116 is subsequently etched, the area near the first window 111 that is not blocked by the second photoresist layer 114 is blocked by the hard mask layer 104, and the position and size of the first groove 116 will be strictly limited by the first window 111 in the hard mask layer 104. Therefore, the exposure process window of the second photoresist layer 114 is larger and the exposure accuracy requirement is lower, which can greatly provide a process window and reduce process costs. The position and size of the first groove 116 will not be affected by the exposure accuracy of the second photoresist layer 114, which can greatly improve the manufacturing stability and accuracy of the first groove 116.

[0050] like Figure 5 As shown, step 5 is then performed, the second dielectric layer 103, the first dielectric layer 102 and the substrate 101 in the first window 111 are etched based on the first etching window 115 to form a first groove 116 extending into the interior of the substrate 101, and the second photoresist layer 114 is removed by an ashing process.

[0051] In one embodiment, the depth of the first groove 116 is between 30 nanometers and 500 nanometers. For example, the depth of the first groove 116 may be 100 nanometers, 200 nanometers, 250 nanometers, etc., which may be determined according to actual requirements.

[0052] like Figure 6As shown, step 6 is then performed), a third photoresist layer 117 is formed on the hard mask layer 104, and a second etching window 118 is formed on the third photoresist layer 117 by a photolithography process, wherein the second etching window 118 reveals the second window 112, and the third photoresist layer 117 covers the first window 111 and the third window 113.

[0053] In one embodiment, the exposure accuracy required for the third photoresist layer 117 is lower than the exposure accuracy required for the first photoresist layer 107 , so as to increase the exposure process window of the third photoresist layer 117 . Since the third photoresist layer 117 only needs to block the first window 111 and the third window 113 and expose the second window 112, the second etching window 118 does not need to be strictly aligned with the second window 112, so the width of the second etching window 118 can be designed to be larger than the width of the second window 112. When the second groove 119 is subsequently etched, the area near the second window 112 that is not blocked by the third photoresist layer 117 is blocked by the hard mask layer 104, and the position and size of the second groove 119 will be strictly limited by the second window 112 in the hard mask layer 104. Therefore, the exposure process window of the third photoresist layer 117 is larger and the exposure accuracy requirement is lower, which can greatly provide a process window and reduce process costs. The position and size of the second groove 119 will not be affected by the exposure accuracy of the third photoresist layer 117, which can greatly improve the manufacturing stability and accuracy of the second groove 119.

[0054] like Figure 7 As shown, then step 7 is performed, based on the second etching window 118, the second dielectric layer 103 and the first dielectric layer 102 in the second window 112 are etched to form a second groove 119 that stops on the surface of the substrate 101, and the third photoresist layer 117 is removed by an ashing process; The depth of the second trench 119 is defined by the total thickness of the second dielectric layer 103 and the first dielectric layer 102 . In one embodiment, the depth of the second trench 119 is between 20 nanometers and 200 nanometers.

[0055] like Figure 8 As shown, step 8 is then performed), a fourth photoresist layer 120 is formed on the hard mask layer 104, and a third etching window 121 is formed on the fourth photoresist layer 120 through an exposure and development process, wherein the third etching window 121 reveals the third window 113, and the fourth photoresist layer 120 covers the first window 111 and the second window 112.

[0056] In one embodiment, the exposure accuracy required for the fourth photoresist layer 120 is lower than the exposure accuracy required for the first photoresist layer 107 , so as to increase the exposure process window of the fourth photoresist layer 120 . Since the fourth photoresist layer 120 only needs to block the first window 111 and the second window 112 and expose the third window 113, the third etching window 121 does not need to be strictly aligned with the third window 113, so the width of the third etching window 121 can be designed to be larger than the width of the third window 113. When the third groove 122 is subsequently etched, the area near the third window 113 that is not blocked by the fourth photoresist layer 120 is blocked by the hard mask layer 104, and the position and size of the third groove 122 will be strictly limited by the third window 113 in the hard mask layer 104. Therefore, the exposure process window of the fourth photoresist layer 120 is larger and the exposure accuracy requirement is lower, which can greatly provide a process window and reduce process costs. The position and size of the third groove 122 will not be affected by the exposure accuracy of the fourth photoresist layer 120, which can greatly improve the manufacturing stability and accuracy of the third groove 122.

[0057] like Figure 9~Figure 10 As shown, step 9 is then performed, the second dielectric layer 103 in the third window 113 is etched based on the third etching window 121 to form a third groove 122 that stops on the surface of the first dielectric layer 102, and the fourth photoresist layer 120 is removed by an ashing process.

[0058] The depth of the third trench 122 is defined by the thickness of the second dielectric layer 103 . In one embodiment, the depth of the third trench 122 is between 10 nanometers and 100 nanometers.

[0059] like Fig.11 As shown, step 10 is then performed to remove the hard mask layer 104 by wet etching, and the wet etching solution used has a high etching selectivity ratio between the hard mask layer 104 and the second dielectric layer 103, the first dielectric layer 102 and the substrate 101.

[0060] In one embodiment, the etchant for removing the hard mask layer 104 is a 1-5wt.% TMAH solution, or in another embodiment, the etchant for removing the hard mask layer 104 is a KOH solution. The present invention uses a high selectivity wet etching solution to remove the hard mask layer 104, which will not cause damage to each groove, greatly improves process stability, and can effectively improve device yield.

[0061] According to the technical solution described in this embodiment, more dielectric layer stacks and more lithography windows can be set in step 1), and more grooves of different depths can be etched in sequence based on more lithography windows and dielectric layer stacks, which should also be deemed to fall within the protection scope required by this application.

[0062] It should be noted that, for the sake of simplicity, this embodiment only shows the preparation of a single groove of different depths. In fact, each groove of depth can be a periodic structure composed of multiple grooves to form a grating structure with corresponding functions. The grating structure is composed of periodically arranged high refractive index regions (such as silicon materials) and low refractive index regions (such as air grooves or low refractive index media filled in the grooves). This periodic structure can achieve diffraction of light at a specific wavelength. Through the precise control of the design and manufacturing of the groove grating, efficient diffraction and propagation of light waves under specific conditions can be achieved.

[0063] As described above, the method for manufacturing a multi-layer grating structure of the present invention has the following beneficial effects: The present invention performs a main pattern exposure and etching of the groove pattern required for the multi-layer grating to transfer the pattern to the hard mask, and then sequentially uses a mask with lower precision requirements to form an etching window with a large line width and shield the etched grooves, and then etches the grooves to be etched, so as to form a multi-layer groove grating structure with different depths. Since the main pattern of the grooves is formed in the same exposure, the subsequent preparation of the grooves will not have problems such as position errors, and the requirements for overlay errors are reduced. Therefore, the present invention can reduce the number of exposures of the main pattern and improve the consistency of the device.

[0064] The present invention forms a multi-layer groove grating structure through a dielectric stack structure, and etching can be set to automatically stop at the surface of different dielectric layers, so that the depth of the groove can be controlled by the deposition thickness of the dielectric layer, which greatly improves the control accuracy of the groove depth, simplifies the process control difficulty, and reduces the process cost.

[0065] The present invention utilizes a wet etching solution with a high selectivity ratio to remove the hard mask layer, which will not cause damage to each groove, greatly improves process stability, and can effectively improve device yield.

[0066] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0067] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a multi-layer grating structure, It is characterized in that The production method comprises: Providing a substrate, and sequentially depositing a first dielectric layer, a second dielectric layer, and a hard mask layer on the substrate; An anti-reflection layer and a first photoresist layer are sequentially formed on the hard mask layer, and a first photoresist window, a second photoresist window and a third photoresist window arranged at intervals are formed in the first photoresist layer by a photolithography process; Transferring the first photolithography window, the second photolithography window and the third photolithography window to the hard mask layer by etching to form a first window, a second window and a third window; forming a second photoresist layer on the hard mask layer, and forming a first etching window on the second photoresist layer by a photolithography process, wherein the first etching window reveals the first window, and the second photoresist layer covers the second window and the third window; Based on the first etching window, the second dielectric layer, the first dielectric layer and the substrate in the first etching window are etched to form a first groove extending into the interior of the substrate, and the second photoresist layer is removed by an ashing process; forming a third photoresist layer on the hard mask layer, and forming a second etching window on the third photoresist layer by a photolithography process, wherein the second etching window reveals the second window, and the third photoresist layer shields the first window and the third window; Based on the second etching window, the second dielectric layer and the first dielectric layer in the second etching window are etched to form a second groove that stops on the surface of the substrate, and the third photoresist layer is removed by an ashing process; forming a fourth photoresist layer on the hard mask layer, and forming a third etching window on the fourth photoresist layer by a photolithography process, wherein the third etching window reveals the third window, and the fourth photoresist layer shields the first window and the second window; Based on the third etching window, the second dielectric layer in the third window is etched to form a third groove that stops on the surface of the first dielectric layer, and the fourth photoresist layer is removed by an ashing process; The hard mask layer is removed by wet etching, and the wet etching solution used has a high etching selectivity ratio between the hard mask layer and the second dielectric layer, the first dielectric layer and the substrate.

2. The method for manufacturing a multi-layer grating structure according to claim 1, Features: The exposure accuracy required for the second photoresist layer, the third photoresist layer, and the fourth photoresist layer is lower than the exposure accuracy required for the first photoresist layer, so as to increase the exposure process window of the second photoresist layer, the third photoresist layer, and the fourth photoresist layer.

3. The method for manufacturing a multi-layer grating structure according to claim 1, Features: The width of the first etching window is greater than the width of the first window, the width of the second etching window is greater than the width of the second window, and the width of the third etching window is greater than the width of the third window.

4. The method for manufacturing a multi-layer grating structure according to claim 1, Features: The substrate includes one of a silicon substrate, a germanium substrate, a germanium silicon substrate, a silicon carbide substrate, a glass substrate and a III-V compound substrate.

5. The method for manufacturing a multi-layer grating structure according to claim 1, Features: The etching selectivity ratio of the hard mask layer to the second dielectric layer, the first dielectric layer and the substrate is greater than or equal to 100:

1.

6. The method for manufacturing a multi-layer grating structure according to claim 1, Features: The first dielectric layer is one of oxide and nitride, the second dielectric layer is the other of oxide and nitride, and the hard mask layer is polysilicon.

7. The method for manufacturing a multi-layer grating structure according to claim 6, Features: The etching solution for removing the hard mask layer is a 1-5 wt % TMAH solution or a KOH solution.

8. The method for manufacturing a multi-layer grating structure according to claim 6, Features: The oxide includes one of silicon oxide and aluminum oxide, and the nitride includes one of silicon nitride and silicon carbide nitride.

9. The method for manufacturing a multi-layer grating structure according to claim 1, Features: The thickness of the first dielectric layer is between 10 nanometers and 100 nanometers, the thickness of the second dielectric layer is between 10 nanometers and 100 nanometers, and the thickness of the hard mask layer is between 100 nanometers and 500 nanometers.

10. The method for manufacturing a multi-layer grating structure according to claim 1, Features: The depth of the first groove is between 30 nanometers and 500 nanometers, the depth of the second groove is between 20 nanometers and 200 nanometers, and the depth of the third groove is between 10 nanometers and 100 nanometers.

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