A multi-core CPU resource dynamic allocation method and device based on SPDK architecture

Abstract

The embodiments of this specification disclose a multi-core CPU resource dynamic allocation method and device based on the SPDK architecture. The method includes dividing CPU resources into multiple processing areas; when a CPU usage application of any target polling thread is detected, searching for a first CPU in the target processing area corresponding to the target polling thread; when the first CPU does not exist, determining the second CPU with the lowest current reference count, and binding the second CPU to the target polling thread. The embodiments of this specification can isolate the various subsystems of the SPDK architecture to avoid resource competition between the various subsystems. When the target polling thread wants to apply for the use of the CPU, it selects the unused CPU or the CPU with the lowest current reference count for binding, which increases the dynamic management capability of CPU resources, and can ensure the effective use of CPU resources in the scenario where polling threads are frequently created and deleted, thereby improving resource utilization.

Description

Technical Field

[0001] One or more embodiments of this specification relate to information processing technology, and more particularly, to a method and device for dynamically allocating multi-core CPU resources based on an SPDK architecture. Background Art

[0002] The Storage Performance Development Kit (SPDK) is widely used to improve the performance of storage and network applications. It bypasses the kernel by running in user space and reduces the overhead on the data path. SPDK consists of multiple subsystems, each of which handles different types of transactions by polling threads. However, it is still difficult to effectively manage and dynamically allocate CPU resources to optimize the performance of the SPDK architecture. In traditional operating systems, CPU allocation and management are usually controlled by the kernel scheduler. The kernel scheduler cannot schedule resources within the process and can only allocate resources as a whole to the SPDK process. It cannot fully meet the SPDK architecture's requirements for fine management of CPU resources. When the SPDK architecture runs on a multi-core processor, it only provides the use of CPU masks to set the CPU resources used. It lacks effective CPU isolation and load balancing strategies, and cannot perform more precise resource management control to reduce latency and improve throughput. Summary of the invention

[0003] In order to solve the above problems, one or more embodiments of this specification describe a multi-core CPU resource dynamic allocation method and device based on the SPDK architecture.

[0004] According to a first aspect, a multi-core CPU resource dynamic allocation method based on an SPDK architecture is provided, the method comprising:

[0005] The CPU resources are divided into multiple processing areas based on the subsystem type of the SPDK architecture, each of which is used to process the polling thread of the subsystem of the specified type, and the CPU resources configured for each processing area are determined based on the subsystem pressure;

[0006] When a CPU usage application of any target polling thread is detected, searching for a first CPU that is currently not in use in a target processing area corresponding to the target polling thread;

[0007] When the first CPU exists, binding any of the first CPUs to the target polling thread;

[0008] When the first CPU does not exist, a second CPU with the lowest current reference count is determined in the target processing area, and the second CPU is bound to the target polling thread, where the current reference count is the number of CPUs that are simultaneously referenced and bound.

[0009] Preferably, the subsystem type based on the SPDK architecture divides CPU resources into multiple processing areas, including:

[0010] Query the demand information corresponding to each subsystem type of the SPDK framework, the demand information including processing speed requirements and resource quantity requirements;

[0011] A processing area is divided for each subsystem type, and CPU resources are allocated to each processing area based on the demand information.

[0012] Preferably, allocating CPU resources to each of the processing areas based on the demand information includes:

[0013] Determine the CPU allocation ratio of each processing area based on the resource quantity requirements, and determine the CPU allocation number of each processing area according to the total number of CPU cores;

[0014] Perform a first sorting of the CPUs according to the processing speed from large to small, and perform a second sorting of the processing areas according to the processing speed requirements from high to low;

[0015] The processing areas are selected in sequence according to the second sorting, and the CPUs of the CPU allocation number are selected according to the first sorting and allocated to the processing areas.

[0016] Preferably, after the subsystem type based on the SPDK architecture divides the CPU resources into multiple processing areas, it also includes:

[0017] Initialize the CPU resources in each of the processing regions, clear the current reference count of each CPU, and mark each CPU as currently unused.

[0018] Preferably, searching for a first CPU that is not currently in use in a target processing area corresponding to the target polling thread includes:

[0019] The subsystem type to which the target polling thread belongs is determined, a target processing area is determined according to the subsystem type, and a first CPU that is not currently in use is searched in the target processing area.

[0020] Preferably, the method further comprises:

[0021] For any CPU, when a polling thread is newly bound to the CPU, the current reference count of the CPU is increased by one.

[0022] Preferably, the method further comprises:

[0023] For any CPU, when the CPU detects a CPU release instruction of any polling thread, the CPU is unbound from the polling thread, and the current reference count of the CPU is reduced by one.

[0024] According to a second aspect, a multi-core CPU resource dynamic allocation device based on an SPDK architecture is provided, the device comprising:

[0025] A partitioning module, used to partition CPU resources into a plurality of processing regions based on the subsystem type of the SPDK architecture, each of the processing regions being used to process a polling thread of a subsystem of a specified type, and the CPU resources configured for each of the processing regions being determined based on the subsystem pressure;

[0026] A search module, configured to search for a first CPU that is currently unused in a target processing area corresponding to the target polling thread when a CPU usage application of any target polling thread is detected;

[0027] A first judgment module, configured to bind any of the first CPUs to the target polling thread when the first CPU exists;

[0028] The second judgment module is used to determine the second CPU with the lowest current reference count in the target processing area when the first CPU does not exist, and bind the second CPU to the target polling thread, wherein the current reference count is the number of CPUs that are referenced and bound at the same time.

[0029] According to a third aspect, there is provided an electronic device, comprising a processor and a memory;

[0030] The processor is connected to the memory;

[0031] The memory is used to store executable program code;

[0032] The processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to execute the steps of the method provided in the first aspect or any possible implementation manner of the first aspect.

[0033] According to a fourth aspect, a computer-readable storage medium is provided, on which a computer program is stored, and the computer-readable storage medium stores instructions, which, when the instructions are executed on a computer or a processor, cause the computer or the processor to execute the method provided in the first aspect or any possible implementation of the first aspect.

[0034] The method and device provided in the embodiments of this specification isolate the CPU resources between the subsystems by dividing the processing areas, thereby improving the system stability, and through the load balancing strategy, configure the number of CPUs in each processing area according to the subsystem pressure, accurately control the allocation of CPU resources, avoid resource competition between the subsystems, give full play to the performance of the CPU, thereby reducing system delays and improving system throughput. In addition, when the target polling thread wants to apply for the use of the CPU, the CPU that is not used or has the smallest current reference count is selected for binding, which increases the dynamic management capability of CPU resources, and can ensure the effective use of CPU resources in the scenario where the polling thread is frequently created and deleted, thereby improving resource utilization. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0036] Figure 1 It is a flowchart of a multi-core CPU resource dynamic allocation method based on the SPDK architecture in one embodiment of this specification.

[0037] Figure 2 It is a structural diagram of a multi-core CPU resource dynamic allocation device based on SPDK architecture in one embodiment of this specification.

[0038] Figure 3 It is a structural diagram of an electronic device in one embodiment of this specification. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0040] In the following introduction, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The following introduction provides multiple embodiments of the present application, and different embodiments can be replaced or combined, so the present application can also be considered to include all possible combinations of the same and / or different embodiments recorded. Therefore, if one embodiment includes features A, B, and C, and another embodiment includes features B and D, then the present application should also be considered to include embodiments containing one or more of all other possible combinations of A, B, C, and D, although the embodiment may not be clearly recorded in the following text.

[0041] The following description provides examples and does not limit the scope, applicability or examples set forth in the claims. Changes may be made to the functions and arrangements of the elements described without departing from the scope of the present application. Various processes or components may be appropriately omitted, substituted or added to each example. For example, the described method may be performed in an order different from the order described, and various steps may be added, omitted or combined. In addition, features described in some examples may be combined in other examples.

[0042] See also Figure 1 , Figure 1 : is a flowchart of a multi-core CPU resource dynamic allocation method based on the SPDK architecture provided in an embodiment of the present application. In an embodiment of the present application, the method includes:

[0043] S101. Divide CPU resources into multiple processing areas based on the subsystem types of the SPDK architecture.

[0044] Each of the processing regions is used to process a polling thread of a subsystem of a specified type, and the CPU resources configured for each of the processing regions are determined based on the subsystem pressure.

[0045] The execution entity of this application can be a cloud server.

[0046] In the embodiments of this specification, the SPDK architecture has subsystems of different subsystem types, and different types of subsystems have different functions. For example, some subsystems are responsible for handling the coordination between the various subsystems of the SPDK architecture and the scheduling of various polling threads, some subsystems are responsible for handling the affairs of the block device subsystem in the SPDK architecture, and some subsystems are responsible for providing underlying dependencies for the remaining subsystems, etc. This application will set up multiple processing areas according to the type of subsystem, so that each processing area is specifically used to process the polling threads generated in a specific type of subsystem, and the amount of CPU resources specifically allocated to each processing area is determined according to the pressure of the subsystem it is responsible for. Among them, the CPU resources configured in each processing area mainly include the number of CPUs and the specific number of CPU cores used. The number of CPUs will affect the concurrent data processing performance of the processing area. In a multi-core processor, the processing efficiency of CPU cores in different positions is different. Taking a processor with a 64-core NUMA architecture as an example, the closer the CPU is to the 0 core, the higher the processing efficiency. At the same time, subsystem pressure is mainly caused by too much data to be processed at the same time or the data being processed is too large and the data processing rate is slow, which delays the processing of other data. Therefore, the cloud server needs to determine the amount of CPU resources allocated to each processing area based on the subsystem pressure. The specific configuration method can be a quantitative method, that is, quantitatively determining the specific subsystem pressure, that is, setting the required concurrency and processing rate for the subsystem in advance according to the processing requirements, and then presetting a mapping table to represent how much concurrency corresponds to how many CPUs, how much processing rate corresponds to how many cores of the CPU, and finally allocating the CPU according to the mapping table. It can also be that the cloud server sends an allocation request to the staff, and the staff returns the allocation information after allocating it according to experience, and the cloud server directly allocates it according to the allocation information, or it can be other feasible implementation methods.

[0047] In one possible implementation, the subsystem type based on the SPDK architecture divides CPU resources into multiple processing areas, including:

[0048] Query the demand information corresponding to each subsystem type of the SPDK framework, the demand information including processing speed requirements and resource quantity requirements;

[0049] A processing area is divided for each subsystem type, and CPU resources are allocated to each processing area based on the demand information.

[0050] In the embodiments of this specification, the staff will set the demand information for each subsystem in the SPDK framework in advance according to the subsystem type, and store it in the cloud server. The demand information includes the quantitatively set processing rate requirements and resource quantity requirements. After the processing area is divided for each subsystem type, the cloud server will allocate CPU resources according to the demand information and any of the aforementioned configuration methods to ensure that each processing area is allocated with a suitable number and performance of CPU resources.

[0051] In one possible implementation, allocating CPU resources to each of the processing areas based on the demand information includes:

[0052] Determine the CPU allocation ratio of each processing area based on the resource quantity requirements, and determine the CPU allocation number of each processing area according to the total number of CPU cores;

[0053] Perform a first sorting of the CPUs according to the processing speed from large to small, and perform a second sorting of the processing areas according to the processing speed requirements from high to low;

[0054] The processing areas are selected in sequence according to the second sorting, and the CPUs of the CPU allocation number are selected according to the first sorting and allocated to the processing areas.

[0055] In the embodiments of the present specification, the cloud server will determine the resource quantity requirements of each processing area respectively, and determine the CPU allocation number ratio of each processing area according to the ratio between the resource quantity requirements. Then, based on the calculation of the CPU allocation number ratio and the total number of CPU cores, the number of CPU allocations actually allocated to each processing area is determined. In addition, the cloud server will also perform a first sorting of each CPU according to the size of the processing speed, so that the CPU with a faster processing speed is sorted higher. Similarly, the processing areas will be sorted in a second order according to the level of processing speed requirements. After completing the first and second sorting, the cloud server will still select the processing area according to the second sorting, and select the corresponding number of CPUs in the first sorting in order according to the number of CPU allocations corresponding to the processing area and allocate them to the processing area, so as to ultimately ensure that the CPU resources allocated to each processing area meet the actual operation requirements of this type of subsystem.

[0056] As an example, taking a 64-core processor of NUMA architecture as an example, after dividing multiple processing regions according to the subsystem type, each processing region can be named differently according to the subsystem type name. For example, MAIN region can be responsible for handling the coordination between various subsystems of SPDK architecture, the scheduling of various polls, etc., and has high requirements for processing speed, so the fastest 0-7 cores are allocated to main region. BDEV region can be responsible for handling the affairs of block device subsystem in SPDK architecture. Block device subsystem is the underlying dependency of all other block device-related subsystems and requires high processing speed, so the faster 7-15 core CPU is allocated to BDEV region. LVSTORE region, ISCSI region, etc. need to handle a large number of IO-related affairs, which require high concurrency, but the requirements for single CPU performance are relatively low. Therefore, the number of CPU resources allocated to these regions is large, but the performance of a single CPU is relatively weak, etc.

[0057] In one possible implementation, after the subsystem type based on the SPDK architecture divides the CPU resources into multiple processing areas, it also includes:

[0058] Initialize the CPU resources in each of the processing regions, clear the current reference count of each CPU, and mark each CPU as currently unused.

[0059] In the embodiment of this specification, after the division of CPU resources in each processing area is completed, the CPU resources need to be initialized before formal work. Specifically, the current reference counts of the CPUs can be cleared to zero, and each CPU can be marked as currently unused. In addition, the number of CPUs in the processing area, CPU affinity and other related information can be re-counted and stored to facilitate query and scheduling when problems arise later.

[0060] S102: When a CPU usage request of any target polling thread is detected, searching for a first CPU that is currently not in use in a target processing area corresponding to the target polling thread.

[0061] In the embodiments of this specification, the target polling thread is only distinguished from the other polling threads for the sake of explanation, and the target polling thread is no different from the other polling threads. When a target polling thread is generated and a CPU needs to be bound to perform specific task processing, the cloud server will detect the CPU usage request sent by the target polling thread. At this time, the cloud server will determine the target processing area corresponding to the target polling thread according to the subsystem type, and search for the first CPU that is not currently in use among all CPUs in the target processing area.

[0062] In one possible implementation, searching for a currently unused first CPU in a target processing area corresponding to the target polling thread includes:

[0063] The subsystem type to which the target polling thread belongs is determined, a target processing area is determined according to the subsystem type, and a first CPU that is not currently in use is searched in the target processing area.

[0064] In the embodiment of the present specification, the cloud server will determine the subsystem to which the target polling thread belongs based on the location generated by the target polling thread, and then determine the type of subsystem to which it belongs, and then determine the corresponding target processing area based on the subsystem type, and finally query the first CPU in the target processing area.

[0065] S103: When the first CPU exists, bind any of the first CPUs to the target polling thread.

[0066] In the embodiment of the present specification, if there is a first CPU in the target processing area, the cloud server will select any first CPU therefrom and bind it to the target polling thread so that the first CPU can support the data processing work of the target polling thread.

[0067] S104: When the first CPU does not exist, determine a second CPU with the lowest current reference count in the target processing area, and bind the second CPU to the target polling thread.

[0068] The current reference count is the number of CPUs that are referenced and bound at the same time.

[0069] In the embodiment of this specification, if the first CPU does not exist in the target processing area, it means that all CPUs are being used, and only a CPU being used can be bound to the target polling thread so that the CPU can process multiple threads at the same time. In order to make the pressure of each CPU as similar as possible and give full play to the performance of each CPU, each CPU will be set with a current reference count to indicate how many threads the CPU is currently processing at the same time. The cloud server will determine the second CPU with the lowest current reference count and bind the second CPU to the target polling thread to avoid further increasing the load of some CPUs that have already processed a large number of threads.

[0070] In one embodiment, the method further comprises:

[0071] For any CPU, when a polling thread is newly bound to the CPU, the current reference count of the CPU is increased by one.

[0072] In the embodiment of the present specification, for any CPU, as long as the CPU is newly bound to a polling thread, its corresponding current reference count will be increased by one at the same time to ensure that the current reference count can represent the actual load status of each CPU in real time.

[0073] In one embodiment, the method further comprises:

[0074] For any CPU, when the CPU detects a CPU release instruction of any polling thread, the CPU is unbound from the polling thread, and the current reference count of the CPU is reduced by one.

[0075] In the embodiments of this specification, under the SPDK architecture, polling threads are frequently created and deleted. If a CPU release instruction of any polling thread is detected, it means that a polling thread has been processed and will be deleted. At this time, the cloud server will control the CPU bound to the polling thread to unbind it from the polling thread, and reduce the current reference count corresponding to the CPU by one.

[0076] The following will be combined with the attached Figure 2 , a multi-core CPU resource dynamic allocation device based on SPDK architecture provided in the embodiment of the present application is introduced in detail. It should be noted that the attached Figure 2 The multi-core CPU resource dynamic allocation device based on the SPDK architecture shown is used to execute the application Figure 1 For the convenience of explanation, only the part related to the embodiment of the present application is shown. For the specific technical details not disclosed, please refer to the present application. Figure 1 The embodiment shown.

[0077] See also Figure 2 , Figure 2 Schematic diagram of a multi-core CPU resource dynamic allocation device based on SPDK architecture provided by an embodiment of the present application. Figure 2 As shown, the device comprises:

[0078] A partitioning module 201 is used to partition CPU resources into a plurality of processing regions based on the subsystem type of the SPDK architecture, each of the processing regions is used to process the polling thread of the subsystem of a specified type, and the CPU resources configured for each of the processing regions are determined based on the subsystem pressure;

[0079] A search module 202 is used to search for a currently unused first CPU in a target processing area corresponding to the target polling thread when a CPU usage application of any target polling thread is detected;

[0080] A first judgment module 203 is used to bind any of the first CPUs to the target polling thread when the first CPU exists;

[0081] The second judgment module 204 is used to determine the second CPU with the lowest current reference count in the target processing area when the first CPU does not exist, and bind the second CPU to the target polling thread, wherein the current reference count is the number of CPUs that are referenced and bound at the same time.

[0082] In one possible implementation, the partitioning module 201 is specifically used for:

[0083] Query the demand information corresponding to each subsystem type of the SPDK framework, the demand information including processing speed requirements and resource quantity requirements;

[0084] A processing area is divided for each subsystem type, and CPU resources are allocated to each processing area based on the demand information.

[0085] In one possible implementation, the division module 201 is further specifically used for:

[0086] Determine the CPU allocation ratio of each processing area based on the resource quantity requirements, and determine the CPU allocation number of each processing area according to the total number of CPU cores;

[0087] Perform a first sorting of the CPUs according to the processing speed from large to small, and perform a second sorting of the processing areas according to the processing speed requirements from high to low;

[0088] The processing areas are selected in sequence according to the second sorting, and the CPUs of the CPU allocation number are selected according to the first sorting and allocated to the processing areas.

[0089] In one possible implementation, the division module 201 is further specifically used for:

[0090] Initialize the CPU resources in each of the processing regions, clear the current reference count of each CPU, and mark each CPU as currently unused.

[0091] In one possible implementation, the search module 202 is specifically used for:

[0092] The subsystem type to which the target polling thread belongs is determined, a target processing area is determined according to the subsystem type, and a first CPU that is not currently in use is searched in the target processing area.

[0093] In one embodiment, the device further comprises:

[0094] The first counting module is used for increasing the current reference count of any CPU by one when a polling thread is newly bound to the CPU.

[0095] In one embodiment, the device further comprises:

[0096] The second counting module is used for unbinding any CPU from the polling thread and reducing the current reference count of the CPU by one when the CPU detects a CPU release instruction of any polling thread.

[0097] Those skilled in the art can clearly understand that the technical solutions of the embodiments of the present application can be implemented with the help of software and / or hardware. The "unit" and "module" in this specification refer to software and / or hardware that can independently complete or cooperate with other components to complete specific functions, where the hardware can be, for example, a field programmable gate array (FPGA), an integrated circuit (IC), etc.

[0098] Each processing unit and / or module of the embodiments of the present application may be implemented by an analog circuit that implements the functions described in the embodiments of the present application, or may be implemented by software that executes the functions described in the embodiments of the present application.

[0099] See also Figure 3 , which shows a schematic diagram of the structure of an electronic device involved in an embodiment of the present application, the electronic device can be used to implement Figure 1 The method in the embodiment shown. Figure 3 As shown, the electronic device 300 may include: at least one processor 301 , at least one network interface 304 , a user interface 303 , a memory 305 , and at least one communication bus 302 .

[0100] The communication bus 302 is used to realize the connection and communication between these components.

[0101] The user interface 303 may include a display screen (Display) and a camera (Camera). Optionally, the user interface 303 may also include a standard wired interface and a wireless interface.

[0102] The network interface 304 may optionally include a standard wired interface or a wireless interface (such as a WI-FI interface).

[0103] Among them, the processor 301 may include one or more processing cores. The processor 301 uses various interfaces and lines to connect various parts of the entire electronic device 300, and executes various functions and processes data of the electronic device 300 by running or executing instructions, programs, code sets or instruction sets stored in the memory 305, and calling data stored in the memory 305. Optionally, the processor 301 can be implemented in at least one hardware form of digital signal processing (Digital Signal Processing, DSP), field programmable gate array (Field-Programmable Gate Array, FPGA), and programmable logic array (Programmable Logic Array, PLA). The processor 301 can integrate one or a combination of a central processing unit (Central Processing Unit, CPU), a graphics central processing unit (Graphics Processing Unit, GPU) and a modem. Among them, the CPU mainly processes the operating system, user interface and application programs; the GPU is responsible for rendering and drawing the content to be displayed on the display screen; the modem is used to process wireless communications. It can be understood that the above-mentioned modem may not be integrated into the processor 301, and it can be implemented separately through a chip.

[0104] Among them, the memory 305 may include a random access memory (Random Access Memory, RAM) and may also include a read-only memory (Read-Only Memory). Optionally, the memory 305 includes a non-transitory computer-readable storage medium. The memory 305 can be used to store instructions, programs, codes, code sets or instruction sets. The memory 305 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playback function, an image playback function, etc.), instructions for implementing the above-mentioned various method embodiments, etc.; the data storage area may store data involved in the above-mentioned various method embodiments, etc. The memory 305 may optionally be at least one storage device located away from the aforementioned processor 301. As Figure 3 As shown, the memory 305 as a computer storage medium may include an operating system, a network communication module, a user interface module, and program instructions.

[0105] exist Figure 3In the electronic device 300 shown, the user interface 303 is mainly used to provide an input interface for the user and obtain the data input by the user; and the processor 301 can be used to call the multi-core CPU resource dynamic allocation application based on the SPDK architecture stored in the memory 305, and specifically perform the following operations:

[0106] The CPU resources are divided into multiple processing areas based on the subsystem type of the SPDK architecture, each of which is used to process the polling thread of the subsystem of the specified type, and the CPU resources configured for each processing area are determined based on the subsystem pressure;

[0107] When a CPU usage application of any target polling thread is detected, searching for a first CPU that is currently not in use in a target processing area corresponding to the target polling thread;

[0108] When the first CPU exists, binding any of the first CPUs to the target polling thread;

[0109] When the first CPU does not exist, a second CPU with the lowest current reference count is determined in the target processing area, and the second CPU is bound to the target polling thread, where the current reference count is the number of CPUs that are simultaneously referenced and bound.

[0110] The present application also provides a computer-readable storage medium on which a computer program is stored, and when the program is executed by a processor, the steps of the above method are implemented. The computer-readable storage medium may include, but is not limited to, any type of disk, including a floppy disk, an optical disk, a DVD, a CD-ROM, a micro drive, and a magneto-optical disk, a ROM, a RAM, an EPROM, an EEPROM, a DRAM, a VRAM, a flash memory device, a magnetic card or an optical card, a nanosystem (including a molecular memory IC), or any type of medium or device suitable for storing instructions and / or data.

[0111] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0112] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0113] In the several embodiments provided in the present application, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of the units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some service interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0114] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0115] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0116] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a memory, including a number of instructions to enable a computer device (which can be a personal computer, server or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned memory includes: U disk, read-only memory (ROM), random access memory (RAM), mobile hard disk, disk or optical disk and other media that can store program codes.

[0117] A person skilled in the art may understand that all or part of the steps in the various methods of the above embodiments may be completed by entering a program to instruct related hardware, and the program may be stored in a computer-readable memory, which may include a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0118] The above is only an exemplary embodiment of the present disclosure, and the scope of the present disclosure cannot be limited thereto. That is, any equivalent changes and modifications made according to the teachings of the present disclosure are still within the scope of the present disclosure. After considering the specification and practicing the disclosure here, those skilled in the art will easily think of the implementation scheme of the present disclosure. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary technical means in the technical field not recorded in the present disclosure. The description and examples are regarded as exemplary only, and the scope and spirit of the present disclosure are defined by the claims.

Claims

1. A multi-core CPU resource dynamic allocation method based on SPDK architecture, characterized in that: The method comprises: The CPU resources are divided into multiple processing areas based on the subsystem type of the SPDK architecture, each of which is used to process the polling thread of the subsystem of the specified type, and the CPU resources configured for each processing area are determined based on the subsystem pressure; When a CPU usage application of any target polling thread is detected, searching for a first CPU that is currently not in use in a target processing area corresponding to the target polling thread; When the first CPU exists, binding any of the first CPUs to the target polling thread; When the first CPU does not exist, determine a second CPU with the lowest current reference count in the target processing area, and bind the second CPU to the target polling thread, where the current reference count is the number of CPUs that are referenced and bound at the same time; The subsystem types based on the SPDK architecture divide the CPU resources into multiple processing areas, including: Query the demand information corresponding to each subsystem type of the SPDK framework, the demand information including processing speed requirements and resource quantity requirements; A processing area is divided for each subsystem type, and CPU resources are allocated to each processing area based on the demand information.

2. The method according to claim 1, characterized in that The allocating CPU resources to each of the processing areas based on the demand information includes: Determine the CPU allocation ratio of each processing area based on the resource quantity requirements, and determine the CPU allocation number of each processing area according to the total number of CPU cores; Perform a first sorting of the CPUs according to the processing speed from large to small, and perform a second sorting of the processing areas according to the processing speed requirements from high to low; The processing areas are selected in sequence according to the second sorting, and the CPUs of the CPU allocation number are selected according to the first sorting and allocated to the processing areas.

3. The method according to claim 1, characterized in that The subsystem type based on the SPDK architecture divides the CPU resources into multiple processing areas, and further includes: Initialize the CPU resources in each of the processing regions, clear the current reference count of each CPU, and mark each CPU as currently unused.

4. The method according to claim 1, characterized in that: The step of searching for a currently unused first CPU in a target processing area corresponding to the target polling thread includes: The subsystem type to which the target polling thread belongs is determined, a target processing area is determined according to the subsystem type, and a first CPU that is not currently in use is searched in the target processing area.

5. The method according to claim 1, characterized in that: The method further comprises: For any CPU, when a polling thread is newly bound to the CPU, the current reference count of the CPU is increased by one.

6. The method according to claim 1, characterized in that The method further comprises: For any CPU, when the CPU detects a CPU release instruction of any polling thread, the CPU is unbound from the polling thread, and the current reference count of the CPU is reduced by one.

7. A multi-core CPU resource dynamic allocation device based on SPDK architecture, characterized in that: The device comprises: A partitioning module, used to partition CPU resources into a plurality of processing regions based on the subsystem type of the SPDK architecture, each of the processing regions being used to process a polling thread of a subsystem of a specified type, and the CPU resources configured for each of the processing regions being determined based on the subsystem pressure; A search module, configured to search for a first CPU that is currently not in use in a target processing area corresponding to the target polling thread when a CPU usage application of any target polling thread is detected; A first judgment module, configured to bind any of the first CPUs to the target polling thread when the first CPU exists; A second judgment module is used for determining, in the target processing area, a second CPU with the lowest current reference count when the first CPU does not exist, and binding the second CPU to the target polling thread, wherein the current reference count is the number of CPUs that are referenced and bound at the same time; Wherein, the division module is specifically used for: Query the demand information corresponding to each subsystem type of the SPDK framework, the demand information including processing speed requirements and resource quantity requirements; A processing area is divided for each subsystem type, and CPU resources are allocated to each processing area based on the demand information.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, wherein the computer-readable storage medium has instructions stored therein, and when the instructions are executed on a computer or a processor, the computer or the processor executes the steps of the method according to any one of claims 1 to 6.

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