Clock protection circuit, clock protection method, storage medium and electronic equipment

Abstract

The invention discloses a clock protection circuit, a clock protection method, a storage medium and electronic equipment. The clock protection circuit comprises a clock monitoring module used for performing fault monitoring on a functional clock signal generated by a functional clock source based on a backup clock signal generated by a backup clock source to obtain a fault monitoring result, and determining a target clock signal from the backup clock signal and the functional clock signal based on the fault monitoring result; and the clock processing module is used for determining a safe clock signal transmitted to the functional module based on the target clock signal. According to the embodiment of the invention, the reliability of the clock signal used by the function module can be ensured, the normal and reliable work of the function module can be ensured, and the normal operation of the chip where the function module is located can be ensured.

Description

Technical Field

[0001] The present disclosure relates to functional safety technology, and in particular to a clock protection circuit, a clock protection method, a storage medium, and an electronic device. Background Art

[0002] Currently, chips are widely used. Each functional module in the chip usually needs to use a clock signal. How to ensure the reliability of the clock signal used by the functional module is a problem worthy of attention for those skilled in the art. Summary of the invention

[0003] In order to solve the above technical problems, the present disclosure provides a clock protection circuit, a clock protection method, a storage medium and an electronic device.

[0004] According to one aspect of an embodiment of the present disclosure, there is provided a clock protection circuit, including:

[0005] A clock monitoring module, configured to perform fault monitoring on a functional clock signal generated by a functional clock source based on a backup clock signal generated by a backup clock source, obtain a fault monitoring result, and determine a target clock signal from the backup clock signal and the functional clock signal based on the fault monitoring result;

[0006] The clock processing module is used to determine a safe clock signal for transmission to a functional module based on the target clock signal.

[0007] According to another aspect of an embodiment of the present disclosure, a clock protection method is provided, including:

[0008] Based on the backup clock signal generated by the backup clock source, a fault monitoring is performed on the functional clock signal generated by the functional clock source to obtain a fault monitoring result;

[0009] Based on the fault monitoring result, determining a target clock signal from the backup clock signal and the functional clock signal;

[0010] Based on the target clock signal, a secure clock signal is determined for transmission to the functional module.

[0011] According to another aspect of an embodiment of the present disclosure, a computer-readable storage medium is provided, wherein the storage medium stores a computer program, and the computer program is used to execute the above clock protection method.

[0012] According to another aspect of the embodiments of the present disclosure, an electronic device is provided, the electronic device comprising:

[0013] processor;

[0014] a memory for storing instructions executable by the processor;

[0015] The processor is used to read the executable instructions from the memory and execute the instructions to implement the clock protection method.

[0016] According to another aspect of an embodiment of the present disclosure, a computer program product is provided. When instructions in the computer program product are executed by a processor, the above-mentioned clock protection method is executed.

[0017] Based on the clock protection circuit, clock protection method, storage medium, electronic device and program product provided by the above embodiments of the present disclosure, two types of clock sources can be set, namely, a functional clock source and a backup clock source. The clock monitoring module can perform fault monitoring on the functional clock signal generated by the functional clock source based on the backup clock signal generated by the backup clock source, so as to reasonably determine the target clock signal from the backup clock signal and the functional clock signal according to the fault monitoring result. The clock processing module can determine the safe clock signal for transmission to the functional module based on the target clock signal. It can be seen that in the embodiments of the present disclosure, through the setting of two types of clock sources, and the coordinated work of the clock monitoring module and the clock processing module, regardless of whether the functional clock signal is abnormal, the functional module can be provided with a clock signal (i.e., a safe clock signal) required for its work and free of faults. In this way, it is conducive to ensuring the reliability of the clock signal used by the functional module, thereby ensuring the normal and reliable operation of the functional module, and ensuring the normal operation of the chip where the functional module is located. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic diagram of a clock protection architecture in some exemplary embodiments of the present disclosure.

[0019] Figure 2 is a schematic diagram of the structure of a clock protection circuit provided by some exemplary embodiments of the present disclosure.

[0020] Figure 3 Schematic diagram of signal waveform of functional clock signal in some exemplary embodiments of the present disclosure.

[0021] Figure 4 Schematic diagram of signal waveforms of functional clock signals in some other exemplary embodiments of the present disclosure.

[0022] Figure 5 is a schematic diagram of the structure of a clock monitoring module in some exemplary embodiments of the present disclosure.

[0023] Figure 6 It is a structural schematic diagram of a clock protection circuit provided by some other exemplary embodiments of the present disclosure.

[0024] Figure 7is a schematic diagram of a clock protection architecture in some other exemplary embodiments of the present disclosure.

[0025] Figure 8 It is a structural diagram of a clock protection method provided by some exemplary embodiments of the present disclosure.

[0026] Fig. 9 It is a flowchart of a method for obtaining fault monitoring results provided by some exemplary embodiments of the present disclosure.

[0027] Fig.10 It is a flowchart of a method for obtaining a secure clock signal provided by some exemplary embodiments of the present disclosure.

[0028] Fig.11 It is a structural schematic diagram of a clock protection method provided by other exemplary embodiments of the present disclosure.

[0029] Fig.12 It is a schematic diagram of the structure of an electronic device provided by some exemplary embodiments of the present disclosure. DETAILED DESCRIPTION

[0030] To explain the present disclosure, example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. It should be understood that the present disclosure is not limited to the example embodiments.

[0031] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

[0032] Application Overview

[0033] Chip technology is the cornerstone of modern scientific and technological development. Chips can be applied to many fields, including but not limited to consumer electronics, communications, computers, medical treatment, automobiles, the Internet of Things, etc. If the chip is applied to the automotive field, the chip can be, for example, a smart driving chip.

[0034] Each functional module in a chip usually requires the use of a clock signal. Specifically, each functional module in a chip can rely on the time reference provided by the clock signal, on which basis, the operation of each functional module can be accurately synchronized, so that different functional modules can work together, effectively avoiding data conflicts and confusion in functional execution. Optionally, a functional module can also be called an IP module.

[0035] How to ensure the reliability of the clock signal used by the functional module is an issue worthy of attention for those skilled in the art.

[0036] Exemplary Systems

[0037] Figure 1 is a schematic diagram of a clock protection architecture in some exemplary embodiments of the present disclosure. Figure 1 The clock protection architecture shown may include: a clock protection circuit 20 , a functional clock source 40 , a backup clock source 60 and a functional module 80 .

[0038] Optionally, the functional clock source 40 may be a clock source for generating a functional clock signal, and the backup clock source 60 may be a clock source for generating a backup clock signal. The functional clock signal generated by the functional clock source 40 and the backup clock signal generated by the backup clock source 60 may be independent of each other and do not affect each other. The functional clock source 40 and the backup clock source 60 may be electrically connected to the clock protection circuit 20, respectively. The clock protection circuit 20 may also be electrically connected to the functional module 80.

[0039] In the embodiment of the present disclosure, when there is no fault in the functional clock signal generated by the functional clock source 40, the clock protection circuit 20 can determine the clock signal required for the function module 80 to work and not have a fault based on the functional clock signal generated by the functional clock source 40, and transmit the determined clock signal to the functional module 80. When there is a fault in the functional clock signal generated by the functional clock source 40, the clock protection circuit 20 can determine the clock signal required for the function module 80 to work and not have a fault based on the backup clock signal generated by the backup clock source 60, and transmit the determined clock signal to the functional module 80. In this way, it is conducive to ensuring the reliability of the clock signal used by the functional module 80, thereby ensuring the normal and reliable operation of the functional module 80, and ensuring the normal operation of the chip where the functional module 80 is located.

[0040] Example Circuit

[0041] Figure 2 FIG. 2 is a schematic diagram of the structure of a clock protection circuit 20 provided by some exemplary embodiments of the present disclosure. Figure 2 As shown, the clock protection circuit 20 may include:

[0042] The clock monitoring module 202 is used to perform fault monitoring on the functional clock signal generated by the functional clock source 40 based on the backup clock signal generated by the backup clock source 60, obtain a fault monitoring result, and determine a target clock signal from the backup clock signal and the functional clock signal based on the fault monitoring result;

[0043] The clock processing module 204 is used to determine a safe clock signal for transmission to the functional module 80 based on the target clock signal.

[0044] Optionally, the clock monitoring module 202 may be a module capable of performing clock monitoring on the functional clock source 40. The clock processing module 204 may be a module capable of processing clock failures. The clock monitoring module 202 may be electrically connected to the functional clock source 40 and the backup clock source 60, respectively. The clock processing module 204 may be electrically connected to the clock monitoring module 202 and the functional module 80, respectively.

[0045] Through the electrical connection between the clock monitoring module 202 and the functional clock source 40, the functional clock source 202 can transmit the functional clock signal to the clock monitoring module 202, and accordingly, the clock monitoring module 202 can receive the functional clock signal. Through the electrical connection between the clock monitoring module 202 and the backup clock source 60, the backup clock source 60 can transmit the backup clock signal to the clock monitoring module 202, and accordingly, the clock monitoring module 202 can receive the backup clock signal. The clock monitoring module 202 can perform fault monitoring on the functional clock signal based on the backup clock signal to obtain a fault monitoring result, and the fault monitoring result can be used to characterize whether the functional clock signal has a fault. For example, the clock monitoring module 202 can determine whether the waveform of the functional clock signal meets expectations based on the backup clock signal. If the waveform of the functional clock signal meets expectations, the fault monitoring result can be used to characterize that the functional clock signal does not have a fault. If the waveform of the functional clock signal does not meet expectations, the fault monitoring result can be used to characterize that the functional clock signal has a fault.

[0046] Optionally, if there is a fault in the functional clock signal, the fault type of the functional clock signal may include but is not limited to a frequency fault type and a lock fault type. Assuming that there is no fault in the functional clock signal such as Figure 3 As shown in CLK1 in FIG, the functional clock signal of the fault type of frequency fault type can be as follows Figure 3 As shown in CLK2 in the figure, it is easy to see that there are glitches in CLK2. Assuming that there is no fault in the functional clock signal such as Figure 4 As shown in CLK3 in FIG. 1 , the functional clock signal of the fault type of the locked fault type can be as follows: Figure 4 As shown in CLK4 or CLK5 in.

[0047] The clock monitoring module 202 can determine the target clock signal from the backup clock signal and the functional clock signal based on the fault monitoring result. The target clock signal can be a clock signal that matches the fault monitoring result between the backup clock signal and the functional clock signal. Through the electrical connection between the clock processing module 204 and the clock monitoring module 202, the clock monitoring module 202 can transmit the target clock signal to the clock processing module 204, and accordingly, the clock processing module 204 can receive the target clock signal.

[0048] The clock processing module 204 can determine a safe clock signal for transmission to the functional module 80 based on the target clock signal. The safe clock signal can be understood as a clock signal that is required for the function module 80 to work and does not have any faults. Through the electrical connection between the clock processing module 204 and the function module 80, the clock processing module 204 can transmit the safe clock signal to the function module 80, and accordingly, the function module 80 can receive the safe clock signal, and the function module 80 can rely on the time reference provided by the safe clock signal to work normally.

[0049] In the embodiment of the present disclosure, two types of clock sources can be set, namely, a functional clock source 40 and a backup clock source 60. The clock monitoring module 202 can perform fault monitoring on the functional clock signal generated by the functional clock source 40 based on the backup clock signal generated by the backup clock source 60, so as to reasonably determine the target clock signal from the backup clock signal and the functional clock signal according to the fault monitoring result. The clock processing module 204 can determine the safe clock signal for transmission to the functional module 80 based on the target clock signal. It can be seen that in the embodiment of the present disclosure, through the setting of two types of clock sources, and the coordinated work of the clock monitoring module 202 and the clock processing module 204, regardless of whether there is an abnormality in the functional clock signal, the functional module 80 can be provided with a clock signal (i.e., a safe clock signal) required for its work and free of faults. In this way, it is conducive to ensuring the reliability of the clock signal used by the functional module 80, thereby ensuring the normal and reliable operation of the functional module 80, and ensuring the normal operation of the chip where the functional module 80 is located.

[0050] In some optional examples, such as Figure 5 As shown, the clock monitoring module 202 may include: a first interaction unit 2022, a second interaction unit 2024 and a first determination unit 2026;

[0051] The clock monitoring module 202 is used to perform fault monitoring on the functional clock signal generated by the functional clock source 40 based on the backup clock signal generated by the backup clock source 60 to obtain a fault monitoring result, which may include:

[0052] The first interaction unit 2022 is used to generate a handshake request in response to a rising edge of the backup clock signal;

[0053] The second interaction unit 2024 is used for generating a response to the handshake request driven by the functional clock signal in response to receiving the handshake request;

[0054] The first determination unit 2026 is used to count the number of times the second interaction unit 2024 does not generate a response within a preset time period after receiving a handshake request, determine a first numerical relationship between the counted number of times and the preset number of times, and determine a fault monitoring result based on the first numerical relationship.

[0055] Optionally, the first interaction unit 2022 and the second interaction unit 2024 may both be units for information interaction. The first determination unit 2026 may be a unit for determining a fault monitoring result. The first interaction unit 2022 may be electrically connected to the second interaction unit 2024. A line for electrical connection may be provided between the first interaction unit 2022 and the second interaction unit 2024, and the first determination unit 2026 may be electrically connected to the line.

[0056] Optionally, the backup clock signal may be defaulted to a clock signal without a fault. As an example, the backup clock signal may be a square wave signal.

[0057] Whenever the backup clock signal has a rising edge, the first interaction unit 2022 may generate a handshake request. Through the electrical connection between the first interaction unit 2022 and the second interaction unit 2024, the first interaction unit 2022 may transmit the generated handshake request to the second interaction unit 2024, and accordingly, the second interaction unit 2024 may receive the handshake request.

[0058] Whenever the second interaction unit 2024 receives a handshake request, the second interaction unit 2024 may generate a response to the handshake request driven by the functional clock signal.

[0059] It should be noted that, since the generation of the response to the handshake request needs to rely on the driving of the functional clock signal, when there is no fault in the functional clock signal, the response to the handshake request can usually be generated normally, and when there is a fault in the functional clock signal, the response to the handshake request may not be generated normally. The first determination unit 2026 can count the number of times the second interaction unit 2024 does not generate a response within a preset time period after receiving the handshake request. The duration of the preset time period can be a pre-software configured duration, which can be the maximum duration required for the generation of the response to the handshake request.

[0060] The first determination unit 2026 may determine a first numerical relationship between the counted number of times and a preset number of times. For example, the first determination unit 2026 may compare the counted number of times with the preset number of times, and determine the magnitude relationship between the counted number of times and the preset number of times as the first numerical relationship. As an example, the preset number of times may be 3, 4, 5, 6, etc., which are not listed here one by one.

[0061] If the first numerical relationship is used to characterize that the number of statistics is greater than the preset number, it means that the number of times the second interaction unit 2024 fails to generate a response normally is not within a reasonable range, and the second interaction unit 2024 and the first interaction unit 2022 cannot shake hands normally, which is most likely caused by a fault in the functional clock signal. Then, the fault monitoring result determined by the first determination unit 2026 can be used to characterize that there is a fault in the functional clock signal.

[0062] If the first numerical relationship is used to characterize that the number of times counted is less than or equal to the preset number, this means that the number of times the second interaction unit 2024 fails to generate a response normally is within a reasonable range, and the second interaction unit 2024 and the first interaction unit 2022 can shake hands normally, then the fault monitoring result determined by the first determination unit 2026 can be used to characterize that there is no fault in the functional clock signal.

[0063] In some embodiments, the magnitude relationship between the counted number of times and the preset number of times may not be determined as the first numerical relationship, but the proportional relationship or linear relationship between the counted number of times and the preset number of times may be determined as the first numerical relationship. For example, the ratio of the counted number of times to the preset number of times may be used as the first numerical relationship. If the ratio of the counted number of times to the preset number of times is greater than the preset ratio, the fault monitoring result determined by the first determination unit 2026 can be used to characterize the presence of a fault in the functional clock signal. If the ratio of the counted number of times to the preset number of times is less than or equal to the preset ratio, the fault monitoring result determined by the first determination unit 2026 can be used to characterize the absence of a fault in the functional clock signal. As an example, the preset ratio may be 0.7, 0.75, 0.8, 0.85, etc., which are not listed one by one here.

[0064] In the embodiment of the present disclosure, the number of times that the second interaction unit 2024 does not generate a response within a preset time period after receiving the handshake request can be used to determine the generation of the response to the handshake request. Since the response to the handshake request needs to be generated under the drive of the functional clock signal, by referring to the generation of the response to the handshake request, it is possible to efficiently and reliably infer whether the functional clock signal has a fault to obtain a fault monitoring result. In addition, since the clock monitoring module 202 includes the first interaction unit 2022, the second interaction unit 2024 and the first determination unit 2026, the clock monitoring module 202 has a simple structure and low cost.

[0065] In some optional examples, the clock monitoring module 202 is configured to determine the target clock signal from the backup clock signal and the functional clock signal based on the fault monitoring result, and may include:

[0066] A clock monitoring module 202, for determining a target clock signal including a backup clock signal and a functional clock signal in response to a fault monitoring result indicating that the functional clock signal has a fault;

[0067] or,

[0068] The clock monitoring module 202 is configured to determine the functional clock signal as a target clock signal in response to the fault monitoring result indicating that the functional clock signal does not have a fault.

[0069] If the fault monitoring result is used to characterize that the functional clock signal does not have a fault, the target clock signal determined by the clock monitoring module 202 may only include the functional clock signal. After receiving the target clock signal from the clock monitoring module 202, the clock processing module 204 may use the functional clock signal that does not have a fault for determining the safe clock signal, which is conducive to ensuring the reliability of the clock signal used by the functional module 80.

[0070] If the fault monitoring result is used to characterize that the functional clock signal has a fault, the target clock signal determined by the clock monitoring module 202 may include both the backup clock signal and the functional clock signal. After receiving the target clock signal from the clock monitoring module 202, the clock processing module 204 may switch the clock signal with a fault to the backup clock signal, so that the backup clock signal without a fault is used for determining the safe clock signal, which is conducive to ensuring the reliability of the clock signal used by the functional module 80.

[0071] In some optional examples, such as Figure 6 As shown, the clock processing module 204 may include: a glitch-free clock switching unit 2042, a clock lock switching unit 2044, and a second determining unit 2046;

[0072] The clock processing module 204 is used to determine the safe clock signal for transmission to the functional module 80 based on the target clock signal, which may include:

[0073] a glitch-free clock switching unit 2042, configured to output a backup clock signal in response to receiving a target clock signal including a backup clock signal and a functional clock signal;

[0074] The clock lock switching unit 2044 is used to output the backup clock signal in response to receiving the target clock signal including the backup clock signal and the functional clock signal;

[0075] The second determining unit 2046 is used to determine the safe clock signal based on the backup clock signal output by one of the glitch-free clock switching unit 2042 and the clock lock switching unit 2044 .

[0076] Optionally, both the glitch-free clock switching unit 2042 and the clock deadlock switching unit 2044 can be units for switching the functional clock signal to a backup clock signal. The main difference between the glitch-free clock switching unit 2042 and the clock deadlock switching unit 2044 is that the glitch-free clock switching unit 2042 is suitable for switching the functional clock signal whose fault type is a frequency fault type to a backup clock signal, and the clock deadlock switching unit 2044 is suitable for switching the functional clock signal whose fault type is a deadlock fault type to a backup clock signal. It should be noted that clock signal switching is an inherent function of the glitch-free clock switching unit 2042 and the clock deadlock switching unit 2044. The specific switching principle can refer to the working principle of the two switching units in the relevant technology, which will not be repeated here. In addition, the glitch-free clock switching unit 2042 and the clock deadlock switching unit 2044 can be electrically connected to the clock monitoring module 202 respectively. The second determining unit 2046 can be electrically connected to the glitch-free clock switching unit 2042 and the clock deadlock switching unit 2044 respectively.

[0077] Through the electrical connection between the glitch-free clock switching unit 2042 and the clock monitoring module 202, the clock monitoring module 202 can transmit the target clock signal including the backup clock signal and the functional clock signal to the glitch-free clock switching unit 2042, and accordingly, the glitch-free clock switching unit 2042 can receive the target clock signal including the backup clock signal and the functional clock signal. Through the clock signal switching at the glitch-free clock switching unit 2042, the glitch-free clock switching unit 2042 can output a glitch-free backup clock signal. Through the electrical connection between the second determining unit 2046 and the glitch-free clock switching unit 2042, the second determining unit 2046 can receive the backup clock signal output by the glitch-free clock switching unit 2042.

[0078] Through the electrical connection between the clock lock switching unit 2044 and the clock monitoring module 202, the clock monitoring module 202 can transmit the target clock signal including the backup clock signal and the functional clock signal to the clock lock switching unit 2044, and accordingly, the clock lock switching unit 2044 can receive the target clock signal including the backup clock signal and the functional clock signal. Through the clock signal switching at the clock lock switching unit 2044, the clock lock switching unit 2044 can output a backup clock signal without clock lock. Through the electrical connection between the second determining unit 2046 and the clock lock switching unit 2044, the second determining unit 2046 can receive the backup clock signal output by the clock lock switching unit 2044.

[0079] The second determination unit 2046 may determine the safe clock signal based on the backup clock signal output by one of the glitch-free clock switching unit 2042 and the clock deadlock switching unit 2044 .

[0080] In some optional implementations of the present disclosure, the second determining unit 2046, configured to determine the safe clock signal based on the backup clock signal output by one of the glitch-free clock switching unit and the clock lock switching unit, may include:

[0081] The second determination unit 2046 is used to obtain the fault type of the functional clock signal, determine the target switching unit adapted to the fault type from the glitch-free clock switching unit 2042 and the clock lock switching unit 2044, and determine the safe clock signal based on the backup clock signal output by the target switching unit.

[0082] If the glitch-free clock switching unit 2042 receives a target clock signal including a backup clock signal and a functional clock signal, the glitch-free clock switching unit 2042 may determine whether the functional clock signal has a frequency fault, and obtain a first determination result. If the glitch-free clock switching unit 2042 determines that the functional clock signal has a frequency fault, the first determination result may be a first value for characterizing the presence of the frequency fault. If the glitch-free clock switching unit 2042 determines that the functional clock signal does not have a frequency fault, the first determination result may be a second value for characterizing the absence of the frequency fault. As an example, the first value may be 1, and the second value may be 0.

[0083] If the clock deadlock switching unit 2044 receives a target clock signal including a backup clock signal and a functional clock signal, the clock deadlock switching unit 2044 may determine whether the functional clock signal has a deadlock fault, and obtain a second determination result. If the clock deadlock switching unit 2044 determines that a deadlock fault occurs in the functional clock signal, the second determination result may be a third value for characterizing the presence of a deadlock fault. If the clock deadlock switching unit 2044 determines that there is no deadlock fault in the functional clock signal, the second determination result may be a fourth value for characterizing the absence of a deadlock fault. As an example, the third value may be 1, and the fourth value may be 0.

[0084] The second determination unit 2046 can determine the fault type of the functional clock signal based on the first determination result and the second determination result. For example, if the first determination result is 1 and the second determination result is 0, it can be determined that the fault type of the functional clock signal is a frequency fault type. If the first determination result is 0 and the second determination result is 1, it can be determined that the fault type of the functional clock signal is a locked fault type.

[0085] The second determination unit 2046 can determine a target switching unit adapted to the fault type from the glitch-free clock switching unit 2042 and the clock deadlock switching unit 2044. For example, if the fault type is a frequency fault type, the second determination unit 2046 can determine the glitch-free clock switching unit 2042 as the target switching unit. If the fault type is a deadlock fault type, the second determination unit 2046 can determine the clock deadlock switching unit 2044 as the target switching unit. Based on the backup clock signal output by the target switching unit, the second determination unit 2046 can determine the safe clock signal.

[0086] In this way, referring to the fault type of the functional clock signal, the target switching unit can be reasonably selected from the glitch-free clock switching unit 2042 and the clock lock switching unit 2044, and the backup clock signal output by the target switching unit is used to determine the safe clock signal. In the case of a frequency fault in the functional clock signal, the clock signal switching at the glitch-free clock switching unit 2042 is conducive to avoiding glitches in the switching process, so as to ensure the quality of the clock signal provided to the functional module 80. In the case of a lock fault in the functional clock signal, the clock signal switching at the clock lock switching unit 2044 is conducive to providing a clock signal without a lock fault to the functional module 80, and can also ensure the quality of the clock signal provided to the functional module 80.

[0087] In some other optional embodiments of the present disclosure, Figure 6 As shown, the clock protection circuit 20 may further include:

[0088] Register 206, used to store signal frequency division configuration information;

[0089] The second determining unit 2046 is configured to generate a safe clock signal based on a backup clock signal output by one of the glitch-free clock switching unit 2042 and the clock lock switching unit 2044, and may include:

[0090] The second determination unit 2046 is used to determine the frequency requirement information corresponding to each of the multiple functional modules 80 based on the signal frequency division configuration information, and to perform frequency division processing on the backup clock signal output by one of the glitch-free clock switching unit 2042 and the clock lock switching unit 2044 based on the frequency requirement information corresponding to each of the multiple functional modules 80, so as to obtain the safe clock signal corresponding to each of the multiple functional modules 80.

[0091] Optionally, the second determining unit 2046 may be electrically connected to N functional modules 80 . As an example, N may be 2, 3, 4, 5, etc., which are not listed here one by one. The second determining unit 2046 may be electrically connected to the register 206 .

[0092] Optionally, the register 206 may store the signal frequency division configuration information sent by the configuration module. The signal frequency division configuration information may include: frequency requirement information corresponding to each functional module 80 included in the chip; wherein the frequency requirement information corresponding to any functional module 80 is used to indicate the frequency of the clock signal that the functional module 80 needs to use.

[0093] Through the electrical connection between the second determination unit 2046 and the register 206, the second determination unit 2046 can obtain the signal frequency division configuration information stored in the register 206. The second determination unit 2046 can extract the frequency requirement information corresponding to each of the N functional modules 80 electrically connected to the second determination unit 2046 from the signal frequency division configuration information. According to the frequency requirement information corresponding to each of the N functional modules 80, the second determination unit 2046 can perform frequency division processing on the backup clock signal output by the target switching unit to obtain the safety clock signal corresponding to each of the N functional modules 80.

[0094] In one example, the N functional modules 80 are three functional modules 80, and the three functional modules 80 are respectively represented as IP1, IP2, and IP3. The frequency indicated by the frequency requirement information corresponding to IP1 is f1, the frequency indicated by the frequency requirement information corresponding to IP2 is f2, and the frequency indicated by the frequency requirement information corresponding to IP3 is f3. Then, by frequency division processing of the backup clock signal output by the target switching unit, a clock signal with a frequency of f1, a clock signal with a frequency of f2, and a clock signal with a frequency of f3 can be obtained. The clock signal with a frequency of f1 can be used as a safe clock signal corresponding to IP1. The clock signal with a frequency of f2 can be used as a safe clock signal corresponding to IP2. The clock signal with a frequency of f3 can be used as a safe clock signal corresponding to IP3.

[0095] In this way, by performing frequency division processing based on the signal frequency division configuration information stored in the reference register 206 , a set of safety protection circuits can be used to obtain safety clock signals corresponding to each of the multiple functional modules 80 to meet the working requirements of different functional modules 80 .

[0096] Of course, the number of the functional modules 80 electrically connected to the second determination unit 2046 may not be multiple, but may be one, and the present disclosure does not limit this.

[0097] In an embodiment of the present disclosure, when a functional clock signal fails, through the coordinated work of the glitch-free clock switching unit 2042, the clock lock switching unit 2044 and the second determination unit 2046, a backup clock signal with better quality can be used to determine the safe clock signal, which is beneficial to ensuring the reliability of the clock signal used by the functional module 80.

[0098] In some optional examples, such as Figure 6 As shown, the clock protection circuit 20 may further include:

[0099] Register 206, used to store fault reporting configuration information;

[0100] The fault reporting module 208 is used to determine the fault reporting attribute based on the fault reporting configuration information, determine the fault information to be reported based on the fault monitoring result and / or the fault type in response to the fault reporting attribute indicating that the fault needs to be reported, and report the fault information.

[0101] Optionally, the register 206 may store fault reporting configuration information sent by the configuration module, and the fault reporting configuration information may be used to indicate whether to shield the fault.

[0102] Optionally, the fault reporting module 208 may be a module for performing fault reporting. The fault reporting module 208 may be electrically connected to the register 206 .

[0103] Through the electrical connection between the fault reporting module 208 and the register 206, the fault reporting module 208 can obtain the fault reporting configuration information stored in the register 206. If the fault reporting configuration information indicates that the fault does not need to be shielded, the fault reporting attribute determined by the fault reporting module 208 can be used to characterize that the fault needs to be reported. If the fault reporting configuration information indicates that the fault needs to be shielded, the fault reporting attribute determined by the fault reporting module 208 can be used to characterize that the fault does not need to be reported.

[0104] If the fault reporting attribute is used to characterize the need to report a fault, the fault reporting module 208 can obtain the fault monitoring result. For example, the fault monitoring module 202 can store the fault monitoring result in the register 206, and the fault reporting module 208 can obtain the fault monitoring result stored in the register 206. In addition, the fault reporting module 208 can also obtain the fault type. For example, the glitch-free clock switching unit 2042 can store the first determination result in the above text in the register 206, and the clock lock switching unit 2044 can store the second determination result in the above text in the register 206, and the fault reporting module 208 can obtain the first determination result and the second determination result stored in the register 206, and determine the fault type based on the first determination result and the second determination result. Based on the acquired fault monitoring result and / or fault type, the fault reporting module 208 can determine the fault information to be reported. The fault information to be reported may include the fault monitoring result and / or the fault type. The fault reporting module 208 can report the fault information.

[0105] If the fault reporting attribute is used to indicate that the fault does not need to be reported, the fault reporting module 208 may only record the fault monitoring result and the fault type without reporting the fault information.

[0106] In an example, Figure 7 As shown, there may be two clock protection circuits 20 in the clock protection architecture, wherein each clock protection circuit 20 may be electrically connected to a plurality of functional modules 80. The fault reporting configuration information may be directed to Figure 7 The clock protection circuit 20 on the left side indicates a shielding fault and Figure 7 The clock protection circuit 20 on the right side indicates that the fault is not masked. Then, if Figure 7 The clock monitoring module 202 in the clock protection circuit 20 on the left side detects that the functional clock signal has a fault. Figure 7 The fault reporting module 208 in the clock protection circuit 20 on the left side may not report the fault information. Figure 7 The clock monitoring module 202 in the clock protection circuit 20 on the right side detects that the functional clock signal has a fault. Figure 7 The fault reporting module 208 in the clock protection circuit 20 on the right side can report fault information, for example, Figure 7 The fault reporting module 208 in the clock protection circuit 20 on the right side can send fault information to the fault collection and processing module 90. The fault collection and processing module 90 can collect and classify the fault information, and then report it to the central processing unit (CPU) so that the upper layer application can perceive the fault information.

[0107] In the embodiments of the present disclosure, whether to report fault information can be flexibly controlled through information configuration, which can facilitate upper-layer applications to perceive fault information on the one hand, and avoid resource consumption and power consumption caused by unnecessary information reporting on the other hand.

[0108] In some optional examples, such as Figure 6 As shown, the clock protection circuit 20 may further include:

[0109] Register 206, used to store signal frequency division configuration information;

[0110] The clock processing module 204 is used to determine the safe clock signal for transmission to the functional module 80 based on the target clock signal, including:

[0111] The clock processing module 204 is used to determine the frequency requirement information corresponding to each of the multiple functional modules 80 in response to determining the functional clock signal as the target clock signal, based on the signal frequency division configuration information, and to perform frequency division processing on the functional clock signal based on the frequency requirement information corresponding to each of the multiple functional modules 80 to obtain the safe clock signals corresponding to each of the multiple functional modules 80.

[0112] It should be noted that the specific implementation of this embodiment can refer to the above description of the case where the target clock signal includes a functional clock signal and a backup clock signal, and the frequency requirement information is determined based on the signal division configuration information stored in register 206, and the related introduction of further frequency division processing is not repeated here.

[0113] In the case where the functional clock signal is determined as the target clock signal, the signal frequency division configuration information stored in the reference register 206 is used for frequency division processing. Through a set of safety protection circuits, the safety clock signals corresponding to the multiple functional modules 80 can be obtained to meet the working requirements of different functional modules 80.

[0114] In summary, by adopting the embodiments of the present disclosure and setting up two types of clock sources, when a functional clock signal fails, it is possible to quickly switch to using the backup clock source 60, which is beneficial to ensuring the reliability of the clock signal used by the functional module 80, effectively reducing the adverse effects of clock failures, and ensuring the normal operation of the chip.

[0115] Exemplary Methods

[0116] Figure 8 It is a structural diagram of a clock protection method provided by some exemplary embodiments of the present disclosure. Figure 8 The method shown may include step 810 , step 820 , and step 830 .

[0117] Step 810: Based on the backup clock signal generated by the backup clock source, perform fault monitoring on the functional clock signal generated by the functional clock source to obtain a fault monitoring result.

[0118] Step 820: Determine a target clock signal from the backup clock signal and the functional clock signal based on the fault monitoring result.

[0119] Step 830 , based on the target clock signal, determine a secure clock signal for transmission to the functional module.

[0120] In the embodiments of the present disclosure, regardless of whether there is an abnormality in the functional clock signal, a clock signal (i.e., a safe clock signal) required for its operation and free of faults can be provided to the functional module. This is conducive to ensuring the reliability of the clock signal used by the functional module, thereby ensuring the normal and reliable operation of the functional module and the normal operation of the chip where the functional module is located.

[0121] In some optional examples, such as Fig. 9 As shown, step 810 may include step 910 , step 920 , step 930 , step 940 , step 950 and step 960 .

[0122] Step 910: Determine a second numerical relationship between the frequency of the backup clock signal and the frequency of the functional clock signal.

[0123] Optionally, the functional clock source can be used to generate a functional clock signal with a first frequency, and the backup clock source can be used to generate a backup clock signal with a second frequency. That is, the frequency of the functional clock signal generated by the functional clock source is theoretically the first frequency, and the frequency of the backup clock signal generated by the backup clock source is theoretically the second frequency. In step 910, the proportional relationship between the first frequency and the second frequency can be determined, and the determined proportional relationship can be used as the second numerical relationship.

[0124] Step 920, determining a first number of times that a rising edge of the backup clock signal occurs within a target time period.

[0125] Optionally, the duration of the target time period can be set according to actual conditions. As an example, the duration of the target time period can be 1 second, 2 seconds, 3 seconds, etc., which are not listed here one by one.

[0126] In step 920, the waveform of the backup clock signal may be detected to count the total number of rising edges of the backup clock signal within the target time period, and the total number may be used as the first count.

[0127] Step 930, determining a second number of times that a rising edge of the functional clock signal occurs within a target time period.

[0128] In step 930, the waveform of the functional clock signal may be detected to count the total number of rising edges of the functional clock signal within the target time period, and the total number may be used as the second count.

[0129] Step 940, determining a third numerical relationship between the first number and the second number.

[0130] In step 940, a proportional relationship between the first number and the second number may be determined, and the determined proportional relationship may be used as the third numerical relationship.

[0131] Step 950: Determine the matching degree between the second numerical relationship and the third numerical relationship.

[0132] Optionally, the second numerical relationship may be a first ratio of the first frequency to the second frequency, and the third numerical relationship may be a second ratio of the first frequency to the second frequency. If the first ratio and the second ratio are the same or substantially the same, it may be determined that the matching degree between the second numerical relationship and the third numerical relationship is 1. If the first ratio and the second ratio differ greatly, it may be determined that the matching degree between the second numerical relationship and the third numerical relationship is 0.

[0133] Step 960: Determine the fault monitoring result based on the matching degree.

[0134] Optionally, if the matching degree is 1, the fault monitoring result can be used to indicate that the functional clock signal does not have a fault. If the matching degree is 0, the fault monitoring result can be used to indicate that the functional clock signal has a fault.

[0135] It should be noted that, when a certain proportional relationship is satisfied between the frequency of the backup clock signal and the frequency of the functional clock signal, if the functional clock signal does not have a fault, theoretically, the number of times the backup clock signal has a rising edge in the target time period and the number of times the functional clock signal has a rising edge in the target time period should also satisfy a corresponding proportional relationship. In view of this, the second numerical relationship and the third numerical relationship can be determined, and the matching degree between the second numerical relationship and the third numerical relationship can be further determined. Based on the determined matching degree, it can be determined whether the actual situation is consistent with the theoretical situation when the functional clock signal does not have a fault, thereby efficiently and reliably inferring that the functional clock signal has a fault to obtain a fault monitoring result.

[0136] In some optional examples, step 820 may include:

[0137] In response to the fault monitoring result being used to characterize that a fault exists in the functional clock signal, a target clock signal including a backup clock signal and the functional clock signal is determined.

[0138] In some optional examples, step 820 may include:

[0139] In response to the fault monitoring result being used to indicate that the functional clock signal does not have a fault, the functional clock signal is determined as the target clock signal.

[0140] In some optional examples, such as Fig.10 As shown, step 830 may include step 1010 and step 1020.

[0141] Step 1010 , in response to determining the functional clock signal as the target clock signal, determining frequency requirement information corresponding to each of the plurality of functional modules based on the signal frequency division configuration information stored in the register.

[0142] Step 1020: Based on the frequency requirement information corresponding to each of the multiple functional modules, the functional clock signal is frequency-divided to obtain the safety clock signals corresponding to each of the multiple functional modules.

[0143] In some optional examples, such as Fig.11As shown, the register can be configured first. For example, fault reporting configuration information, signal frequency division configuration information, etc. can be stored in the register 206 mentioned above. Next, it can be determined whether the functional clock signal has a fault. For example, it can be determined whether the functional clock signal has a fault based on whether the second interaction unit 2024 and the first interaction unit 2022 mentioned above can shake hands normally. If the functional clock signal has a fault, it can be switched to the backup clock signal. For example, based on the backup clock signal output by the target switching unit mentioned above, a safe clock signal for transmission to the functional module 80 can be determined. In addition, it can be determined whether the clock fault needs to be reported based on the fault reporting configuration information. If the clock fault needs to be reported, the fault information can be reported to the error collection and processing module. If the clock fault does not need to be reported, the fault information may not be reported to the error collection and processing module.

[0144] In the method disclosed in the present invention, various optional embodiments, optional implementation methods and optional examples disclosed in the above exemplary circuit part can be flexibly selected and combined as needed to achieve corresponding functions and effects, and the present invention does not list them one by one.

[0145] Exemplary Electronic Devices

[0146] Fig.12 The block diagram of an electronic device according to an embodiment of the present disclosure is illustrated. The electronic device 1200 includes one or more processors 1210 and a memory 1220 .

[0147] The processor 1210 may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 1200 to perform desired functions.

[0148] The memory 1220 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 1210 may execute one or more computer program instructions to implement the methods of the various embodiments of the present disclosure described above and / or other desired functions.

[0149] In one example, the electronic device 1200 may further include: an input device 1230 and an output device 1240 , and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0150] The input device 1230 may also include, for example, a keyboard, a mouse, etc.

[0151] The output device 1240 can output various information to the outside, and may include, for example, a display, a speaker, a printer, a communication network and its connected remote output device, etc.

[0152] Of course, to simplify, Fig.12 Only some of the components related to the present disclosure in the electronic device 1200 are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application situations, the electronic device 1200 may also include any other appropriate components.

[0153] Exemplary computer program products and computer-readable storage media

[0154] In addition to the above-mentioned methods and devices, an embodiment of the present disclosure may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the method according to various embodiments of the present disclosure described in the above-mentioned "Exemplary Method" section of this specification.

[0155] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0156] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, enables the processor to execute the steps of the method according to various embodiments of the present disclosure described in the above “Exemplary Method” section of this specification.

[0157] The computer readable storage medium can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can include, for example, but is not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0158] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations. It cannot be considered that these advantages, strengths, effects, etc. must be possessed by each embodiment of the present disclosure. The specific details disclosed above are only for the purpose of illustration and ease of understanding, not limitation. The above details do not limit the present disclosure to being implemented by adopting the above specific details.

[0159] Those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the present disclosure claims and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A clock protection circuit, comprising: A clock monitoring module, configured to perform fault monitoring on a functional clock signal generated by a functional clock source based on a backup clock signal generated by a backup clock source, obtain a fault monitoring result, and determine a target clock signal from the backup clock signal and the functional clock signal based on the fault monitoring result; The clock processing module is used to determine a safe clock signal for transmission to a functional module based on the target clock signal.

2. The clock protection circuit according to claim 1, wherein: The clock monitoring module includes: a first interaction unit, a second interaction unit and a first determination unit; The clock monitoring module is used to perform fault monitoring on the functional clock signal generated by the functional clock source based on the backup clock signal generated by the backup clock source to obtain a fault monitoring result, including: The first interaction unit is used to generate a handshake request in response to a rising edge of the backup clock signal; The second interaction unit is configured to generate a response to the handshake request driven by the functional clock signal in response to receiving the handshake request; The first determination unit is used to count the number of times the second interaction unit fails to generate the response within a preset time period after receiving the handshake request, determine a first numerical relationship between the counted number of times and the preset number of times, and determine the fault monitoring result based on the first numerical relationship.

3. The clock protection circuit according to claim 1, wherein: The clock monitoring module is used to determine a target clock signal from the backup clock signal and the functional clock signal based on the fault monitoring result, including: The clock monitoring module is used to determine the target clock signal including the backup clock signal and the functional clock signal in response to the fault monitoring result used to characterize that the functional clock signal has a fault; or, The clock monitoring module is used to determine the functional clock signal as the target clock signal in response to the fault monitoring result being used to characterize that the functional clock signal does not have a fault.

4. The clock protection circuit according to any one of claims 1 to 3, wherein: The clock processing module includes: a glitch-free clock switching unit, a clock lock switching unit, and a second determination unit; The clock processing module is used to determine a safe clock signal for transmission to a functional module based on the target clock signal, including: The glitch-free clock switching unit is configured to output the backup clock signal in response to receiving the target clock signal including the backup clock signal and the functional clock signal; The clock lock switching unit is used to output the backup clock signal in response to receiving the target clock signal including the backup clock signal and the functional clock signal; The second determining unit is used to determine the safe clock signal based on the backup clock signal output by one of the glitch-free clock switching unit and the clock deadlock switching unit.

5. The clock protection circuit according to claim 4, wherein: The second determining unit is used to determine the safe clock signal based on the backup clock signal output by one of the glitch-free clock switching unit and the clock lock switching unit, including: The second determination unit is used to obtain the fault type of the functional clock signal, determine the target switching unit adapted to the fault type from the glitch-free clock switching unit and the clock lock switching unit, and determine the safe clock signal based on the backup clock signal output by the target switching unit.

6. The clock protection circuit according to claim 5, further comprising: Register, used to store fault reporting configuration information; The fault reporting module is used to determine the fault reporting attribute based on the fault reporting configuration information, determine the fault information to be reported based on the fault monitoring result and / or the fault type in response to the fault reporting attribute indicating that the fault needs to be reported, and report the fault information.

7. The clock protection circuit according to claim 4, further comprising: Register, used to store signal frequency division configuration information; The second determining unit is used to generate the safe clock signal based on the backup clock signal output by one of the glitch-free clock switching unit and the clock lock switching unit, including: The second determination unit is used to determine the frequency requirement information corresponding to each of the multiple functional modules based on the signal frequency division configuration information, and to perform frequency division processing on the backup clock signal output by one of the glitch-free clock switching unit and the clock lock switching unit based on the frequency requirement information corresponding to each of the multiple functional modules, so as to obtain the safe clock signal corresponding to each of the multiple functional modules.

8. The clock protection circuit according to any one of claims 1 to 3, wherein: The clock protection circuit also includes: Register, used to store signal frequency division configuration information; The clock processing module is used to determine a safe clock signal for transmission to a functional module based on the target clock signal, including: The clock processing module is used to determine the functional clock signal as the target clock signal, determine the frequency requirement information corresponding to each of the multiple functional modules based on the signal frequency division configuration information, and perform frequency division processing on the functional clock signal based on the frequency requirement information corresponding to each of the multiple functional modules to obtain the safe clock signals corresponding to each of the multiple functional modules.

9. A clock protection method, comprising: Based on the backup clock signal generated by the backup clock source, a fault monitoring is performed on the functional clock signal generated by the functional clock source to obtain a fault monitoring result; Based on the fault monitoring result, determining a target clock signal from the backup clock signal and the functional clock signal; Based on the target clock signal, a secure clock signal is determined for transmission to the functional module.

10. The clock protection method according to claim 9, wherein: The performing fault monitoring on the functional clock signal generated by the functional clock source based on the backup clock signal generated by the backup clock source to obtain the fault monitoring result includes: determining a second numerical relationship between the frequency of the backup clock signal and the frequency of the functional clock signal; Determine a first number of times that a rising edge of the backup clock signal occurs within a target time period; Determine a second number of times that a rising edge of the functional clock signal occurs within the target time period; determining a third numerical relationship between the first number and the second number; Determining a degree of match between the second numerical relationship and the third numerical relationship; Based on the matching degree, the fault monitoring result is determined.

11. A computer-readable storage medium storing a computer program, wherein the computer program is used to execute the clock protection method according to claim 9 or 10.

12. An electronic device, comprising: processor; a memory for storing instructions executable by the processor; The processor is used to read the executable instructions from the memory and execute the instructions to implement the clock protection method described in claim 9 or 10.

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