CRC error automatic injection verification system and method based on UVM

Abstract

The invention provides a UVM-based CRC error automatic injection verification system and method. The system comprises a test layer, and the test layer comprises a to-be-tested component DUT and an environment layer which are in communication connection; the environment layer comprises a reference model, an input agent component, an error injection component, an output agent component and a scoreboard; the UVM verification system is used for verifying the to-be-tested component DUT with the CRC verification function, the error injection component is used for injecting error data, the situation that different data errors occur in the actual use environment is simulated, the verification coverage rate is increased, and the accuracy of the error injection position and type is ensured. The main data flow of the verification environment only needs to be fully verified by means of daily regression and the like, so that more boundary conditions are found, and the verification completeness is ensured. Meanwhile, the development time of other verification engineers can be saved, and the verification cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of data verification, and in particular to a UVM-based CRC error automatic injection verification system and method. Background Art

[0002] In an integrated circuit, the physical circuit of the chip consists of a transmission medium and a communication device. When a data signal passes through the physical circuit from the transmitter, due to the presence of noise in the physical circuit, when the data signal is transmitted to the receiver through the physical circuit, the received signal must be a superposition of the data and noise signal levels, such as Figure 1 As shown. At the receiving end, the receiving circuit judges the superimposed signal during sampling to determine the 0 or 1 value of the data.

[0003] In order to reduce transmission errors in physical lines, it is important to study methods for detecting and correcting bit stream transmission errors, that is, error control. At present, the error control method is to use error detection codes. Among them, the most commonly used error detection method in the data link layer is the Cyclic Redundancy Check (CRC). CRC is a technology that generates a fixed-length check value by performing specific mathematical operations on data. During data transmission or storage, the sender calculates the CRC value and appends it to the data. After receiving the data, the receiver recalculates the CRC value and compares it with the received CRC value. If the two CRC values ​​are equal, it means that there is no error in the data transmission or storage process; otherwise, it means that the data has an error. The basic principle of the CRC algorithm is to use polynomial division, regard the original data as a binary polynomial, select a specific generating polynomial, and then divide the original data polynomial by the generating polynomial. The remainder is the CRC check code. At the receiving end, the same generating polynomial is used to divide the received data (including the check code). If the remainder is zero, it means that the data is correct. CRC can detect various types of errors, including single-bit errors, multi-bit errors, and burst errors. It can be implemented through hardware or software and has a fast calculation speed.

[0004] In the prior art, in order to verify the system's ability to handle CRC errors, Force (a syntax supported by SystemVerilog) is often used to force data modification to generate error stimulus, thereby simulating the situation where data errors occur in the actual use environment. Specifically, in the verification environment, the CRC value in the data is directly modified by using the Force statement to make it different from the correct CRC value, thereby simulating the occurrence of CRC errors. However, the method of using Force to force modification of the CRC field segment has the following defects: (1) The method of using Force to modify the CRC field is a man-made error injection method that lacks authenticity and randomness. In actual digital systems, CRC errors are usually caused by various random factors, such as noise interference, hardware failure, etc. The Force modification method cannot simulate these random factors, resulting in a large gap between the verification results and the actual situation.

[0005] (2) The method of using Force to modify the CRC field segment is usually carried out for specific data formats and transmission protocols, and has poor scalability. When the data format or transmission protocol of the digital system changes, the Force statement needs to be rewritten to inject errors, which increases the workload and difficulty of verification. Summary of the invention

[0006] The present invention aims to provide a UVM-based CRC error automatic injection verification system and method, which effectively solves the technical problems of poor scalability and lack of authenticity and randomness in the error excitation mode of the prior art.

[0007] In order to solve the above technical problems, the present invention provides a UVM-based CRC error automatic injection verification system, comprising a test layer, the test layer comprising a component under test DUT and an environment layer connected to the component under test DUT in communication; the environment layer comprises a reference model, an input proxy component, an error injection component, an output proxy component and a scoreboard; wherein, The input agent component includes a sequencer and a driver; the sequencer is used to start the sequence, obtain input data from the sequence and send the input data to the driver; the driver is used to input the input data to the component under test DUT; The reference model is used to process the input data sent by the input agent component and send the expected data to the scoreboard; The error injection component is used to insert error data when the input data is input into the component under test DUT; The component under test (DUT) is used to perform error detection and CRC check on the inserted error data and mark the erroneous data; The output agent component is used to monitor the component under test (DUT) to obtain output data and send the output data to the scoreboard; The scoreboard is used to compare the expected data with the output data and output the comparison results; Among them, the UVM-based CRC error automatic injection verification process specifically includes: Step 1: Obtain various different stimuli for verifying the component under test (DUT) as input data through a sequence generator; Step 2: Input the stimulus to the reference model and the component under test DUT respectively, insert errors into the transaction package set input to the component under test DUT through the error injection component, simulate the situation where data errors occur in the real use environment, and verify whether the CRC check function of the component under test DUT is correct; specifically including: During the CRC check of the stimulus by the component under test DUT, the component under test DUT marks the transaction packet with error data. When the CRC check function is normal, the CRC check function cannot correct the error, and the output data of the component under test DUT after the processing is completed includes the transaction packet with error data and the mark; The scoreboard compares the output data of the reference model and the component under test DUT. It only compares the unmarked transaction packages output by the component under test DUT and the transaction package set output by the reference model. If the comparison result passes, it means that the CRC check function is correct and the marking logic of the component under test DUT is correct.

[0008] Preferably, the error injection component is also used to collect the number of error data and / or the inserted position when the input data is input into the component under test DUT.

[0009] Preferably, the output proxy component includes a first listener, which filters out output data with error marks through the callback module of the first listener, and outputs unmarked data to a scoreboard; the scoreboard is used to compare expected data with unmarked data and output the comparison result.

[0010] Preferably, the input proxy component also includes a second listener, the input end of the second listener is communicatively connected to the component under test DUT, and receives a response data packet returned by the component under test DUT; the output end of the second listener is communicatively connected to the reference model, and sends the response data packet to the reference model, so that the reference model performs simulation operation according to the response data packet and generates expected data.

[0011] Preferably, the test layer also includes a first interface component and a second interface component; the first listener is communicatively connected to the component under test DUT through the first interface component; the second listener is communicatively connected to the component under test DUT through the second interface component and receives the output signal of the component under test DUT.

[0012] In a second aspect, the present invention provides a UVM-based CRC error automatic injection verification method, which is applied to the UVM-based CRC error automatic injection verification system of the first aspect, comprising the following steps: Use the sequence generator to start the sequence and obtain input data from the sequence; receiving input data through a driver and inputting the input data to a component under test DUT; The second listener of the input proxy component receives the response data packet returned by the component under test DUT, and sends the response data packet to the reference model, processes the response data packet using the reference model to obtain expected data, and sends the expected data to the scoreboard through the reference model; Insert error data into input data by using the error injection component, perform error detection and CRC check on the inserted error data through the component under test DUT, mark the data with error, output the marked and unmarked data as output data, and send the output data to the output proxy component; Send output data to the scoreboard through the output proxy component; Use the scoreboard to compare the expected data and output data, and output the comparison results.

[0013] Preferably, the method further comprises the following steps: The output data output by the component under test (DUT) is monitored and received, and the data with error marks in the output data is filtered out by using the callback module of the first monitor.

[0014] Preferably, when the comparison result passes, it is determined that the process of performing error detection and CRC verification on inserted erroneous data through the component under test DUT and marking the erroneous data is correct; when the comparison result fails, it is determined that the process of performing error detection and CRC verification on inserted erroneous data through the component under test DUT and marking the erroneous data is wrong.

[0015] Preferably, the step of receiving the input data through a driver and inputting the input data into the component under test DUT specifically includes: the driver receives transaction-level stimulus data sent from a sequence generator, and converts the transaction-level stimulus into an interface-level or signal-level stimulus that can be recognized by the component under test DUT, and inputs the interface-level or signal-level stimulus into the component under test DUT.

[0016] Preferably, the output data is sent to the scoreboard through the output proxy component, specifically including: after the first listener of the output proxy component monitors the component under test DUT to obtain the data processing result, the interface-level or signal-level output of the component under test DUT is converted into transaction-level data that is easy for the verification engineer to understand, and a callback mechanism is introduced to filter the transaction packets with error marks output by the component under test DUT, only the transaction packets without marks are sent to the scoreboard, and the filtered transaction packets with marks are counted and checked.

[0017] In a third aspect, the present invention provides a computer device comprising a processor, an input device, an output device and a memory, wherein the processor, the input device, the output device and the memory are interconnected, wherein the memory is used to store a computer program, the computer program comprises program instructions, and the processor is configured to call the program instructions to execute the steps of the UVM-based CRC error automatic injection verification method of the second aspect.

[0018] In a fourth aspect, the present invention further provides a computer-readable storage medium, comprising: an executable computer program, which, when executed by an executor, is used to implement the steps of the UVM-based CRC error automatic injection verification method of the second aspect.

[0019] Compared with the prior art, the technical solution provided by the present invention has the following advantages: By using the UVM verification system to verify the DUT component with CRC check function, the error data is injected through the error injection component to simulate the situation of different data errors in the actual use environment, improve the coverage of verification, and ensure the accuracy of the error injection position and type. The DUT component to be tested can mark the transaction package with inserted error data, and can only compare the unmarked transaction package. While verifying whether the CRC check logic is correct based on the comparison results, the marking logic of the DUT component to be tested can also be verified. The main data flow of the verification environment only needs some simple transformation and configuration, and can be fully verified through daily regression and other means, so as to discover more boundary conditions and ensure the completeness of the verification. At the same time, it can also save the development time of other verification engineers and reduce verification costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the prior art and the embodiments of the present application, the drawings required for use in the description of the prior art and the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 Schematic diagram of data signal transmission process.

[0022] Figure 2 A schematic diagram of the structure of a UVM-based CRC error automatic injection verification system provided in an embodiment of the present application.

[0023] Figure 3 A schematic flow chart of a UVM-based CRC error automatic injection verification method provided in an embodiment of the present application.

[0024] Figure 4 A schematic diagram of the structure of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to better understand the purpose, structure and function of the present invention, a kind of CRC error automation injection verification system and method based on UVM provided by the present invention are described in further detail below in conjunction with the accompanying drawings, so that those skilled in the art can better understand the present invention and can implement it, but the embodiments are not intended to limit the present invention.

[0026] UVM (Universal Verification Methodology) is a methodology and library for functional verification. It provides a standardized verification framework for building an efficient and reusable verification environment.

[0027] See also Figure 2 As shown, in an embodiment of the present application, a UVM-based CRC error automatic injection verification system is provided, including a test layer, the test layer includes a device under test (DUT) and an environment layer that is communicatively connected to the device under test (DUT); the environment layer includes a reference model (reference), an input agent component (agent input), an error injection component (error inject), an output agent component (agent out) and a scoreboard (scoreboard); wherein the input agent component (agent The input component includes a sequencer and a driver; the sequencer is used to start the sequence, obtain input data from the sequence and send the input data to the driver; the driver is used to input the input data to the component under test DUT; the reference model is used to process the input data sent by the input agent and send the expected data to the scoreboard; the error injection component is used to insert error data when the input data is input into the component under test DUT; the component under test DUT is used to perform error detection and CRC check on the inserted error data, and mark the erroneous data; the output agent component is used to monitor the component under test DUT to obtain output data, and send the output data to the scoreboard; the scoreboard is used to compare the expected data and the output data, and output the comparison result.

[0028] In the embodiment of the present application, the component DUT to be tested with the CRC check function is verified by utilizing the verification system of UVM, and the error data is injected by the error injection component (error inject), for example, different types of errors such as single-bit errors, multi-bit errors, and burst errors can be injected, and the position of the error data injection can be randomly selected or selected according to specific rules, simulating the situation of different data errors in the actual use environment, improving the coverage of verification, and ensuring that the error injection position and type are accurate. The component DUT to be tested can mark the transaction package into which the error data is inserted, and can only compare the unmarked transaction package. While verifying whether the CRC check logic is correct according to the comparison result, the marking logic of the component DUT to be tested can also be verified. The main data flow of the verification environment only needs to make some simple modifications and configurations, and can be fully verified by means such as daily regression, so as to find more boundary conditions and ensure the completeness of the verification. At the same time, it can also save the development time of other verification engineers and reduce the verification cost.

[0029] Specifically, in the process of verifying the component under test DUT with CRC check function by using UVM verification system, firstly, various different stimuli (i.e., input data) used to verify the component under test DUT can be obtained through sequencer; then, the stimuli are respectively input into reference model (reference) and component under test DUT. In order to verify whether the CRC check function of component under test DUT is correct, error can be inserted into the transaction packet set input into component under test DUT through error injection component (error inject), so as to simulate the situation that data error occurs in the real use environment. During the CRC check of the stimulus by the component under test DUT, the component under test DUT can mark the transaction packets with erroneous data, that is, when the CRC check function is normal, the CRC check function cannot correct the error, then the output data of the component under test DUT after the processing is completed will include the transaction packets with erroneous data (and the transaction packets are marked); when the scoreboard (scoreboar) compares the output data of the reference model (reference) and the component under test DUT, it can only compare the transaction packets without marks (that is, the transaction packets without erroneous data) output by the component under test DUT and the transaction packet set output by the reference model (reference). If the comparison result passes, it means that the CRC check function is correct and the marking logic of the component under test DUT is also correct.

[0030] Furthermore, the UVM verification system can configure various parameters in the verification environment through the environment configuration (env cfg), such as setting the number of instantiations of different components, and according to the verification requirements, determine how many specific types of input agent components (agent input), output agent components (agent out), monitors and other components are created in the environment, configure the generation method of the stimulus, determine the degree of randomness of the stimulus, the data range, etc., to meet the requirements of different test scenarios for the stimulus. Specifically, the input agent component (agent input) is connected to the reference model (reference) and the component under test DUT for communication, and is used to generate stimulus (i.e., input data) and input stimulus to the reference model (reference) and the component under test DUT; the driver (driver) can be used to forward the data sent by the sequencer (sequencer) to the component under test DUT, and convert the transaction-level stimulus into an interface-level or signal-level stimulus that the component under test DUT can recognize, and the monitor (monitor) can convert the interface-level or signal-level output of the component under test DUT into transaction-level data.

[0031] The reference model (reference) is connected to the input agent component (agent input) and the scoreboard (scoreboard) for processing the input data sent by the input agent component (agent input), generating expected data and sending the expected data to the scoreboard (scoreboar), providing data basis for the scoreboard (scoreboard) to perform data comparison.

[0032] The scoreboard is connected to the reference model (reference) and the output agent component (agent out) for receiving the expected data sent by the reference model (reference) and the output data obtained by the output agent component (agent out) monitoring the component under test DUT, and comparing the two. Finally, the comparison result can be output so that the verification engineer can analyze the accuracy and completeness of the function and logic of the component under test DUT based on the comparison result. In an embodiment of the present application, when a CRC check error occurs in the component under test DUT, the first listener can filter out the marked transaction packets output by the component under test DUT, and send the unmarked transaction packets to the scoreboard, and the scoreboard can compare only the unmarked transaction packets with the expected data output by the reference model (reference). When the unmarked transaction package output by the component under test DUT is consistent with part of the expected data output by the reference model (reference), the comparison result is passed, indicating that the CRC check and marking process of the component under test DUT is correct; when the unmarked transaction package output by the component under test DUT is inconsistent with part of the expected data output by the reference model (reference), the comparison result fails, indicating that the unmarked transaction package output by the component under test DUT contains erroneous data, and the marking process of the component under test DUT is wrong, failing to completely mark the transaction package with erroneous data, or marking the transaction package without erroneous data but not marking the transaction package with erroneous data. For example, the input data of the component under test DUT in the memory (memory) is a, b, c, and the output data is a, b, c; the expected data output by the reference model (reference) is a, b, c, and the scoreboard (scoreboard) determines whether it passes by comparing the output data with the expected data. If the DUT component under test is implemented correctly, the error injection component (error inject) is used to insert a CRC error into the data a, and the data a is modified to a'. After being processed by the DUT component under test and output from the memory (memory), the logic determines that the CRC does not match, and the a' data is output after being marked with crc_error. The first listener of the output agent component (agent out) discards all the messages with the crc_error mark through the callback (callback) module, and finally only transmits the outputs b and c to the scoreboard (scoreboard). At this time, the scoreboard (scoreboard) allows comparison based on the comparison strategy that the error-marked packets can be discarded, and the number of discards is counted and checked. If the number of discarded transactions is within an acceptable range and the order and content of the remaining transactions meet the requirements, then the verification may pass.Understandably, when the scoreboard needs to compare the expected data output by the reference model (reference) with the output data output by the component under test (DUT), the first listener filters out the marked transaction packages in the output data, namely, transaction package a', and only compares the transaction packages b and c in the output data with the transaction packages a, b, and c in the expected data. Because the transaction packages b and c output by the component under test (DUT) do not contain erroneous data, the comparison result of the scoreboard will pass when compared with the transaction packages b and c output by the reference model (reference).

[0033] The output agent component (agent out) is communicatively connected with the scoreboard and the component under test DUT, and is used to monitor the component under test DUT to obtain data processing results (i.e., the output data of the component under test DUT), and forward the data processing results to the scoreboard. The output agent component (agent out) may include a first listener and other units. After the first listener monitors the component under test DUT to obtain the data processing results, it may convert the interface-level or signal-level output of the component under test DUT into transaction-level data that is easy for verification engineers to understand, and finally send the transaction-level data to the scoreboard.

[0034] The error injection component (error inject) can be connected to the component under test DUT in communication, and is used to perform error processing (such as inserting CRC error data) on the stimulus input by the input agent component (agent input), so as to simulate the situation of data errors in the actual use environment, and in addition, the specific location of the error and the number of the error can be collected. In the embodiment of the present application, the error injection component (error inject) can perform error insertion on any one or several memories (memory) in the component under test DUT, and can perform error insertion when data is written to the memory or when data is read from the memory. The specific error insertion configuration in the data is random, and can be performed on the valid data bit or the check data bit.

[0035] Preferably, the error injection component (error inject) is also used to collect the number of error data and / or the inserted position when the input data is input into the component under test DUT. By collecting the information of the error data, it can be determined whether the component under test DUT can correctly detect and correct the error when facing the error, thereby ensuring the integrity and reliability of the data. At the same time, it is conducive to adjusting the error injection strategy. If it is found that the error at certain positions has little impact on the component under test DUT, the error injection at these positions can be reduced, thereby improving the verification efficiency. On the contrary, if the error at certain positions has a greater impact on the system performance, the error injection at these positions can be increased to more comprehensively test the stability of the system.

[0036] Preferably, the output agent component (agent out) includes a first listener, and the callback module of the first listener filters out the output data with error marks, and outputs the unmarked data to the scoreboard; the scoreboard is used to compare the expected data with the unmarked data, and output the comparison result. By introducing a callback mechanism (i.e., callback module) to the first listener, the first listener can filter the transaction packets with error marks output by the component under test DUT through a callback, and only send the transaction packets without marks to the scoreboard (Scoreboard).

[0037] Preferably, the input agent component (agent input) further includes a second listener, the input end of the second listener is connected to the component under test DUT in communication, and receives the response data packet returned by the component under test DUT; the output end of the second listener is connected to the reference model (reference) in communication, and sends the response data packet to the reference model (reference), so that the reference model (reference) performs simulation operation according to the response data packet and generates expected data. The second listener can receive the response data packet returned by the component under test DUT in real time, which ensures that the response data packet returned from the component under test DUT can be accurately captured, providing accurate original data for subsequent reference model (reference) processing and analysis.

[0038] Preferably, the test layer further includes a first interface component and a second interface component; the first listener is connected to the component under test DUT through the first interface component; the second listener is connected to the component under test DUT through the second interface component and receives the output signal of the component under test DUT. The first interface component and the second interface component can support multiple interface standards, so that the input agent component (agent input) and the output agent component (agent out) can adapt to different types of components under test DUT, thereby improving the scalability of verification.

[0039] See also Figure 3 As shown, a UVM-based CRC error automatic injection verification method is provided in an embodiment of the present application, which is applied to the above-mentioned UVM-based CRC error automatic injection verification system, comprising the following steps: Step S1: Start a sequence using a sequencer and obtain input data from the sequence.

[0040] In the process of verifying the component under test (DUT) by using the UVM verification system, firstly, the stimulus data for verifying the function and logic of the component under test (DUT) is obtained through a sequencer, that is, the input data corresponding to the component under test (DUT).

[0041] Step S2: receiving input data through a driver, and inputting the input data to the component under test DUT.

[0042] The driver receives transaction-level stimulus data from the sequencer, converts the transaction-level stimulus into an interface-level or signal-level stimulus that can be recognized by the DUT, and inputs the interface-level or signal-level stimulus to the DUT.

[0043] Step S3, the second listener of the input agent component (agent input) receives the response data packet returned by the component under test DUT, and sends the response data packet to the reference model (reference), processes the response data packet using the reference model (reference), obtains expected data, and sends the expected data to the scoreboard through the reference model (reference).

[0044] Specifically, the response data packet returned by the component under test DUT is received in real time through the second listener of the input agent component (agent input), ensuring that the response data packet returned from the component under test DUT can be accurately captured, providing accurate original data for subsequent reference model (reference) processing and analysis.

[0045] Step S4, using the error injection component (error inject) to insert error data into the input data, and performing error detection and CRC check on the inserted error data through the component under test DUT, marking the erroneous data, outputting the marked and unmarked data as output data, and sending the output data to the output agent component (agent out).

[0046] Specifically, error data is injected through an error injection component (error inject), for example, different types of errors such as single-bit errors, multi-bit errors, and burst errors can be injected. The location of the error data injection can be randomly selected or selected according to specific rules to simulate the occurrence of different data errors in the actual use environment, improve the verification coverage, and ensure that the error injection location and type are accurate. The component under test DUT marks the transaction packet with error data. When the CRC check function is normal, the CRC check function cannot correct the error. Then, the output data of the component under test DUT after processing is completed will include a transaction packet with error data (and the transaction packet is marked); when the scoreboard (scoreboar) compares the output data of the reference model (reference) and the component under test DUT, it can only compare the unmarked transaction packets (i.e., transaction packets without error data) output by the component under test DUT and the transaction packet set output by the reference model (reference). If the comparison result passes, it means that the CRC check function is correct and the marking logic of the component under test DUT is also correct. Step S5: Send the output data to a scoreboard through an output agent component (agent out).

[0047] Specifically, after the first listener of the output agent component (agent out) monitors the component under test DUT to obtain the data processing result, it converts the interface-level or signal-level output of the component under test DUT into transaction-level data that is easy for the verification engineer to understand, and introduces a callback mechanism to filter the transaction packets with error marks output by the component under test DUT, and only send the transaction packets without marks to the scoreboard, and perform statistics and inspection on the filtered out transaction packets with marks.

[0048] Step S6: Use a scoreboard to compare the expected data with the output data, and output the comparison result.

[0049] Specifically, the scoreboard compares the unmarked transaction packets output by the output agent component (agent out) with the expected data output by the reference model (reference) based on the comparison strategy that the error-marked packets can be discarded. When the unmarked transaction packets output by the component under test DUT and the expected data output by the reference model (reference) are partially consistent, the comparison result is determined to be passed, indicating that the CRC checksum and marking process of the component under test DUT is correct; when the unmarked transaction packets output by the component under test DUT and the expected data output by the reference model (reference) are partially inconsistent, the comparison result is determined to be failed, indicating that the unmarked transaction packets output by the component under test DUT contain error data, and the marking process of the component under test DUT is wrong, and the transaction packets with error data are not completely marked, or the transaction packets without error data are marked, but the transaction packets with error data are not marked.

[0050] In summary, in the embodiment of the present application, the component DUT to be tested with the CRC check function is verified by utilizing the verification system of UVM, and the error data is injected by the error injection component (error inject), and the position of the error data injection can be randomly selected or selected according to specific rules, simulating the situation of different data errors in the actual use environment, improving the coverage of verification, and ensuring that the error injection position and type are accurate. The component DUT to be tested can mark the transaction package into which the error data is inserted, and can only compare the unmarked transaction package. While verifying whether the CRC check logic is correct according to the comparison result, the marking logic of the component DUT to be tested can also be verified. While expanding the scope of verification, it can also reduce the excessive dependence of the verification effect on the ability of the verification engineer, reduce the cost of chip verification, and improve the versatility of the verification scheme.

[0051] like Figure 4 As shown, a computer device 4 is also provided in an embodiment of the present application, including a processor 41, an input device 42, an output device 43 and a memory 44, wherein the processor 41, the input device 42, the output device 43 and the memory 44 are interconnected, wherein the memory 44 is used to store a computer program, the computer program includes program instructions, and the processor 41 is configured to call the program instructions to execute the steps of the above-mentioned UVM-based CRC error automatic injection verification method.

[0052] A computer-readable storage medium is also provided in an embodiment of the present application, including: an executable computer program, which is used to implement the steps of the above-mentioned UVM-based CRC error automatic injection verification method when executed by an executor.

[0053] It is to be understood that the present invention is described by some embodiments, and it is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the scope of protection of the present invention.

Claims

1. A UVM-based CRC error automatic injection verification system, comprising a test layer, characterized in that: The test layer includes a component under test (DUT) and an environment layer that is in communication with the component under test (DUT); the environment layer includes a reference model, an input proxy component, an error injection component, an output proxy component, and a scoreboard; wherein, The input proxy component includes a sequence generator and a driver; the sequence generator is used to start a sequence, obtain input data from the sequence and send the input data to the driver; the driver is used to input the input data to the component under test DUT; The reference model is used to process the input data sent by the input proxy component and send the expected data to the scoreboard; The error injection component is used to insert error data when the input data is input into the component under test DUT; The DUT is used to perform error detection and CRC check on the inserted error data, and mark the erroneous data; The output proxy component is used to monitor the component under test DUT to obtain output data, and send the output data to the scoreboard; The scoreboard is used to compare the expected data with the output data and output a comparison result; Among them, the UVM-based CRC error automatic injection verification process specifically includes: Step 1: Obtain various different stimuli for verifying the component under test (DUT) as input data through a sequence generator; Step 2: Input the stimulus to the reference model and the component under test DUT respectively, insert errors into the transaction package set input to the component under test DUT through the error injection component, simulate the situation where data errors occur in the real use environment, and verify whether the CRC check function of the component under test DUT is correct; specifically including: During the CRC check of the stimulus by the component under test DUT, the component under test DUT marks the transaction packet with error data. When the CRC check function is normal, the CRC check function cannot correct the error, and the output data of the component under test DUT after the processing is completed includes the transaction packet with error data and the mark; The scoreboard compares the output data of the reference model and the component under test DUT. It only compares the unmarked transaction packages output by the component under test DUT and the transaction package set output by the reference model. If the comparison result passes, it means that the CRC check function is correct and the marking logic of the component under test DUT is correct.

2. according to the CRC error automation injection verification system based on UVM described in claim 1, it is characterized in that, The error injection component is also used to collect the number and / or insertion position of the error data when the input data is input into the component under test DUT.

3. according to the CRC error automation injection verification system based on UVM described in claim 1, it is characterized in that, The output proxy component includes a first listener, which filters out the output data with error marks through the callback module of the first listener, and outputs the unmarked data to the scoreboard; the scoreboard is used to compare the expected data with the unmarked data, and output the comparison result.

4. according to the CRC error automation injection verification system based on UVM described in claim 3, it is characterized in that, The input proxy component further includes a second listener, an input end of which is communicatively connected to the component under test DUT and receives a response data packet returned by the component under test DUT; The output end of the second listener is communicatively connected to the reference model, and sends the response data packet to the reference model, so that the reference model performs simulation operation according to the response data packet and generates expected data.

5. according to the CRC error automation injection verification system based on UVM described in claim 4, it is characterized in that, The test layer also includes a first interface component and a second interface component; the first listener is communicatively connected to the component under test DUT through the first interface component; the second listener is communicatively connected to the component under test DUT through the second interface component and receives an output signal of the component under test DUT.

6. A CRC error automation injection verification method based on UVM, applied to a CRC error automation injection verification system based on UVM as described in any one of claims 1 to 5, characterized in that, The steps include: Use the sequence generator to start the sequence and obtain input data from the sequence; Receive the input data through a driver, and input the input data to the component under test DUT; The second listener of the input proxy component receives the response data packet returned by the component under test DUT, and sends the response data packet to the reference model, processes the response data packet using the reference model to obtain expected data, and sends the expected data to the scoreboard through the reference model; Inserting error data into the input data using the error injection component, performing error detection and CRC check on the inserted error data through the component under test DUT, marking the erroneous data, outputting the marked and unmarked data as output data, and sending the output data to the output proxy component; Sending the output data to the scoreboard via an output proxy component; The expected data and the output data are compared using the scoreboard, and a comparison result is output.

7. according to the CRC error automation injection verification method based on UVM described in claim 6, it is characterized in that, The following steps are also included: The output data output by the component under test DUT is monitored and received, and the data with error marks in the output data is filtered out by using a callback module of the first monitor.

8. according to the CRC error automation injection verification method based on UVM described in claim 7, it is characterized in that, When the comparison result passes, it is determined that the process of performing error detection and CRC check on the inserted error data by the component under test DUT and marking the erroneous data is correct; When the comparison result fails, it is determined that the process of performing error detection and CRC check on the inserted error data and marking the erroneous data by the component under test DUT is wrong.

9. according to the CRC error automation injection verification method based on UVM described in claim 8, it is characterized in that, The step of receiving the input data through a driver and inputting the input data into the component under test DUT specifically includes: the driver receives transaction-level stimulus data sent from a sequencer, converts the transaction-level stimulus into an interface-level or signal-level stimulus that can be recognized by the component under test DUT, and inputs the interface-level or signal-level stimulus into the component under test DUT.

10. according to the CRC error automation injection verification method based on UVM described in claim 9, it is characterized in that, The method of sending the output data to the scoreboard through the output proxy component specifically includes: after the first listener of the output proxy component monitors the component under test DUT to obtain the data processing result, the interface-level or signal-level output of the component under test DUT is converted into transaction-level data that is easy for verification engineers to understand, and a callback mechanism is introduced to filter the transaction packets with error marks output by the component under test DUT, only the transaction packets without marks are sent to the scoreboard, and the filtered transaction packets with marks are counted and checked.

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