Off-chip access circuit and method, memory controller, chip and electronic equipment

Abstract

The invention relates to an off-chip access circuit and method, a memory controller, a chip and electronic equipment, and belongs to the field of electronic circuits. The off-chip access circuit based on the SPI bus comprises a first PAD, a second PAD, a clock generation circuit and a data sampling circuit, the first PAD and the second PAD are connected with an off-chip memory through the SPI bus, and the off-chip memory is used for storing firmware; the clock generation circuit is connected with the first PAD, and the clock generation circuit is used for generating a clock signal required by an SPI bus and transmitting the clock signal to the first PAD; the data sampling circuit is connected with the first PAD and the second PAD, the data sampling circuit is used for sampling data transmitted by the second PAD based on a clock signal from the first PAD, and the data transmitted by the second PAD is from the off-chip memory. The off-chip access circuit can improve the access speed of accessing the off-chip firmware.

Description

Technical Field

[0001] The present application belongs to the field of electronic circuits, and specifically relates to an off-chip access circuit, method, memory controller, chip and electronic equipment. Background Art

[0002] Firmware is a program written into EPROM (Erasable Programmable Read-Only Memory) or Flash. It is a program code solidified inside the integrated circuit and is responsible for controlling and coordinating the functions of the integrated circuit. For processing chips, firmware is needed in many places in the chip, so the firmware capacity bytes required are very large. If the firmware is stored in the EPROM inside the chip, the cost is very high, so the usual practice is to save the firmware to the Flash outside the chip. Most of the existing Flash is accessed through the SPI (Serial Peripheral Interface) bus. The current access speed of accessing off-chip firmware based on the SPI bus needs to be improved. Summary of the invention

[0003] In view of this, the purpose of the present application is to provide an off-chip access circuit, method, memory controller, chip and electronic device to improve the access speed of accessing off-chip firmware based on the SPI bus.

[0004] The embodiment of the present application is implemented as follows:

[0005] In a first aspect, an embodiment of the present application provides an off-chip access circuit based on an SPI bus, comprising: a first PAD, a second PAD, a clock generating circuit and a data sampling circuit, wherein the first PAD and the second PAD are connected to an off-chip memory through the SPI bus, and the off-chip memory is used to store firmware; a clock generating circuit is connected to the first PAD, and the clock generating circuit is used to generate a clock signal required for the SPI bus and transmit the clock signal to the first PAD; a data sampling circuit is connected to the first PAD and the second PAD, and the data sampling circuit is used to sample data transmitted by the second PAD based on the clock signal from the first PAD, wherein the data transmitted by the second PAD comes from the off-chip memory.

[0006] In the above embodiment, the off-chip access circuit of the above structure is adopted, so that when the off-chip access circuit samples the transmission data from the off-chip memory, it is no longer based on the high-speed clock inside the conventional processing chip, but is based on the SCK clock of the SPI bus. This can offset part of the SPI transmission delay, thereby improving the access speed of the off-chip firmware.

[0007] In combination with a possible implementation manner of the embodiment of the first aspect, the off-chip access circuit also includes: a data storage circuit and a clock synchronization circuit, the clock of the data storage circuit is different from the clock of the data sampling circuit; the data sampling circuit is connected to the data storage circuit through the clock synchronization circuit, and the clock synchronization circuit is used to convert the sampled data transmitted by the data sampling circuit from a first clock domain to data in a second clock domain adapted to the data storage circuit.

[0008] In the above embodiment, a clock synchronization circuit is set to convert the sampling data transmitted by the data sampling circuit from the first clock domain into data in the second clock domain that is adapted to the data storage circuit, so that the data storage circuit working in the high-speed clock domain (second clock domain) can be multiplexed.

[0009] In combination with a possible implementation manner of the first aspect, the data sampling circuit is used to sample the data transmitted by the second PAD based on the falling edge of the clock signal from the first PAD, wherein the rising edge of the clock signal from the first PAD is used by the off-chip access circuit to send data to the off-chip memory.

[0010] In the above embodiment, the data transmitted by the second PAD is sampled based on the falling edge of the clock signal, which can further improve the access speed compared to sampling the data transmitted by the second PAD based on the rising edge of the clock signal.

[0011] In combination with a possible implementation manner of the embodiment of the first aspect, a transmission distance between the data sampling circuit and the first PAD is the same as a transmission distance between the data sampling circuit and the second PAD.

[0012] In the above embodiment, when the transmission distance between the data sampling circuit and the first PAD is the same as the transmission distance between the data sampling circuit and the second PAD, the transmission delay between the data sampling circuit and the first PAD is the same as the transmission delay between the data sampling circuit and the second PAD.

[0013] In combination with a possible implementation manner of the embodiment of the first aspect, the off-chip access circuit also includes: a third PAD, a fourth PAD, a chip select generating circuit and a data sending circuit, the third PAD and the fourth PAD are connected to the off-chip memory through the SPI bus; the chip select generating circuit is connected to the third PAD, the chip select generating circuit is used to generate a chip select signal required by the SPI bus, and send it to the SPI bus through the third PAD; the data sending circuit is connected to the fourth PAD, the data sending circuit is used to generate the SI signal required by the SPI bus, and send it to the SPI bus through the fourth PAD.

[0014] In the above embodiment, by further setting up a chip select generating circuit and a data sending circuit, when the off-chip access circuit needs to read data from the off-chip memory, the clock signal required by the SPI bus (which can be represented by SPI_SCK) is generated by the internal clock generating circuit based on the high-speed clock, and the clock signal is transmitted to the first PAD to generate the corresponding SPI bus clock SCK. At the same time, the chip select generating circuit and the data sending circuit respectively generate corresponding SS and MOSI signals on the third PAD and the fourth PAD based on the high-speed clock to realize access to the off-chip memory based on the SPI bus.

[0015] In a second aspect, an embodiment of the present application further provides a memory controller, comprising an off-chip access circuit as provided in the above-mentioned first aspect embodiment and / or any possible implementation method in combination with the first aspect embodiment, wherein the memory controller is connected to the memory via an SPI bus.

[0016] In a third aspect, an embodiment of the present application further provides a chip, comprising a memory controller as provided in the embodiment of the second aspect above.

[0017] In a fourth aspect, an embodiment of the present application further provides an electronic device, comprising: a memory and a chip provided in the embodiment of the third aspect, wherein the chip is connected to the memory; the memory is used to store firmware; and the chip is used to access the firmware stored in the memory.

[0018] In the fifth aspect, an embodiment of the present application also provides an off-chip access method based on the SPI bus, which is applied to a memory controller, wherein the memory controller is connected to an off-chip memory, and the method comprises: receiving data sent by the off-chip memory based on the SPI bus; sampling the data from the off-chip memory based on the clock signal in the SPI bus.

[0019] In combination with a possible implementation manner of the fifth aspect, sampling the data from the off-chip memory based on the clock signal in the SPI bus includes: sampling the data from the off-chip memory based on the falling edge of the clock signal in the SPI bus, wherein the rising edge of the clock signal is used by the memory controller to send data to the off-chip memory.

[0020] Other features and advantages of the present application will be described in the following description. The purpose and other advantages of the present application can be realized and obtained through the structures specifically pointed out in the written description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. The above and other purposes, features and advantages of the present application will be more clear as shown in the drawings.

[0022] Figure 1 A schematic diagram of signal delay when a processing chip provided by an embodiment of the present application reads data from an off-chip Flash is shown.

[0023] Figure 2 A schematic diagram showing the connection between a first off-chip access circuit and Flash provided in an embodiment of the present application is shown.

[0024] Figure 3 A schematic diagram showing the connection between the second off-chip access circuit provided by an embodiment of the present application and Flash is shown.

[0025] Figure 4 A schematic diagram showing the connection between the third off-chip access circuit and Flash provided in an embodiment of the present application is shown.

[0026] Figure 5 A flow chart of an off-chip access method provided in an embodiment of the present application is shown.

[0027] Figure 6 A schematic structural diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The following embodiments can be used as examples to more clearly illustrate the technical solutions of the present application, and cannot be used to limit the scope of protection of the present application. It will be appreciated by those skilled in the art that, in the absence of conflict, the features in the following embodiments and embodiments can be combined with each other.

[0029] It should be noted that similar numbers and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. At the same time, in the description of this application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0030] Furthermore, the term "and / or" in this application is merely a term used to describe the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B may represent three situations: A exists alone, A and B exist at the same time, and B exists alone.

[0031] In the description of the embodiments of the present application, unless otherwise clearly specified or limited, the technical term "connection" may refer to a direct connection or an indirect connection through an intermediate medium.

[0032] When studying the reasons why the current processing chip has a low access speed to off-chip firmware based on the SPI bus, the inventors of the present application discovered that when the current processing chip needs to read data from off-chip Flash, the SPI controller inside the processing chip generates the corresponding clock SPI_SCK based on the high-speed clock, and sends it to the chip PAD as the SPI bus clock SCK. When the SPI controller needs to receive data from external Flash, the SO signal on the SPI bus is transmitted to the inside of the processing chip through the PAD to obtain the SPI_SO signal, and the data from the SPI_SO signal is sampled through the rising edge of the high-speed clock. The time required for the current processing chip to read off-chip Flash is as follows: The time required for the processing chip to read off-chip Flash based on the SPI bus is as follows: The delay T1 of the SPI_SCK clock from the inside of the SPI controller to the PAD pin, the delay T2 of the internal Flash output to its own PAD pin, the delay T3 of the SO signal from the chip PAD pin to the SPI_SO inside the SPI controller, and the connection delay T4 between the PAD pin of the SPI controller and the PAD pin of the off-chip Flash. The delays are as follows: Figure 1 As shown, Figure 1 The delay T4 is not shown.

[0033] The main reason that currently restricts the access speed of off-chip firmware is that since SO data must be sampled at the next rising edge of SCK, the sum of these delays (T1+T2+T3+T4) needs to be less than the period of the SCK clock. These factors limit the increase in the rate of the SPI bus clock SCK, making the maximum access speed of off-chip firmware the frequency of the SCK signal, resulting in the inability to increase the access speed of off-chip firmware.

[0034] In order to improve the access speed of accessing off-chip firmware based on the SPI bus, the embodiment of the present application provides an off-chip access circuit based on the SPI bus. When sampling the transmission data from the off-chip memory, the off-chip access circuit no longer samples based on the high-speed clock inside the conventional processing chip, but samples based on the SCK clock of the SPI bus. This can offset part of the SPI transmission delay, thereby improving the access speed of accessing the off-chip firmware. Figure 2 As shown, the off-chip access circuit includes: a first PAD (which can be represented as PAD1), a second PAD (which can be represented as PAD2), a clock generation circuit and a data sampling circuit. The off-chip access circuit is connected to the off-chip memory via the SPI bus. It can be understood that Figure 1 Only the case where the off-chip memory is a Flash memory is shown. The off-chip memory includes but is not limited to the Flash memory. The off-chip memory is used to store firmware.

[0035] Among them, the first PAD and the second PAD are connected to the off-chip memory through the SPI bus. For example, the first PAD can be connected to the off-chip memory through the SCK line in the SPI bus, and the second PAD can be connected to the off-chip memory through the MISO line in the SPI bus.

[0036] The clock generating circuit is connected to the first PAD, and is used to generate a clock signal required by the SPI bus and transmit the clock signal to the first PAD. The clock generating circuit generates the clock signal required by the SPI bus based on a high-speed clock.

[0037] The data sampling circuit is connected to the first PAD and the second PAD. The data sampling circuit is used to sample the data transmitted by the second PAD based on the clock signal from the first PAD, wherein the data transmitted by the second PAD comes from an off-chip memory. When the data sampling circuit samples the data transmitted by the second PAD, it is no longer based on the high-speed clock, but based on the clock signal from the first PAD, which can offset part of the transmission delay, thereby improving the access speed of accessing the off-chip firmware based on the SPI bus.

[0038] The SPI (Serial Peripheral Interface) bus is a high-speed, full-duplex, synchronous communication bus used to handle data transmission between chips and peripheral devices. The basic signal lines included are as follows:

[0039] SS (Slave Select): Device select line, used to select slave devices. Only when the SS signal is a pre-defined enable signal (usually a low level), the master device's operation on the slave device is effective. Multiple SPI devices can be connected to the same bus.

[0040] SCK (Serial Clock): Clock line, generated by the master device, controls the data transmission rate and timing.

[0041] MOSI (Master Out Slave In): Master device data output line, slave device data input line.

[0042] MISO (Master In Slave Out): Master device data input line, slave device data output line.

[0043] The first PAD and the second PAD mentioned above may be connected to the off-chip memory via SCK and MISO in the SPI bus.

[0044] In one implementation manner, the off-chip access circuit further includes: a third PAD (which may be represented as PAD3), a fourth PAD (which may be represented as PAD4), a chip selection generating circuit and a data sending circuit, such as Figure 3 shown.

[0045] The third PAD and the fourth PAD are connected to the off-chip memory via the SPI bus. For example, the third PAD is connected to the off-chip memory via the SS line in the SPI bus, and the fourth PAD is connected to the off-chip memory via the MOSI line in the SPI bus.

[0046] The chip select generating circuit is connected to the third PAD, and the chip select generating circuit is used to generate the chip select signal required by the SPI bus, and send it to the SPI bus through the third PAD. The data sending circuit is connected to the fourth PAD, and the data sending circuit is used to generate the SI signal required by the SPI bus, and send it to the SPI bus through the fourth PAD. The data sending circuit is also used to send data to the off-chip memory based on the SI signal.

[0047] When the off-chip access circuit needs to read data from the off-chip memory, the clock signal required by the SPI bus (which can be represented by SPI_SCK) is generated by the internal clock generation circuit based on the high-speed clock, and the clock signal is transmitted to the first PAD to generate the corresponding SPI bus clock SCK. At the same time, the chip selection generation circuit and the data transmission circuit generate corresponding SS and MOSI signals on the third PAD and the fourth PAD based on the high-speed clock respectively. When the off-chip access circuit needs to receive data from the off-chip memory, the SCK and MISO signals on the bus are transmitted to the data sampling circuit through the first PAD and the second PAD, and the data sampling circuit uses the SCK from the SPI bus to sample the data of the SO signal transmitted by the second PAD.

[0048] In a possible implementation, the transmission distance between the data sampling circuit and the first PAD is the same as the transmission distance between the data sampling circuit and the second PAD, so that the transmission delay between the data sampling circuit and the first PAD can be the same as the transmission delay (T3) between the data sampling circuit and the second PAD. At this time, since the sampling clock of the data sampling circuit comes from the SPI bus, its delay is: the transmission delay (T1) between the clock generation circuit and the first PAD + the transmission delay (T3) between the data sampling circuit and the first PAD. Based on the above analysis, it can be known that the time required for the current processing chip to read the off-chip Flash is: T1+T2+T3+T4. Since the clock delay for sampling based on the SCK clock of the SPI bus in this application is T1+T3, that is, the time required for the SCK clock of the SPI bus to read the off-chip Flash in this application is T2+T4, which can offset the delay of T1+T3 in (T1+T2+T3+T4), so that the maximum frequency of the clock SCK can be set to the frequency that the Flash can receive, and the speed of the off-chip access circuit to access the Flash will be greatly accelerated.

[0049] It can be understood that the transmission delay between the above-mentioned data sampling circuit and the first PAD is the same as the transmission delay between the data sampling circuit and the second PAD. The same here includes but is not limited to being completely the same. As long as the error between the two is within the allowable error range, they are considered to be the same.

[0050] In one implementation, the data sampling circuit is used to sample the data transmitted by the second PAD based on the falling edge of the clock signal from the first PAD, wherein the rising edge of the clock signal from the first PAD is used by the off-chip access circuit to send data to the off-chip memory. Compared with sampling the data transmitted by the second PAD based on the rising edge of the clock signal from the first PAD, the delay in (T1+T2+T3+T4) can be further offset, and the access speed can be further improved.

[0051] Since the data sampling circuit is no longer based on a high-speed clock for sampling, but based on the clock signal of the first PAD for sampling, therefore, in a possible implementation, the off-chip access circuit further includes: a data storage circuit and a clock synchronization circuit, such as Figure 4 The clock of the data storage circuit is different from the clock of the data sampling circuit. For example, the clock of the data storage circuit is a high-speed clock.

[0052] The high-speed clock mentioned above is relative to the SCK clock. The frequency of the high-speed clock is greater than the SCK clock. Usually, the frequency of the high-speed clock is not less than 200 MHz, while the frequency of the SCK clock is less than 200 MHz.

[0053] The data sampling circuit is connected to the data storage circuit through a clock synchronization circuit, and the clock synchronization circuit is used to convert the sampled data transmitted by the data sampling circuit from the first clock domain to data in the second clock domain adapted to the data storage circuit. The first clock domain may be the clock domain where the clock signal of the first PAD is located, and the second clock domain may be the clock domain where the high-speed clock is located. Since the clocks of the data sampling circuit and the data storage circuit are different, a clock synchronization circuit is required for clock synchronization.

[0054] In some possible implementations, the data storage circuit in the processing chip may not be reused, but a data storage circuit whose clock is synchronized with the data sampling circuit may be separately provided. In this implementation, a clock synchronization circuit may not be required.

[0055] The specific implementation of the above-mentioned clock generation circuit, data sampling circuit, chip selection generation circuit, data transmission circuit, clock synchronization circuit and data storage circuit is not the focus of this application and can be implemented using existing technologies in related technologies.

[0056] The embodiment of the present application also provides an off-chip access method based on the SPI bus, which is applied to a memory controller, and the memory controller is connected to the off-chip memory based on the SPI bus. The memory controller includes the above-mentioned off-chip access circuit. Figure 5 Describe its process.

[0057] S1: receiving data sent by the off-chip memory based on the SPI bus.

[0058] Before the memory controller receives the data sent by the off-chip memory based on the SPI bus, the method also includes: the memory controller generates the clock signal required by the SPI bus through the internal clock generation circuit. At the same time, the chip selection generation circuit and the data transmission circuit respectively generate corresponding SS and MOSI signals on the third PAD and the fourth PAD based on the high-speed clock, the off-chip Flash analyzes the data received from the SPI bus to obtain the corresponding command and read address, and then the internal circuit of the off-chip Flash sends the corresponding data to the MISO of the SPI bus according to the obtained command and address, so that the memory controller can receive the data sent by the off-chip memory based on the SPI bus.

[0059] S2: Sampling data from the off-chip memory based on the clock signal in the SPI bus.

[0060] When the memory controller samples the data from the off-chip memory based on the clock signal in the SPI bus, it may be based on the rising edge of the clock signal in the SPI bus to sample the data from the off-chip memory. In a possible implementation, when the data from the off-chip memory is sampled based on the clock signal in the SPI bus, it may include: sampling the data from the off-chip memory based on the falling edge of the clock signal in the SPI bus, wherein the rising edge of the clock signal is used by the memory controller to send data to the off-chip memory.

[0061] The off-chip access method provided in the embodiment of the present application has the same implementation principle and technical effects as those of the aforementioned off-chip access circuit embodiment. For the sake of brief description, for matters not mentioned in the method embodiment, reference may be made to the corresponding contents in the aforementioned off-chip access circuit embodiment.

[0062] An embodiment of the present application also provides a memory controller, which includes the above-mentioned off-chip access circuit. The memory controller is connected to the memory via an SPI bus. Since the memory controller accesses the memory based on the SPI bus, the memory controller can also be called an SPI controller.

[0063] The SPI controller sends command data (such as a read command) to the memory through the SPI bus. The memory parses the command data received from the SPI bus, obtains the corresponding command and read address, and then sends the corresponding data to the MISO of the SPI bus according to the obtained command and address. In this way, the memory controller can receive the data sent by the memory based on the SPI bus.

[0064] The memory controller provided in the embodiment of the present application has the same implementation principle and technical effects as those of the aforementioned off-chip access circuit embodiment. For the sake of brief description, for matters not mentioned in the memory controller embodiment, reference may be made to the corresponding contents in the aforementioned off-chip access circuit embodiment.

[0065] The embodiment of the present application also provides a chip, which includes the above-mentioned memory controller. The chip can be various chips including a memory controller, for example, a memory controller chip, a memory interface chip, and a processing chip. The processing chip can include but is not limited to a processor, and the processor can be divided into mobile processors, such as Apple A series, Qualcomm Snapdragon series, Huawei Kirin series, etc., and desktop and server processors, such as Intel Core series, AMD Ryzen series, etc. In some possible implementations, the above-mentioned chip can be a graphics processing unit (GPU).

[0066] The chip provided in the embodiment of the present application has the same implementation principle and technical effects as those of the aforementioned off-chip access circuit embodiment. For the sake of brief description, for matters not mentioned in the chip embodiment, reference may be made to the corresponding contents in the aforementioned off-chip access circuit embodiment.

[0067] An embodiment of the present application also provides an electronic device, which includes a memory and a chip as described above, wherein the chip is connected to the memory; the memory is used to store firmware; and the chip is used to access the firmware stored in the memory.

[0068] In a possible implementation manner, when the chip is a processor, the structure of an electronic device provided in an embodiment of the present application is as follows: Figure 6 The electronic device comprises: a transceiver, a memory, a communication bus and a processor.

[0069] The transceiver, the memory, and the processor are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these elements can be electrically connected to each other through one or more communication buses or signal lines. Among them, the transceiver is used to send and receive data. The memory is used to store computer programs, such as firmware. Among them, the firmware includes at least one software function module that can be stored in the memory in the form of software or firmware (Firmware) or solidified in the operating system (Operating System, OS) of the electronic device. The processor is used to access and execute the executable module stored in the memory.

[0070] Among them, the memory can be, but is not limited to, random access memory (Random Access Memory, RAM), read only memory (Read Only Memory, ROM), programmable read-only memory (Programmable Read-Only Memory, PROM), erasable programmable read-only memory (Erasable Programmable Read-Only Memory, EPROM), electrically erasable read-only memory (Electric Erasable Programmable Read-Only Memory, EEPROM), etc.

[0071] The processor may be an integrated circuit chip with signal processing capabilities. The above-mentioned processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a microprocessor, etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. Or the processor may also be any conventional processor, etc.

[0072] The above-mentioned electronic devices include but are not limited to mobile devices, computing devices, household devices, medical devices, gaming devices, security devices, network and communication devices, vehicles, etc. Among them, mobile devices include but are not limited to smart phones, tablets, wearable devices. Computing devices include but are not limited to personal computers, servers, computing cards, etc. Household devices include but are not limited to smart TVs, refrigerators, washing machines, air conditioners, etc. Medical devices include but are not limited to ultrasound equipment, electrocardiogram machines, radiation equipment, etc. Gaming devices include but are not limited to game consoles, game consoles, etc. Security devices include but are not limited to cameras, smart locks, access control systems, etc. Network and communication devices include but are not limited to routers, switches, firewalls, etc. Vehicles include but are not limited to various vehicles containing electronic control units.

[0073] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0074] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0075] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0076] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a computer-readable storage medium, including several instructions for a computer device (which can be a personal computer, a laptop, a server, or an electronic device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned computer-readable storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0077] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An off-chip access circuit based on SPI bus, characterized in that: include: A first PAD and a second PAD, wherein the first PAD and the second PAD are connected to an off-chip memory through the SPI bus, and the off-chip memory is used to store firmware; A clock generating circuit connected to the first PAD, the clock generating circuit is used to generate a clock signal required by the SPI bus and transmit the clock signal to the first PAD; A data sampling circuit is connected to the first PAD and the second PAD, and is used to sample data transmitted by the second PAD based on a clock signal from the first PAD, wherein the data transmitted by the second PAD comes from the off-chip memory.

2. The off-chip access circuit according to claim 1, characterized in that: The off-chip access circuit further includes: a data storage circuit, wherein a clock of the data storage circuit is different from a clock of the data sampling circuit; A clock synchronization circuit, wherein the data sampling circuit is connected to the data storage circuit via the clock synchronization circuit, and the clock synchronization circuit is used to convert the sampled data transmitted by the data sampling circuit from a first clock domain into data adapted to a second clock domain of the data storage circuit.

3. The off-chip access circuit according to claim 1, characterized in that: The data sampling circuit is used to sample the data transmitted by the second PAD based on the falling edge of the clock signal from the first PAD, wherein the rising edge of the clock signal from the first PAD is used by the off-chip access circuit to send data to the off-chip memory.

4. The off-chip access circuit according to claim 1, characterized in that: A transmission distance between the data sampling circuit and the first PAD is the same as a transmission distance between the data sampling circuit and the second PAD.

5. The off-chip access circuit according to any one of claims 1 to 4, characterized in that: The off-chip access circuit further includes: A third PAD and a fourth PAD, wherein the third PAD and the fourth PAD are connected to an off-chip memory via the SPI bus; A chip select generating circuit, connected to the third PAD, the chip select generating circuit is used to generate a chip select signal required by the SPI bus, and send the chip select signal to the SPI bus through the third PAD; A data sending circuit is connected to the fourth PAD, and is used to generate the SI signal required by the SPI bus and send it to the SPI bus through the fourth PAD.

6. A memory controller, characterized in that: The invention comprises the off-chip access circuit as claimed in any one of claims 1 to 5, wherein the memory controller is connected to the memory via an SPI bus.

7. A chip, characterized in that: Comprising the memory controller of claim 6.

8. An electronic device, characterized in that: include: A memory and a chip as claimed in claim 7, wherein the chip is connected to the memory; The memory is used to store firmware; The chip is used to access the firmware stored in the memory.

9. An off-chip access method based on SPI bus, characterized in that: Applied to a memory controller, the memory controller is connected to an off-chip memory, the method comprising: Receiving data sent by an off-chip memory based on the SPI bus; Data from the off-chip memory is sampled based on a clock signal in the SPI bus.

10. The off-chip access method according to claim 9, characterized in that: Sampling data from the off-chip memory based on a clock signal in the SPI bus includes: The data from the off-chip memory is sampled based on the falling edge of the clock signal in the SPI bus, wherein the rising edge of the clock signal is used by the memory controller to send data to the off-chip memory.

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