Power supply integrity simulation method and device, storage medium and electronic equipment

Abstract

The invention relates to a power supply integrity simulation method and device, a storage medium and electronic equipment, belongs to the technical field of simulation, and improves the reliability of a power supply integrity simulation result. The power supply integrity simulation method comprises the steps that a target operation code pattern is determined, the target operation code pattern is used for controlling an energy peak value of simulation dynamic current of a chip power consumption model in a frequency domain to correspond to a target frequency, and the target frequency comprises a frequency corresponding to a target anti-resonance point; the target anti-resonance point comprises the highest anti-resonance point of a simulation power distribution network curve of the chip power consumption model in a frequency domain; a simulation output circuit corresponding to the chip power consumption model is controlled to operate in the target operation code pattern, and target simulation dynamic current corresponding to the chip power consumption model is obtained; and performing simulation according to the target simulation dynamic current to obtain a simulation result for representing the integrity of the power supply.

Description

Technical Field

[0001] The present disclosure relates to the field of simulation technology, and in particular to a power integrity simulation method, device, storage medium and electronic device. Background Art

[0002] In the existing power integrity simulation process, the power integrity simulation is achieved by controlling the peak-to-peak value of the simulated current of the chip power model (CPM) to reach the maximum. However, during the simulation process, the peak-to-peak value of the simulated current at the chip bump reaches the maximum, and the corresponding peak-to-peak value of the simulated voltage may be smaller than the actual situation, that is, the peak-to-peak value of the dynamic voltage at the measured chip bump may be greater than the peak-to-peak value of the simulated voltage, resulting in unreliable power integrity simulation results. Summary of the invention

[0003] The purpose of the present disclosure is to provide a power integrity simulation method, device, storage medium and electronic device, which improve the reliability of power integrity simulation results.

[0004] In order to achieve the above objectives, in a first aspect, the present disclosure provides a power integrity simulation method, the power integrity simulation method comprising: Determine a target operating code pattern, wherein the target operating code pattern is used to control the energy peak of the simulated dynamic current of the chip power consumption model in the frequency domain to correspond to a target frequency, wherein the target frequency includes a frequency corresponding to a target anti-resonance point, and the target anti-resonance point includes a highest anti-resonance point of a simulated power distribution network curve of the chip power consumption model in the frequency domain; Controlling the simulation output circuit corresponding to the chip power consumption model to run with the target running code pattern to obtain the target simulation dynamic current corresponding to the chip power consumption model; A simulation is performed according to the target simulated dynamic current to obtain a simulation result for characterizing power integrity.

[0005] Optionally, determining the target running code type includes: Performing simulation in the frequency domain to obtain the simulated power distribution network curve; Determining the target frequency according to the simulated power distribution network curve; determining a maximum operating rate of the simulation output circuit; A target operating code pattern is determined according to the target frequency and the maximum operating rate.

[0006] Optionally, determining a target operating code pattern according to the target frequency and the maximum operating rate includes: Determining a target quantity according to the target frequency and the maximum operating rate; At least according to the target number, a target running code pattern is determined, the target running code pattern is a periodic code pattern, and each period includes the target number of consecutive digital 0s and the target number of consecutive digital 1s.

[0007] Optionally, determining a target quantity according to the target frequency and the maximum operating rate includes: Substituting the target frequency and the maximum operating rate into a calculation formula to obtain a target quantity; The calculation formula includes: N=M / 2P, N represents the target number, M represents the maximum operating rate, and P represents the target frequency.

[0008] Optionally, determining the target running code type includes: Determine the spectrum of the simulated dynamic current of the chip power consumption model when the simulated output circuit runs with the initial running code pattern; Determining a current spectrum diagram corresponding to the initial operation code pattern according to the spectrum; When the highest energy peak in the current spectrum diagram corresponds to the target frequency, the initial operating code pattern is used as the target operating code pattern, and the target operating code pattern is a periodic code pattern, each of the periods includes consecutive digital 0s and consecutive digital 1s, and the number of digital 0s and digital 1s is the same.

[0009] Optionally, the determining a spectrum of a simulated dynamic current of the chip power consumption model when the simulated output circuit runs with an initial running code pattern includes: Controlling the simulation output circuit to run with an initial running code pattern to obtain a first simulation dynamic current corresponding to the chip power consumption model, wherein the first simulation dynamic current is a time domain current; Performing Fourier transform on the first simulated dynamic current to obtain a second simulated dynamic current, where the second simulated dynamic current is a frequency domain current; A frequency spectrum of the second simulated dynamic current is determined.

[0010] Optionally, determining the target running code type further includes: When the highest energy peak in the current spectrum diagram does not correspond to the target frequency, the operating code pattern of the simulation output circuit is adjusted until the maximum amplitude in the current spectrum diagram corresponding to the operating code pattern corresponds to the target frequency, thereby obtaining the target operating code pattern.

[0011] In a second aspect, the present disclosure provides a power integrity simulation device, comprising: A determination module, used to determine a target operating code pattern, wherein the target operating code pattern is used to control the energy peak of the simulated dynamic current of the chip power consumption model in the frequency domain to correspond to a target frequency, wherein the target frequency includes a frequency corresponding to a target anti-resonance point, and the target anti-resonance point includes a highest anti-resonance point of a simulated power distribution network curve of the chip power consumption model in the frequency domain; A control module, used for controlling the simulation output circuit corresponding to the chip power consumption model to run with the target running code pattern, so as to obtain the target simulation dynamic current corresponding to the chip power consumption model; A simulation module is used to simulate the dynamic current according to the target simulation to obtain a simulation result for characterizing the power integrity. In a third aspect, the present disclosure provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the power integrity simulation method described in the first aspect. In a fourth aspect, the present disclosure provides an electronic device, including: a memory having a computer program stored thereon; A processor is used to execute the computer program in the memory to implement the steps of the power integrity simulation method according to the first aspect.

[0012] Through the above technical solution, the present disclosure controls the simulation output circuit corresponding to the chip power consumption model to run with the target operation code type, obtains the target simulation dynamic current corresponding to the chip power consumption model, performs simulation according to the target simulation dynamic current, and obtains the simulation result for characterizing the power integrity. The energy peak of the simulated dynamic current of the chip power consumption model in the frequency domain is controlled by the target operation code to correspond to the target frequency, thereby ensuring that the peak-to-peak value of the dynamic voltage obtained by the simulation reaches the maximum, and improving the reliability of the power integrity simulation result.

[0013] Other features and advantages of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings: Figure 1 The figure is a flow chart of a power integrity simulation method according to an exemplary embodiment of the present disclosure.

[0015] Figure 2 The block diagram of a system-level power integrity simulation model is shown according to an exemplary embodiment of the present disclosure.

[0016] Figure 3aFIG. 4 is a schematic diagram of a dynamic current corresponding to a PRBS31 operating pattern according to an exemplary embodiment of the present disclosure.

[0017] Figure 3b 1 is a schematic diagram of a dynamic current corresponding to a long-0-long-1 running code pattern according to an exemplary embodiment of the present disclosure.

[0018] Figure 4 The figure is a simulated power distribution network curve diagram of a system-level power integrity simulation model according to an exemplary embodiment of the present disclosure.

[0019] Figure 5a It is a schematic diagram of a simulated single-ended signal output circuit of a sixth-generation GDDR video memory according to an exemplary embodiment of the present disclosure.

[0020] Figure 5b is a schematic diagram of a simulated differential signal output circuit of a deserializer according to an exemplary embodiment of the present disclosure.

[0021] Figure 6 is another flow chart showing step S11 according to an exemplary embodiment of the present disclosure.

[0022] Figure 7 is a flowchart of step S61 according to an exemplary embodiment of the present disclosure.

[0023] Figure 8 is a flowchart of step S11 according to an exemplary embodiment of the present disclosure.

[0024] Fig. 9 is a flowchart of step S84 according to an exemplary embodiment of the present disclosure.

[0025] Fig.10 It is a full-link simulated power distribution network curve diagram shown according to an exemplary embodiment of the present disclosure.

[0026] Fig.11a FIG. 4 is another dynamic current schematic diagram corresponding to the PRBS31 operating pattern according to an exemplary embodiment of the present disclosure.

[0027] Fig.11b It is a dynamic flow chart showing a corresponding target running code type according to an exemplary embodiment of the present disclosure.

[0028] Fig.12a FIG. 4 is a spectrum diagram of a dynamic current corresponding to a PRBS31 operating pattern according to an exemplary embodiment of the present disclosure.

[0029] Figure 12b is a spectrum diagram of a dynamic current corresponding to a target operating code pattern according to an exemplary embodiment of the present disclosure.

[0030] Fig.13a is a schematic diagram of a dynamic voltage corresponding to a PRBS31 operating pattern according to an exemplary embodiment of the present disclosure.

[0031] Fig.13b is a schematic diagram of a dynamic voltage corresponding to a target operating code type according to an exemplary embodiment of the present disclosure.

[0032] Fig.14 The figure is a block diagram of a power integrity simulation device according to an exemplary embodiment of the present disclosure.

[0033] Fig.15 is a block diagram of an electronic device according to an exemplary embodiment of the present disclosure.

[0034] Description of Reference Numerals 101 chip power consumption model, 102 package power distribution network, 103 printed circuit board power distribution network, 104 power supply model, 141 determination module, 142 control module, 143 simulation module, 150 electronic device, 151 processor, 152 memory, 153 multimedia component, 154 I / O interface, 155 communication component. DETAILED DESCRIPTION

[0035] The specific implementation of the present disclosure is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the present disclosure, and is not used to limit the present disclosure.

[0036] It should be noted that all actions of acquiring signals, information or data in the present disclosure are carried out in compliance with the relevant data protection laws and policies of the country where the device is located and with the authorization given by the owner of the corresponding device.

[0037] As mentioned in the background art, in the related art, the peak-to-peak value of the simulated current of CPM is controlled to be maximum, thereby determining the simulated dynamic current, and then performing power integrity simulation based on the simulated dynamic current.

[0038] It is worth noting that see Figure 2 The system-level power integrity simulation model includes a chip power consumption model (CPM) 101, a package power distribution network (Package Power Delivery Network, PKG PDN) 102, a printed circuit board power distribution network (Printed Circuit Board Power Delivery Network, PCB PDN) 103 and a power supply model 104, which are connected in series. Among them, CPM101 is divided into chip PDN parasitic parameters and dynamic current. Figure 2The system-level power integrity simulation model shown simulates the time domain noise of the corresponding power supply as: Δu t =Δi t ΔR d , Δu t Characterizes the dynamic voltage at C4 Bump, Δi t Characterizing the dynamic current in CPM, ΔR d Characterize the equivalent dynamic resistance of the PDN composed of CPM, PKG, and PCB cascade.

[0039] Δi t It is strongly related to the behavior of the output circuit in CPM (the output circuit in the I / O circuit), that is, when the output circuit runs different operating patterns, Δi in CPM t Take the example of 16 output circuits in CPM. The output circuit runs PRBS (Pseudo-Random Binary Sequence) 31 code at 6400Mpbs. The following is obtained: Figure 3a The dynamic current generated by the PRBS31 pattern shown in the figure; the output circuit runs the long 0 long 1 pattern at a rate of 6400Mpbs, and the following is obtained Figure 3b The dynamic current generated by the long 0 long 1 pattern shown in the figure shows that when CPM runs different running patterns, the corresponding Δi t Completely different. Figure 3a and Figure 3b The horizontal axis represents the time time, the unit is nanoseconds nsec, and the vertical axis represents the current i, the unit is milliampere mA.

[0040] The inventors found that during the simulation process, when the simulated dynamic current peak-to-peak value is guaranteed to reach the maximum, the corresponding simulated dynamic voltage peak-to-peak value may be smaller than the actual dynamic voltage peak-to-peak value, resulting in the Δu at C4 Bump obtained by the power integrity simulation. t When the corresponding dynamic voltage peak-to-peak value meets the requirements, the Δu at C4 Bump is measured. t The corresponding dynamic voltage peak-to-peak value does not meet the requirements, making the simulation results unreliable.

[0041] The inventors also found that during the simulation, the dynamic voltage Δu at C4 Bump t The dynamic current Δi in CPM t The equivalent dynamic resistance ΔR of the PDN composed of CPM, PKG, and PCB cascade d Determined jointly. Among them, ΔR d It is not only determined by the PDN of CPM, PKG, and PCB, but also by Δi t The spectral distribution intensity is related to ΔR d and Δi tThey are not completely independent, so it is not possible to simply determine the Δu corresponding to the maximum dynamic voltage peak-to-peak value in the time domain. t .

[0042] In view of this, the present disclosure provides a power integrity simulation method, device, storage medium and electronic device, which control the energy peak of the dynamic current in the frequency domain to correspond to the target frequency through the target running code, ensuring that the peak-to-peak value of the dynamic voltage obtained by simulating the dynamic current reaches the maximum, thereby improving the reliability of the power integrity simulation results.

[0043] Figure 1 1 is a flowchart of a power integrity simulation method according to an exemplary embodiment of the present disclosure. The power integrity method can be applied to terminal devices such as mobile phones, computers, tablet devices, personal digital assistants, etc. Figure 1 , the power integrity simulation method may include the following steps: In step S11, the target operating code type is determined. The target operating code type is used to control the energy peak of the simulated dynamic current of the chip power consumption model in the frequency domain to correspond to the target frequency. The target frequency includes the frequency corresponding to the target anti-resonance point. The target anti-resonance point includes the highest anti-resonance point of the simulated power distribution network curve of the chip power consumption model in the frequency domain.

[0044] It is worth noting that it is not possible to simply determine the Δu corresponding to the maximum dynamic voltage peak-to-peak value in the time domain. t , so it is converted to the frequency domain, and the relationship between the simulated dynamic voltage and the simulated dynamic current in the frequency domain is: U f =I f ·Z, U f Characterize the frequency domain dynamic voltage at C4 Bump, I f Characterizes the frequency domain dynamic current in CPM. Z characterizes the full link impedance after CPM+PKG+PCB cascade. Z is determined by CPM, PKG and PCB and has nothing to do with the frequency domain dynamic current I f .

[0045] For example, see Figure 4 , the system power supply simulation power distribution network curve (PDN curve) will form a peak at one or more frequency points, that is, the anti-resonance point, such as Figure 4 The anti-resonance point 1 and anti-resonance point 2 are shown. Therefore, the energy of the dynamic current controlled by the target operation pattern is concentrated near the frequency corresponding to the highest anti-resonance point, and the dynamic voltage corresponding to the maximum dynamic voltage peak-to-peak value can be determined. Among them, Figure 4 The horizontal axis represents the frequency freq, the unit is Hertz Hz, and the vertical axis represents the amplitude mag.

[0046] It is worth noting that the control chip power consumption model CPM is a SPICE (Simulation Program with Integrated Circuit Emphasis) netlist format, which can include the PDN (Power Delivery Network) parasitic parameters of the chip C4 Bump and the transistor-level dynamic current source, where the transistor-level dynamic current source is used to regenerate current for each C4 Bump, so CPM is essential for the PDN time domain analysis of PKG (Package) and PCB (Printed Circuit Board). Therefore, the embodiment of the present disclosure controls the spectrum of the simulated dynamic current of CPM in the frequency domain through the target running code type, thereby improving the reliability of the simulation results obtained based on the simulated dynamic current.

[0047] In step S12, the simulation output circuit corresponding to the chip power consumption model is controlled to run with a target running code pattern to obtain a target simulation dynamic current corresponding to the chip power consumption model.

[0048] It is worth noting that the simulation output circuit (output circuit in the I / O circuit) can also be called a simulation signal output circuit. The CPM may include multiple simulation signal output circuits, and each simulation signal output circuit is powered by the same power supply terminal VDD. For each simulation signal output circuit, the simulation signal output circuit is composed of two transistors. When the simulation signal output circuit is in a working state, the gate of the transistor has a level input, thereby controlling the opening and closing of each transistor, and the opening and closing state of each transistor is different. For example, when the simulation signal output circuit is composed of two transistors, when the simulation signal output circuit is in a working state and the gate of the transistor has a level input, the first transistor is turned on when the second transistor is turned off, and the first transistor is turned off when the second transistor is turned on.

[0049] For example, two simulation signal output circuits with different circuit structures are taken as examples below: Reference Figure 5a, the simulated single-ended signal output circuit structure of GDDR6 (Graphics Double Data Rate, version 6, the sixth generation of GDDR video memory) includes: the source of transistor 1 is connected to the power supply VDDQ (operating voltage), the drain of transistor 1 is connected to the drain of transistor 2 and the load respectively, the source of transistor 2 is connected to VSSQ (common ground terminal voltage), the conduction state of transistor 1 is controlled by the digital signal PILL UP (pull-up), and the conduction state of transistor 2 is controlled by the digital signal PULL DOWN (pull-down). The working principle of the circuit includes: the digital signals PILL UP and PULL DOWN control the conduction of transistor 1 and transistor 2. When transistor 1 is in the on state and transistor 2 is in the off state, the current on VDDQ flows into the load through the current path 1; when transistor 1 is in the off state and transistor 2 is in the on state, the load is discharged through the current path 2. When the digital signal is in the high-low level switching process, transistor 1 and transistor 2 will be turned on at the same time, and the current on VDDQ will flow to the load and transistor 2 to the ground through transistor 1 at the same time. Δi t That is, it is the transient current generated by the power supply when multiple simulation signal output circuits work simultaneously.

[0050] Reference Figure 5b , the simulated differential signal output circuit structure of SERDES (SERializer DESerializer) includes: a first resistor R1, a second resistor R2, a transistor 3, a transistor 4 and a current source, the first end of the first resistor R1 and the first end of the second resistor R2 are connected to the power supply VCC, the second end of the first resistor R1 is respectively connected to the source and load of the transistor 3, the drain of the transistor 3 is connected to the first end of the current source, the second end of the second resistor R2 is respectively connected to the source and load of the transistor 4, and the drain of the transistor 4 is connected to the first end of the current source. Among them, the first resistor R1 and the second resistor R2 are both 50Ω, and the current source is 16mA. The working principle of this circuit is similar to the simulated single-ended signal output circuit of GDDR6, except that the digital signal that controls the on and off of the transistor is changed from a single-ended signal to a differential signal, and the output signal is also changed from a single-ended signal to a differential signal.

[0051] In step S13, simulation is performed according to the target simulated dynamic current to obtain a simulation result for characterizing power integrity.

[0052] The disclosed embodiment controls the energy peak of the simulated dynamic current of CPM in the frequency domain through the target running code, corresponding to the frequency corresponding to the highest anti-resonance point of the PDN curve, and performs simulation based on the simulated dynamic current to obtain simulation results for characterizing power integrity, thereby avoiding the situation where the peak-to-peak value of the simulated dynamic voltage may be smaller than the peak-to-peak value of the actual dynamic voltage, thereby improving the reliability and accuracy of the power integrity simulation results.

[0053] In order to facilitate those skilled in the art to better understand the current integrity simulation method provided by the present disclosure, the relevant steps involved in the power integrity simulation method are described in detail below with examples.

[0054] The disclosed embodiment can determine the target operating code pattern through two different methods, thereby controlling the simulation output circuit corresponding to the chip power consumption model to run with the target operating code pattern, obtaining the target simulation dynamic current corresponding to the chip power consumption model, and performing simulation according to the target simulation dynamic current to obtain a simulation result for characterizing power integrity.

[0055] Method 1: Adjust the initial running code pattern until the chip power consumption model runs the initial running code pattern to obtain the target simulated dynamic current, and the highest energy peak in the current spectrum diagram of the simulated dynamic current corresponds to the target frequency, so that the initial running code pattern is used as the target running code pattern.

[0056] In a possible embodiment, in step S11, determining the target running code pattern may further include the following steps: Determine the spectrum of the simulated dynamic current of the chip power consumption model when the simulated output circuit runs with the initial running code pattern; According to the frequency spectrum, a current spectrum diagram corresponding to the initial operation code pattern is determined; When the highest energy peak in the current spectrum diagram corresponds to the target frequency, the initial running code pattern is used as the target running code pattern, and the target running code pattern is a periodic code pattern, each period includes continuous digital 0s and continuous digital 1s, and the number of digital 0s and digital 1s is the same.

[0057] It is worth noting that the long 0 long 1 code pattern can control the spectrum of the simulated dynamic current of the chip power consumption model in the frequency domain. Therefore, the initial running code pattern in the embodiment of the present disclosure preferably selects the long 0 long 1 code pattern, thereby shortening the time for determining the target running code pattern.

[0058] For example, when the simulated output circuit runs an arbitrary length-0-length-1 code pattern, the spectrum of the simulated dynamic current of the CPM is determined, and the current spectrum diagram corresponding to the length-0-length-1 code pattern is determined. When the highest anti-resonance point 1 in the current spectrum diagram corresponds to the target frequency, the length-0-length-1 code pattern is used as the target operating code pattern.

[0059] In a possible embodiment, determining the target running code pattern may further include: When the highest energy peak in the current spectrum diagram does not correspond to the target frequency, the operation pattern of the simulation output circuit is adjusted until the maximum amplitude in the current spectrum diagram corresponding to the operation pattern corresponds to the target frequency, thereby obtaining the target operation pattern.

[0060] For example, when the simulated output circuit runs an arbitrary length-0-length-1 code pattern, the spectrum of the simulated dynamic current of the CPM is determined, and the current spectrum diagram corresponding to the long-0-length-1 code pattern is determined. When the highest anti-resonance point 1 in the current spectrum diagram does not correspond to the target frequency, the long-0-length-1 code pattern is adjusted until the highest anti-resonance point 1 in the current spectrum diagram of the adjusted long-0-length-1 code pattern corresponds to the target frequency, thereby obtaining the target operating code pattern.

[0061] For example, see Figure 6 , the first method for determining the target running code type provided by the embodiment of the present disclosure may include the following steps: In step S61 , a spectrum of a simulated dynamic current of a chip power consumption model when the simulated output circuit runs with an initial running code pattern is determined.

[0062] In step S62, a current spectrum diagram corresponding to the initial operation pattern is determined according to the spectrum.

[0063] In step S63, it is determined whether the highest energy peak in the current spectrum diagram corresponds to the target frequency. If so, step S64 is executed, and if not, step S65 is executed.

[0064] In step S64, the initial operation pattern is used as the target operation pattern.

[0065] In step S65, the operation pattern of the simulation output circuit is adjusted.

[0066] In one possible embodiment, see Figure 7 In step S61, determining the spectrum of the simulated dynamic current of the chip power consumption model when the simulated output circuit runs with the initial running code pattern may include the following steps: In step S71, the simulation output circuit is controlled to run with an initial running code pattern to obtain a first simulation dynamic current corresponding to the chip power consumption model, where the first simulation dynamic current is a time domain current.

[0067] In step S72, Fourier transform is performed on the first simulated dynamic current to obtain a second simulated dynamic current, where the second simulated dynamic current is a frequency domain current.

[0068] In step S73 , the frequency spectrum of the second simulated dynamic current is determined.

[0069] It is worth noting that in the time domain, ΔR d and Δi t They are not completely independent, so it is not possible to simply determine the Δu corresponding to the maximum dynamic voltage peak-to-peak value in the time domain. t , and after conversion to the frequency domain, the full link impedance Z is determined by CPM, PKG and PCB, and has nothing to do with the frequency domain dynamic current I fTherefore, in the embodiment of the present disclosure, the frequency domain current is obtained by Fourier transforming the time domain current, and the spectrum of the frequency domain current is determined. The current spectrum diagram corresponding to the initial operation pattern is determined according to the spectrum, and the target operation pattern is determined according to the spectrum diagram.

[0070] Because the first method requires continuous adjustment of the running code pattern to perform calculations until a target code pattern that meets the requirements is obtained, and the entire calculation process is complicated, the embodiment of the present disclosure also provides a second method for determining the target running code pattern.

[0071] Method 2: Determine the target code type based on the target frequency and maximum operating rate.

[0072] In one possible embodiment, see Figure 8 In step S11, determining the target running code type may include the following steps: In step S81, simulation is performed in the frequency domain to obtain a simulated power distribution network curve.

[0073] For example, simulation is performed in the frequency domain, and the following is obtained: Fig.10 The PDN curve diagram of the CPM+PKG+PCB full link is shown.

[0074] In step S82, a target frequency is determined according to the simulated power distribution network curve.

[0075] For example, determine Fig.10 The amplitude mag of the highest anti-resonance point m1 in the PDN curve diagram is 0.619, and the frequency corresponding to the highest anti-resonance point m1 is 79.28 MHz, which is recorded as P.

[0076] In step S83, the maximum operating rate of the simulation output circuit is determined.

[0077] It is worth noting that the maximum operating rate is the highest rate at which the output circuit can operate safely. In this embodiment, the maximum operating rate is denoted as M, in units of Mbps.

[0078] In step S84, a target operating code pattern is determined according to the target frequency and the maximum operating rate.

[0079] For example, the target operating code pattern is determined according to the target frequency P and the maximum operating rate M.

[0080] In one possible embodiment, see Fig. 9 In step S84, determining the target operating code pattern according to the target frequency and the maximum operating rate may include the following steps: In step S91, a target quantity is determined according to the target frequency and the maximum operating rate.

[0081] For example, the target number is determined according to the target frequency P and the maximum operating rate M.

[0082] In step S92, a target running code pattern is determined at least according to the target number, the target running code pattern being a periodic code pattern, each period including a target number of consecutive digital 0s and a target number of consecutive digital 1s.

[0083] It is worth noting that the long 0 and long 1 code pattern can control the spectrum of the simulated dynamic current of the chip power consumption model in the frequency domain. Therefore, the embodiment of the present disclosure determines the target number N based on the target frequency P and the maximum operating rate M, and determines the target operating code pattern based on the target number N combined with the binary digits 0 and 1.

[0084] For example, when the target number is 4, each cycle of the target running code pattern can be: 4 consecutive digital 0s followed by 4 consecutive digital 1s, such as 00001111; it can also be 4 consecutive digital 1s followed by 4 consecutive digital 0s, such as 11110000.

[0085] In a possible embodiment, in step S91, determining the target quantity according to the target frequency and the maximum operating rate may include the following steps: Substitute the target frequency and maximum operating rate into the calculation formula to obtain the target number; The calculation formula includes: N=M / 2P, N represents the number of targets, M represents the maximum operating rate, and P represents the target frequency.

[0086] For example, when the target frequency P corresponding to the highest anti-resonance point m1 in the PDN curve is 79.28MHz and the maximum operating rate M of the simulated output circuit is 6400Mbps, substitute P and M into the calculation formula: N=M / 2P=6400 / (2×79.28)≈40. Each cycle of the target operating pattern can be obtained as: 000000000000000000000000000000000000000001 ... You can also: 11111111111111111111111111111111111111111000000000000000000000000000000000000000.

[0087] The second method provided by the embodiment of the present disclosure is to calculate the target number of each binary digit in the target operating code pattern based on the target frequency and the maximum operating rate, thereby determining the target operating code pattern. The entire calculation process is simple, and the target operating code pattern can be determined quickly and accurately, which greatly shortens the determination time of the target operating code, and the result is reliable.

[0088] For example, all output circuits in CPM run the PRBS31 pattern simultaneously, and the following is obtained: Fig.11a The simulated dynamic current is shown in FIG. 1 , and all output circuits in the CPM simultaneously run the target operation pattern determined by the embodiment of the present disclosure, and the following is obtained: Fig.11b As shown in the simulated dynamic current, the peak-to-peak value of the simulated dynamic current corresponding to the PRBS31 code is 190mA, and the peak-to-peak value of the simulated dynamic current corresponding to the target running code is 170mA. It can be seen that the peak-to-peak value of the simulated dynamic current corresponding to the PRBS31 code is greater than the peak-to-peak value of the simulated dynamic current corresponding to the target running code.

[0089] The current spectrum of the simulated dynamic current corresponding to the PRBS31 code is as follows Fig.12a As shown, the current spectrum of the simulated dynamic current corresponding to the target running code is as follows Figure 12b As shown, it can be seen that the simulated dynamic current spectra obtained by the two methods provided in the embodiments of the present disclosure have a maximum energy peak at 80 MHz, which corresponds to the frequency corresponding to the highest anti-resonance point of the PDN.

[0090] The system-level power integrity simulation model is simulated according to the simulated dynamic current corresponding to the PRBS31 pattern, and the following is obtained: Fig.13a The simulated dynamic voltage shown in FIG. 1 has a peak-to-peak value of 15 mV. The system-level power integrity simulation model is simulated according to the simulated dynamic current of the corresponding target running code type, and the following is obtained: Fig.13b The simulated dynamic voltage shown has a peak-to-peak value of 70mV. It can be seen that the peak-to-peak value of the simulated dynamic voltage of C4 Bump obtained by the target operation code type determined by the two methods provided in the embodiment of the present disclosure is much larger than the peak-to-peak value of the simulated dynamic voltage obtained by the prior art, and the simulation result is closer to the actual worst scenario, which improves the reliability and accuracy of the simulation result.

[0091] Based on the same inventive concept, the present disclosure also provides a power integrity simulation model, see Fig.14 The power integrity simulation model includes a determination module 141 , a control module 142 and a simulation module 143 .

[0092] Among them, the determination module 141 is used to determine the target operating code type, and the target operating code type is used to control the energy peak of the simulated dynamic current of the chip power consumption model in the frequency domain corresponding to the target frequency, the target frequency includes the frequency corresponding to the target anti-resonance point, and the target anti-resonance point includes the highest anti-resonance point of the simulated power distribution network curve of the chip power consumption model in the frequency domain.

[0093] The control module 142 is used to control the simulation output circuit corresponding to the chip power consumption model to run with a target running code pattern to obtain a target simulation dynamic current corresponding to the chip power consumption model.

[0094] The simulation module 143 is used to perform simulation according to the target simulation dynamic current to obtain a simulation result for characterizing the power integrity.

[0095] The disclosed embodiment controls the energy peak of the simulated dynamic current of CPM in the frequency domain through the target running code, corresponding to the frequency corresponding to the highest anti-resonance point of the PDN curve, and performs simulation based on the simulated dynamic current to obtain simulation results for characterizing power integrity, thereby avoiding the situation where the peak-to-peak value of the simulated dynamic voltage may be smaller than the peak-to-peak value of the actual dynamic voltage, thereby improving the reliability and accuracy of the power integrity simulation results.

[0096] For example, the determination module 141 is used to perform simulation in the frequency domain to obtain a simulated power distribution network curve; Determine the target frequency based on the simulated power distribution network curve; Determine the maximum operating rate of the simulation output circuit; Determine the target operating pattern based on the target frequency and maximum operating rate.

[0097] For example, the determination module 141 is used to determine the target quantity according to the target frequency and the maximum operating rate; At least according to the target number, a target running code pattern is determined, the target running code pattern is a periodic code pattern, and each period includes a target number of consecutive digital 0s and a target number of consecutive digital 1s.

[0098] For example, the determination module 141 is used to substitute the target frequency and the maximum operating rate into a calculation formula to obtain a target quantity; The calculation formula includes: N=M / 2P, N represents the number of targets, M represents the maximum operating rate, and P represents the target frequency.

[0099] Exemplarily, the determination module 141 is further configured to determine a spectrum of a simulated dynamic current of a chip power consumption model when the simulated output circuit runs with an initial running code pattern; According to the frequency spectrum, a current spectrum diagram corresponding to the initial operation code pattern is determined; When the highest energy peak in the current spectrum diagram corresponds to the target frequency, the initial running code pattern is used as the target running code pattern, and the target running code pattern is a periodic code pattern, each period includes continuous digital 0s and continuous digital 1s, and the number of digital 0s and digital 1s is the same.

[0100] For example, the determination module 141 is further used to control the simulation output circuit to run with an initial running code pattern to obtain a first simulation dynamic current corresponding to the chip power consumption model, where the first simulation dynamic current is a time domain current; Performing Fourier transformation on the first simulated dynamic current to obtain a second simulated dynamic current, where the second simulated dynamic current is a frequency domain current; A frequency spectrum of the second simulated dynamic current is determined.

[0101] For example, when the highest energy peak in the current spectrum diagram does not correspond to the target frequency, the operating code pattern of the simulation output circuit is adjusted until the maximum amplitude in the current spectrum diagram corresponding to the operating code pattern corresponds to the target frequency, thereby obtaining the target operating code pattern.

[0102] Regarding the power integrity simulation device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0103] Based on the same inventive concept, the present disclosure also provides an electronic device, including: a memory having a computer program stored thereon; A processor is used to execute the computer program in the memory to implement the steps of the power integrity simulation method.

[0104] The disclosed embodiment controls the energy peak of the simulated dynamic current of CPM in the frequency domain through the target running code, corresponding to the frequency corresponding to the highest anti-resonance point of the PDN curve, and performs simulation based on the simulated dynamic current to obtain simulation results for characterizing power integrity, thereby avoiding the situation where the peak-to-peak value of the simulated dynamic voltage may be smaller than the peak-to-peak value of the actual dynamic voltage, thereby improving the reliability and accuracy of the power integrity simulation results.

[0105] Fig.15 1 is a block diagram of an electronic device 150 according to an exemplary embodiment. The electronic device 150 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a tablet device, a personal digital assistant, etc. Fig.15 As shown, the electronic device 150 may include: a processor 151 , a memory 152 . The electronic device 150 may also include one or more of a multimedia component 153 , an input / output (I / O) interface 154 , and a communication component 155 .

[0106] The processor 151 is used to control the overall operation of the electronic device 150 to complete all or part of the steps in the above-mentioned power integrity simulation method. The memory 152 is used to store various types of data to support the operation of the electronic device 150, and these data may include instructions for any application or method used to operate on the electronic device 150, as well as application-related data, such as dynamic simulation current, dynamic simulation voltage, spectrum, etc. The memory 152 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (Static Random Access Memory, referred to as SRAM), electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only Memory, referred to as EEPROM), erasable programmable read-only memory (Erasable Programmable Read-Only Memory, referred to as EPROM), programmable read-only memory (Programmable Read-Only Memory, referred to as PROM), read-only memory (Read-Only Memory, referred to as ROM), magnetic memory, flash memory, magnetic disk or optical disk. The multimedia component 153 may include a screen and an audio component. The screen may be, for example, a touch screen, and the audio component is used to output and / or input audio signals. For example, the audio component may include a microphone for receiving external audio signals. The received audio signal may be further stored in the memory 152 or sent through the communication component 155. The audio component also includes at least one speaker for outputting audio signals. The I / O interface 154 provides an interface between the processor 151 and other interface modules, and the above-mentioned other interface modules may be a keyboard, a mouse, a button, etc. These buttons may be virtual buttons or physical buttons. The communication component 155 is used for wired or wireless communication between the electronic device 150 and other devices. Wireless communication, such as Wi-Fi, Bluetooth, Near Field Communication (NFC), 2G, 3G, 4G, NB-IOT, eMTC, or other 5G, etc., or a combination of one or more of them, is not limited here. Therefore, the corresponding communication component 155 may include: a Wi-Fi module, a Bluetooth module, an NFC module, and the like.

[0107] In an exemplary embodiment, the electronic device 150 can be implemented by one or more application specific integrated circuits (ASIC), digital signal processors (DSP), digital signal processing devices (DSPD), programmable logic devices (PLD), field programmable gate arrays (FPGA), controllers, microcontrollers, microprocessors or other electronic components to perform the above-mentioned power integrity simulation method.

[0108] In another exemplary embodiment, a computer-readable storage medium including program instructions is also provided, and when the program instructions are executed by a processor, the steps of the above-mentioned power integrity simulation method are implemented. For example, the computer-readable storage medium can be the above-mentioned memory 152 including program instructions, and the above-mentioned program instructions can be executed by the processor 151 of the electronic device 150 to complete the above-mentioned power integrity simulation method.

[0109] In another exemplary embodiment, a computer program product is further provided. The computer program product includes a computer program executable by a programmable device. The computer program has a code portion for executing the above power integrity simulation method when executed by the programmable device.

[0110] The preferred embodiments of the present disclosure are described in detail above in conjunction with the accompanying drawings; however, the present disclosure is not limited to the specific details in the above embodiments. Within the technical concept of the present disclosure, a variety of simple modifications can be made to the technical solution of the present disclosure, and these simple modifications all fall within the protection scope of the present disclosure.

[0111] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present disclosure will not further describe various possible combinations.

[0112] In addition, various embodiments of the present disclosure may be arbitrarily combined, and as long as they do not violate the concept of the present disclosure, they should also be regarded as the contents disclosed by the present disclosure.

Claims

1. A power integrity simulation method, characterized in that: The power integrity simulation method comprises: Determine a target operating code pattern, wherein the target operating code pattern is used to control the energy peak of the simulated dynamic current of the chip power consumption model in the frequency domain to correspond to a target frequency, wherein the target frequency includes a frequency corresponding to a target anti-resonance point, and the target anti-resonance point includes a highest anti-resonance point of a simulated power distribution network curve of the chip power consumption model in the frequency domain; Controlling the simulation output circuit corresponding to the chip power consumption model to run with the target running code pattern to obtain the target simulation dynamic current corresponding to the chip power consumption model; A simulation is performed according to the target simulated dynamic current to obtain a simulation result for characterizing power integrity.

2. The power integrity simulation method according to claim 1, characterized in that: The determining of the target running code pattern comprises: Performing simulation in the frequency domain to obtain the simulated power distribution network curve; Determining the target frequency according to the simulated power distribution network curve; determining a maximum operating rate of the simulation output circuit; A target operating code pattern is determined according to the target frequency and the maximum operating rate.

3. The power integrity simulation method according to claim 2, characterized in that: The step of determining a target operating code pattern according to the target frequency and the maximum operating rate includes: Determining a target quantity according to the target frequency and the maximum operating rate; At least according to the target number, a target running code pattern is determined, the target running code pattern is a periodic code pattern, and each period includes the target number of consecutive digital 0s and the target number of consecutive digital 1s.

4. The power integrity simulation method according to claim 3, characterized in that: The step of determining a target quantity according to the target frequency and the maximum operating rate includes: Substituting the target frequency and the maximum operating rate into a calculation formula to obtain a target quantity; The calculation formula includes: N=M / 2P, N represents the target number, M represents the maximum operating rate, and P represents the target frequency.

5. The power integrity simulation method according to claim 1, characterized in that: The determining of the target running code pattern comprises: Determine the spectrum of the simulated dynamic current of the chip power consumption model when the simulated output circuit runs with the initial running code pattern; Determining a current spectrum diagram corresponding to the initial operation code pattern according to the spectrum; When the highest energy peak in the current spectrum diagram corresponds to the target frequency, the initial operating code pattern is used as the target operating code pattern, and the target operating code pattern is a periodic code pattern, each of the periods includes consecutive digital 0s and consecutive digital 1s, and the number of digital 0s and digital 1s is the same.

6. The power integrity simulation method according to claim 5, characterized in that: The determining of the spectrum of the simulated dynamic current of the chip power consumption model when the simulated output circuit runs with the initial running code pattern includes: Controlling the simulation output circuit to run with an initial running code pattern to obtain a first simulation dynamic current corresponding to the chip power consumption model, wherein the first simulation dynamic current is a time domain current; Performing Fourier transform on the first simulated dynamic current to obtain a second simulated dynamic current, where the second simulated dynamic current is a frequency domain current; A frequency spectrum of the second simulated dynamic current is determined.

7. The power integrity simulation method according to claim 5, characterized in that: The determining of the target running code pattern further comprises: When the highest energy peak in the current spectrum diagram does not correspond to the target frequency, the operating code pattern of the simulation output circuit is adjusted until the maximum amplitude in the current spectrum diagram corresponding to the operating code pattern corresponds to the target frequency, thereby obtaining the target operating code pattern.

8. A power integrity simulation device, characterized in that: include: A determination module, used to determine a target operating code pattern, wherein the target operating code pattern is used to control the energy peak of the simulated dynamic current of the chip power consumption model in the frequency domain to correspond to a target frequency, wherein the target frequency includes a frequency corresponding to a target anti-resonance point, and the target anti-resonance point includes a highest anti-resonance point of a simulated power distribution network curve of the chip power consumption model in the frequency domain; A control module, used for controlling the simulation output circuit corresponding to the chip power consumption model to run with the target running code pattern, so as to obtain the target simulation dynamic current corresponding to the chip power consumption model; The simulation module is used to simulate the target dynamic current to obtain a simulation result for characterizing the power integrity.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps of the power integrity simulation method described in any one of claims 1 to 7 are implemented.

10. An electronic device, characterized in that: include: a memory having a computer program stored thereon; A processor, configured to execute the computer program in the memory to implement the steps of the power integrity simulation method according to any one of claims 1 to 7.

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