Circuit layout inspection method and circuit layout inspection system
The circuit layout inspection method and system address the issue of unnecessary mask remaking by checking layout patterns and spacings, reducing manufacturing costs through compliance with preset layout restrictions.
Patent Information
- Application Number
- CN202310734159.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-20
- Publication Date
- 2024-12-20
AI Technical Summary
The need to remake masks during the manufacturing of integrated circuits due to structural violations after engineering change orders (ECOs) and optical proximity correction (OPC) increases manufacturing costs.
A circuit layout inspection method and system that checks for layout patterns and their spacings to ensure compliance with preset distances, avoiding the need to remake masks by confirming the existence and enclosure of specific patterns and their boundaries, thereby adhering to re-tape out (RTO) rules.
Reduces the frequency of mask remaking, thereby saving manufacturing costs by ensuring that layout designs meet the necessary constraints without requiring re-manufacturing.
Smart Images
Figure CN119167864A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a circuit layout inspection system, and more particularly to a circuit layout inspection method and system which can avoid the need to re-manufacture masks during the process of manufacturing integrated circuits. Background Art
[0002] During the chip design phase, integrated circuits can use engineering change orders (ECOs) to modify the related operations of functional units in the integrated circuit. On the other hand, with the development of semiconductor technology, the size of transistors is getting smaller and smaller, making it difficult for the pattern achieved by photolithography to be completely consistent with the expected pattern. To solve the above problems, optical proximity correction (OPC) can be used to correct or adjust the mask to correct inaccurate patterns. In practice, integrated circuits that have undergone ECO need to undergo OPC. At this stage, the re-tape out (RTO) rule can be used to confirm that the masks corresponding to the layout patterns in the integrated circuits that have undergone ECO need to be remade due to OPC. In some cases, structures that have not been changed after ECO may still violate the re-tape rule due to OPC, and the corresponding masks must be remade or corrected, resulting in an increase in overall manufacturing costs. Summary of the invention
[0003] In some implementations, one of the purposes of the present disclosure is (but not limited to) to provide a circuit layout inspection method and system that can avoid remaking masks, so as to improve the deficiencies of the prior art.
[0004] In some embodiments, a circuit layout inspection method includes the following operations: confirming whether only at least one of a first layout pattern or a second layout pattern exists in a first area extending outward from a first layout pattern, wherein the first layout pattern corresponds to a first logic gate array unit, and the second layout pattern corresponds to a filling unit or a second logic gate array unit; confirming whether a first pattern in the first layout pattern is enclosed by a second pattern in the first layout pattern and whether the spacing between all boundaries of the first pattern and all boundaries of the second pattern is not less than a first preset distance, wherein the first pattern corresponds to an electrical connection layer, and the second pattern corresponds to a metal layer; and if only at least one of the first layout pattern or the second layout pattern exists in the first area, and if the first pattern is enclosed by the second pattern and the spacing between all boundaries of the first pattern and all boundaries of the second pattern is not less than the first preset distance, generating data indicating a layout design of an integrated circuit.
[0005] In some embodiments, the circuit layout inspection system includes a memory circuit and a processor circuit. The memory circuit is used to store at least one computer program code. The processor circuit is used to execute the at least one computer program code to perform the following operations: confirm whether only at least one of the first layout pattern or the second layout pattern exists in a first area extending outward from a first layout pattern, wherein the first layout pattern corresponds to a first logic gate array unit, and the second layout pattern corresponds to a filling unit or a second logic gate array unit; confirm whether a first pattern in the first layout pattern is enclosed by a second pattern in the first layout pattern and whether the intervals between all boundaries of the first pattern and all boundaries of the second pattern are not less than a first preset distance, wherein the first pattern corresponds to an electrical connection layer, and the second pattern corresponds to a metal layer; and if only at least one of the first layout pattern or the second layout pattern exists in the first area, and if the first pattern is enclosed by the second pattern and the intervals between all boundaries of the first pattern and all boundaries of the second pattern are not less than the first preset distance, generate data indicating the layout design of an integrated circuit.
[0006] The features, implementation and technical effects of the present disclosure are described in detail below with reference to the accompanying drawings as preferred embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Figure 1 A schematic diagram of a circuit layout checking system according to some embodiments of the present disclosure;
[0008] Figure 2 A flow chart of a circuit layout checking method drawn according to some embodiments of the present disclosure;
[0009] Figure 3A A schematic diagram of a layout design drawn according to an embodiment of the present disclosure;
[0010] Figure 3B According to the embodiment of the present disclosure, Figure 3A A schematic diagram of a layout pattern in; and
[0011] Figure 4 A schematic diagram of a layout design according to some embodiments of the present disclosure.
[0012] Explanation of symbols
[0013] 100: Circuit layout inspection system
[0014] 110: Memory Circuit
[0015] 120: Processor circuit
[0016] 130: At least one input / output interface
[0017] 200: Circuit layout inspection method
[0018] 300,400: Layout design
[0019] DI,DO: Data
[0020] FC: Layout Pattern
[0021] FNC: Layout Pattern
[0022] GDCAP: Decoupling Unit
[0023] GFILL: Filling Cell
[0024] GP1~GP6: Layout pattern
[0025] P1~P2: Pattern
[0026] S210, S220, S230, S240: Operation
[0027] SP1, SP2: Region
[0028] d1, d2: preset distance DETAILED DESCRIPTION
[0029] All words used herein have their ordinary meanings. The definitions of the above words in commonly used dictionaries and the use examples of any words discussed herein in the content of this disclosure are only illustrative and should not limit the scope and meaning of this disclosure. Similarly, this disclosure is not limited to the various embodiments shown in this specification.
[0030] As used herein, "coupled" or "connected" may refer to two or more elements making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, or may refer to two or more elements operating or acting on each other. As used herein, the term "circuit" may be a device composed of at least one transistor and / or at least one active and passive element connected in a certain manner to process signals.
[0031] As used herein, the term "and / or" includes any combination of one or more of the listed associated items. In this article, the words first, second, third, etc. are used to describe and distinguish each element. Therefore, the first element in this article can also be called the second element without departing from the original intention of the present disclosure. For ease of understanding, similar elements in the various drawings will be designated with the same reference numerals.
[0032] Figure 1A schematic diagram of a circuit layout checking system 100 according to some embodiments of the present disclosure is shown. In some embodiments, the circuit layout checking system 100 can automatically check whether a layout design for manufacturing an integrated circuit meets a preset layout restriction to avoid re-manufacturing masks, thereby saving overall manufacturing costs.
[0033] In some embodiments, the circuit layout checking system 100 includes a memory circuit 110, a processor circuit 120, and at least one input / output interface 130. In some embodiments, the processor circuit 120 may be, but is not limited to, a central processing unit (CPU), an application-specific integrated circuit (ASIC), a multiprocessor, a distributed processing system, or a suitable processing unit. Various circuits or units used to implement the processor circuit 120 are all within the scope of the present disclosure.
[0034] The memory circuit 110 can store at least one computer program code that can be used to assist in the design of the integrated circuit. For example, the at least one computer program code can be encoded via a plurality of instruction sets, wherein the plurality of instruction sets are used to check whether a plurality of layout patterns in the integrated circuit meet the aforementioned preset layout restrictions. The processor circuit 120 can execute the at least one computer program code stored in the memory circuit 110, and a plurality of operations for checking the layout patterns can be automatically performed. In some embodiments, the aforementioned at least one computer program code can be integrated with existing computer-aided design tools. In some embodiments, the memory circuit 110 can be a non-transitory computer-readable storage medium that stores instructions for executing Figure 2 In some embodiments, the non-transitory computer-readable storage medium may include, but is not limited to, semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk and / or optical disk. In some embodiments, the aforementioned optical disk may include, but is not limited to, compact disk-read only memory (CD-ROM), compact disk-rewritable (CD-R / W) and / or digital video disk (DVD).
[0035] The at least one input / output interface 130 may receive a plurality of data and / or commands, wherein the data and / or commands may be issued by a device controlled by a circuit designer or layout designer. Thus, the circuit layout checking system 100 may be controlled via commands received by the at least one input / output interface 130. In some embodiments, the at least one input / output interface 130 may include a screen configured to display the status of program code execution. In some embodiments, the at least one input / output interface 130 may include, but is not limited to, a graphical user interface, a keyboard, a mouse, a trackball, a touch screen, a cursor arrow key, or a combination thereof, to communicate information and a plurality of commands to the processor circuit 120.
[0036] In some embodiments, the processor circuit 120 may receive data DI via at least one input / output interface 130, wherein the data DI is used to indicate the layout design of the integrated circuit. The processor circuit 120 may execute at least one computer program code in the memory circuit 110 to parse the data DI to obtain multiple layout patterns in the data DI and perform the following steps. Figure 2 , to check whether the multiple layout patterns in the data DI meet the preset layout constraints. If the multiple layout patterns in the data DI all meet the preset layout constraints, the processor circuit 120 can output the data DI as data DO and store the data DO in the memory circuit 110. In this way, the circuit designer or layout designer can obtain the data DO through at least one input-output interface 130 and provide the data DO to a wafer foundry to manufacture the integrated circuit.
[0037] In some embodiments, the “layout pattern” or “pattern” mentioned herein may generally refer to a planar geometric shape used in computer-aided design tools, which can be used to present the layout design of an integrated circuit and corresponds to metal layers, electrical connection layers, oxide layers and / or semiconductor layers, etc., that constitute various components in the integrated circuit.
[0038] Figure 2 FIG. 2 is a flow chart of a circuit layout checking method 200 according to some embodiments of the present disclosure. In some embodiments, the circuit layout checking method 200 may be, but is not limited to, Figure 1 The circuit layout checking system 100 performs.
[0039] In operation S210, it is confirmed whether only one of the first layout pattern or the second layout pattern exists in the first region extending outward from the first layout pattern. The first layout pattern corresponds to a first logic gate array cell, and the second layout pattern corresponds to a filler cell or a second logic gate array cell. If only the first layout pattern and / or the second layout pattern exists in the first region, operation S220 is performed. Alternatively, if other layout patterns exist in the first region, operation S240 is performed.
[0040] To illustrate operation S210, refer to Figure 3A , Figure 3A It is a schematic diagram of a layout design 300 drawn according to an embodiment of the present disclosure. Figure 3A The layout design 300 shown may be a portion of a layout pattern in an integrated circuit. Figure 1The processor circuit 120 can obtain information of multiple layout patterns in the layout design 300 by parsing the data DI. For example, the layout design 300 includes multiple layout patterns GP1 and GP2 corresponding to multiple logic gate array cells, multiple layout patterns FC corresponding to multiple filling cells, and multiple layout patterns FNC corresponding to multiple function cells. In some embodiments, the aforementioned logic gate array cell may be a programmable logic gate array cell used to perform an engineering change order (ECO). For example, the logic gate array cell may include at least one standard cell circuit, which may be implemented via a digital circuit that can perform one or more logic functions. Before performing ECO, the inputs and outputs of these logic gate array cells will not be coupled to the aforementioned multiple function cells. After performing ECO, the inputs and outputs of some logic gate array cells may be adjusted to be coupled to nodes in multiple function cells to modify or adjust the operation and / or signal transmission of these function cells to meet the design requirements. In some embodiments, the logic gate array cell can be configured to operate as a decap cell (labeled as GDCAP in the figure) of a capacitor, which can be used to maintain voltage stability in the system. In some embodiments, the logic gate array cell can be configured to operate as a fill cell (labeled as GFILL in the figure), which can be used to increase continuity between power rails. On the other hand, the fill cells corresponding to the plurality of layout patterns FC can be, but are not limited to, fill cells implemented by standard cell circuits or fill cells implemented via logic gate array cells. In some embodiments, the plurality of functional cells corresponding to the plurality of layout patterns FNC can be main circuits in an integrated circuit, which can be used to perform a specific logic operation.
[0041] like Figure 3AAs shown, in an area SP1 (drawn with dotted lines) extending outward from the plurality of layout patterns GP1 and GP2, only the plurality of layout patterns GP1, GP2 and FC corresponding to the logic gate array unit and / or the filling unit exist. In other words, the plurality of layout patterns FNC corresponding to the functional unit are not located in the area SP1. In this way, the plurality of layout patterns FNC can be sufficiently spaced from the plurality of layout patterns GP1 and GP2 (which correspond to the logic gate array units used for ECO) to avoid modifying the mask (which is caused by violating the re-line-out (RTO) rule after ECO). In some embodiments, the area SP1 is an area formed by extending outward from all boundaries of the layout pattern GP1 and / or the layout pattern GP2 by a preset distance d1. In this example, since the plurality of layout patterns GP1 and GP2 are arranged adjacent to each other (and the two are in contact with each other), the plurality of layout patterns GP1 and GP2 can be combined and regarded as the same layout pattern, and the area SP1 is defined by extending outward from all boundaries of this layout pattern by a preset distance d1. In other embodiments, if the plurality of layout patterns GP1 and GP2 are not arranged adjacent to each other, a first region may be defined by extending a preset distance d1 outward from all boundaries of the layout pattern GP1, and a second region may be defined by extending a preset distance d1 outward from all boundaries of the layout pattern GP2, and it is respectively checked whether only layout patterns corresponding to filling units and / or logic gate array units exist in the first region and the second region.
[0042] In some embodiments, the preset distance d1 may be between about 0.19 micrometers (μm) and 0.3 micrometers. In some embodiments, the preset distance d1 may be about 0.25 micrometers or 0.24 micrometers. The above values of the preset distance d1 are for example only, and the values may be set according to the semiconductor process, and the present disclosure is not limited thereto. In some embodiments, the value of the preset distance d1 may be ±5%, ±10% and / or ±20% of the above-mentioned numerical range or specific value.
[0043] Continue to refer to Figure 2 In operation S220, it is confirmed whether the first pattern in the first layout pattern is enclosed by the second pattern in the first layout pattern and whether the intervals between all boundaries of the first pattern and all boundaries of the second pattern are not less than (i.e., greater than or equal to) a predetermined distance. The first pattern corresponds to the electrical connection layer, and the second pattern corresponds to the metal layer.
[0044] To illustrate operation S220, refer to Figure 3B , Figure 3B According to the embodiment of the present disclosure, Figure 3A Schematic diagram of the layout pattern GP1. Figure 3B The layout pattern shown can be Figure 3AIn some embodiments, the layout pattern GP1 may include a pattern P1 corresponding to an electrical connection layer and a pattern P2 corresponding to a metal layer. In some embodiments, the electrical connection layer may include a connection layer for connecting to a transistor, such as a contact layer. In some embodiments, the electrical connection layer may include a connection layer for connecting to different metal layers, such as a via. In some embodiments, the metal layer may be a wiring layer adjusted in ECO, which may be the topmost metal layer. For example, the wiring layer may be a first metal layer (often labeled M1 in layout software) or a second metal layer (often labeled M2 in layout software).
[0045] As previously described, the input or output of the logic gate array unit used for ECO will not be coupled to the functional unit. After performing ECO, the input or output of some logic gate array units used for ECO may be adjusted and coupled to the functional unit. The above adjustment is usually achieved by modifying the layout position and / or connection relationship of the above-mentioned metal layer and the electrical connection layer. By checking the pattern P1 and the pattern P2 corresponding to the electrical connection layer and the metal layer respectively through operation S220, it is possible to avoid the above adjustment from violating the re-line rule. In some embodiments, the inspection conditions set in operation S220 are mainly applicable to the electrical connection layer located at the line end of the metal layer, but the present disclosure is not limited thereto.
[0046] like Figure 3B As shown, pattern P1 is enclosed by pattern P2, and the interval between each boundary of pattern P1 and each boundary of pattern P2 is greater than or equal to the preset distance d2. In some embodiments, the preset distance d2 may be approximately between 0.004 microns and 0.02 microns. In some embodiments, in some embodiments, the preset distance d2 may be approximately 0.015 microns or 0.005 microns. The above-mentioned numerical value of the preset distance d2 is used for example, and the numerical value may be set according to the semiconductor process, and the present disclosure is not limited to this. In some embodiments, the numerical value of the preset distance d2 may be ±5%, ±10% and / or ±20% of the numerical range or specific numerical value mentioned above. If the layout design 300 can meet the inspection conditions set by operation S210 and operation S220 (equivalent to the preset layout restrictions mentioned above), it can be ensured that the layout design 300 does not need to remake the mask after ECO, or the number of masks to be remade is reduced. In this way, the overall manufacturing cost can be saved. Similarly, it is also necessary to Figure 3A The inspection of operation S220 is performed on the layout pattern GP2 in FIG.
[0047] Continue to refer to Figure 2In operation S230, data indicating the layout design of the integrated circuit is generated. In operation S240, the layout design is corrected. For example, if the layout design 300 meets the preset layout constraints set in operation S210 and operation S220, it means that each layout pattern in the layout design 300 meets the preset layout constraints. Under this condition, the current layout design 300 can be stored as data DO to provide the data DO to a wafer foundry to manufacture an integrated circuit corresponding to the layout design 300. Alternatively, if the layout design 300 does not meet the preset layout constraints of operation S210 or operation S220, the layout design 300 can be corrected by an automated routing tool or by notifying the layout designer, and the corrected layout design 300 can be checked again.
[0048] In some embodiments, the above examples mainly illustrate the layout check performed in the process of filling the layout pattern corresponding to the logic gate array unit in the layout design 300, but the present disclosure is not limited to this. In some embodiments, if the layout design corresponding to the data DI is filled with the logic gate array unit, before performing ECO, the circuit layout check method 200 may also include the following operations: selecting a corresponding layout pattern from a plurality of third layout patterns, wherein a fourth layout pattern does not exist in a second area extending outward from the corresponding layout pattern, the third layout patterns respectively correspond to a plurality of third logic gate array units, and the fourth layout pattern corresponds to a functional unit; and modifying the corresponding layout pattern to perform an engineering change command. To illustrate the above operations, refer to Figure 4 , Figure 4 It is a schematic diagram of a layout design 400 drawn according to some embodiments of the present disclosure. Figure 1 The processor circuit 120 can obtain information of multiple layout patterns in the layout design 400 by parsing the data DI. For example, different from the layout design 300, the layout design 400 further includes multiple layout patterns GP3-GP6 corresponding to logic gate array units (which are configured as decoupling units, labeled as GDCAP) and more layout patterns FNC corresponding to functional units.
[0049] In this example, multiple layout patterns GP1-GP6 all correspond to logic gate array units, and multiple layout patterns GP3-GP6 are arranged adjacent to layout patterns corresponding to functional units. To avoid the distance between the logic gate array unit and the functional unit used in ECO being too close, the above operation can be used to select a suitable logic gate array unit to avoid violating the re-line rule. For example, Figure 4 In the example of FIG. 1 , since there is no layout pattern corresponding to the functional unit in the region SP2 extending outward from the layout pattern GP1, the layout pattern GP1 can be selected for ECO. The region SP2 can be a region formed by extending outward from all boundaries of the layout pattern GP1 by a distance d1 (similar to Figure 3A Thus, since there is a sufficient distance between the layout pattern GP1 corresponding to the logic gate array unit and the layout pattern corresponding to the functional unit, the layout pattern GP1 corrected by ECO does not violate the re-line rule, so re-manufacturing of the mask can be avoided. Then, after performing ECO, the processor circuit 120 can output the corrected layout design 400 as data DO (i.e., operation S230).
[0050] In some embodiments, Figure 4 The operation may be performed before operation S230, and may be performed in parallel with operation S210 and operation S220, but the present disclosure is not limited thereto. The description of the multiple operations of the above-mentioned circuit layout inspection method 200 can refer to the aforementioned multiple embodiments, so it will not be repeated here. The above-mentioned multiple operations are only examples and are not limited to being performed in the order in this example. Without violating the operating mode and scope of each embodiment of the present disclosure, the various operations under the circuit layout inspection method 200 can be appropriately increased, replaced, omitted or performed in a different order. Alternatively, one or more operations under the circuit layout inspection method 200 can be performed simultaneously or partially simultaneously.
[0051] In summary, the circuit layout checking method and system provided by some embodiments of the present disclosure can check whether the layout design meets the preset layout restrictions, so as to avoid remaking the mask and thus save ECO cost and overall manufacturing cost.
[0052] Although the embodiments of the present disclosure are described above, these embodiments are not intended to limit the present disclosure. Those skilled in the art may make changes to the technical features of the present disclosure based on the explicit or implicit contents of the present disclosure. All these changes may fall within the scope of patent protection sought by the present disclosure. In other words, the scope of patent protection of the present disclosure shall be based on what is defined in the claims of this specification.
Claims
1. A circuit layout inspection method, comprising: confirming whether only one of the first layout pattern or the second layout pattern exists in a first region extending outward from a first layout pattern, wherein the first layout pattern corresponds to a first logic gate array unit, and the second layout pattern corresponds to a filling unit or a second logic gate array unit; confirming whether a first pattern in the first layout patterns is enclosed by a second pattern in the first layout patterns and whether intervals between all boundaries of the first pattern and all boundaries of the second pattern are not less than a first predetermined distance, wherein the first pattern corresponds to an electrical connection layer, and the second pattern corresponds to a metal layer; and If only at least one of the first layout pattern or the second layout pattern exists in the first area, and if the first pattern is enclosed by the second pattern and the intervals between all boundaries of the first pattern and all boundaries of the second pattern are not less than the first preset distance, data indicating a layout design of an integrated circuit is generated. 2 . The circuit layout inspection method as claimed in claim 1 , wherein the electrical connection layer comprises a contact layer or a through hole. 3 . The circuit layout checking method as claimed in claim 1 , wherein each of the first logic gate array unit and the second logic gate array unit is a programmable logic gate array unit for an engineering change command. 4 . The circuit layout inspection method according to claim 1 , wherein the first area is an area formed by extending outwards from all boundaries of the first layout pattern by a second predetermined distance. 5 . The circuit layout inspection method as claimed in claim 4 , wherein the second predetermined distance is between 0.19 micrometers and 0.3 micrometers. 6 . The circuit layout inspection method as claimed in claim 1 , wherein the first predetermined distance is between 0.004 μm and 0.02 μm. 7 . The circuit layout checking method as claimed in claim 1 , wherein the metal layer is a wiring layer adjusted in an engineering change order.
8. The circuit layout inspection method according to claim 1, further comprising: Select a corresponding layout pattern from a plurality of third layout patterns, wherein a fourth layout pattern does not exist in a second region extending outward from the corresponding layout pattern, the plurality of third layout patterns respectively correspond to a plurality of third logic gate array units, and the fourth layout pattern corresponds to a functional unit; and The corresponding layout pattern is modified to perform an engineering change order. 9 . The circuit layout inspection method according to claim 8 , wherein the second area is an area extending outwards from all boundaries of the fourth layout pattern by a second predetermined distance.
10. A circuit layout inspection system, comprising: a memory circuit for storing at least one computer program code; and a processor circuit for executing the at least one computer program code to: confirming whether only one of the first layout pattern or the second layout pattern exists in a first region extending outward from a first layout pattern, wherein the first layout pattern corresponds to a first logic gate array unit, and the second layout pattern corresponds to a filling unit or a second logic gate array unit; confirming whether a first pattern in the first layout patterns is enclosed by a second pattern in the first layout patterns and whether intervals between all boundaries of the first pattern and all boundaries of the second pattern are not less than a first predetermined distance, wherein the first pattern corresponds to an electrical connection layer, and the second pattern corresponds to a metal layer; and If only the first layout pattern or the second layout pattern exists in the first area, and if the first pattern is enclosed by the second pattern and the intervals between all boundaries of the first pattern and all boundaries of the second pattern are not less than the first preset distance, data indicating a layout design of an integrated circuit is generated.