Data storage system, data storage method and photoelectric memory

Abstract

The invention relates to a data storage system, a data storage method and a photoelectric memory. A plurality of stacked storage pages are arranged in the transparent material, and each storage page comprises a plurality of data storage units in an array form. The data storage cell has an anode and a cathode and an electrochromic layer therebetween. The data stored in the data storage unit is set to be different by setting the electrochromic layers of the data storage unit to be different. The data of the data storage unit is extracted by using the voltage applied between the anode and the cathode of the data storage unit, and on the premise of the applied voltage, different electrochromic layers display different colors and transmit different data; and the color displayed by the electrochromic layer of the data storage unit is used for representing the stored data.

Description

Technical Field

[0001] The present invention mainly relates to the technical field of data storage, and more specifically, to a data storage system and a data storage method as well as an optoelectronic storage device in the data storage link. Background Art

[0002] When it comes to the basic building blocks of transistors used in the traditional memory field, there are three main and almost irreconcilable defects. The first drawback is the limited capacity of semiconductor transistors. The number of bits that can be expressed by each memory cell is very limited and is limited by the specific number of layers of the floating gate (such as SLC, MLC, TLC, etc.).

[0003] The second drawback of traditional memory is that data operations generate high heat. Conventional data copying or reading and writing data can give people a hot touch, and the larger the amount of data or the faster the operation speed, the stronger the heat sensation.

[0004] The biggest drawback or threat is actually the lack of security in data storage and the easy loss of data. For example, although the storage capacity of single-layer or multi-layer floating gate flash memory is getting larger and larger, non-volatile accumulators mostly use charge to express data and the inherent characteristics of charge determine that it will also leak. Usually, NAND FLASH storage cells will lose most of their charge in about a few years or decades without operation. This is a problem to be solved. Summary of the invention

[0005] The present application relates to a data storage method, characterized in that it includes: arranging a plurality of stacked storage pages in a transparent material, each storage page including a plurality of data storage units in an array form, the data storage unit having an anode and a cathode and an electrochromic layer located therebetween, the electrochromic layers of the data storage unit are set to be different so that the data stored in the data storage unit is set to be different; the data stored in the data storage unit is extracted by the voltage applied between the anode and the cathode thereof, and based on the applied voltage, different electrochromic layers display different colors and transmit different data; the data stored in the data storage unit is represented by the color displayed by the electrochromic layer of the data storage unit.

[0006] In the above data storage method, the transparent material at least includes a transparent semiconductor wafer or a transparent ceramic wafer or a glass or acrylic plate.

[0007] In the above data storage method, the electrochromic layer includes any one of a single inorganic electrochromic material, a single organic electrochromic material, a mixture of two or more organic electrochromic materials, and a dopant of an inorganic and organic electrochromic material. The inorganic electrochromic material contains tungsten trioxide WO3 or its derivatives. The organic electrochromic material contains any one of tetrathiafulvalene, viologen compounds, polythiophenes and their derivatives, metal phthalocyanine compounds or terpyridine derivatives and complexes. The anode and cathode are selected from transparent conductive materials. The anode and cathode are selected from ITO (tin-doped indium oxide) materials.

[0008] The above-mentioned data storage method sets the electrochromic layer in different ways, including: different materials are selected for the electrochromic layer; when the electrochromic layer uses a mixture of multiple organic electrochromic materials, the mixing ratios of the various organic electrochromic materials are adjusted to provide different electrochromic layers; or when the electrochromic layer is doped with inorganic and organic electrochromic materials, the doping concentrations of the inorganic and organic electrochromic materials are adjusted to provide different electrochromic layers.

[0009] In the above data storage method, the anodes of all the data storage units in any storage page are interconnected, and the cathodes of all the data storage units in any storage page are interconnected.

[0010] In the above data storage method, in any storage page, the anodes of adjacent data storage units are connected to each other through a conductive material until the anodes of all data storage units in any storage page are interconnected.

[0011] In the above data storage method, in any storage page, the cathodes of adjacent data storage units are connected to each other through a conductive material until the cathodes of all data storage units in any storage page are interconnected.

[0012] In the above data storage method, in any storage page, all data storage units share a common anode layer and all data storage units share a common cathode layer, but the electrochromic layers of different data storage units are discrete from each other.

[0013] In the above data storage method, when a data storage unit of any storage page is applied with voltage and enters a read state for data extraction, the data storage units of the remaining other storage pages are prohibited from entering a read state, that is, a series of storage pages at different levels or layers are read in time-sharing (for example, reading is staggered in time).

[0014] In the above data storage method, voltages are applied to the data storage units of multiple storage pages in sequence to sequentially enter the read state for data extraction. When any storage page is in the read state, other storage pages are prohibited from entering the read state.

[0015] In the above-mentioned data storage method, multiple data storage units arranged on the plane or layer of any storage page serve as a set of pixel points of any storage page, and each data storage unit serves as an independent pixel point; an image containing all pixel points of any storage page serves as parallel data read in parallel at one time, that is, the data of an entire storage page is read at a time with the storage page as the minimum reading unit.

[0016] The above-mentioned data storage method selects multiple data storage units of multiple storage pages, provides corresponding data as specimens under different color renderings of the data storage units, and thus trains a neural network; and uses the trained neural network to infer the data represented by the data storage units of other storage pages under their own color rendering or coloring conditions.

[0017] The present application relates to a photoelectric memory, characterized in that it comprises: a transparent material, a plurality of stacked storage pages are arranged in the transparent material, the storage page comprises a plurality of data storage units in an array form; each data storage unit is equipped with an anode, a cathode and an electrochromic layer, the electrochromic layer is located between the anode and the cathode, and when a voltage is applied between the anode and the cathode, the electrochromic layer develops color (or colors), and when the voltage is removed between the anode and the cathode, the electrochromic layer fades, and the data stored in the data storage unit is set to be different by setting the electrochromic layer of the data storage unit to be different;

[0018] The data stored in the data storage unit is extracted using the voltage applied between its anode and cathode. Based on the applied voltage, different electrochromic layers display different colors and transmit different data, so that the color displayed by the electrochromic layer of the data storage unit represents the data stored therein.

[0019] The above-mentioned photoelectric memory selects multiple data storage units of multiple storage pages, and provides corresponding data as specimens under different color renderings of the data storage units to train a neural network; and uses the trained neural network to infer the data represented by the data storage units of other storage pages under their own color rendering or coloring conditions.

[0020] The present application relates to a data storage system, characterized in that it comprises: a plurality of stacked storage pages are arranged in a transparent material, each storage page comprises a plurality of data storage units in an array form; an anode, a cathode and an electrochromic layer are provided for each data storage unit, the electrochromic layer is located between the anode and the cathode and the electrochromic layer develops color when a voltage is applied between the anode and the cathode, and fades when the voltage is removed between the anode and the cathode, and the data stored in the data storage unit is set to be different by setting the electrochromic layer of the data storage unit to be different;

[0021] A power supply module provides a voltage between the anode and cathode of each data storage unit. The data stored in the data storage unit is extracted using the voltage applied between the anode and cathode. Based on the applied voltage, different electrochromic layers display different colors and transmit different data, so that the color displayed by the electrochromic layer of the data storage unit represents the data stored therein;

[0022] A computer is provided with a camera, and multiple data storage units of multiple storage pages are selected. The camera photographs different colors of the data storage units and matches corresponding data as a specimen for each color. A neural network is trained by the computer; and the trained neural network is used to infer the data represented by the data storage units of other storage pages under their own color conditions.

[0023] In the above data storage system, a transparent material is used to divide a plurality of storage pages, and all data storage units arranged on the plane of any storage page serve as a set of pixels of the storage, and each data storage unit represents a pixel.

[0024] In the above data storage system, two pixels belonging to any two different storage pages but with the same address are set to be non-overlapping (ie, non-overlapping in a direction perpendicular to the storage page or the transparent material).

[0025] In the above data storage system, two pixels belonging to any two different storage pages but with the same address are set to overlap up and down (i.e. overlap each other in a direction perpendicular to the storage page or transparent material). At this time, the physical structures of different storage pages are basically the same, because any pixel with a certain address has a fixed physical position on the storage page, which will bring great convenience in the production and preparation process of the memory. The process conditions for preparing the upper layer of storage pages and the preparation of the next layer of storage pages will be roughly the same, thus bringing great convenience to the production and manufacturing of the memory. On the contrary, if two pixels with the same address are set to be non-overlapping, it is necessary to consider the physical offset of the pixels with the same address, for example, there is an offset between the physical positions of two pixels with the same address belonging to any two different storage pages.

[0026] In the above data storage system, the captured image containing all pixels of each storage page is used as parallel data to be read in parallel at one time, and the data of an entire storage page is read at a time with the storage page as the minimum reading unit (for example, the interconnected anodes and cathodes of all data storage units of the entire storage page only need to be energized once when reading data, no matter how many pixels there are in the storage page).

[0027] In the above-mentioned data storage system, after the data corresponding to the captured image of each pixel point of each storage page is read, the data of the next pixel point is read, and each time a single pixel point is used as the minimum reading unit and the data of only one pixel point is read at a time in a serial manner (for example, the interconnected anodes and interconnected cathodes of all data storage units in the entire storage page need to be energized once each time the data of any pixel point is read, and they need to be energized as many times as there are pixels in the storage page).

[0028] In the above-mentioned data storage system, the computer includes a classical computer or a server or a quantum computer or a mobile terminal computer (such as a tablet or a mobile phone or an industrial computer or a laptop computer, etc.) or an optical quantum computer, etc.

[0029] The present application relates to an optical electronic memory, comprising: arranging a plurality of stacked storage pages in a transparent material, the storage page comprising a plurality of data storage units in an array form; an anode, a cathode and an electrochromic layer provided for each data storage unit, the electrochromic layer being located between the anode and the cathode and developing color when a voltage is applied between the anode and the cathode, and fading when the voltage is removed between the anode and the cathode, and setting the data stored in the data storage unit to be different by setting the electrochromic layer of the data storage unit to be different;

[0030] A plurality of data storage units are arranged on the plane of any storage page as a set of pixels of the any storage page and each data storage unit is an independent pixel. Two pixels belonging to any two different storage pages but with the same address are arranged to overlap up and down. The data stored in the data storage unit is extracted using the voltage applied between its anode and cathode. Based on the applied voltage, different electrochromic layers display different colors and transmit different data, so that the color displayed by the electrochromic layer of the data storage unit represents the data stored therein.

[0031] In the above-mentioned optoelectronic memory, in any storage page, the anodes of adjacent data storage units are connected to each other through a conductive material until the anodes of all data storage units in any storage page are interconnected.

[0032] In the above-mentioned optoelectronic memory, in any storage page, the cathodes of adjacent data storage units are connected to each other through a conductive material until the cathodes of all data storage units in any storage page are interconnected.

[0033] In the above-mentioned photoelectric memory, in any storage page, all data storage units share a common anode layer and all data storage units share a common cathode layer, but the electrochromic layers of different data storage units are discrete from each other (the electrochromic layers of different data storage units are separated from each other).

[0034] The above-mentioned photoelectric memory selects multiple data storage units of multiple storage pages, and provides corresponding data as specimens under different color renderings of the data storage units to train a neural network; and uses the trained neural network to infer the data represented by the data storage units of other storage pages under their own color rendering or coloring conditions.

[0035] The examples introduced in the context of this application have the following advantages: since data is no longer stored using electric charge, there is almost no charge leakage and the accompanying data loss problem; there is no need to move to the target position on a fast-rotating disk to write and read like a mechanical hard disk, which consumes a lot of tasks on mechanical movements. Furthermore, the optoelectronic storage device of this application is a cold medium, and there is almost no abnormal situation related to overheating during data operation.

[0036] Another difference from traditional transistor memory is that traditional transistor memory is arranged into minimum read and write units or minimum operation units of different sizes. This also means that each read and write operation must be implemented with a minimum operation unit including tens of thousands or more transistors. A large number of bit lines and word lines inside the minimum operation unit need to be classified and manipulated using a lot of control data, which not only makes the read and write operations complicated, but also requires the introduction of many auxiliary circuits such as instruction decoding and address decoding to complete these operations. The minimum operation unit of traditional transistor memory is often a zoning mode such as block, page or sector. Given that the bit lines, word lines and set auxiliary circuits occupy a large amount of chip space, the integration of the memory is low or the storage density still has room for further improvement.

[0037] The example introduced in the context of this application has the advantage that the image of all pixels in each storage page is read in parallel as parallel data at one time, that is, the data of one page is read at a time with the page as the minimum reading unit. It has a high degree of data operation flexibility and convenience, and the data reading speed is extremely high. The coloring or fading process of the electrochromic layer itself is related to the photoelectric effect of electrons, for example, but the carrier of the stored data is not the electron or other electric charge itself, and whether the charge leaks or is annihilated does not directly affect the permanence of the data, so there is no longer a problem of data loss. In addition to the data storage unit itself, there are no more redundant components in the storage page that occupy the physical space of the storage chip. Therefore, compared with the traditional semiconductor transistor memory, the photoelectric memory of this application has a higher storage density. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to make the above purposes, features and advantages more understandable, the following text will explain the specific implementation methods in detail in conjunction with the drawings. After reading the following description and referring to the following drawings, the features and advantages of the present application will become apparent.

[0039] Figure 1 Each memory page includes a plurality of data storage cells in an array form.

[0040] Figure 2 The data storage unit has an anode and a cathode and an electrochromic layer therebetween.

[0041] Figure 3 The data storage units share a common anode layer and a common cathode layer.

[0042] Figure 4 It is the anode interconnect of the data storage unit and the cathode interconnect of the data storage unit.

[0043] Figure 5 The stored data is represented by the color of the electrochromic layer of the data storage unit.

[0044] Figure 6 It is a data storage unit that stores data using the voltage between the anode and cathode.

[0045] Figure 7 It is the data provided as specimens under different color rendering to train the neural network.

[0046] Figure 8 The data storage units that overlap each other use different voltages for the anode and cathode. DETAILED DESCRIPTION

[0047] The technical solutions disclosed in the present application will be clearly and completely described below in conjunction with specific embodiments. However, the embodiments described are only embodiments used for narrative explanation in the present application and are not all embodiments. Based on these embodiments, technicians in this field should realize that any solution obtained without creative work falls within the scope of protection of the present application.

[0048] See also Figure 5 The internal structure of the storage particle DIE or optoelectronic storage device is roughly as shown in the figure. The storage particle is a transparent material and its preparation process is compatible with traditional semiconductor processes. The reason for using traditional semiconductor processes is that it can provide output quickly and efficiently based on the equipment and process conditions of the wafer factory. In fact, traditional glass manufacturers can also manufacture storage particles DIE by slicing glass with a diamond knife. For example, after each layer of glass is manufactured by the glass manufacturer, a data storage unit is prepared on the glass layer, and then another layer of glass with a data storage unit is stacked on it. After stacking many layers of glass, a structure like this can be formed. Figure 5 The storage particles DIE shown.

[0049] See also Figure 1 The multiple stacked memory pages contained in the memory particle DIE are shown in the figure. The figure shows a certain memory page P0 and a memory page PK as an example. The memory page P0 is the abbreviation of the memory page Page0, and the other memory pages are basically similar, for example, PK is the abbreviation of PageK.

[0050] See also Figure 1 For example, the storage page P0 includes a plurality of data storage units in an array form, and the figure specifically shows data storage unit P0_addr (x0, y0) to data storage unit P0_addr (x1, y2), etc. Each data storage unit has an anode and a cathode and an electrochromic layer located therebetween. Each storage page also includes a plurality of data storage units in an array form, and the storage page P0 is used as an example to explain it.

[0051] See also Figure 1 As shown in the figure, the data storage unit P0_addr(x0, y0) at the address addr(x0, y0) in the storage page P0 has an anode A1 and a cathode C1, and an electrochromic layer EC between the anode A1 and the cathode C1.

[0052] See also Figure 1 As shown in the figure, the data storage unit P0_addr(x0,y1) at the address addr(x0,y1) in the storage page P0 has an anode A2 and a cathode C2, and an electrochromic layer EC between the anode A2 and the cathode C2.

[0053] See also Figure 1 As shown in the figure, the data storage unit P0_addr(x0,y2) at the address addr(x0,y2) in the storage page P0 has an anode A3 and a cathode C3, and an electrochromic layer EC between the anode A3 and the cathode C3.

[0054] See also Figure 1 As shown in the figure, the data storage unit P0_addr(x1,y0) at the address addr(x1,y0) in the storage page P0 has an anode A4 and a cathode C4, and an electrochromic layer EC between the anode A4 and the cathode C4.

[0055] See also Figure 1 As shown in the figure, the data storage unit P0_addr(x1,y1) at the address addr(x1,y1) in the storage page P0 has an anode A5 and a cathode C5, and an electrochromic layer EC between the anode A5 and the cathode C5.

[0056] See also Figure 1As shown in the figure, the data storage unit P0_addr(x1, y2) at the address addr(x1, y2) in the storage page P0 has an anode A6 and a cathode C6, and an electrochromic layer EC between the anode A6 and the cathode C6.

[0057] See also Figure 5 In order to make the memory mentioned in this application compatible with traditional manufacturing processes, the storage particles DIE derived from wafer cutting are used as an example to illustrate. The wafer uses 4 inches, 6 inches, 8 inches or 12 inches and part of the wafer manufacturing is compatible with traditional wafer processes such as CMOS process, Bipolar process, BiCMOS process, typically the crystal pulling process and wafer cutting process, and the sputtering or plating or chemical vapor deposition or physical vapor deposition or coating of the anode and cathode and the color-changing layer on the wafer. In addition to being compatible with traditional wafer manufacturing processes, the cathode and cathode and the color-changing layer can also be replaced by new technologies that have emerged recently, such as printing films for the anode and cathode and the color-changing layer.

[0058] See also Figure 1 , the wafer material for manufacturing storage particle DIE: it should use transparent semiconductor wafers or transparent ceramic wafers or directly use glass materials, or even transparent acrylic materials. If it is purely from the perspective of material selection, acrylic materials or plastic materials can also be selected. However, compared with rigid materials such as semiconductors, ceramics or glass, the inherent flexibility or flexure of acrylic materials or plastic materials will cause local changes in the physical properties of the data storage unit. For example, the color of the stretched data storage unit is not completely consistent with the color of the original undeformed data storage unit.

[0059] See also Figure 1 , manufacturing transparent wafers for storage particle DIE: One of the biggest features of semiconductor wafers such as SiC-based GaN materials is the transparency of the wafer. Third-generation compound semiconductors can be used. GaN HEMT devices, as representative devices of third-generation compound semiconductors, are widely used in the field of microwave power amplification with high electron mobility, high breakdown voltage, high current density and high reliability. The lattice constant of SiC material is close to that of GaN material, so high-quality GaN HEMT heterojunction structure can be epitaxially grown on SiC substrate. At the same time, the thermal conductivity of SiC material is high and meets the requirements of high-power heat dissipation. The SiC-based transparent semiconductor wafer is one of the optional options.

[0060] See also Figure 1, transparent ceramic wafers are used to manufacture storage particle DIE: magnesium aluminate MgAl2O4 ceramic wafer or crystal SiO2 ceramic wafer, strontium aluminum tantalate LSAT ceramic wafer, strontium titanate SrTiO3 ceramic wafer, or titanium dioxide TiO2 ceramic wafer, YSZ ceramic wafer, magnesium oxide MgO ceramic wafer, zinc oxide ZnO ceramic wafer or sapphire Al2O3 ceramic wafer, terbium scandate TbScO3 ceramic wafer, dysprosium scandate DyScO3 wafer, etc.

[0061] See also Figure 1 , manufacturing glass for DIE storage particles: the main components of glass are silicon dioxide and other oxides or silicate complex salts, reflecting an amorphous solid with irregular structure. High-transmittance glass or traditional household ordinary glass or quartz glass can be used, and even acrylic plates can be used to replace glass.

[0062] See also Figure 5 After the wafer for manufacturing the memory particle DIE has prepared the memory page, the wafer cutting (Saw) process can be performed on it according to the traditional wafer process. The memory particle DIE after the wafer cutting is shown in the figure. After the wafer is cut, many smaller memory chips or memory particle DIEs are provided. The memory particle DIE is transparent. The preparation demonstration of arranging multiple stacked memory pages in a transparent material is described later.

[0063] See also Figure 2 , the storage particle DIE is explained by taking the preparation process of semiconductor wafer as an example: a data storage unit array arr is arranged on a transparent substrate, which is regarded as the first (carrying the first page Page1) transparent layer; the second transparent layer (carrying the second page Page2) continues to grow epitaxially on the first transparent layer, and the storage unit array arr is also arranged; the third transparent layer (carrying the third page Page3) continues to grow epitaxially on the second transparent layer, and the storage unit array arr is also arranged; the fourth transparent layer (carrying the fourth page Page4) continues to grow epitaxially on the third transparent layer, and the storage unit array arr is also arranged. According to this rule, multiple layers of superimposed transparent material layers can be generated and each transparent layer carries a data storage unit array arr. The many storage unit arrays arr on each transparent layer are called a page. Based on the wafer process, multiple levels of pages Page1 to Page3 as data storage carriers, and even more layers of undisplayed pages, are finally prepared in the storage particle DIE.

[0064] See also Figure 2, the storage particle DIE is further explained by taking the improvement of the ordinary glass preparation process as an example: a data storage unit array arr is set on a layer of transparent glass, which is regarded as the first (carrying the first page Page1) glass layer; the second glass layer (carrying the second page Page2) is continuously stacked and laminated on the first glass layer, and the storage unit array arr is also arranged; the third glass layer (carrying the third page Page3) is continuously stacked and laminated on the second glass layer, and the storage unit array arr is also arranged; the fourth glass layer (carrying the fourth page Page4) is continuously stacked and laminated on the third glass layer, and the storage unit array arr is also arranged. According to this rule, multiple layers of stacked transparent glass layers can be generated and each glass layer carries many storage unit arrays arr. The many storage unit arrays arr on each glass layer are called a page. Based on the glass preparation, multiple levels of pages Page1 to Page3 as data storage carriers and even more storage pages that are not shown are finally prepared in the storage particle DIE. The glass layers can be easily melted together at a suitable temperature, and ultrasonic welding can also make them easily melted together.

[0065] See also Figure 2 The data storage material of the data storage unit of the storage particle DIE can be arranged on the wafer or glass in a variety of optional ways, such as sputtering, plating, chemical vapor deposition, physical vapor deposition or coating on the wafer or glass, or directly printing the data storage material on the wafer or glass.

[0066] See also Figure 1 , taking the preparation of the storage cell array arr of the storage page P0 as an example, a cathode material layer, an electrochromic layer, and an anode material layer are sequentially generated on the transparent layer where the current storage page P0 is located, and then the stack with the cathode material layer, the electrochromic layer, and the anode material layer is etched, and the retained part of the stack forms the array arr and the other non-data storage unit areas of the stack are peeled off. Photolithography can easily meet this demand. Etching the stack includes both etching the cathode material layer, the electrochromic layer, or the anode material layer separately, and etching the stack uniformly at the same time. The patterns of cathode and anode materials, color-changing materials, etc. can be etched as needed.

[0067] See also Figure 1 , the array arr includes a reserved area of ​​the stack, such as a data storage unit P0_addr (x0, y0) as shown in the figure, with an anode A1 and a cathode C1 and an electrochromic layer EC between the anode and cathode (see Figure 2 ) area.

[0068] See also Figure 1, the array arr includes a reserved area of ​​the stack, such as a data storage unit P0_addr (x0, y1) as shown in the figure, with an anode A2 and a cathode C2 and an electrochromic layer EC between the anode and cathode.

[0069] See also Figure 1 , the array arr includes a reserved area of ​​the stack, such as a data storage unit P0_addr (x0, y2) as shown in the figure, with an anode A3 and a cathode C3 and an electrochromic layer EC between the anode and cathode.

[0070] See also Figure 1 , the array arr includes a reserved area of ​​the stack, such as a data storage unit P0_addr (x1, y0) as shown in the figure, with an anode A4 and a cathode C4 and an electrochromic layer EC between the anode and cathode.

[0071] See also Figure 1 , the array arr includes a reserved area of ​​the stack, such as a data storage unit P0_addr (x1, y1) as shown in the figure, with an anode A5 and a cathode C5 and an electrochromic layer EC between the anode and cathode.

[0072] See also Figure 1 , the array arr includes a reserved area of ​​the stack, such as a data storage unit P0_addr (x1, y2) as shown in the figure, with an anode A6 and a cathode C6 and an electrochromic layer EC between the anode and cathode.

[0073] See also Figure 4 , still taking the preparation of the data storage unit array arr of the storage page P0 as an example, during the formation of the array arr using the reserved part of the aforementioned stack, the data storage unit itself is mainly reserved, and other non-data storage unit areas of the stack are stripped off. Figure 4 The reserved part of the aforementioned stack also includes an interconnection structure bg, so that the anodes of two adjacent data storage units such as P0_addr (x0, y0) and P0_addr (x1, y0) are interconnected, and the anodes of two adjacent data storage units such as P0_addr (x1, y0) and P0_addr (x2, y0) are interconnected. Or the anodes of two adjacent data storage units such as P0_addr (x0, y0) and P0_addr (x0, y1) are interconnected, and the anodes of two adjacent data storage units such as P0_addr (x0, y1) and P0_addr (x0, y2) are connected to each other. Note that not all interconnection structures bg are drawn in the figure, but only a limited number of interconnection structures are given as examples. Until the anodes of all data storage units in the same storage page are interconnected, interconnected with a common anode A_P0.

[0074] See also Figure 4 , still taking the retained part of the aforementioned stack as an example, such as the so-called interconnection structure bg, the cathodes of two adjacent data storage units such as P0_addr(x0,y0) and P0_addr(x1,y0) are interconnected, and the cathodes of two adjacent data storage units such as P0_addr(x1,y0) and P0_addr(x2,y0) are interconnected. Or the cathodes of two adjacent data storage units such as P0_addr(x0,y0) and P0_addr(x0,y1) are interconnected, and the cathodes of two adjacent data storage units such as P0_addr(x0,y1) and P0_addr(x0,y2) are interconnected. Note that not all interconnection structures bg are drawn in the figure, only a limited number of interconnection structures are given as examples. Until the cathodes of all data storage units in the same storage page are interconnected, and a common cathode C_P0 is interconnected.

[0075] See also Figure 1 Taking the preparation of the memory cell array arr from the memory page PK as an example, a cathode material layer, an electrochromic layer, and an anode material layer are sequentially generated on the transparent layer where the current memory page PK is located, and then the stack with the cathode material layer, the electrochromic layer, and the anode material layer is etched, and the retained part of the stack forms the array arr and the other non-data storage unit areas of the stack are stripped off. After generating any layer such as the cathode material layer, the electrochromic layer, or the anode material layer, it is allowed to perform a grinding and polishing step on this layer.

[0076] See also Figure 1 , the array arr includes a reserved area of ​​the stack such as the data storage unit PK_addr (x0, y0) as shown in the figure with an anode and a cathode and an electrochromic layer EC between the anode and cathode (see Figure 2 ) area.

[0077] See also Figure 1 , the array arr includes a reserved area of ​​the stack such as the data storage unit PK_addr (x0, y1) as shown in the figure, with an anode and a cathode and an electrochromic layer EC between the anode and the cathode.

[0078] See also Figure 1 , the array arr includes a reserved area of ​​the stack such as the data storage unit PK_addr (x0, y2) as shown in the figure, with an anode and a cathode and an electrochromic layer EC between the anode and the cathode.

[0079] See also Figure 1 , the array arr includes a reserved area of ​​the stack such as the data storage unit PK_addr (x1, y0) as shown in the figure, with an anode and a cathode and an electrochromic layer EC between the anode and the cathode.

[0080] See also Figure 1 , the array arr includes a reserved area of ​​the stack such as the data storage unit PK_addr (x1, y1) as shown in the figure, with an anode and a cathode and an electrochromic layer EC between the anode and the cathode.

[0081] See also Figure 1 , the array arr includes a reserved area of ​​the stack such as the data storage unit PK_addr (x1, y2) as shown in the figure, with an anode and a cathode and an electrochromic layer EC between the anode and the cathode.

[0082] See also Figure 3 , compared with Figure 1 Embodiments, different preparation schemes and storage structures are proposed. In order to contrast with the preparation scheme mentioned above, taking the preparation of the storage unit array arr using the storage page P0 as an example, a cathode material layer and an electrochromic layer are first generated on the transparent layer where the current storage page P0 is located, and the electrochromic layer is etched. The retained portion of the electrochromic layer forms each data storage unit area in the array arr, and the remaining portion of the electrochromic layer is stripped off or etched. Based on the retained electrochromic layer, an anode material layer is then generated on the cathode material layer and the etched electrochromic layer. Compared to Figure 1 In the embodiment, it can be found that at this time in the current storage page P0, all data storage units in the same storage page share a common anode layer A_P0 and all data storage units in the same storage page share a common cathode layer C_P0, and the electrochromic layers of different data storage units are discrete from each other. In this example, the cathode material layer and the anode material layer reduce one etching step. It is worth noting that in addition to being derived from the etching of an electrochromic layer, the electrochromic layer of each data storage unit can also be directly printed or coated with an isolated electrochromic layer at the physical location of each data storage unit. Then, the electrochromic layers of different data storage units are naturally discrete and unconnected. That is, Figure 3 The discrete relationship between the electrochromic layers of different data storage units and Figure 1 Exactly the same, but only in Figure 1 The anodes of different data storage units are discrete and the cathodes are also discrete. Figure 3 The anode of each of the different data storage units appears as a complete whole without being discrete, and the cathode also appears as a complete whole without being discrete.

[0083] See also Figure 3, the array arr contains a reserved area of ​​the electrochromic layer such as the data storage unit P0_addr (x0, y0) as shown in the figure, which is an isolated electrochromic layer EC area between the common anode A_P0 and the common cathode C_P0.

[0084] See also Figure 3 , the array arr contains a reserved area of ​​the electrochromic layer such as the data storage unit P0_addr (x0, y1) as shown in the figure, which is an isolated electrochromic layer EC area between the common anode A_P0 and the common cathode C_P0.

[0085] See also Figure 3 , the array arr contains a reserved area of ​​the electrochromic layer such as the data storage unit P0_addr (x0, y2) as shown in the figure, which is an isolated electrochromic layer EC area between the common anode A_P0 and the common cathode C_P0.

[0086] See also Figure 3 , the array arr contains a reserved area of ​​the electrochromic layer such as the data storage unit P0_addr (x1, y0) as shown in the figure, which is an isolated electrochromic layer EC area between the common anode A_P0 and the common cathode C_P0.

[0087] See also Figure 3 , the array arr contains a reserved area of ​​the electrochromic layer such as the data storage unit P0_addr (x1, y1) as shown in the figure, which is an isolated electrochromic layer EC area between the common anode A_P0 and the common cathode C_P0.

[0088] See also Figure 3 , the array arr contains a reserved area of ​​the electrochromic layer such as the data storage unit P0_addr (x1, y2) as shown in the figure, which is an isolated electrochromic layer EC area between the common anode A_P0 and the common cathode C_P0.

[0089] See also Figure 3 , the isolated electrochromic layer EC areas at the data storage unit P0_addr (x2, y0), the data storage unit P0_addr (x2, y1) and other data storage units P0_addr (x2, y2) are no longer listed one by one.

[0090] See also Figure 3 , compared with Figure 1Embodiments, different preparation schemes and storage structures are proposed. In order to contrast with the preparation scheme mentioned above, taking the preparation of the storage unit array arr by the storage page PK as an example, a cathode material layer and an electrochromic layer are first generated on the transparent layer where the current storage page PK is located, and the electrochromic layer is etched. The retained part of the electrochromic layer forms each data storage unit area in the array arr, and the remaining part of the electrochromic layer is peeled off or etched. Based on the retained electrochromic layer, an anode material layer is then generated on the cathode material layer and the etched electrochromic layer. Compared to Figure 1 In the embodiment, it can be found that at this time in the current storage page PK, all data storage units in the same storage page share a common anode layer A_PK and all data storage units in the same storage page share a common cathode layer C_PK, and the electrochromic layers of different data storage units are discrete from each other.

[0091] See also Figure 3 , the array arr contains a reserved area of ​​the electrochromic layer such as the data storage unit PK_addr (x0, y0) as shown in the figure, which is an isolated electrochromic layer EC area between the common anode A_PK and the common cathode C_PK.

[0092] See also Figure 3 , the array arr contains a reserved area of ​​the electrochromic layer such as the data storage unit PK_addr (x0, y1) as shown in the figure, which is an isolated electrochromic layer EC area between the common anode A_PK and the common cathode C_PK.

[0093] See also Figure 3 , the array arr contains a reserved area of ​​the electrochromic layer such as the data storage unit PK_addr (x0, y2) as shown in the figure, which is an isolated electrochromic layer EC area between the common anode A_PK and the common cathode C_PK.

[0094] See also Figure 3 , the array arr contains a reserved area of ​​the electrochromic layer such as the data storage unit PK_addr (x1, y0) as shown in the figure, which is an isolated electrochromic layer EC area between the common anode A_PK and the common cathode C_PK.

[0095] See also Figure 3 , the array arr contains a reserved area of ​​the electrochromic layer such as the data storage unit PK_addr (x1, y1) as shown in the figure, which is an isolated electrochromic layer EC area between the common anode A_PK and the common cathode C_PK.

[0096] See also Figure 3, the array arr contains a reserved area of ​​the electrochromic layer such as the data storage unit PK_addr (x1, y2) as shown in the figure, which is an isolated electrochromic layer EC area between the common anode A_PK and the common cathode C_PK.

[0097] See also Figure 3 , the isolated electrochromic layer EC areas at the data storage unit PK_addr (x2, y0), the data storage unit PK_addr (x2, y1) and other data storage units PK_addr (x2, y2) are no longer listed one by one.

[0098] See also Figure 3 In an optional embodiment, the anodes of all data storage units in any storage page such as PK are interconnected and interconnected to a common anode A_PK, and the cathodes of all data storage units in any storage page such as PK are interconnected and interconnected to a common cathode C_PK. The anode A_PK uses an entire anode material layer as the common anode of the current page, and the cathode C_PK uses an entire cathode material layer as the common cathode of the current page.

[0099] See also Figure 4 In an optional embodiment, the anodes of all data storage units in any storage page such as P0 are interconnected and interconnected by an interconnection structure bg, and the cathodes of all data storage units in any storage page such as P0 are interconnected and interconnected by an interconnection structure bg. The anodes of all data storage units in any storage page such as P0 are interconnected, but the anodes are discrete from each other, and the cathodes of all data storage units in any storage page such as P0 are interconnected, but the cathodes are discrete from each other.

[0100] See also Figure 2 In an optional embodiment, the data stored in a data storage unit such as P1_addr (x0, y0) is extracted using the voltage V_adjustX applied between its anode A1 and cathode C1. Based on the applied voltage, the data storage unit such as P1_addr (x0, y0) will have different reactions: if the P1_addr (x0, y0) uses a different electrochromic layer, then the different electrochromic layers EC display different colors and transmit different data.

[0101] See also Figure 2In an optional embodiment, the data storage unit, such as P1_addr (x0, y0), assumes that its coloring or color value or color value of the electrochromic layer EC or the gray value based on the color is GS (x0, y0). The data storage unit is based on the premise of the applied voltage V_adjustX. If different electrochromic layers EC are used, the colors displayed by different electrochromic layers are different, for example, the gray value GS (x0, y0) is also different. The color displayed by the electrochromic layer of the data storage unit is designed to represent the stored data. Assuming that there is GS1 (x0, y0) under the first electrochromic layer and GS2 (x0, y0) under the second electrochromic layer, GS1 (x0, y0) represents the data as 0xf2 and GS2 (x0, y0) represents the data under the current condition as 0xe3. Thereby, different electrochromic layers display different colors and different electrochromic layers transmit different data, and the color display of the electrochromic layer of the data storage unit represents the stored data. If each color has eight bits of grayscale data, then any single-color reference color will have 256 grayscale levels. If each color has ten bits of grayscale data, then any single-color reference color will have 1024 grayscale levels.

[0102] See also Figure 2 , based on 8-bit grayscale data, if three primary colors are mixed, about 16 trillion colors can be formed. For another example, if based on 10-bit grayscale data, three primary colors can be mixed to form nearly 1 billion colors. Therefore, the optional range and optional value of GS(x0,y0) are very sufficient and bring a larger color recognition flexibility space.

[0103] See also Figure 2 Electrochromic materials EC include inorganic electrochromic materials and organic electrochromic materials. The typical representative of inorganic electrochromic materials is tungsten trioxide. Organic electrochromic materials include polythiophene and its derivatives, viologens, tetrathiafulvalene, metal phthalocyanine compounds, etc.

[0104] See also Figure 2 Inorganic electrochromic materials are mostly transition metal oxides or their derivatives. Transition metals have unstable electron layers and unpaired single electrons. Ions of transition metal elements generally have colors, and the energy difference between the ground state and the excited state is small. Under certain conditions, the valence state undergoes a reversible change, forming a state of mixed valence ion coexistence. As the valence state and concentration of the ions change, the color will also change accordingly.

[0105] See also Figure 2 There are relatively many types of organic electrochromic films, which can be divided into two categories: organic small molecule electrochromic materials and conductive polymer electrochromic materials.

[0106] See also Figure 2The typical representative of organic small molecule color-changing materials is viologens, which change color during the oxidation-reduction process, so they are also redox compounds. Generally speaking, due to the special structure of neutral viologens, the electron migration within the molecule is prohibited, so the color is lighter. As the applied potential increases, the neutral state structure gradually changes to a partially oxidized state, and finally generates a stable divalent cation form, which is colorless in this state. Due to the strong photoelectric transfer between molecules, the monovalent cation will have the darkest color.

[0107] See also Figure 2 , a newly developed class of substances of conductive polymer electrochromic materials. As conjugated polymers show high conductivity and electrochromic phenomenon after being doped with small molecules, conductive polymers have quickly developed as electrochromic materials. The principle of conductive polymer color change is mainly the doping process. The essence of doping is the migration and exit of ions in the polymer chain, accompanied by the gain and loss of electrons. Therefore, the doping process of conductive polymers is a reversible process of redox. In the process of doping, the transition between the molecular conduction band and the valence band is triggered, including the transition of polar energy level, soliton energy level, bipolar energy level, and different energy levels of electrons, which causes different changes in the spectrum. In practical applications, the voltage is controlled to determine the degree of doping, resulting in different absorption in the visible light region, showing a change in color, and the electrochromic phenomenon required by this application occurs. It can be seen that the material selection of the electrochromic material EC is diverse.

[0108] See also Figure 2 In an optional embodiment, the electrochromic layer EC includes an inorganic electrochromic material.

[0109] See also Figure 2 In an optional embodiment, the electrochromic layer EC includes an organic electrochromic material.

[0110] See also Figure 2 In an optional embodiment, the electrochromic layer EC includes a mixture of two or more organic electrochromic materials (for example, a mixture of two or more materials selected from polythiophenes and their derivatives, viologens, tetrathiafulvalene, metal phthalocyanine compounds, etc.).

[0111] See also Figure 2 In an optional embodiment, the electrochromic layer EC may include dopants of inorganic electrochromic materials and organic electrochromic materials (for example, one or more organic materials selected from polythiophenes and their derivatives, viologens, tetrathiafulvalene, metal phthalocyanine compounds, etc. are doped with inorganic electrochromic materials).

[0112] See also Figure 2In an optional embodiment, the electrochromic layer EC is configured in different ways including: the materials of the electrochromic layer are different. For example, the first electrochromic layer uses an inorganic electrochromic material and the second electrochromic layer uses an organic electrochromic material. For example, the first electrochromic layer has a gray value and the second electrochromic layer has another gray value. In addition, there are multiple optional ways for inorganic electrochromic materials and multiple optional ways for organic electrochromic materials, and the final optional colors of the electrochromic layer EC will be quite abundant.

[0113] See also Figure 2 In an optional embodiment, the electrochromic layer EC is set in different ways including: when the electrochromic layer uses a variety of organic electrochromic materials for mixing, the mixing ratios of the various organic electrochromic materials are adjusted to provide different electrochromic layers. For example, when the electrochromic layer EC uses materials such as viologens, tetrathiafulvalene, polythiophenes and their derivatives or metal phthalocyanine compounds for mixing, the mixing ratio of viologens in the mixed mixture can be adjusted, the mixing ratio of tetrathiafulvalene in the mixture can be adjusted, the mixing ratio of polythiophenes and their derivatives in the mixture can be adjusted, and the mixing ratio of metal phthalocyanine compounds in the mixture can be adjusted. When the mixing ratio of any material in the mixture changes, the color of the electrochromic layer EC will change.

[0114] See also Figure 2 In an optional embodiment, the mixing ratio of the viologen compounds is assumed to be 30% and the mixing ratio of the terpyridine derivatives is assumed to be 70%, at which time the electrochromic layer EC has one color; the mixing ratios of the organic electrochromic materials in the electrochromic layer are adjusted, the mixing ratio of the viologen compounds is assumed to be 40% and the mixing ratio of the terpyridine derivatives is assumed to be 60%, at which time the electrochromic layer EC has another color. Different electrochromic layers are provided by adjusting the mixing ratios of various organic electrochromic materials.

[0115] See also Figure 2 In an optional embodiment, the electrochromic layer EC is configured in different ways including: when the electrochromic layer is doped with inorganic and organic electrochromic materials, the doping concentrations of the inorganic electrochromic material and the organic electrochromic material can be adjusted to provide different electrochromic layers. For example, if the electrochromic layer EC is doped with viologens and inorganic transition metal oxides or their derivatives, the doping concentration of the viologens and / or the doping concentration of the inorganic transition metal oxides or their derivatives can be adjusted, and when the doping concentrations of the viologens and / or the inorganic transition metal oxides or their derivatives are changed, the color of the electrochromic layer EC is changed. Viologens can also be replaced with other organic electrochromic materials to be doped with inorganic materials.

[0116] See also Figure 2 In an optional embodiment, the doping concentration of the viologen compound is assumed to be 10% and the doping concentration of the inorganic tungsten trioxide is assumed to be 90%, at which time the electrochromic layer EC has one color; the doping concentrations of the inorganic electrochromic material and the organic electrochromic material are adjusted, and the mixing ratio of the viologen compound is assumed to be 50% and the doping concentration of the inorganic tungsten trioxide is assumed to be 50%, at which time the electrochromic layer EC has another color. The doping concentrations of the inorganic electrochromic material and the organic electrochromic material are adjusted to provide different electrochromic layers.

[0117] See also Figure 2 , transparent materials such as storage particles DIE are divided into multiple storage pages, and the data storage units arranged on any storage page serve as the pixel point set of any storage page, and each data storage unit serves as a pixel point. For example, in the figure, the transparent material is divided into multiple pages Page1 to Page3, or even more layers of pages that are not displayed. The data storage unit array arr arranged on any page such as Page1 can be used as the pixel point set of any page Page1, and each data storage unit at this time can be regarded as a pixel point. Pixel arrangement: The coordinates of the upper left corner are P1_addr (x0, y0), which is the address of the 0th pixel, and the coordinates of other pixel points are incremented on this basis.

[0118] See also Figure 3 , the anodes of all data storage units P0_addr(xj,yq) of the storage page P0 are connected to the common anode A_P0, and the cathodes of all data storage units P0_addr(xj,yq) of the storage page P0 are connected to the common cathode C_P0. 0≤j≤n, 0≤q≤m. j=0, 1…n and q=0, 1…m. The pixel point or data storage unit array of the storage page P0 can be assumed to have n+1 columns and m+1 rows. Figures 1 to 4 Same here.

[0119] See also Figure 3 , the anodes of all data storage units P1_addr(xj,yq) of the storage page P1 are connected to the common anode A_P1, and the cathodes of all data storage units P1_addr(xj,yq) of the storage page P1 are connected to the common cathode C_P1. 0≤j≤n, 0≤q≤m. j=0, 1…n and q=0, 1…m.

[0120] See also Figure 3, the anodes of all data storage units PK_addr (xj, yq) of the storage page PK are connected to a common anode A_PK, and the cathodes of all data storage units PK_addr (xj, yq) of the storage page PK are connected to a common cathode C_PK. 0≤j≤n, 0≤q≤m. j=0, 1…n and q=0, 1…m.

[0121] See also Figure 2 The reading of the memory pages P0 to PK is performed using a scanning voltage signal, and the following will be explained using the scanning voltage signals V_adjust1 to V_adjustK (i.e., scanning voltage) as an example. A series of memory pages at different levels or layers are read in time-sharing, and different memory pages are read in time-sharing staggered manner.

[0122] See also Figure 2 , the data stored in the memory page P0 can be read out by using the voltage V_adjust0 applied between the anode A_P0 and the cathode C_P0. V_adjust0 omitted in the figure appears earliest in the scan signal.

[0123] See also Figure 2 , the data stored in the memory page P1 can be read out by using the voltage V_adjust1 applied between the anode A_P1 and the cathode C_P1. The timing when V_adjust1 appears in the scanning signal is later than V_adjust0.

[0124] See also Figure 2 , the data stored in the memory page P2 can be read out by using the voltage V_adjust2 applied between the anode A_P2 and the cathode C_P2. The timing when V_adjust2 appears in the scanning signal is later than V_adjust1.

[0125] See also Figure 2 , the data stored in the memory page P3 can be read out by using the voltage V_adjust3 applied between the anode A_P3 and the cathode C_P3. The timing when V_adjust3 appears in the scanning signal is later than that of V_adjust2.

[0126] See also Figure 2 , the data stored in the storage page PK can be extracted by applying a voltage V_adjustK between the anode A_PK and the cathode C_PK. Natural number X = 0, 1, 2, 3...K. Therefore, it can be seen that when a data storage unit of any storage page is applied with a voltage and enters a read state for data extraction, the data storage units of the remaining other storage pages may not enter a read state. Avoid read confusion between different storage pages. For example, multiple scan voltages are set to a set of sequential pulse signals that appear in sequence in time, and their effective logic values, such as high levels, do not overlap.

[0127] See also Figure 2 In an optional embodiment, when a voltage is applied to the data storage unit of any storage page and the data storage unit enters the read state of data extraction, the data storage units of the remaining other storage pages are prohibited from entering the read state, that is, a series of storage pages at different levels are read in time-sharing. For example, when the data storage units of the storage page P1 are applied with a voltage V_adjust1 and enter the read state of data extraction, the data storage units of other storage pages P0 and P2-PK are prohibited from entering the read state, that is, the series of storage pages P0-PK at different levels are staggered in time and read separately. In an optional implementation example, a plurality of stacked storage pages P0-PK are arranged in a transparent material, and based on the stacking relationship, any storage page of the storage pages P0-PK has a level or layer or a stratum belonging to itself.

[0128] See also Figure 4 In an optional embodiment, in any storage page, all data storage units share a common anode layer and all data storage units share a common cathode layer, but the electrochromic layers of different data storage units are discrete from each other. For example, in the storage page PK, all data storage units of the storage page PK share a common anode layer A_PK and all data storage units of the storage page PK share a common cathode layer C_PK, but the electrochromic layers EC of different data storage units are discrete from each other (the discrete relationship can be seen in FIG. Figure 1 ).

[0129] See also Figure 4 In an optional embodiment, the respective anodes of all data storage units in any storage page are interconnected, and the respective cathodes of all data storage units in any storage page are interconnected. For example, the respective anodes of all data storage units in storage page P0 are interconnected to anode A_P0, and corresponding to the anodes, for example, the respective cathodes of all data storage units in storage page P0 are interconnected to cathode C_P0.

[0130] See also Figure 2 , as anode or cathode, transparent electrode materials usually have the characteristics of high transparency, low resistivity and high conductivity. Transparent electrode materials include tin oxide SnO2, indium tin oxide ITO, indium zinc oxide IZO, and with the continuous advancement of materials, zinc oxide, aluminum oxide Al2O3, cadmium oxide CdO, etc. are also gradually introduced. Its preparation methods mainly include physical evaporation, sputtering, and ion beam sputtering. This is an example of the cathode and anode of a data storage unit.

[0131] See also Figure 4In an optional embodiment, a plurality of data storage units arranged on the plane of any storage page are used as a set of pixels of the any storage page and each data storage unit is used as an independent pixel; an image of all pixels of any storage page is used as parallel data to be read in parallel at one time, that is, the data of one storage page is read at one time with the storage page as the minimum reading unit each time. For example, for example, a plurality of data storage units arranged on the plane of storage page P0 are used as a set of pixels of storage page P0, and one data storage unit is used as an independent pixel; an image of all pixels of storage page P0 is used as parallel data to be read in parallel at one time, and the storage page P0 is used as the minimum reading unit each time so that the data of the entire storage page P0 is read at one time in the reading stage (all pixels of P0 are captured at one time).

[0132] See also Figure 5 , transparent materials such as storage particles DIE are divided into multiple pages. Each data storage unit arranged on the plane of storage page PageK is used as a set of pixels of storage page PageK. The camera Foc-Ca shoots each data storage unit or pixel on page PageK to obtain the corresponding image ImageK, and the camera Foc-Ca shoots each data storage unit or pixel on page PageK+1 to obtain the corresponding image ImageK+1.

[0133] See also Figure 6 When the camera Foc-Ca takes a picture of each data storage unit of the storage page PageK, the anode A_PK and the cathode C_PK should be energized according to the prior reading arrangement, and the voltage V_adjustK should be applied to drive the electrochromic film, that is, each electrochromic layer EC or each pixel of the storage page PageK to achieve the coloring effect. On the contrary, if the applied voltage V_adjustK is removed, each pixel of the storage page PageK will achieve the effect of fading. Usually, it is best to apply a forward voltage to the electrochromic layer to the coloring depth state, that is, the darkest color state, and then read it. Removing the applied voltage or applying a reverse voltage can make the electrochromic layer EC fade to a colorless state (transparent state).

[0134] See also Figure 6 When the camera Foc-Ca takes a picture of the storage unit of the storage page PageK+1, the anode A_PK+1 and the cathode C_PK+1 should be powered on according to the pre-reading arrangement, and the voltage V_adjustK+1 should be applied to drive the electrochromic film, that is, each electrochromic layer EC or pixel of the storage page PageK+1 to achieve a coloring effect. If the applied voltage V_adjustK+1 is removed, each pixel of the storage page PageK+1 will achieve a fading effect.

[0135] See also Figure 5When the data storage unit of the storage page PageK is applied with voltage V_adjustK and enters the read state of data extraction, the data storage units of the remaining other storage pages such as PageK+1 are prohibited from entering the read state, that is, a series of storage pages Page0 to PageK+1 at different levels are required to be read in a time-sharing manner.

[0136] See also Figure 5 , the time TK when the voltage V_adjustK appears high (e.g., about 0.5V-1.5V) appears earlier because the data of the storage page PageK is read earlier than the storage page PageK+1. The time TK+1 when the voltage V_adjustK+1 appears high appears later because the data of the storage page PageK+1 is read later. The reading times of the two can also be reversed, such as the high level of the voltage V_adjustK is the time TK+1, and the high level of the voltage V_adjustK+1 is the time TK. This is an example of setting the storage page PageK and PageK+1 or other pages to be read in time-sharing.

[0137] See also Figure 6 , the power supply module SMPS can provide voltages V_adjustK and V_adjustK+1, etc. The power supply module can use a digital power supply, a switching power supply, or a linear power supply, etc. For example, the voltage provided by the voltage output port IO1 of the power supply module SMPS can be regarded as the voltage V_adjustK and the voltage output port IO1 is connected to the anode A_PK of the storage page PageK, and the ground port of the power supply module is connected to the cathode C_PK of the storage page PageK. For example, the voltage provided by the voltage output port IO2 of the power supply module SMPS can be regarded as the voltage V_adjustK+1 and the voltage output port IO2 is connected to the anode A_PK+1 of the storage page PageK+1, and the ground port of the power supply module is connected to the cathode C_PK+1 of the storage page PageK+1. The ground port is assumed to be IO3.

[0138] See also Figure 6 A switch S1 is provided on the line between the voltage output port IO1 of the power supply module and the anode A_PK of the storage page PageK. The switch S1 can be turned on to output V_adjustK to the anode A_PK.

[0139] See also Figure 6 Furthermore, a switch S2 is provided on the line between the voltage output port IO2 and the anode A_PK+1 of the storage page PageK+1. When the switch S2 is turned on, V_adjustK+1 can be input to the anode A_PK+1.

[0140] See also Figure 6, the switches S1 and S2 are operated to be turned on in sequence, for example, the switch S1 is turned on at time TK so that the preset voltage V_adjustK can be applied to the anode A_PK of the storage page PageK, such as Figure 5 shown.

[0141] See also Figure 6 , based on the switches S1 and S2 being turned on in sequence, for example, the switch S2 is turned on at time TK+1 so that the preset voltage V_adjustK+1 can be applied to the anode A_PK+1 of the storage page PageK+1, such as Figure 5 shown.

[0142] See also Figure 1 In an optional embodiment, two pixels belonging to any two different pages but having the same address are set to overlap each other. An example of pixel arrangement of any two different pages is as follows.

[0143] See also Figure 1 In an optional embodiment, two pixels belonging to any two different pages (Page0 and Page1) but with exactly the same addresses are set to overlap up and down: a pixel with address P0_addr(x0,y0) of page Page0 and a pixel with address P1_addr(x0,y0) of another page Page1 are set to overlap up and down.

[0144] See also Figure 1 In an optional embodiment, two pixels belonging to any two different pages (Page1 and PageK) but with exactly the same addresses are set to overlap up and down: a pixel with address P1_addr (x0, y0) of page Page1 and a pixel with address PK_addr (x0, y0) of another page PageK are set to overlap up and down.

[0145] See also Figure 1 In an optional embodiment, two pixels belonging to any two different pages (Page0 and PageK) but with exactly the same addresses are set to overlap up and down: a pixel with address P0_addr(xn,ym) of page Page0 and a pixel with address PK_addr(xn,ym) of another page PageK are set to overlap up and down.

[0146] See also Figure 1 In an optional embodiment, two pixels belonging to any two different pages but with the same address are set to be non-overlapping or partially overlapping, which is also feasible. Imagine that there is an offset between two pixels in two adjacent pages but with the same address. When there are many storage pages, if each subsequent page is offset relative to the previous page, the storage density will be reduced, so it is not the best choice, but only an option.

[0147] See also Figure 7 , extracting image data (such as ImageK) of the data storage unit under the premise of applying voltage from a transparent material provided in advance as a sample, such as a storage page PageK or more pages, can provide training data for the neural network NET and can also label these training data.

[0148] See also Figure 7 , the color value or color value or color-based gray value of each pixel on the sample image is recorded in the color value table Color0_ext. For example, the color value of the data storage unit or pixel at the address PK_addr (x0, y0) is recorded as GS (x0, y0), and this color value corresponds to the label 1101 (just an example and not a limitation), and the label value of the same address PK_addr (x0, y0) in the label value table is recorded as 1101 or other forms. In addition to the color value table, the label value table Data0_tag corresponding to the color value table of the sample image is also shown.

[0149] See also Figure 7 In an optional embodiment, for example, the color value of the data storage unit or pixel with the address PK_addr (x1, y0) is recorded as GS (x1, y0), and the color value corresponds to the label 1100 (just an example and not a limitation), and the label value of the same address PK_addr (x1, y0) in the label value table is recorded as 1100.

[0150] See also Figure 7 In an optional embodiment, for example, the color value of the data storage unit or pixel with the address PK_addr (x0, y1) is recorded as GS (x0, y1), and the color value corresponds to the label 1001 (just an example and not a limitation), and the label value of the same address PK_addr (x0, y1) in the label value table is recorded as 1001.

[0151] See also Figure 7 In an optional embodiment, for example, the color value of the data storage unit or pixel at the address PK_addr (x1, y1) is recorded as GS (x1, y1), and the color value corresponds to the label 1011 (just an example and not a limitation), and the label value of the same address PK_addr (x1, y1) in the label value table is recorded as 1011. The color values ​​of other addresses and the corresponding label values ​​can be matched according to the above rules, so they are not described one by one.

[0152] See also Figure 7It has been reported that image data (such as ImageK) of a data storage unit under the premise of applying voltage can be extracted from a transparent material such as a storage page PageK or more pages as a sample. The material model of the data storage unit can be changed to provide different types of electrochromic layers, or the mixing ratio of various organic electrochromic materials can be adjusted to provide different types of electrochromic layers, or the doping concentration of inorganic and organic electrochromic materials can be adjusted to provide different types of electrochromic layers. If the type of electrochromic layer changes, its color will also change. By using different types of electrochromic layers to provide a series of image data sets (such as ImageK), that is, any change in the electrochromic layer can obtain a corresponding color value. After configuring the label, the label value of the label value form Data0_tag and the color value of the color value form Color0_ext can be rich and varied, so they can be regarded as training data sets used to train the neural network NET.

[0153] See also Figure 7 In an optional embodiment, multiple data storage units of a storage page (such as PageK or more pages) are selected and corresponding data as specimens or samples or tags, such as data of the tag value form Data0_tag, are provided under different coloring (for example, using different types of electrochromic layers) of the data storage unit to train the NET. For example, corresponding specimen data such as 1101 is provided under the coloring GS (x0, y0) of the data storage unit, and the same can be said, for example, corresponding specimen data such as 1100 is provided under the coloring GS (x1, y0) of the data storage unit. This is an example of using data storage units with different addresses to generate training data, and a single data storage unit can also generate training data. For example, the coloring GS1 (x0, y0) of a single data storage unit is based on a first electrochromic material and corresponds to specimen data such as 1101, while the coloring GS2 (x0, y0) of the same data storage unit is based on a second electrochromic material and corresponds to specimen data such as 1100. This is an example of generating training data based on data storage units with the same address but using different electrochromic materials.

[0154] See also Figure 7 In an optional embodiment, the trained neural network NET can infer data storage units of other storage pages (such as Figure 2In an optional embodiment, it is known that the anode and cathode of the data storage unit P1_addr (x0, y0) of the storage page P1 are applied with voltage, so this data storage unit P1_addr (x0, y0) displays a color, and the trained neural network NET can infer the data represented by the data storage unit P1_addr (x0, y0) of this storage page when it is self-colored (i.e., displays color).

[0155] See also Figure 7 In an optional embodiment, a plurality of stacked storage pages are arranged in a transparent material, each storage page includes a plurality of data storage units PK_addr (xn, ym) in an array form, the data storage unit has an anode and a cathode and an electrochromic layer EC located therebetween, and the data stored in the data storage unit is set to be different by setting the electrochromic layer of the data storage unit PK_addr (xn, ym) to be different; the data stored in the data storage unit is extracted using the voltage applied between the anode and the cathode, and based on the applied voltage, different electrochromic layers display different colors and transmit different data; thus, the color displayed by the electrochromic layer of the data storage unit PK_addr (xn, ym) represents the stored data. Set n and m to be equal to 0, 1, 2, 3…

[0156] See also Figure 7 , if the page is taken as the smallest basic unit, the image containing all pixels of each page is used as parallel data to be read in parallel at one time, that is, the data of one page is read at a time with the page as the smallest reading unit. For example, the camera can take a complete image ImageK of a page such as page PageK at a time, and the image ImageK contains all the data storage units or all the pixels of the page that are taken, such as the data of the data storage unit at each address PK_addr(xj,yq) of the image is inferred by the neural network NET. 0≤j≤n, 0≤q≤m. j=0, 1…n and q=0, 1…m. Then the image ImageK containing all pixels corresponding to the page is used as parallel data to be read in parallel at one time (one shot), that is, the data of one page PageK is read at a time with the page as the smallest reading unit. Obviously, the data reading efficiency is extremely high, and it can cope with those scenarios with massive processing data and high data bandwidth.

[0157] See also Figure 6Due to the stacking relationship of the storage pages P0 to PK+1 in the transparent material, when extracting the stored data, the data storage unit of any storage page may couple the voltage applied to the adjacent storage page and superimpose the color of the adjacent storage page on the data storage unit of any storage page in the reading state. This is because the structure of the stacked storage pages together with the transparent material between them is equivalent to forming a multi-layer parasitic capacitor. This parasitic capacitor exists between any two adjacent storage pages or between any two non-adjacent storage pages. For example, if the data storage unit of page PK+1 is assumed to be PK+1_addr(x0,y0), when extracting the stored data, the voltage applied to page PK+1 may be coupled to the storage page PK. For example, V_adjustK+1 is coupled to the anode A_PK of PK by parasitic capacitance. In this case, it is equivalent to enabling the unit PK_addr(x0,y0) of PK with the voltage coupled by V_adjustK+1. Then, the color of PK_addr(x0,y0) is mixed in the result of reading the data storage unit PK+1_addr(x0,y0). In essence, the color of the adjacent storage page, such as PK_addr(x0,y0), is superimposed on PK+1_addr(x0,y0) in the read state. As the storage density increases, the distance between the two storage pages will naturally be further compressed. In other words, the higher the storage density, the higher the probability of the aforementioned read error. This disadvantage restricts Figure 2 Integrate more storage units in a smaller space.

[0158] See also Figure 8 The solution to the read error is as follows. When the data storage unit of any storage page extracts the stored data (such as applying voltage to the anode and cathode), the adjacent storage page of any storage page is synchronously applied with a reverse voltage to avoid coupling the voltage applied to any storage page to the adjacent storage page, and prevent the coupled voltage from superimposing the color of the adjacent storage page on the data storage unit of any storage page in the read state.

[0159] See also Figure 8For example, when a voltage is applied to the data storage unit PK+1_addr(x0,y0) of any storage page PK+1 to extract the stored data, a reverse voltage is synchronously applied to the adjacent storage page PK of the any storage page PK+1. The reverse voltage is a negative voltage relative to the voltage V_adjustK+1 applied to the any storage page PK+1. The time of applying the reverse voltage is synchronized with the time when the data storage unit PK+1_addr(x0,y0) extracts the data. For example, at the time TK+1, the reverse voltage represented by the dotted line can be synchronously applied to the anode A_PK of the adjacent storage page PK. V_adjustK is a negative voltage in this case and the time when the voltage is negative is TK+1. In an optional embodiment, the absolute value of this negative voltage is smaller than the absolute value of the voltage V_adjustK+1 applied to the storage page PK+1, so as to avoid color inversion of the data storage unit PK+1_addr(x0,y0) in the storage page PK+1. It is easy to understand that the above scheme will try to avoid coupling the voltage V_adjustK+1 applied to the storage page PK+1 to the adjacent storage page PK, thereby preventing the coupled voltage from accidentally superimposing the display color of the adjacent storage page PK, such as PK_addr (x0, y0), on the data storage unit of any storage page PK+1 in the read state, such as PK+1_addr (x0, y0).

[0160] See also Figure 8 The above solution to read errors has another important use. When the data storage unit of any storage page extracts the stored data, the adjacent storage page of the any storage page is synchronously applied with a reverse voltage, which is also used to shield the parasitic charges induced by the data extraction of any storage page at the remaining other storage pages, thereby ensuring that the data extraction tasks performed by the data storage units of the remaining other storage pages are implemented under the condition that the remaining other storage pages themselves do not carry parasitic charges.

[0161] See also Figure 8For example, when a voltage is applied to the data storage unit PK+1_addr(x0,y0) of any storage page PK+1 to extract the stored data, a reverse voltage is synchronously applied to the adjacent storage page PK of the any storage page PK+1. The reverse voltage is a negative voltage relative to the voltage V_adjustK+1 applied to the any storage page PK+1. The reverse voltage is also used to shield the parasitic charges induced by the extraction of data from the remaining other storage pages, such as P0 to PK-1. The anode A_PK+1 of any storage page PK+1 is applied with V_adjustK+1, and this voltage will also be coupled to the anodes of other storage pages, such as A_P0, A_P1 to A_PK-1, through parasitic capacitance, which will induce the anodes of other storage pages to accumulate charges. The more times it is read, the more charge is accumulated. When the data storage unit of the memory page P0 performs the data extraction task, the anode A_P0 needs to apply the voltage V_adjust0. The voltage V_adjust0 plus the accumulated charge will obviously exceed the voltage V_adjust0 itself. Therefore, the data storage unit of the memory page P0 does not display the original color at this time but is much darker than the original color. This is also a kind of read error. The reverse voltage is used to shield such parasitic charges generated by the remaining memory pages. In this way, the data extraction task (this task requires applying voltages to the anode and cathode) performed by the data storage units of the remaining memory pages such as P0 to PK-1 is protected during the remaining memory pages such as P0 to PK-1 (see Figure 2 ) is implemented under the condition that the anode of other memory pages, such as P0 to PK-1, does not carry parasitic charges. This is equivalent to suppressing the anode accumulation of charges in other memory pages, such as P0 to PK-1, and preventing them from having read errors.

[0162] See also Figure 2 The photoelectric memory includes a transparent material in which a plurality of stacked storage pages are arranged, and each storage page includes a plurality of data storage units in an array form; each data storage unit is equipped with an anode, a cathode and an electrochromic layer, and the electrochromic layer is located between the anode and the cathode, and when a voltage is applied between the anode and the cathode, the electrochromic layer will show color, and when the voltage is removed between the anode and the cathode, the electrochromic layer will fade, thereby setting the electrochromic layer of the data storage unit to be different so that the data stored in the data storage unit is set to be different. The data of the data storage unit is extracted using the voltage applied between its anode and cathode. Based on the applied voltage, different electrochromic layers display different colors and transmit different data, so that the color displayed by the electrochromic layer of the data storage unit represents the data stored therein. For specific implementation methods, please refer to Figure 7 Embodiments of the invention are described.

[0163] See also Figure 2, a data storage system includes a transparent material and a power supply module such as an SMPS and a computer not shown in the figure. A plurality of stacked storage pages are arranged in the transparent material, each storage page includes a plurality of data storage units in an array form; and an anode and a cathode and an electrochromic layer are provided for each data storage unit in the transparent material, the electrochromic layer is located between the anode and the cathode, and the electrochromic layer will develop color when a voltage is applied between the anode and the cathode, and will fade when the voltage is removed between the anode and the cathode, thereby setting the electrochromic layer of the data storage unit to be different so as to set the data stored in the data storage unit to be different.

[0164] See also Figure 2 In data storage systems, the power supply module SMPS (combined Figure 6 ) provides a voltage between the anode and cathode of each data storage unit. The data stored in the data storage unit can be extracted using the voltage applied between the anode and cathode. Based on the applied voltage, different electrochromic layers display different colors and transmit different data, so that the color displayed by the electrochromic layer of the data storage unit represents the data stored therein.

[0165] See also Figure 2 , data storage system, the computer is equipped with a camera (combined Figure 5 ), multiple data storage units of multiple storage pages are selected, different colors of the data storage units are photographed by a camera and corresponding data as a specimen are matched for each color, a neural network is trained by a computer; the trained neural network is used to infer the data represented by the data storage units of other storage pages under their own color conditions.

[0166] The above description and drawings provide typical embodiments of specific structures of specific embodiments. The above invention provides existing preferred embodiments, but these contents are not intended to be limiting. For those skilled in the art, various changes and modifications will undoubtedly be obvious after reading the above description. Therefore, the attached claims should be regarded as covering all changes and modifications of the true intent and scope of the present invention. Any and all equivalent scopes and contents within the scope of the claims should be considered to still be within the intent and scope of the present invention.

Claims

1. A data storage method, characterized in that: include: Arranging a plurality of stacked storage pages in a transparent material, each storage page comprising a plurality of data storage units in an array form, the data storage unit having an anode and a cathode and an electrochromic layer located therebetween, and setting the electrochromic layers of the data storage units to be different so as to set the data stored in the data storage units to be different; The data stored in the data storage unit is extracted using the voltage applied between its anode and cathode. Based on the voltage applied, different electrochromic layers display different colors and transmit different data. Therefore, the color displayed by the electrochromic layer of the data storage unit represents the data stored therein.

2. The data storage method according to claim 1, characterized in that: The electrochromic layer includes any one of an inorganic electrochromic material, an organic electrochromic material, a mixture of two or more organic electrochromic materials, and a dopant of an inorganic and organic electrochromic material.

3. The data storage method according to claim 1, characterized in that: The electrochromic layer may be arranged in different ways including: The electrochromic layer is made of different materials; or When the electrochromic layer is made of a mixture of multiple organic electrochromic materials, the mixing ratio of each organic electrochromic material is adjusted to provide different electrochromic layers; or When the electrochromic layer is doped with inorganic and organic electrochromic materials, the doping concentrations of the inorganic and organic electrochromic materials are adjusted to provide different electrochromic layers.

4. The data storage method according to claim 1, characterized in that: The anodes of all the data storage cells in any memory page are interconnected, and the cathodes of all the data storage cells in any memory page are interconnected.

5. The data storage method according to claim 4, characterized in that: When a data storage unit of any memory page is applied with a voltage and enters a read state for data extraction, the data storage units of the remaining other memory pages are prohibited from entering a read state, that is, a series of memory pages at different levels are read in a time-sharing manner.

6. The data storage method according to claim 4, characterized in that: In any storage page, all data storage cells share a common anode layer and all data storage cells share a common cathode layer, but the electrochromic layers of different data storage cells are discrete from each other.

7. The data storage method according to claim 1, characterized in that: A plurality of data storage units arranged on a plane of any storage page serve as a pixel point set of the any storage page and each data storage unit serves as an independent pixel point; An image containing all pixels of any storage page is used as parallel data to be read in parallel at one time, that is, the data of one storage page is read at a time with the storage page as the minimum reading unit.

8. The data storage method according to claim 1, characterized in that: Select multiple data storage units of multiple storage pages, provide corresponding data as specimens under different color renderings of the data storage units, so as to train a neural network; use the trained neural network to infer the data represented by the data storage units of other storage pages under their own color renderings.

9. An optoelectronic memory, characterized in that: include: A transparent material, in which a plurality of stacked storage pages are arranged, each storage page including a plurality of data storage units in an array form; as well as An anode and a cathode and an electrochromic layer are provided for each data storage unit, wherein the electrochromic layer is located between the anode and the cathode and develops color when a voltage is applied between the anode and the cathode and fades when the voltage is removed between the anode and the cathode, thereby setting the data stored in the data storage unit to be different by setting the electrochromic layer of the data storage unit to be different; The data stored in the data storage unit is extracted using the voltage applied between its anode and cathode. Based on the applied voltage, different electrochromic layers display different colors and transmit different data, so that the color displayed by the electrochromic layer of the data storage unit represents the data stored therein.

10. A data storage system, characterized in that: include: A transparent material, in which a plurality of stacked storage pages are arranged, each storage page including a plurality of data storage units in an array form; as well as An anode, a cathode and an electrochromic layer are provided for each data storage unit in the transparent material, the electrochromic layer is located between the anode and the cathode and develops color when a voltage is applied between the anode and the cathode, and fades when the voltage is removed between the anode and the cathode, thereby setting the data stored in the data storage unit to be different by setting the electrochromic layer of the data storage unit to be different; A power supply module provides a voltage between the anode and cathode of each data storage unit. The data stored in the data storage unit is extracted using the voltage applied between the anode and cathode. Based on the applied voltage, different electrochromic layers display different colors and transmit different data, so that the color displayed by the electrochromic layer of the data storage unit represents the data stored therein; A computer is provided with a camera, and multiple data storage units of multiple storage pages are selected. The camera photographs different colors of the data storage units and matches corresponding data as a specimen for each color. A neural network is trained by the computer; and the trained neural network is used to infer the data represented by the data storage units of other storage pages under their own color conditions.

Images